A signal correlation synchronization method and system based on parallel processing

Abstract

The present invention discloses a signal correlation synchronization method and system based on parallel processing, which relates to the technical field of signal synchronization and includes the following: The receiving end receives the radio frequency signal sent by the transmitting end; the receiving end performs coherent demodulation and low-pass filtering on the radio frequency signal to obtain a complex baseband signal, and samples the complex baseband signal to obtain a complex sequence; wherein, the complex sequence includes a known subsequence inserted by the transmitting end; the receiving end inputs the complex sequence into a linear shift register constructed by an FPGA, and the linear shift register calculates the correlation value between the complex sequence and the local known sequence; when the input complex sequence matches the target subsequence in the local known sequence, the absolute value of the correlation value will reach the maximum, forming a correlation peak; determine the clock moment corresponding to the correlation peak, so as to find the position of the known subsequence of the transmitting end in the complex sequence of the receiving end, complete signal correlation synchronization, and the synchronization system includes a receiving end and a transmitting end, and applies the signal correlation synchronization method based on parallel processing.

Description

Technical Field

[0001] The present invention relates to the technical field of signal synchronization, and particularly to a signal correlation synchronization method and system based on parallel processing. Background Art

[0002] In the field of modern communication technologies, RF link IQ dual-channel transceiver systems are widely used in various wireless communication devices, and their performance plays a key role in communication quality.

[0003] There are inevitably phase offset and frequency offset phenomena between the transmitter and the receiver. Phase offset will change the phase of the received signal, affecting the correct demodulation of the signal; frequency offset will make the frequency of the received signal inconsistent with the frequency of the transmitted signal, causing the offset of the signal spectrum, increasing the demodulation difficulty, and reducing the reliability and accuracy of the communication system.

[0004] The signals transmitted in the RF link are essentially real signals, but in the actual processing process, complex means are often used for processing. Traditional phase offset and frequency offset correction methods lack systematic and efficient methods in dealing with the relationship between real signals and complex processing means. Summary of the Invention

[0005] To solve the problem in the prior art that during signal synchronization, phase offset and frequency offset will cause the distortion of the received signal, making it difficult for the receiver to accurately identify the transmitted sequence, thus resulting in synchronization difficulties, the present invention provides a signal correlation synchronization method based on parallel processing.

[0006] The technical solution adopted by the present invention is as follows:

[0007] The first aspect of the present application provides a signal correlation synchronization method based on parallel processing, including the following:

[0008] The receiving end receives the RF signal sent by the transmitting end; the receiving end performs coherent demodulation and low-pass filtering on the RF signal to obtain a complex baseband signal, and samples the complex baseband signal to obtain a complex sequence; wherein, the complex sequence includes a known subsequence inserted by the transmitting end; the receiving end pre-stores a local known sequence identical to the known subsequence inserted by the transmitting end, and the receiving end inputs the complex sequence into a linear shift register constructed by an FPGA (Field-Programmable Gate Array), and calculates the correlation value between the complex sequence and the local known sequence through the linear shift register; when the input complex sequence matches the target subsequence in the local known sequence, the absolute value of the correlation value will reach the maximum, forming a correlation peak; determine the clock moment corresponding to the correlation peak, so as to find the position of the known subsequence of the transmitting end in the complex sequence of the receiving end, and complete signal correlation synchronization.

[0009] Preferably, the linear shift register constructed by the FPGA includes a plurality of delay elements, a plurality of multipliers, and an adder.

[0010] Preferably, calculating the correlation value between the complex sequence and the locally known sequence by the linear shift register includes the following:

[0011] The complex sequence is sequentially input into the linear shift register. Among them, each delay element is controlled by a sampling clock, so that the output signal of the right delay element lags one clock cycle behind the input signal of the left delay element. At each clock cycle, the complex sequence moves one bit to the right in the shift register in sequence, so as to realize the sequential processing of elements at different positions of the complex sequence; at each sampling moment, for the output of each delay element in the linear shift register, a multiplier is used to multiply it by the conjugate of the element at the corresponding position in the locally known sequence to obtain a plurality of intermediate results; the adder adds the intermediate results output by each multiplier to obtain the correlation value between the complex sequence and the locally known sequence.

[0012] Preferably, when the input complex sequence matches the target subsequence in the locally known sequence, the absolute value of the correlation value will reach the maximum value, forming a correlation peak; determining the clock moment corresponding to the correlation peak, so as to find the position of the known subsequence at the transmitting end in the complex sequence at the receiving end, and completing the signal correlation synchronization includes the following:

[0013] Generate an absolute value sequence of the correlation value in the order of sampling moments and store it in the FPGA; analyze the stored absolute value sequence of the correlation value. Starting from the starting position of the absolute value sequence, compare the absolute value of each correlation value with the absolute values of its adjacent previous and subsequent correlation values. If the absolute value of a certain correlation value is greater than the absolute values of its adjacent previous and next correlation values at the same time, then mark this point as a correlation peak candidate point; if there are multiple correlation peak candidate points, compare the absolute values of the correlation values of each candidate point one by one to find the maximum value among them. Determine the candidate point corresponding to the maximum value as the correlation peak; according to the position information of the correlation peak in the stored absolute value sequence of the correlation value, combined with the period parameter of the sampling clock, calculate the clock moment corresponding to the correlation peak; based on the clock moment, the receiving end locates the position of the known subsequence at the transmitting end in the received complex sequence to complete the signal correlation synchronization.

[0014] The second aspect of the present application provides a signal correlation synchronization system based on parallel processing, including a receiving end and a transmitting end, and applying the above-mentioned signal correlation synchronization method based on parallel processing.

[0015] The beneficial effects of the present invention are at least one of the following:

[0016] Use a linear shift register constructed by an FPGA to calculate the correlation value. The FPGA has powerful parallel processing capabilities and flexibility, and can complete the relevant calculations quickly and accurately. Through the correlation peak judgment mechanism, useful synchronization information can be accurately extracted from the signals affected by phase deviation, frequency deviation, and noise interference.

[0017] By constructing a linear shift register with an FPGA for correlation value calculation, compared with the traditional signal processing method, the processing time is greatly shortened. When calculating the correlation value between a complex sequence and a locally known sequence, a large number of multiplication and accumulation operations can be quickly completed, improving the efficiency of signal processing. Brief Description of the Drawings

[0018] Figure 1 It is a schematic flowchart of the method according to the first embodiment of the present invention;

[0019] Figure 2 It is a schematic diagram of the system structure and signal flow of the transceiver link in the first embodiment of the present invention;

[0020] Figure 3 It is a schematic diagram of the structure of the linear shift register in the first embodiment of the present invention. Detailed Description of the Preferred Embodiments

[0021] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0022] The first embodiment provides a signal correlation synchronization method based on parallel processing, as Figure 1 shown, including the following steps:

[0023] Step 1, the receiving end receives the radio frequency signal sent by the transmitting end.

[0024] For reference, in this example, the receiving end can be a receiver, and the transmitting end can be a transmitter; as Figure 2 shown, the signal sent by the transmitter is a modulated electromagnetic wave signal, that is, a real number signal, and the signal on the receiving antenna is also real. The signals transmitted on the transceiver link, including the expressions of the iq path signals, are all real numbers, but usually complex means or methods are used to process the signals.

[0025] From Figure 2 it can be seen that the path sequence and of the transmitter, after D / A, up-conversion, power amplifier, antenna transmission and reception, low-noise amplifier (LNA), down-conversion, low-pass filtering, and A / D, the digital path sequence and , in this process, after the communication system structure and settings are determined, the intermediate operation process does not require interference or processing, and only the above four sequences can be operated on.

[0026] Specifically, when transmitting, it is necessary to send and to the software radio system (such as ad9361). When receiving, only and these two sequences are involved. All demodulation, signal extraction, and other tasks rely on these two sequences. To correctly complete signal extraction, demodulation, and other tasks, the radio system can be regarded as a black box. The input of this black box is and , and the output is and .

[0027] In Figure 2 , if is not equal to , there is a phase deviation. If is not equal to , there is a frequency deviation. When the system has factors such as phase deviation and frequency deviation, the relationship between the received sequence and the transmitted sequence can be used for signal synchronization.

[0028] To obtain the relationship between the sequences , and the sequences , , first, the relationship between the analog signals , and , needs to be obtained. First, the real signal of the transmitter is assembled into a complex baseband signal, and then the expression of the complex baseband signal received by the receiver is derived using the signal processing process of the system. Then, the relationship between the transmitted and received signals is obtained through the expression.

[0029] Among them, the part signal of the transmitter plus the

[0030] (1)

[0031] where, represents the part signal of the transmitter, represents the part signal of the transmitter, represents the complex baseband signal of the transmitter, and j represents the imaginary number.

[0032] Usually, the complex baseband signal is Channel modulation, specifically Channel and Channel are respectively multiplied by With , and then added together. Thus, the expression of the RF signal obtained is as follows, which can also be regarded as the signal expression on the transmitting antenna:

[0033] (2)

[0034] Among them, represents the RF signal transmitted by the transmitting antenna, represents the part signal of the transmitter, represents the part signal of the transmitter, represents the complex baseband signal of the transmitter, represents the angular frequency of the transmitter, represents the initial phase of the signal transmitted by the transmitter.

[0035] Then the RF signal will pass through the channel, and the channel has two effects on the RF signal. One is the amplitude change effect, that is, the amplitude of the signal received by the receiver may not be equal to the amplitude of the transmitter. Since the analog signal will finally be presented to the user in the form of a 12-bit signed digital signal after being amplified by the low-noise amplifier (LNA), adjusted by the automatic gain control (AGC), and converted by the analog-to-digital converter (ADC), the attenuation of the signal amplitude can be ignored, and it is considered that the amplitude of the received signal is equal to the amplitude of the transmitted signal; the other is the delay effect, that is, if the transmitter assumes to transmit a signal at a certain moment t1, then the receiver will definitely receive the signal at another moment t2. If the receiver and the transmitter both use the same starting reference time, then t2 is not equal to t1, and t2 must be greater than t1. Assume , if the receiver uses the same starting reference time as the transmitter, then there is always a in the expression of the receiver signal, which is rather troublesome. If the reference time of the receiver is set to start when the receiver receives the first signal, the signal expression in the receiver will be simplified. Using the above simplification, it can be considered that the expression of the analog signal transmitted by the receiving antenna is equal to in formula (2). As Figure 2 shown, the signal expressions marked on the transmitting antenna and the receiving antenna are both .

[0036] Step 2, the receiving end coherently demodulates and low-pass filters the RF signal to obtain a complex baseband signal, and samples the complex baseband signal to obtain a complex sequence; among them, the complex sequence includes the known subsequence inserted by the transmitting end.

[0037] Among them, the receiver processes the radio frequency signal through coherent demodulation and low-pass filtering to obtain a complex baseband signal, including the following content:

[0038] The part signal of the receiver is to multiply by , and then take its low-pass filtering. The expression of the part signal of the receiver is:

[0039] (3)

[0040] The part signal of the receiver is multiplied by , and then through low-pass filtering. The expression of the part signal of the receiver is:

[0041] (4)

[0042] Among them, is the expression of the part signal of the receiver, is the expression of the part signal of the receiver, represents the part signal of the transmitter, represents the part signal of the transmitter, represents the complex baseband signal of the transmitter, represents the angular frequency of the transmitter, represents the initial phase of the transmitter signal, represents the angular frequency of the receiver, represents the initial phase of the receiver.

[0043] The derivations of formula (3) and formula (4) utilize the product-to-sum formula in formula (5). In the last step of formula (3) and formula (4), is ignored because the analog signal has undergone multiple attenuation and amplification operations during transmission, and finally the ADC converts it into a digital quantity with an appropriate dynamic range. Therefore, there is no need to care about the specific magnitude of the analog signal.

[0044] (5)

[0045] Let is the received complex baseband signal, and the expression of the complex baseband signal is:

[0046] (6)

[0047] Equation (6) shows that the complex baseband signal of the iq path of the receiver is equal to the complex baseband signal of the transmitter multiplied by a rotation factor, and the expression of this rotation factor is .

[0048] Based on Equation (6), first consider the case where there is no frequency offset between the receiver and the transmitter, that is When, it is found that at any moment, the complex baseband signal formed by the iq path of the received signal is just multiplied by a constant compared with the complex baseband signal sent by the transmitter at the same moment. This constant can be called the phase offset factor. If it is known that the signal transmitted at time is , and the received signal is , then using the phase offset factor can be obtained. If the conjugate of this phase offset factor is multiplied by any subsequent received signal, the signal of the transmitter can be obtained, and its real part and imaginary part are respectively and . After sampling, the digital sequences of the ADC and can also be correctly obtained.

[0049] However, this method of using and at a certain moment to obtain the phase offset factor has deficiencies, because both of these two signals at a certain moment contain noise, making the obtained phase offset factor not very accurate. To improve the accuracy, multiple phase offset factors can be obtained using signals of multiple periods and then averaged.

[0050] When , that is, when there is a frequency offset, assuming that the analog signals and are both sampled at a frequency of , then the sampling time interval . Let , then Equation (6) can be written as:

[0051] (7)

[0052] Among them, represents the discrete sampling sequence number, , represents the sampling time interval, represents the th sampling moment, represents the value of the complex baseband signal of the transmitter at the th sampling moment, respectively represent the carrier frequencies of the transmitter and the receiver, with the unit of Hz.

[0053] Assume that = at the moment of and are known, then the corresponding phase deviation factor can be calculated to be equal to . For this phase deviation factor, there is no need to deduce the value from this. Obviously, is equal to the current moment divided by . However, it is meaningless to calculate the current moment in this way. What is needed is how many degrees the subsequent signal needs to be rotated relative to the phase deviation factor at this time, or what kind of phase deviation factor needs to be multiplied on this basis. For this purpose, it can be assumed that . Obviously, . Since is originally a random number between 0 and , must also be a random number, and the method for calculating the phase deviation in the above text is applicable to any random number. After a period of time, assume that > . According to Equation (7), we can obtain:

[0054] (8)

[0055] Equation (8) shows that when the received complex baseband signal at the moment is equal to multiplying the transmitted complex baseband signal by a , the received complex baseband signal at the moment needs to multiply the transmitted complex baseband signal by a rotation factor with a larger angle . This rotation factor is more than the rotation factor at the moment. Obviously, is the larger, the larger the deviation angle of the rotation factor. If we let be the unit rotation angle and be the unit rotation factor, then the above process shows that the moment relative to Rotate more frequently by an angle, where the rotation factor is the power of the unit rotation factor.

[0056] Assume that the transmitter sends out a pair of sampled values on the I / Q channels every time, forming a complex sequence , and the receiver also receives the complex sequence , .

[0057] Among them, the sequence of the transmitter contains the subsequence , and it is necessary to find from the complex sequence of the receiver.

[0058] Step 3: The receiving end pre-stores a local known sequence that is the same as the known subsequence inserted by the transmitting end. The receiving end inputs the complex sequence into a linear shift register constructed by an FPGA, and calculates the correlation value between the complex sequence and the local known sequence through the linear shift register.

[0059] In a specific implementation process, in order to find from the complex sequence of the receiver, the receiving end inputs the complex sequence into a linear shift register constructed by an FPGA. In a possible implementation manner, as Figure 3 shown, the linear shift register constructed by the FPGA includes multiple delayers, multiple multipliers, and adders.

[0060] In a possible implementation manner, calculating the correlation value between the complex sequence and the local known sequence through the linear shift register includes the following: Input the complex sequence into the linear shift register in sequence. Among them, each delayer is controlled by a sampling clock, so that the output signal of the right delayer is one clock cycle later than the input signal of the left delayer. At each clock cycle, the complex sequence moves one bit to the right in the shift register in sequence, so as to achieve sequential processing of elements at different positions of the complex sequence. At each sampling moment, for the output of each delayer in the linear shift register, use a multiplier to multiply it by the conjugate of the element at the corresponding position in the local known sequence to obtain multiple intermediate results. The adder adds the intermediate results output by each multiplier to obtain the correlation value between the complex sequence and the local known sequence.

[0061] Exemplarily, as Figure 3 shown, Figure 3 each in represents a delayer, and the output signal of each delayer on the right is one clock cycle later than the input signal on the left. All the delayers are controlled by the same sampling clock controlled by the rising or falling edge of Figure 3 Taking a 6th-order filter as an example. Generally, an Nth-order filter requires N - 1 delay elements. Starting from Figure 3 it can be seen that the sequence output by the delay element closer to the right is more "ancient", that is, the independent variable in the parentheses is smaller, and the smaller value represents an earlier time.

[0062] In the figure, represents a multiplier. One input of each multiplier is taken from the output of a certain delay element, and the other input is set to be one of the local sequences here denotes taking the conjugate of a complex number. The + sign below the multiplier represents adding the results output by each multiplier.

[0063] clk_ represents the sampling clock of the ADC and is also the driving clock for all multipliers, delay elements, adders, etc. The structure of the entire system is that at the rising edge of each clk_ the system will input a complex number , and at the same time y( ) will also output a complex number. The expression of y( ) is:

[0064] (9)

[0065] where represents the degree of correlation between the received complex sequence and the local known sequence at the th sampling moment. There are 6 terms added in formula (9), and each term is the multiplication of two complex numbers. Obviously, when , formula (10) can be obtained:

[0066]

[0067] Each term in formula (10) is the multiplication of a certain complex number and its conjugate complex number. From the conclusion of formula (7), it is found that relative to there is a common rotation factor , which can be factored out. At this time, taking the absolute value of will obtain the maximum value. When the input at this moment is not , due to , it is uncorrelated with . The argument between the two input complex numbers of each multiplier is randomly and uniformly distributed between 0 and , and the modulus value of each complex number is considered to be equal (for example, if it is QPSK modulation, these complex numbers are all One of them has a modulus value equal to ), which will cause the real and imaginary parts to cancel each other out when multiple products are added together, resulting in being relatively small and definitely less than when At that time. Obviously, when the order of the filter is larger, the effect of mutual cancellation without synchronization becomes more obvious, and the value of the correlation peak is also larger when synchronized.

[0068] Step 4: When the input complex sequence matches the target subsequence in the local known sequence, the absolute value of the correlation value reaches the maximum, forming a correlation peak.

[0069] Step 5: Determine the clock moment corresponding to the correlation peak, so as to find the position of the known subsequence at the transmitting end in the complex sequence at the receiving end, and complete signal correlation synchronization.

[0070] In a possible implementation manner, when the input complex sequence matches the target subsequence in the local known sequence, the absolute value of the correlation value reaches the maximum, forming a correlation peak; determining the clock moment corresponding to the correlation peak, so as to find the position of the known subsequence at the transmitting end in the complex sequence at the receiving end, and completing signal correlation synchronization includes the following:

[0071] Generate a sequence of absolute values of correlation values in the order of sampling moments and store it in the FPGA according to the calculated absolute values of correlation values.

[0072] Analyze the stored sequence of absolute values of correlation values. Starting from the starting position of the absolute value sequence, compare the absolute value of each correlation value with the absolute values of its adjacent previous and next correlation values. If the absolute value of a certain correlation value is greater than the absolute values of its adjacent previous and next correlation values at the same time, mark this point as a candidate correlation peak point.

[0073] If there are multiple candidate correlation peak points, compare the absolute values of the correlation values of each candidate point one by one, find the maximum value among them, and determine the candidate point corresponding to the maximum value as the correlation peak.

[0074] According to the position information of the correlation peak in the stored sequence of absolute values of correlation values and combined with the cycle parameter of the sampling clock, calculate the clock moment corresponding to the correlation peak.

[0075] Based on the clock moment, the receiving end locates the position of the known subsequence at the transmitting end in the received complex sequence, and completes the correlation synchronization of the signal.

[0076] Exemplarily, continuously search with a hardware description language For the highest peak, the highest peak found is the correlation peak. When the clk_ corresponding to the correlation peak is known After that, it is possible to know that the subsequent signal will be a useful information-carrying sequence.

[0077] In summary, this application uses an FPGA to construct a linear shift register for correlation value calculation, giving full play to the parallel processing ability of the FPGA. The FPGA can process multiple data simultaneously. When calculating the correlation value between a complex sequence and a locally known sequence, multiple multipliers and adders can work in parallel, greatly shortening the processing time. Compared with the traditional serial processing method, the parallel processing of the FPGA can complete a large number of multiplication and accumulation operations in a shorter time, improving the efficiency of signal processing.

[0078] Embodiment 2 provides a signal correlation synchronization system based on parallel processing, including a receiving end and a transmitting end, and applying the above-mentioned signal correlation synchronization method based on parallel processing.

[0079] The above-described embodiments only represent the specific implementation manners of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention.

Claims

1. A signal correlation synchronization method based on parallel processing, characterized in that, It includes the following: The receiving end receives the radio frequency signal sent by the transmitting end; The receiving end obtains a complex baseband signal by coherently demodulating and low-pass filtering the radio frequency signal, and samples the complex baseband signal to obtain a complex sequence; wherein, the complex sequence includes a known subsequence inserted by the transmitting end; wherein, the complex baseband signal at the receiving end is equal to the complex baseband signal at the transmitting end multiplied by a rotation factor, and the expression of the rotation factor is ; wherein, represents the angular frequency of the transmitter, represents the initial phase of the transmitter signal, represents the angular frequency of the receiver, represents the initial phase of the receiver; When , that is, when there is a frequency offset, assume that the analog signals and are both sampled at the frequency of , then the sampling time interval . Let , and we get: Among them, represents the discrete sampling sequence number, , represents the sampling time interval, represents the moment of the -th sampling, represents the value of the complex baseband signal at the transmitter at the -th sampling moment, respectively represent the carrier frequencies of the transmitter and the receiver; Suppose the transmitting end sends out a pair of sampled values on the iq channels every time, and the complex sequence of the transmitter is . The receiving end will also receive the complex sequence , ; The channel sampling sequence at the transmitting end, is the channel sampling sequence at the transmitting end; The channel sampling sequence at the receiving end, is the channel sampling sequence at the receiving end; Among them, the sequence in the transmitter contains a known subsequence ; represents the sequence value of the th sampling point in the transmitter complex sequence; represents the sequence value of the th sampling point in the transmitter complex sequence; The receiving end pre-stores a local known sequence identical to the known subsequence inserted by the transmitting end. The receiving end inputs the complex sequence into the linear shift register constructed by the FPGA, and calculates the correlation value between the complex sequence and the local known sequence through the linear shift register; The linear shift register constructed by the FPGA includes multiple delayers, multiple multipliers and adders; The calculating the correlation value between the complex sequence and the local known sequence through the linear shift register includes the following: Input the complex sequence into the linear shift register in sequence. Among them, each delayer is controlled by the sampling clock, so that the output signal of the right delayer is one clock cycle later than the input signal of the left delayer. At each clock cycle, the complex sequence moves one bit to the right in the shift register in sequence, so as to realize the sequential processing of the elements at different positions of the complex sequence; At each sampling moment, for the output of each delay element in the linear shift register, a multiplier is used to multiply it by the conjugate of the element at the corresponding position in the locally known sequence, obtaining a plurality of intermediate results; wherein, one input of each multiplier is taken from the output of a certain delay element, and the other input is set to be one of the local sequences here denotes taking the conjugate of a complex number; The adder adds up the intermediate results output by each multiplier to obtain the correlation value between the complex sequence and the local known sequence; When the input complex sequence matches the target subsequence in the local known sequence, the absolute value of the correlation value will reach the maximum value, forming a correlation peak; Determine the clock moment corresponding to the correlation peak, so as to find the position of the known subsequence of the transmitting end in the complex sequence of the receiving end, and complete the signal correlation synchronization.

2. The signal correlation synchronization method based on parallel processing according to claim 1, wherein When the input complex sequence matches the target subsequence in the local known sequence, the absolute value of the correlation value will reach the maximum value, forming a correlation peak; determining the clock moment corresponding to the correlation peak, so as to find the position of the known subsequence of the transmitting end in the complex sequence of the receiving end, and completing the signal correlation synchronization includes the following: Generate an absolute value sequence of the correlation value in the order of sampling moments and store it in the FPGA according to the calculated absolute value of the correlation value; Analyze the stored absolute value sequence of the correlation value. Starting from the starting position of the absolute value sequence, compare the absolute value of each correlation value with the absolute values of its adjacent front and rear correlation values. If the absolute value of a certain correlation value is greater than the absolute values of its adjacent previous and next correlation values at the same time, mark this position as a correlation peak candidate point; If there are multiple correlation peak candidate points, compare the absolute values of the correlation values of each candidate point one by one, find the maximum value among them, and determine the candidate point corresponding to the maximum value as the correlation peak; According to the position information of the correlation peak in the stored absolute value sequence of the correlation value, combined with the cycle parameter of the sampling clock, calculate the clock moment corresponding to the correlation peak; Based on the clock moment, the receiving end locates the position of the known subsequence of the transmitting end in the received complex sequence, and completes the correlation synchronization of the signal.

3. A signal correlation synchronization system based on parallel processing, comprising a receiving end and a transmitting end, characterized in that, Apply the signal correlation synchronization method based on parallel processing described in any one of claims 1-2.

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