Method for load balancing and acceleration of lossless switch multiple cross-chip channels

Abstract

The application provides a method for load balancing and acceleration of multiple crossbar channels of a non-loss switch, comprising: a crossbar node traffic distribution module distributing data for nodes based on a source port mode, each packet recombination module recombining data according to a predetermined byte interval; an asynchronous clock arbitration module performing asynchronous arbitration on recombined data frames; a multi-channel balanced distribution module distributing recombined data frames to each crossbar channel in a pipeline mode, and receiving recombined data frames of other FPGAs; a multi-channel traffic aggregation module aggregating data frames in a pipeline mode; and each packet recombination module recombining and distributing the aggregated data frames to corresponding switching nodes. The application can effectively improve the data transmission efficiency and performance of the crossbar channel, ensure efficient and balanced data flow between different FPGAs, and thus improve the stability and reliability of the entire communication network.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of FPGA data interaction, and particularly relates to a method for load balancing and acceleration of multiple cross-chip channels of a lossless switch. BACKGROUND

[0002] With the continuous progress of communication technology, the role of switches in data exchange networks becomes increasingly critical. They not only need to handle the growing data traffic, but also need to ensure the efficiency and stability of data transmission. Switches use FPGA internal resources to build efficient crossbar architecture and input-output processing architecture, allowing data frames to be quickly exchanged between different ports. This architecture allows switches to maintain low latency and high throughput in high-speed data transmission, meeting the needs of modern communication networks.

[0003] However, with the explosive growth of user data traffic, traditional single-chip FPGA switches begin to show their limitations, especially in scenarios that require handling large-scale data exchange. The limited resources of a single FPGA cannot meet the growing demand for data exchange, which requires multiple FPGAs to work together to achieve larger-scale data exchange. This collaborative work requires real-time communication and large amounts of data exchange between FPGAs to ensure data continuity and integrity.

[0004] In order to further improve cross-chip traffic, multiple cross-chip Aurora channels are used for cascading to achieve higher data transmission rates. However, due to the limitations of the crossbar architecture and the Aurora cross-chip channel itself, there is often a lack of effective coordination mechanism between these channels, resulting in some channels being overloaded while others are idle. This uneven load distribution not only reduces the overall data transmission efficiency, but also can cause network congestion and data delay, seriously affecting the performance of the communication network. SUMMARY

[0005] In order to solve the above problems existing in the prior art, the application provides a method for load balancing and acceleration of multiple cross-chip channels of a lossless switch. The technical problem to be solved by the application is solved by the following technical scheme:

[0006] A method for load balancing and acceleration of multiple cross-chip channels of a lossless switch is applied to each FPGA, the FPGA includes a crossbar node traffic distribution module, an n packet reassembly module, an asynchronous clock arbitration module, a multi-channel balanced shunt module, a multi-channel traffic aggregation module and a switching node, the method for load balancing and acceleration of multiple cross-chip channels of a lossless switch includes:

[0007] a crossbar node traffic distribution module, which distributes data frames to two switch nodes in each column of the switch node based on a source port mode and sends the data frames of the two switch nodes to a corresponding packet reassembly module;

[0008] each packet reassembly module reassembles the sent data frames according to a predetermined byte interval to obtain two reassembled data frames and sends the two reassembled data frames to an asynchronous clock arbitration module;

[0009] the asynchronous clock arbitration module arbitrates the two reassembled data frames of each packet reassembly module to distinguish the reassembled data frames sent first and the reassembled data frames sent later to obtain an arbitration result and sends the arbitration result to a multi-channel balanced distribution module;

[0010] the multi-channel balanced distribution module evenly distributes all the reassembled data frames to each cross-chip channel in a pipeline mode and sends the reassembled data frames to other FPGAs through the corresponding cross-chip channel; and the cross-chip channel receives the reassembled data frames sent by other FPGAs;

[0011] the multi-channel traffic aggregation module selects data from the received reassembled data frames for aggregation in a pipeline mode and sends the aggregated data frames to a corresponding packet reassembly module;

[0012] each packet reassembly module disassembles and distributes the aggregated data frames to a corresponding switch node.

[0013] Advantages:

[0014] 1. The application solves the problem that the long data frames in the prior art consume too much FPGA resource and the short data frames seriously affect the switching performance by reassembling the data frames into a length for cross-chip, and the application takes into account the cross-chip traffic rate and the use of FPGA resource, thereby improving the switching performance of the switch.

[0015] 2. The application provides a traffic balancing scheme, which can ensure that n cross-chip channels are evenly distributed and does not cause frame disordering.

[0016] 3. The application is based on the traditional crossbar architecture, adds an asynchronous clock arbitration module and a crossbar node traffic distribution module, improves the upper limit of the cross-chip traffic speed, and further improves the cross-chip efficiency.

[0017] 4. The application adds a lossless flow control module, uses an NFC flow control frame, realizes lossless transmission of cross-chip traffic when multiple FPGAs are cascaded, and solves the problem that in a traditional switch, the sending end cannot perceive the load condition of the receiving end when crossing the chip, cannot dynamically adjust the data traffic of the sending end, and easily causes data loss in a high load condition.

[0018] The application will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is an internal architecture diagram of the FPGA provided by the embodiment of the application;

[0020] Figure 2 is a simple diagram of the internal module of the FPGA provided by the embodiment of the application;

[0021] Figure 3 is a flowchart of a method for load balancing and acceleration of multiple cross-chip channels of a lossless switch provided by the embodiment of the application;

[0022] Figure 4 is a schematic diagram of crossbar node traffic distribution based on a data frame destination port number provided by the embodiment of the application.

[0023] Figure 5 is a schematic diagram of crossbar node traffic distribution based on a data frame source port number provided by the embodiment of the application;

[0024] Figure 6 is a timing diagram of a packet reassembly module provided by the embodiment of the application;

[0025] Figure 7 is a general flowchart of cross-chip traffic convergence and balanced shunting provided by the embodiment of the application;

[0026] Figure 8 is a sending channel balanced shunting module architecture diagram provided by the embodiment of the application;

[0027] Figure 9 is a channel flow arbitration flowchart of a sending channel provided by the embodiment of the application;

[0028] Figure 10 is a receiving channel balanced shunting module architecture diagram provided by the embodiment of the application;

[0029] Figure 11 is a bus flow arbitration flowchart of a receiving channel provided by the embodiment of the application;

[0030] Figure 12 is a cross-chip channel lossless flow control module architecture diagram provided by the embodiment of the application;

[0031] Figure 13 is a flowchart of cross-chip lossless flow control provided by an embodiment of the present application. DETAILED DESCRIPTION

[0032] The present application will be further described in conjunction with specific embodiments, but the embodiments of the present application are not limited thereto.

[0033] The present application provides a method for load balancing and acceleration of multiple cross-chip channels of lossless switches, which is used to realize traffic load balancing and acceleration of multiple cross-chip channels of lossless switches, aiming to solve the problems of unbalanced channel traffic and too low acceleration ratio encountered by traditional switches when processing cross-chip traffic. By optimizing key links such as data packet reassembly, asynchronous clock arbitration, and crossbar node traffic distribution, the present application can effectively improve the data transmission efficiency and performance of cross-chip channels, ensure efficient and balanced flow of data between different FPGAs, and thus improve the stability and reliability of the entire communication network.

[0034] The present application provides a method for load balancing and acceleration of multiple cross-chip channels of lossless switches, which is applied to each FPGA, combined with Figure 1 and Figure 2 , the FPGA includes a crossbar node traffic distribution module, an n packet reassembly module, an asynchronous clock arbitration module, a multi-channel balanced distribution module, a multi-channel traffic aggregation module, and a switching node. The switching node includes ordinary switching nodes and cross-chip switching nodes. The number of columns of the cross-chip switching nodes is 4 columns; the number of packet reassembly modules, cross-chip channels, and FIFOs is 4.

[0035] As shown in Figure 3 , the present application provides a method for load balancing and acceleration of multiple cross-chip channels of lossless switches, which includes:

[0036] S100, a crossbar node traffic distribution module, which distributes data frames to 2 switching nodes in each column of the switching node based on a source port mode, and sends the data frames of the 2 switching nodes into the corresponding packet reassembly module;

[0037] Referring to Figure 2 , the crossbar node traffic distribution module distributes data frames to 2 cross-chip switching nodes in each column of the switching node based on a source port mode, and sends the data frames of the 2 cross-chip switching nodes into the corresponding packet reassembly module; wherein the cross-chip switching nodes are divided into 4 columns, and the source port mode is used to assign the same number of cross-chip switching nodes in each column.

[0038] It needs to be further explained that the application changes the traditional strategy of distributing crossbar channels based on destination ports to the strategy of distributing crossbar channels based on source ports, and the highest processing efficiency of the latter is n times (n=crossbar channel number) of that of the former.

[0039] If the traffic is distributed according to destination ports, a column of crossbar nodes will have data packets, as shown in Figure 4 Figure 4 is the strategy of distributing crossbar channels based on destination ports. Assuming that the arbitration module rate is 76 Gb / s, eight nodes are arbitrated, and each node is allocated a rate of 9.5 Gb / s.

[0040] Referring to Figure 5 , Figure 5 is the strategy of distributing crossbar channels based on source ports, which only needs to arbitrate two nodes. When the arbitration rate is constant, the fewer nodes arbitrated, the higher the rate allocated to each node. Assuming that the arbitration module rate is 76 Gb / s, two nodes are arbitrated, and each node is allocated a rate of 38 Gb / s, which is 4 times that of the previous strategy.

[0041] S200, each packet reassembly module reassembles the incoming data frame according to a predetermined byte interval to obtain two reassembled data frames, and sends them to the asynchronous clock arbitration module;

[0042] Among them, each packet reassembly module reassembles the incoming short data frame into a long data frame according to the 1518-3000 byte interval to obtain two reassembled data frames, and sends them to the asynchronous clock arbitration module; wherein the short data frame is a data frame with a byte number less than 1518, and the long data frame is a data frame with a byte number greater than 1518.

[0043] It needs to be further explained that because the data processing logic of the switch and the clock frequency are constant, when the traffic is large, the minimum interval between data packets is constant, and thus the highest processing rate of the switch data packet can be calculated, as shown in Figure 6

[0044] However, due to the minimum logical interval and the TAG header (a field used to store data frame information) between data packets, the actual processing rate F is related to the byte length M as follows:

[0045]

[0046] ​​Taking 1518 bytes and 64 bytes data frame as an example, assuming that the frame minimum interval N is TAG header + minimum logical processing interval = 1 + 5 = 6 beats (1 beat corresponds to 384 bit width, i.e. 48 bytes). For 200M clock, 384 bit width processing module, the highest processing rate P of theoretical data is equal to 384bit*200M = 76Gb / s.

[0047] For M = 1518 bytes data frame, substituting into the above formula, the highest processing rate F of theoretical data is equal to 64Gb / s

[0048] For M = 64 bytes data frame, substituting into the above formula, the highest processing rate F of theoretical data is equal to 19Gb / s

[0049] Therefore, it can be concluded that the processing rate of short frame in the switching process is much lower than that of long frame, so the application can splice short frames into long frames for cross-chip, which can greatly improve the processing efficiency of cross-chip.

[0050] Considering that too long data frame will consume too high FPGA resource, and too short data frame will seriously affect the switching performance, according to the above formula, the application splices data packet into a relatively moderate length, i.e. 1518-3000 bytes data frame for cross-chip, which takes into account the cross-chip traffic rate and the use of FPGA resource. When the recombined data frame enters the packet recombination module of another chip, the module will perform packet processing on the spliced data frame, and distribute it to different end nodes according to the destination port number.

[0051] S300, the asynchronous clock arbitration module, performs asynchronous arbitration on two recombined data frames of each packet recombination module to distinguish the first sent and the second sent recombined data frames to obtain an arbitration result; and sends the arbitration result to the multi-channel balanced shunting module.

[0052] The asynchronous clock arbitration module performs asynchronous arbitration on two recombined data frames of each packet recombination module to distinguish the first sent and the second sent recombined data frames to obtain an arbitration result, and stores the recombined data frame output by the arbitration module in the corresponding FIFO according to the arbitration result, and sends the arbitration result to the multi-channel balanced shunting module.

[0053] It's important to note that the synchronous arbitration module uses a 200M user clock frequency. The crossbar arbitration module retrieves data from the crossbar nodes and sends it to the channel balancing and distribution module. For a 10x10 crossbar switch architecture, the synchronous arbitration module retrieves data from a column of 10 crossbar nodes. Because arbitration uses fair round-robin, the maximum processing speed achieved by each node is the maximum processing rate of the arbitration module divided by 10, i.e., P / 10 = 76 / 10 = 7.6 Gb / s.

[0054] The asynchronous arbitration module uses a cross-chip clock frequency of 390 MHz. To increase the processing rate of each node, the present invention uses an asynchronous clock arbitration module to change the data fetch clock frequency of the crossbar cross-chip switch node FIFO to 390 MHz, while the data storage clock of the crossbar cross-chip switch node FIFO remains at the user clock frequency of 200 MHz. At this point, the asynchronous clock arbitration module achieves a maximum processing rate of P = 390 MHz * 384 = 150 Gb / s, and an average rate of P / 10 = 15 Gb / s per node, improving cross-chip data processing efficiency.

[0055] S400, the multi-channel balancing and distribution module distributes all reassembled data frames evenly to each cross-chip channel in a pipeline manner, and sends the reassembled data frames to other FPGAs through the corresponding cross-chip channels; and receives the reassembled data frames sent by other FPGAs through the cross-chip channels;

[0056] Among them, the channel balancing and diversion module includes 4 channel arbitration modules. When at least one of the 4 FIFOs has data, the 4 channel arbitration modules use a pipeline method to take data from the FIFO and evenly distribute it to the corresponding cross-chip channels in the order from the first to the last FIFO with data.

[0057] The channel balancing and traffic distribution module works by evenly distributing traffic from a crossbar bus across n crossbar channels when the FPGA is acting as the transmitter, achieving load balancing. The receiver retrieves data frames from the n crossbar channels and aggregates them onto the source crossbar bus based on the source bus information in the frame's TAG header field.

[0058] The data frames from the asynchronous clock arbitration module enter the traffic aggregation module for aggregation. After the aggregation is completed, the data is sent to the channel balancing and distribution module. Through channel arbitration, the frames are sent to the four channels in sequence, that is, a frame is sent to channel 1 first, and then to channels 2, 3 and 4 in sequence, and then the cycle is repeated to achieve the purpose of balancing the data traffic of each cross-chip channel. Figure 7 shown.

[0059] In an alternative embodiment of the present application, the four channel arbitration modules take data from the FIFOs in a pipelined manner and send the data to the corresponding cross-chip channels in an equal manner, including:

[0060] The four channel arbitration modules select the FIFO corresponding to the channel arbitration module from the FIFOs in the order of the first to the fourth;

[0061] Each channel arbitration module takes data frames from the FIFOs in a pipelined manner, and the time at which the different channel arbitration modules start the same stage of the pipeline is different.

[0062] The four channel arbitration modules of the present application take data frames from the FIFOs in a pipelined manner, including: first stage pipeline start: the first stage pipeline takes one frame of data from the FIFO corresponding to the channel arbitration module and sends the data to the first cross-chip channel; second stage pipeline start: according to whether the FIFO corresponding to the channel arbitration module is empty, one frame of data is continuously taken from the FIFO or an idle frame is sent to the second cross-chip channel; third stage pipeline start: according to whether the FIFO corresponding to the channel arbitration module is empty, one frame of data is continuously taken from the FIFO or an idle frame is sent to the third cross-chip channel; fourth stage pipeline start: according to whether the FIFO corresponding to the channel arbitration module is empty, one frame of data is continuously taken from the FIFO or an idle frame is sent to the fourth cross-chip channel.

[0063] In Figure 8 , the present application instantiates four FIFOs for storing data from different buses, and the channel arbitration module of channel 1 can take the FIFOs of cross-chip buses 1-4. In order for the channel arbitration module of the receiving end of another chip to know the source bus of the data and correctly distribute the data frames, each FIFO needs to modify the TAG field of the data frame before storing the data, which is used to identify the bus from which the frame comes. This field is 2 bits, 2'b00 represents bus 1, 2'b01 represents bus 2, 2'b10 represents bus 3, and 2'b11 represents bus 4.

[0064] In order to improve the distribution speed of the module, a channel pipelined arbitration based on a pipelined architecture is adopted, i.e. multiple stages of channel arbitration can be performed simultaneously. The channel arbitration of the sending channel is as shown in Figure 9 .

[0065] When at least one of the four FIFOs has data, the flow arbitration module is started, that is, the first stage of flow is started, the channel 1 arbitration module arbitrates the fair polling of the first FIFO having data, takes out a frame and sends it to the cross-chip channel 1. After the stage of flow is finished, the second stage of flow is started, a frame is still taken out from the FIFO and sent to the cross-chip channel 2, if the FIFO is empty at this time, an idle frame is sent to the cross-chip channel 2. After the stage of flow is finished, the third stage of flow is started, a frame is still taken out from the FIFO and sent to the cross-chip channel 3, if the FIFO is empty at this time, an idle frame is sent to the cross-chip channel 3. After the stage of flow is finished, the fourth stage of flow is started, a frame is still taken out from the FIFO and sent to the cross-chip channel 4, if the FIFO is empty at this time, an idle frame is sent to the cross-chip channel 4. Since the flow pipeline architecture is used, when a stage of flow is idle, it can be started immediately, and the flow pipeline architecture can meet the full theoretical rate of 76 Gb / s of four or N cross-chip channels during the traffic peak period. Compared with the arbitration module of the non-flow pipeline architecture (the rate of each channel is 76 / N Gb / s, N is the number of cross-chip channels), it is N times higher.

[0066] If the FPGA is a receiving end, the multi-channel equalization and distribution module is responsible for converging the received cross-chip traffic and sending it to the multi-channel traffic convergence module.

[0067] S500, the multi-channel traffic convergence module converges data from the received reorganized data frames by using a pipeline mode, and then sends the data into corresponding packet reorganization modules;

[0068] The FPGA is a receiving end, receives data frames from another FPGA, converges the data frames into corresponding FIFOs according to cross-chip channels, and then distributes the data frames to different cross-chip buses according to the source bus numbers in the TAG headers of the data frames, as shown in the figure. Figure 10

[0069] In an optional embodiment of the present application, the multi-channel traffic convergence module is used for:

[0070] starting the first stage of flow, determining the frame header of the first data frame of the first cross-chip channel from the received reorganized data frames, taking out the frame header information converging to the corresponding cross-chip bus from the frame header, and converging the first data frame of the first cross-chip channel to the corresponding cross-chip bus according to the frame header information;

[0071] starting the second stage of flow, converging the first data frame of the second cross-chip channel to the corresponding cross-chip bus according to the frame header information of the first stage of flow;

[0072] starting the third stage of flow, converging the first data frame of the third cross-chip channel to the corresponding cross-chip bus according to the frame header information of the first stage of flow; ​

[0073] Start the fourth stage of pipelining: according to the frame header information of the first stage of pipelining, the first data frame of the fourth crossbar channel is converged to the corresponding crossbar bus.

[0074] The working mode of the receiving channel equalization module is:

[0075] If the four FIFOs all have data, the source bus number in the TAG of the data of the first FIFO is judged, and the frame is taken out and sent to the corresponding bus. Assuming that the bus is bus 1, the first stage of pipelining is started, and the first frame of the crossbar channel 1 data convergence FIFO is taken out and sent to bus 1; after the first stage of pipelining is finished, the second stage of pipelining is started, and the second stage of pipelining. The first frame of the crossbar channel 2 data convergence FIFO is taken out and sent to bus 1; after the second stage of pipelining is finished, the third stage of pipelining is started, and the third stage of pipelining. The first frame of the crossbar channel 3 data convergence FIFO is taken out and sent to bus 1; after the third stage of pipelining is finished, the fourth stage of pipelining is started, and the fourth stage of pipelining. The first frame of the crossbar channel 4 data convergence FIFO is taken out and sent to bus 1. (Because the sending end sends one frame to each of the four crossbar channels, the first frames of the four crossbar channel data convergence FIFOs of the receiving end must go to the same crossbar bus)

[0076] The difference between the sending channel and the receiving channel is that the sending channel performs pipelining arbitration according to the crossbar channel, and the pipelining arbitration of the receiving channel is performed according to the crossbar bus. The bus pipelining arbitration process of the receiving channel is as shown in Figure 11 .

[0077] The data frames output from the four-way crossbar channel enter the traffic convergence module for convergence. The traffic convergence module converges according to the crossbar bus respectively. After convergence, the sending data stream is evenly divided into n crossbar channels through the channel arbitration module. The traffic convergence module converges according to the crossbar channel respectively. After convergence, the source bus number in the TAG header of the receiving data stream is divided into the corresponding crossbar bus through the bus arbitration module of the crossbar.

[0078] S600, each packet reassembly module, the converged data frame is reassembled and distributed to the corresponding switching node.

[0079] In a specific embodiment of the application, each cross-chip channel is provided with a flow control module, a FIFO water line monitoring module and an NFC flow control frame group module; the FIFO water line monitoring module monitors the flow of data frames received by itself, and if the flow exceeds the capacity of itself, the FIFO water line monitoring module feeds back to the NFC flow control frame group module; after receiving the feedback, the NFC flow control frame group module generates an NFC flow control frame and feeds it back to the flow control module of the FPGA sending the data frame; the flow control module of the FPGA sending the data frame controls the flow of the data frame sent by itself.

[0080] The lossless flow control module is integrated in the cross-chip channel, and the NFC flow control function is used to dynamically adjust the size of the sending end flow, so as to achieve the purpose of lossless flow control of data. The architecture is shown in Figure 12 The lossless control flow of two pieces of data frame is shown in Figure 13 When any one of the FIFOs of the receiving end flow convergence module reaches the water line (depth 512, water line value 317, and 2-3 giant frame lengths are reserved), the FIFO water line monitoring module of the receiving end convergence module sends a framing signal to the NFC flow control frame group framing module, the NFC flow control frame group framing module groups a flow control start frame according to the flow control information given by the FIFO water line monitoring module of the receiving end convergence module, the flow control start frame goes to the sending end of the other FPGA through the cross-chip channel, and the sending end pauses the flow sending of the congested cross-chip channel according to the information in the NFC flow control frame. When the FIFO of the receiving end reaching the water line decreases below the water line, the FIFO water line monitoring module of the receiving end convergence module sends a framing signal to the NFC flow control frame group framing module, the NFC flow control frame group framing module groups a flow control stop frame according to the flow control information given by the FIFO water line monitoring module of the receiving end convergence module, the flow control stop frame goes to the sending end of the other FPGA through the cross-chip channel, and the sending end starts the flow sending of the corresponding cross-chip channel according to the information in the NFC flow control frame. Through the inter-chip lossless flow control module, the size of the inter-chip cross-chip flow load is dynamically adjusted, and the lossless transmission of the inter-chip multi-cross-chip channel is realized.

[0081] The application provides a method for load balancing and acceleration of multiple cross-chip channels of a lossless switch, comprising: a crossbar node flow distribution module distributes data to nodes based on a source port mode; each packet reassembly module reassembles data in a predetermined byte interval; an asynchronous clock arbitration module performs asynchronous arbitration on the reassembled data frames; a multi-channel balanced distribution module distributes the reassembled data frames to each cross-chip channel in a pipeline mode, and receives reassembled data frames of other FPGAs; a multi-channel flow convergence module converges the data frames in a pipeline mode; and each packet reassembly module disassembles and distributes the converged data frames to corresponding switching nodes. The application can effectively improve the data transmission efficiency and performance of the cross-chip channel, ensure efficient and balanced flow of data between different FPGAs, and thus improve the stability and reliability of the entire communication network.

[0082] Referring to Figure 1 In practical application, the present application adopts 12*12 crossbar architecture, in which 8 rows and 8 columns are used for data frame switching in the switch chip, and 4 rows and 4 columns are used for cross-chip traffic switching, i.e. 4 cross-chip channels are adopted, and data flow crosses from FPGA1 to FPGA2.

[0083] Referring to Figure 2 When cross-chip traffic needs to enter the crossbar architecture, it will first enter the crossbar node traffic distribution module. This module distributes traffic according to the source port number to improve the arbitration speed of cross-chip bus traffic, which will be described in detail in Figure 6 When the crossbar cross-chip switching node has data, the asynchronous clock arbitration module will make the node output data, but at this time the data will not go directly to the asynchronous clock arbitration module, but will first go to the packet reassembly module (each vertical column of cross-chip switching node corresponds to an asynchronous clock arbitration module). In the packet reassembly module, multiple short data packets are reassembled into a compromised length (1518-3000 bytes), and the long frame after reassembly enters the asynchronous clock arbitration module, and then goes to the multi-channel balanced distribution module.

[0084] The packet reassembly module is to solve the problem that short frames seriously affect the cross-chip switching rate during the cross-chip process. The combination method is described in detail in Figure 6 The asynchronous clock arbitration module is to improve the processing rate of each node. The influence of the two on the cross-chip rate and the acceleration efficiency is referred to formula 1.

[0085] Referring to Figure 7 When the data flow from the asynchronous clock arbitration module enters the multi-channel balanced distribution module, the module will equally distribute the data traffic of each bus to the 4 cross-chip channels to achieve the purpose of load balancing.

[0086] Referring to Figure 8When the traffic enters the sending channel equalization module, the traffic of each bus is stored in the corresponding FIFO for buffering. Assuming that the cross-chip bus 1 data aggregation FIFO has data at this time, the pipeline is started, and at this time, the first stage of the pipeline, i.e., the channel 1 arbitration, arbitrates to the above FIFO, and the first frame is taken out from the FIFO. After the first stage of the pipeline ends, the second stage of the pipeline, i.e., the channel 2 arbitration, still arbitrates to the above FIFO, and the second frame is taken out from the FIFO. After the second stage of the pipeline ends, the third stage of the pipeline, i.e., the channel 3 arbitration, still arbitrates to the above FIFO, and the third frame is taken out from the FIFO. After the third stage of the pipeline ends, the fourth stage of the pipeline, i.e., the channel 4 arbitration, still arbitrates to the above FIFO, and the fourth frame is taken out from the FIFO. The different stages of the pipeline are independent of each other, and the current stage of the pipeline is idle to start. The purpose of this is that, in the traditional non-pipelined arbitration, only the data in a certain FIFO can be given to a certain cross-chip channel at the same time, and after the transmission ends, another frame of data in the FIFO can be given to another cross-chip channel, i.e., only one of the four channels can transmit data at the same time, and the efficiency is extremely low. The pipelined arbitration can enable the four channels to transmit data at the same time, and there is no frame reordering problem. The channel pipelining process of the sending channel is described in detail in Figure 8 .

[0087] When the data frame is arbitrated out of the channel, it enters the cross-chip channel and is transmitted to the cross-chip receiving channel of another FPGA through the existing Aurora IP core cross-chip.

[0088] Details are shown in Figure 10 After the cross-chip channel receives the cross-chip data frame, it enters the traffic aggregation module for aggregation, and the data of each cross-chip channel is buffered in the corresponding cross-chip channel data aggregation FIFO. When there is at least one frame in the four FIFOs, the bus arbitration module starts the pipelining. When the first stage of the pipelining is started, the source bus information in the first frame TAG header field of the cross-chip channel 1 data aggregation FIFO is judged. If it is a data frame going to bus 1, a frame is taken out from the cross-chip channel 1 data aggregation FIFO and sent to bus 1, and then the second, third, and fourth stages of the pipelining are started, and a frame is taken out from the cross-chip channel 2, 3, and 4 data aggregation FIFO and sent to bus 1.

[0089] Details are shown in Figure 11 In order to improve the receiving efficiency, the receiving end also uses the pipelining architecture. When there is data in the four FIFOs, the TAG header of the first frame of the FIFO of channel 1 is used to judge the bus number to which the first frames of the FIFOs of channels 1-4 go. That is, when the four FIFOs have data, the pipelining is started, the first stage of the pipelining takes the first frame from the FIFO area of channel 1, judges the destination bus number of the frame at the same time, and sends the frame to the bus. The second, third, and fourth stages of the pipelining take one frame from the FIFOs of channels 2, 3, and 4 respectively, and aggregate the frames to the bus.

[0090] Details are shown inFigure 12 When the data frame is cross-chipped, the sending end cannot sense whether the load of the receiving end exceeds the receiving capability of the receiving end, if the receiving end is congested, the sending end still sends the data frame, which will cause the loss of the data frame. In order to perform lossless exchange of cross-chipping, the application adds a lossless flow control module, which dynamically adjusts the flow size of the sending end by using the NFC flow control function, so as to achieve the flow control purpose of data lossless. The flow control principle is that the receiving end aggregation module FIFO water line monitoring module will monitor the four FIFOs in the receiving end flow aggregation module, when the receiving channel FIFO is full, the NFC flow control frame framing module will be enabled, and the flow control start frame will be sent to the sending end, the corresponding sending channel of the sending end is enabled, and the data frame transmission is stopped. When the FIFO can receive, the receiving end aggregation module FIFO water line monitoring module will enable the NFC flow control frame framing module, and send the flow control stop frame to the sending end, so as to start the corresponding sending channel of the sending end, so as to achieve the purpose of lossless. The detailed control process is shown in Figure 13 .

[0091] It should be noted that the terms "first", "second" in the present application are only used for description purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0092] Although the present application is described herein in conjunction with various embodiments, other variations of the disclosed embodiments can be understood and implemented by those skilled in the art with reference to the drawings, the disclosure, and the appended claims in the process of implementing the claimed present application. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude a plurality.

[0093] The above is a further detailed description of the present application in conjunction with specific preferred embodiments, and cannot be considered as limiting the specific implementation of the present application to these descriptions. For those skilled in the art to which the present application belongs, without departing from the concept of the present application, a number of simple deductions or replacements can be made, which should be considered as belonging to the protection scope of the present application.

Claims

1. A method for load balancing and accelerating multiple cross-chip channels of a lossless switch, characterized in that: Applied to each FPGA, the FPGA includes a crossbar node traffic distribution module, an n-packet reassembly module, an asynchronous clock arbitration module, a multi-channel balancing and distribution module, a multi-channel traffic aggregation module, and a switching node. The method for load balancing and accelerating multiple cross-chip channels of a lossless switch includes: A crossbar node traffic distribution module distributes data frames to the two switch nodes in each column of the switch nodes based on the source port, and sends the data frames of the two switch nodes to the corresponding packet reassembly module; Each packet reassembly module reassembles the input data frame according to the predetermined byte interval to obtain two reassembled data frames and sends them to the asynchronous clock arbitration module; The asynchronous clock arbitration module performs asynchronous arbitration on the two reassembled data frames of each packet reassembly module to distinguish the reassembled data frames sent first and last to obtain an arbitration result; and sends the arbitration result to the multi-channel balancing and diversion module; the asynchronous clock arbitration module performs asynchronous arbitration on the two reassembled data frames of each packet reassembly module to distinguish the reassembled data frames sent first and last to obtain an arbitration result, and stores the reassembled data frames output by the arbitration module in the corresponding FIFO according to the arbitration result and sends the arbitration result to the multi-channel balancing and diversion module; The multi-channel balancing and distribution module uses a pipeline method to evenly distribute all reassembled data frames to each cross-chip channel, and sends them to other FPGAs through the corresponding cross-chip channels; and receives the reassembled data frames sent by other FPGAs through the cross-chip channels; The multi-channel traffic aggregation module selects data from the received reassembled data frames in a pipeline mode for aggregation, and then sends them to the corresponding packet reassembly module; Each packet reassembly module decompresses and reassembles the aggregated data frames and distributes them to the corresponding switching nodes; Each cross-chip channel is equipped with a flow control module, a FIFO waterline monitoring module, and an NFC flow control frame group module; The FIFO waterline monitoring module monitors the flow of data frames received by itself, and if it exceeds its own capacity, it feeds back to the NFC flow control frame group module; After receiving the feedback, the NFC flow control frame group module generates an NFC flow control frame and feeds it back to the flow control module of the FPGA that sends the data frame; The flow control module of the FPGA that sends the data frames controls the flow of the data frames sent by itself.

2. The method for load balancing and accelerating multiple cross-chip channels of a lossless switch according to claim 1, characterized in that: The switching nodes include common switching nodes and cross-chip switching nodes; The crossbar node traffic distribution module distributes data frames to the two cross-chip switching nodes in each column of the switching nodes based on the source port, and sends the data frames of the two cross-chip switching nodes to the corresponding packet reassembly module; wherein the cross-chip switching nodes are divided into four columns, and the number of cross-chip switching nodes allocated data frames in each column based on the source port is the same.

3. The method for load balancing and accelerating multiple cross-chip channels of a lossless switch according to claim 1, characterized in that: Each packet reassembly module reassembles the short data frames into long data frames according to the range of 1518-3000 bytes, obtains two reassembled data frames, and sends them to the asynchronous clock arbitration module; among them, the short data frame is a data frame with less than 1518 bytes, and the long data frame is a data frame with more than 1518 bytes.

4. The method for load balancing and accelerating multiple cross-chip channels of a lossless switch according to claim 1, characterized in that: The number of columns of the cross-chip switching node is 4; the number of the packet reassembly module, the cross-chip channel and the FIFO is 4.

5. The method for load balancing and accelerating multiple cross-chip channels of a lossless switch according to claim 4, characterized in that: The channel balancing and diversion module includes four channel arbitration modules. When at least one of the four FIFOs has data, the four channel arbitration modules use a pipeline method to take data from the FIFOs and evenly distribute it to the corresponding cross-chip channels in the order from the first to the last FIFO with data.

6. The method for load balancing and accelerating multiple cross-chip channels of a lossless switch according to claim 5, characterized in that: The four channel arbitration modules use a pipelined approach to take data from the FIFOs and evenly distribute the data to the corresponding cross-chip channels in the order of the first to the last FIFO with data, including: In the order of 1 to 4, the 4 channel arbitration modules select their corresponding FIFO from the FIFO with data; Each channel arbitration module takes data frames from the FIFO in a pipeline manner, and different channel arbitration modules start the same level of pipeline at different times.

7. The method for load balancing and accelerating multiple cross-chip channels of a lossless switch according to claim 5, characterized in that: The pipeline method of taking data frames from FIFO includes: First-stage pipeline start: The first-stage pipeline takes out one frame of data from its corresponding FIFO and sends it to the first cross-chip channel; Second-stage pipeline start: Depending on whether the corresponding FIFO is empty, it continues to take out a frame of data from the FIFO or sends an idle frame to the second cross-chip channel; The third-level pipeline starts: Depending on whether the corresponding FIFO is empty, it continues to take out a frame of data from the FIFO or sends an idle frame to the third cross-chip channel; The fourth-level pipeline starts: depending on whether the corresponding FIFO is empty, it continues to take out a frame of data from the FIFO or sends an idle frame to the fourth cross-chip channel.

8. The method for load balancing and accelerating multiple cross-chip channels of a lossless switch according to claim 1, characterized in that: The multi-channel traffic convergence module is used to: Start the first stage of the pipeline: determine the frame header of the first data frame of the first cross-chip channel from the received reassembled data frame, and extract the frame header information from the frame header to be aggregated to the corresponding cross-chip bus; According to the frame header information, the first data frame of the first cross-chip channel is aggregated to the corresponding cross-chip bus; Start the second-level pipeline: according to the frame header information of the first-level pipeline, aggregate the first data frame of the second cross-chip channel to the corresponding cross-chip bus; Start the third-level pipeline: according to the frame header information of the first-level pipeline, aggregate the first data frame of the third cross-chip channel to the corresponding cross-chip bus; Start the fourth-level pipeline: according to the frame header information of the first-level pipeline, aggregate the first data frame of the fourth cross-chip channel to the corresponding cross-chip bus.

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