Time sequence description method for IO parallel port output control time sequence
By describing the timing of the IO parallel port output as a clock signal and level signal, and independently describing the characteristics of each IO port signal, the problems of low timing generation efficiency and insufficient universality in the prior art are solved, and more efficient and flexible timing description and generation are achieved.
Patent Information
- Application Number
- CN202311349099.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-18
- Publication Date
- 2025-04-18
AI Technical Summary
When the prior art generates complex timing, programming methods are inefficient, unable to meet diverse generality requirements, and lack the ability to respond to timing changes.
A general timing description method for controlling timing of IO parallel port output is proposed. By dividing the signal into a clock signal and a level signal, independently describing the characteristics of each IO port signal, and combining it to generate a parallel port IO signal, store it in memory, and then reading from memory by the IO port and output the expected timing.
It improves the versatility and development efficiency of timing description, is suitable for most control timing description needs, can flexibly respond to timing changes, and enhances the adaptability and flexibility of the system.
Smart Images
Figure CN119854420A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of peripheral control, and in particular relates to a timing description method for an IO parallel port output control timing. Background Art
[0002] In the peripherals of the prior art, the working principle of the CIS scanner is as follows:
[0003] 1. The photosensitive element on the CIS image sensor device outputs analog power according to the light intensity;
[0004] 2. ADC converts the input analog signal into a digital signal; analog shifting is performed until all the linearly arranged signals on the image sensor are collected, and this direction is opposite to the main scan;
[0005] 3. The scanning control system controls the image sensor device to move to the next scanning line position in the vertical direction (this direction is the sub-scanning direction), and repeats operations 1-2;
[0006] 4. Repeat this process until all the contents on the scanned medium are input;
[0007] 5. The above is completed by the scanning control module, and some data storage, image processing, transmission and other tasks are completed by other modules of the CPU. Figure 1 shown.
[0008] Currently, most common scanner controllers are dedicated printer control chips, such as Qbit's QB63xx. Such dedicated chips have a dedicated timing generation interface to generate timing for the control timing of CIS and AFE. Or the scanning device control is realized in the form of FPGA / MCU+host computer. The control interface connection diagram of CIS and AFE is as follows: Figure 2 As shown, D0-D5 are the serial timing IO ports of ClockGen, and each IO port independently outputs the required timing waveform.
[0009] For the CIS, AFE, etc. mentioned in the above scanning devices, many specific peripherals require specific timing drives to complete various scanning tasks. The methods for outputting the specific timing include: using a dedicated control chip for the specific peripheral environment, or using a general IO port to simulate the required timing through programming.
[0010] Generally, the programming simulation timing is to generate the required timing into the memory, and the IO parallel port output timing is to read the preset content from the memory to the IO port address. Data 0 and 1 correspond to the low level and high level of the parallel port output IO port respectively.
[0011] In the prior art, the most direct method for generating timing in memory is to directly write a program according to the timing content and generate the required timing through a loop. However, this method is not practical for more complex timing transformations. A slight timing change may cause an overall change in the program code, making it impossible to meet more universal requirements and having low development efficiency.
[0012] In addition, commonly used technical terms include:
[0013] Parallel port: A parallel interface that can have N IO ports; n being 8 means there are 8 IO pin ports that can output 8 timing signals in parallel.
[0014] CIS: (Contact image sensor) Contact image sensor. Converts light signals into electrical signals.
[0015] ADC: Analog-to-digital converter, used to convert analog signals into digital signals. Summary of the invention
[0016] In order to solve the above problems, the purpose of this application is to propose a universal control timing description method for the IO parallel port analog output timing problem, which divides the signal into two categories: clock signal and level signal; independently describes the characteristics of each IO port signal, and combines each IO port signal together to generate a parallel port IO signal and save it to the memory; the IO port reads and outputs the expected timing from the memory.
[0017] Specifically, the present invention provides a timing description method for IO parallel port output control timing. The method performs a general control timing description by abstracting signal characteristics according to the functional requirements of using IO port output timing. The method divides the timing into: clock signals: mclk, scaaclk, cdsclk, and the structure describing the clock type signal is named clockDesc; and level signals: TE, R LED, GLED, BLED, and the structure describing the level type signal is named levelDesc;
[0018] Use clockDesc or levelDesc to describe each of the above IO port signals separately, and generate IO parallel port timing data based on the independent description of each IO port.
[0019] The method further comprises:
[0020] S1, describes the signal type:
[0021] S1.1, describe the clock type signal:
[0022] a) Signal characteristics: a periodic clock signal, with M 0s and 1s forming one cycle;
[0023] b) Signal description:
[0024] i.cycle[M]: a description of a clock signal cycle, described by M 0s or 1s;
[0025] ii.init_level: initial level, the level of the IO port before the timing starts;
[0026] iii.idle_level: end level, the level that the IO port maintains after the timing ends;
[0027] iv.start_pos: the starting position of the timing, counted in cycles;
[0028] v.cycle_cnt: the number of cycles of the clock signal;
[0029] S1.2, describes the level type signal:
[0030] a) Signal characteristics: continuous level signal, which flips after the cycle_cnt clock cycle;
[0031] b) Signal description:
[0032] i.init_level: initial IO port starting level signal;
[0033] ii.idle_level: end IO port output signal;
[0034] iii.inverts: the number of times the level signal is reversed;
[0035] iv.cycle_cnt[X]: the number of cycles during each level holding period;
[0036] S2, for the IO parallel port simulation control timing, use the description method of step S1, independently describe the timing characteristics of each IO port, and then combine and generate actual timing data based on the description of each IO port and store it in the memory.
[0037] In step b) of step S1.1, assume that M=5, cycle={1,1,0,0,0} describes a periodic signal, and assume that a tick cycle represents a 0 / or 1, 1 represents a high level, and 0 represents a low level; describe a clock signal, assume init_level=0, idle_level=1, start_pos=1, cycle_cnt=N, cycle[5]={1,1,0,0,0}.
[0038] In step b) of step S1.2, assume init_level=1, idle_level=0, inverts=5, then in the variable cycle_cnt[X] describing the level duration period, X=5, cycle_cnt[0]=5, cycle_cnt[1]=11, cycle_cnt[2]=1, cycle_cnt[3]=2, cycle_cnt[4]=5.
[0039] The step S1 further comprises: individually describing each control signal of the scanning device:
[0040] Cdsclk, corresponding to D0 of the parallel port:
[0041] {init_level=0, idle_level=0, start_pos=0, cycle_cnts=2592, cycle[5]={1,1,1,0,0}};
[0042] Scaaclk, corresponding to D1 of the parallel port:
[0043] {init_level=0, idle_level=0, start_pos=0, cycle_cnt=2592, cycle[5]={0,1,1,0,0}};
[0044] Mclk, corresponding to D2 of the parallel port:
[0045] {init_level=0, idle_level=0, start_pos=1, cycle_cnt=2592, cycle[5]={1,1,0,0,0}};
[0046] Rled, corresponding to D3 of the parallel port:
[0047] {init_level=0, idle_level=0, invert=2, cycle_cnt={80,250}};
[0048] Gled, corresponding to D4 of the parallel port:
[0049] {init_level=0, idle_level=0, invert=2, cycle_cnt={330,250}};
[0050] Bled, corresponding to D5 of the parallel port:
[0051] {init_level=0, idle_level=0, invert=2, cycle_cnt={580,250}};
[0052] TE, corresponding to D6 of the parallel port:
[0053] {init_level=0, idle_level=0, invert=2, cycle_cnt={8,2580}}.
[0054] The step S2 further comprises:
[0055] The seven control signal descriptions in step S1 are combined to generate data output by the IO parallel port;
[0056] Specifically for each bit of an 8-bit data, according to the description of step S1, in the starting cycle, each pin outputs 1, 0, 0, 0, 0, 0, 0 from D0-D6 respectively, corresponding to an 8-bit parallel port data bit 0B0000001; the specific process is as follows:
[0057] S2.1, describe all IO ports Ports according to the timing characteristics, the upper limit of the Ports is the number of actually available IO ports (0,32], and each IO port is ClockDesc or LevelDesc;
[0058] S2.2, apply for memory space *dest[M] to store the timing;
[0059] S2.3, determine whether to loop? That is, loop p from 0 to Ports, the pth loop will fill the pth bit of all dest, when p loops to ports, the loop ends, jump out of the loop; if the loop ends, then end; if it enters the loop, then
[0060] The pth bit starts from 0 and loops through Ports, expressed as:
[0061] for p:0to Ports;
[0062] S2.4, determine whether it is clock timing?
[0063] If yes, proceed to step S2.5; if no, proceed to step S2.8;
[0064] S2.5, fill start_pos init_level to the pth bit of dest[0...M], fill the pth bit, that is, fill the pth bit of the M numbers of dest[0]...dest[M]. The start_ports is the start_pos defined in clockDesc, which is an integer in the range of [1,0xffffffff], indicating the number of cycles of init_level.
[0065] S2.6, fill N cycle_cnt[0......M] to the pth bit of dest[0......M], where N is in the range of [1,0xffffffff];
[0066] S2.7, fill the remaining idle_level to the pth position of dest; return to step S2.3;
[0067] S2.8 is the level sequence, level level = init_level;
[0068] S2.9, determine whether to enter the loop? That is, if the i-th bit is from 0 to inverts, then enter the loop, otherwise the loop ends, expressed as, for i: 0 to inverts, where inverts is the inverts defined in levelDesc, which is an integer, and its value is the number of cycle_cnt arrays in levelDesc, which can theoretically be any 32-bit integer range; if entering the loop, proceed to step S2.10, if the loop ends, return to step S2.3;
[0069] S2.10, fill cycle_cnt[i] levels to the pth bit of dest[0......M];
[0070] S2.11, flip level, level^=1, that is, if level is 0, it will be 1 after flipping, if level is 1, it will be 0 after flipping, and return to step S2.9.
[0071] Therefore, the advantage of the present application is that the present application proposes a general description method for control timing. The present method is not targeted at a specific timing, but describes two main types of signals: clock signals and level signals, which greatly improves the versatility of timing description and is applicable to most control timing descriptions. The timing description method of the present application is universal and easy to use. BRIEF DESCRIPTION OF THE DRAWINGS
[0072] The drawings described herein are used to provide a further understanding of the present invention, constitute a part of this application, and do not constitute a limitation of the present invention.
[0073] Figure 1 It is a schematic diagram of the composition of an existing CIS scanner.
[0074] Figure 2 It is a schematic diagram of the control interface connection between the existing CIS and AFE.
[0075] Figure 3 is a schematic diagram describing a clock signal cycle in an embodiment.
[0076] Figure 4 It is a schematic diagram describing a clock signal embodiment in the embodiments.
[0077] Figure 5 It is a schematic diagram of defining the level signal description levelDesc in the embodiment.
[0078] Figure 6 is a schematic diagram of the process of this method.
[0079] Figure 7 It is a schematic diagram of a specific process of merging and generating data output by an IO parallel port in an embodiment. DETAILED DESCRIPTION
[0080] In order to more clearly understand the technical content and advantages of the present invention, the present invention is now further described in detail in conjunction with the accompanying drawings.
[0081] This application is based on the Ingenic X2 series chip of Beijing Ingenic Integrated Circuit Co., Ltd. (hereinafter referred to as Ingenic). As a general-purpose processor, there is no dedicated serial timing generation interface on it. Therefore, a parallel IO interface is used, such as the IO parallel port of the SLCD controller, or the IO parallel port of the local bus to output the control timing of the CIS and AFE. By describing the characteristics of the timing of each interface of the CIS / AFE, parallel data is generated and output from the IO parallel port.
[0082] Generally, the analog timing is to generate the required timing into the memory, and the IO parallel port output timing is to read the preset content from the memory to the IO port address. Data 0 and 1 correspond to the low level and high level of the parallel port output IO port respectively. Because it is a parallel port output, an integer (int) data describes the timing value of a clock of all interfaces. For example, a data 0B110100 represents the output of the six interfaces D0-D5 at the same time, that is, each bit of 0B110100 corresponds to the IO port of ClockGen {D5, D4, D3, D2, D1, D0} respectively.
[0083] This method describes the timing characteristics and dynamically generates specific timing to memory based on the description. This application proposes a timing description method for analog timing based on the timing requirements of scan control, generates and stores all the timings to be output to memory, and then outputs them from memory to the IO port.
[0084] This application proposes a timing description method for IO parallel port output control timing, that is, according to the functional requirements of using IO port output timing, a general control timing description method is proposed by abstracting signal characteristics; Figure 2 For the control needs of the scanning device, the timing is divided into clock signals: mclk, scaaclk, cdsclk, and the structure describing the clock signal is named clockDesc; and level signals: TE, R LED, GLED, BLED, and the structure describing the level signal is named levelDesc;
[0085] Use clockDesc or levelDesc to describe each of the above IO port signals separately, and generate IO parallel port timing data based on the independent description of each IO port.
[0086] like Figure 6 As shown, the method includes:
[0087] S1, describes the signal type:
[0088] S1.1, describe the clock type signal:
[0089] a) Signal characteristics: a periodic clock signal, with M 0s and 1s forming one cycle;
[0090] b) Signal description:
[0091] i.cycle[M]: Description of a clock signal cycle. Described by M 0s or 1s. Figure 3 As shown in the figure, M=5, cycle={1,1,0,0,0} describes a periodic signal. In the figure, a tick cycle represents a 0 / or 1, 1 represents a high level, and 0 represents a low level. The cycle is flexibly defined according to the actual situation. Figure 4 As shown in the figure, a clock signal is described, assuming init_level = 0, idle_level = 1, start_pos = 1, cycle_cnt = N, cycle[5] = {1, 1, 0, 0, 0}.
[0092] ii.init_level: initial level, the level of the IO port before the timing starts.
[0093] iii.idle_level: end level, the level that the IO port maintains after the timing ends.
[0094] iv.start_pos: The starting position of the timing, counted in cycles.
[0095] v.cycle_cnt: The number of cycles that the clock signal lasts.
[0096] S1.2, describes level type signals: such as TE, RLED, GLED, BLED in scanning device control;
[0097] a) Signal characteristics: continuous level signal, which flips after lasting cycle_cnt clock cycles.
[0098] b) Signal description:
[0099] i.init_level: initial IO port starting level signal.
[0100] ii.idle_level: ends the IO port output signal.
[0101] iii.inverts: The number of times the level signal is reversed.
[0102] iv.cycle_cnt[X]: The number of cycles during each level holding period.
[0103] like Figure 5 As shown, level_desc is defined, where init_level=1, idle_level=0, inverts=5, then the variable cycle_cnt[X] describing the level duration period has X=5, cycle_cnt[0]=5, cycle_cnt[1]=11, cycle_cnt[2]=1, cycle_cnt[3]=2, cycle_cnt[4]=5.
[0104] S2, for the IO parallel port simulation control timing, use the description of the above step S1 to independently describe the timing characteristics of each IO port, and then combine and generate actual timing data based on the description of each IO port and store it in the memory.
[0105] Specifically, using the above method,
[0106] First, in step S1, further, each control signal of the scanning device is described separately:
[0107] Cdsclk, corresponding to D0 of the parallel port
[0108] {init_level=0, idle_level=0, start_pos=0, cycle_cnts=2592, cycle[5]={1,1,1,0,0}}
[0109] Scaaclk, corresponding to D1 of the parallel port:
[0110] {init_level=0, idle_level=0, start_pos=0, cycle_cnt=2592, cycle[5]={0,1,1,0,0}}
[0111] Mclk, corresponding to D2 of the parallel port:
[0112] {init_level=0, idle_level=0, start_pos=1, cycle_cnt=2592, cycle[5]={1,1,0,0,0}}
[0113] Rled, corresponding to D3 of the parallel port:
[0114] {init_level=0,idle_level=0,invert=2,cycle_cnt={80,250}}
[0115] Gled, corresponding to D4 of the parallel port:
[0116] {init_level=0,idle_level=0,invert=2,cycle_cnt={330,250}}
[0117] Bled, corresponding to D5 of the parallel port:
[0118] {init_level=0,idle_level=0,invert=2,cycle_cnt={580,250}}
[0119] TE, corresponding to D6 of the parallel port:
[0120] {init_level=0,idle_level=0,invert=2,cycle_cnt={8,2580}}
[0121] Then in step S2, the above 7 control signal descriptions are combined to generate the data output by the IO parallel port. Specifically, for each bit of an 8-bit data, according to the above description, in the starting cycle, each pin outputs 1, 0, 0, 0, 0, 0, 0 from D0 to D6, corresponding to an 8-bit parallel port data bit 0B0000001;
[0122] The specific process is as follows Figure 7 As shown:
[0123] S2.1, describe all IO ports according to the timing characteristics. For example, if 8 parallel IO ports are used in this application, Ports is 8. The upper limit of Ports is the number of actually available IO parallel ports, usually (0,32], and each IO port is ClockDesc or LevelDesc;
[0124] S2.2, apply for memory space *dest[M] to store the timing;
[0125] S2.3, determine whether to loop? That is, loop p from 0 to Ports, where p is the same as the following p-th bit. The p-th loop will fill all the p-th bits of dest. When p loops to ports, the loop ends and jumps out of the loop; if the loop ends, it ends; if it enters the loop, the p-th bit starts from 0 and loops to Ports, which is expressed as:
[0126] for p:0to Ports;
[0127] S2.4, determine whether it is clock timing?
[0128] If yes, proceed to step S2.5; if no, proceed to step S2.8;
[0129] S2.5, fill start_pos init_level to the pth bit of dest[0...M], where M means filling the pth bit, i.e. filling the pth bit of the M numbers of dest[0]...dest[M]. The start_ports is the start_pos defined in clockDesc, which is an integer in the range of [1,0xffffffff], indicating the number of cycles of init_level.
[0130] S2.6, fill N cycle_cnt[0......M] to the pth bit of dest[0......M], where N is in the range of [1,0xffffffff];
[0131] S2.7, fill the remaining idle_level to the pth position of dest; return to step S2.3;
[0132] S2.8 is the level sequence, level level = init_level;
[0133] S2.9, determine whether to enter a loop? That is, if the i-th bit is from 0 to inverts, then enter the loop, otherwise the loop ends, expressed as, for i: 0 to inverts, where inverts is the inverts defined in levelDesc, which is an integer, and its value is the number of cycle_cnt arrays in levelDesc. Theoretically, this value can be any 32-bit integer range, and the maximum value is defined as 16 in this application; if the loop is entered, proceed to step S2.10, if the loop ends, return to step S2.3;
[0134] S2.10, fill cycle_cnt[i] levels to the pth bit of dest[0......M];
[0135] S2.11, flip level, level^=1, that is, if level is 0, it will be 1 after flipping, if level is 1, it will be 0 after flipping, and return to step S2.9.
[0136] In summary, this method aims at the functional requirement of using IO port output timing, proposes a universal control timing description by abstracting signal characteristics, divides the timing into clock signal and level signal, and describes each IO port signal separately, and generates IO parallel port timing data according to the independent description of each IO port.
[0137] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the embodiments of the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A timing description method for IO parallel port output control timing, characterized in that: The method uses the IO port output timing function to describe the general control timing by abstracting the signal characteristics. The method includes dividing the timing into the following according to the control requirements of the scanning device: Clock signal: mclk, scaaclk, cdsclk, let the structure describing the clock type signal be named clockDesc; and level signal: TE, R LED, GLED, BLED, let the structure describing the level type signal be named levelDesc; Use clockDesc or levelDesc to describe each of the above IO port signals separately, and generate IO parallel port timing data based on the independent description of each IO port.
2. The timing description method of an IO parallel port output control timing according to claim 1, characterized in that: The method further comprises: S1, describes the signal type: S1.1, describe the clock type signal: a) Signal characteristics: a periodic clock signal, with M 0s and 1s forming one cycle; b) Signal description: i.cycle[M]: a description of a clock signal cycle, described by M 0s or 1s; ii.init_level: initial level, the level of the IO port before the timing starts; iii.idle_level: end level, the level that the IO port maintains after the timing ends; iv.start_pos: the starting position of the timing, counted in cycles; v.cycle_cnt: the number of cycles of the clock signal; S1.2, describes the level type signal: a) Signal characteristics: continuous level signal, which flips after the cycle_cnt clock cycle; b) Signal description: i.init_level: initial IO port starting level signal; ii.idle_level: end IO port output signal; iii.inverts: the number of times the level signal is reversed; iv.cycle_cnt[X]: the number of cycles during each level holding period; S2, for the IO parallel port simulation control timing, use the description method of step S1, independently describe the timing characteristics of each IO port, and then combine and generate actual timing data based on the description of each IO port and store it in the memory.
3. The timing description method of an IO parallel port output control timing according to claim 2, characterized in that: In step b) of step S1.1, assume that M=5, cycle={1,1,0,0,0} describes a periodic signal, and assume that a tick cycle represents a 0 / or 1, 1 represents a high level, and 0 represents a low level; describe a clock signal, assume init_level=0, idle_level=1, start_pos=1, cycle_cnt=N, cycle[5]={1,1,0,0,0}.
4. The timing description method of an IO parallel port output control timing according to claim 3, characterized in that: In step b) of step S1.2, assume init_level=1, idle_level=0, inverts=5, then in the variable cycle_cnt[X] describing the level duration period, X=5, cycle_cnt[0]=5, cycle_cnt[1]=11, cycle_cnt[2]=1, cycle_cnt[3]=2, cycle_cnt[4]=5.
5. The timing description method of an IO parallel port output control timing according to claim 4, characterized in that: The step S1 further comprises: individually describing each control signal of the scanning device: Cdsclk, corresponding to D0 of the parallel port: {init_level=0,idle_level=0,start_pos=0,cycle_cnts=2592,cycle[5]={1,1,1,0,0}};·Scaaclk, corresponding to D1 of the parallel port: {init_level=0, idle_level=0, start_pos=0, cycle_cnt=2592, cycle[5]={0,1,1,0,0}}; Mclk, corresponding to D2 of the parallel port: {init_level=0, idle_level=0, start_pos=1, cycle_cnt=2592, cycle[5]={1,1,0,0,0}}; Rled, corresponding to D3 of the parallel port: {init_level=0, idle_level=0, invert=2, cycle_cnt={80,250}}; Gled, corresponding to D4 of the parallel port: {init_level=0, idle_level=0, invert=2, cycle_cnt={330,250}}; Bled, corresponding to D5 of the parallel port: {init_level=0, idle_level=0, invert=2, cycle_cnt={580,250}}; TE, corresponding to D6 of the parallel port: {init_level=0, idle_level=0, invert=2, cycle_cnt={8,2580}}.
6. The timing description method of an IO parallel port output control timing according to claim 5, characterized in that: The step S2 further comprises: The seven control signal descriptions in step S1 are combined to generate data output by the IO parallel port; Specifically for each bit of an 8-bit data, according to the description of step S1, in the starting cycle, each pin outputs 1, 0, 0, 0, 0, 0, 0 from D0-D6 respectively, corresponding to an 8-bit parallel port data bit 0B0000001; the specific process is as follows: S2.1, describe all IO ports Ports according to the timing characteristics, the upper limit of the Ports is the number of actually available IO ports (0,32], and each IO port is ClockDesc or LevelDesc; S2.2, apply for memory space *dest[M] to store the timing; S2.3, determine whether to loop? That is, loop p from 0 to Ports, the pth loop will fill the pth bit of all dest, when p loops to ports, the loop ends, jump out of the loop; if the loop ends, then end; if it enters the loop, then The pth bit starts from 0 and loops through Ports, expressed as: for p:0to Ports; S2.4, determine whether it is clock timing? If yes, proceed to step S2.5; if no, proceed to step S2.8; S2.5, fill start_pos init_level to the pth bit of dest[0...M], fill the pth bit, that is, fill the pth bit of the M numbers of dest[0]...dest[M]. The start_ports is the start_pos defined in clockDesc, which is an integer in the range of [1,0xffffffff], indicating the number of cycles of init_level. S2.6, fill N cycle_cnt[0......M] to the pth bit of dest[0......M], where N is in the range of [1,0xffffffff]; S2.7, fill the remaining idle_level to the pth position of dest; return to step S2.3; S2.8 is the level sequence, level level = init_level; S2.9, determine whether to enter the loop? That is, if the i-th bit is from 0 to inverts, then enter the loop, otherwise the loop ends, expressed as, for i: 0 to inverts, where inverts is the inverts defined in levelDesc, which is an integer, and its value is the number of cycle_cnt arrays in levelDesc, which can theoretically be any 32-bit integer range; if entering the loop, proceed to step S2.10, if the loop ends, return to step S2.3; S2.10, fill cycle_cnt[i] levels to the pth bit of dest[0......M]; S2.11, flip level, level^=1, that is, if level is 0, it will be 1 after flipping, if level is 1, it will be 0 after flipping, and return to step S2.9.