Multi-channel video synchronous display method, device and equipment and storage medium

Abstract

The invention discloses a multi-channel video synchronous display method and device, equipment and a storage medium, and the method comprises the steps: generating a video pixel clock through employing a received global clock signal relative to video data under the condition of receiving the video data inputted by a connected video source, and enabling the global clock signal to act on each channel of video data; generating a video driving time sequence of the corresponding video data according to the video pixel clock; and according to the video driving time sequence, driving the corresponding video data to be output to the connected display area through the associated video interface for display. And the same video driving time sequence can be adopted when each path of video data is output through a set global clock signal. Compared with the prior art, the method has the advantages that the same global clock signal is uniformly adopted for each path of video data to ensure video driving time sequence synchronization, the root problem of asynchronous video display is equivalently solved, and effective synchronization of multi-path video display can be ensured through the technical scheme of the embodiment.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a method, device, equipment and storage medium for synchronously displaying multiple videos. Background Art

[0002] In an application where multiple source end videos are displayed in corresponding display areas, multiple video interfaces can be used to correspond to the multiple source end videos one by one, and the multiple source end videos can be transmitted to the corresponding display areas for display. Generally, the video interface needs to synchronously send a video output signal relative to the source end video to the connected display area according to a predetermined timing signal.

[0003] In order to achieve synchronous display of the video output signal to the display area, it is necessary to ensure the synchronous output of the video output signal. In the prior art, different video interfaces generate timing signals based on independent video processing logics, and the generation of timing signals depends on the pixel clock. However, the frequencies of the reference clocks that the pixel clocks in different video processing logics depend on are not the same, which causes deviations in the timing signals generated under different video processing logics, thereby affecting the output timing of the video signals of each video interface, resulting in the problem of asynchronous display of multiple video images.

[0004] The existing methods for solving the problem of display asynchrony are that the synchronized display achieved is not effective synchronization. When the displayed picture is detected by some signal detection equipment, the display differences between the displayed multiple videos can still be clearly detected. Summary of the invention

[0005] In view of this, the embodiments of the present application provide a method, apparatus, device and storage medium for synchronously displaying multiple videos, which effectively realizes the synchronous display of multiple video picture information on a display screen.

[0006] In a first aspect, an embodiment of the present application provides a method for synchronously displaying multiple channels of video, wherein a video source of each channel of video corresponds to a video interface for outputting video data, each of the video interfaces is integrated in a video processing device, or is independently arranged on a video processing device, and the method is executed by the video processing device, including:

[0007] In the case of receiving video data input from a connected video source, generating a video pixel clock relative to the video data using a received global clock signal, the global clock signal acting on each channel of video data;

[0008] Generate a video driving timing of corresponding video data according to the video pixel clock;

[0009] According to the video driving timing, the corresponding video data is driven to be output to the connected display area through the associated video interface for display.

[0010] Further, the global clock signal is generated by a global crystal oscillator;

[0011] The global crystal oscillator is used as an external component and connected to the corresponding video processing device through the external interface on the video processing device connected to each video source, so as to send the global clock signal to each video processing device; or,

[0012] The crystal oscillator is used as an embedded component and is pre-embedded in a video processing device integrating each of the video interfaces, so that the global clock signal acts on the video data transmitted by each of the video interfaces.

[0013] Further, the video driving timing of generating corresponding video data according to the video pixel clock includes:

[0014] According to the clock signal frequency of the video pixel clock, a line synchronization signal, a field synchronization signal and a data valid signal of the video data are generated to form a video driving timing of the video data.

[0015] Furthermore, when the video driving timing of the corresponding video data is generated according to the video pixel clock, it also includes:

[0016] The generation time of the video driving timing is aligned using a set global pulse signal.

[0017] Furthermore, the use of the set global pulse signal to align the generation time of the video drive timing includes:

[0018] When a reset control signal generated based on the global pulse signal is received, the generated video drive timing is released, and the video drive timing generation logic of the corresponding video data is returned to be re-executed.

[0019] Further, the global pulse signal is generated by a pulse generating device;

[0020] The pulse generating device is an external component, connected to the corresponding video processing device through the external interface on the video processing device connected to each video source, so as to send the global pulse signal to each video processing device; or,

[0021] The pulse generating device is pre-embedded as an embedded component in a video processing device integrating each of the video interfaces, so that the global pulse signal acts on the video driving timing associated with each of the video interfaces.

[0022] Furthermore, each of the display areas is connected to a video interface as an independent sub-display module, and each of the sub-display modules is spliced ​​to form a display screen.

[0023] In a second aspect, an embodiment of the present application provides a synchronous display device for multiple video channels, comprising:

[0024] A pixel clock generation module, for generating a video pixel clock using a received global clock signal relative to the video data when receiving video data inputted by the connected video source, wherein the global clock signal acts on each channel of video data;

[0025] A driving timing generation module, used for generating a video driving timing of corresponding video data according to the video pixel clock;

[0026] The video data driving module is used to drive the corresponding video data to be output to the connected display area for display via the associated video interface according to the video driving timing.

[0027] In a third aspect, an embodiment of the present application provides a video processing device, including:

[0028] One or more processors and one or more video interfaces, wherein the processor runs a method for synchronously displaying multiple channels of video on the video processing device; wherein,

[0029] The processor, when receiving video data inputted by the connected video source, generates a video pixel clock relative to the video data using a received global clock signal, wherein the global clock signal acts on each channel of video data;

[0030] The processor generates a video driving timing of corresponding video data according to the video pixel clock;

[0031] The processor drives the corresponding video data to be output to the connected display area through the associated video interface for display according to the video driving timing;

[0032] The video processing device further includes: a memory for storing one or more programs;

[0033] When the one or more programs are executed by the one or more processors, the one or more processors implement the method described in the above-mentioned first aspect embodiment.

[0034] In a third aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed, implements the method described in the embodiment of the first aspect above.

[0035] The above-mentioned embodiment provides a method, device, equipment and storage medium for synchronous display of multiple videos, wherein each video source of each video corresponds to a video interface for video data output, each of the video interfaces is integrated in a video processing device, or is independently set on a video processing device, and the method is executed by the video processing device, and the method includes generating a video pixel clock relative to the video data using the received global clock signal when receiving the video data input by the connected video source, and the global clock signal acts on each video data; generating a video drive timing of the corresponding video data according to the video pixel clock; and driving the corresponding video data to be output to the connected display area through the associated video interface according to the video drive timing for display. This technical solution ensures that the same video drive timing can be used when each video data is output by setting a global clock signal. Compared with the existing method of realizing video synchronous display by adding video frames or skipping frames, this technical solution uniformly uses the same global clock signal for each video data to ensure video drive timing synchronization, which is equivalent to solving the root problem of video asynchronous display, thereby ensuring effective synchronization of multi-channel video display through the technical solution of this embodiment. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0037] Figure 1 A schematic diagram of a flow chart of a method for synchronously displaying multiple videos provided in an embodiment of the present application;

[0038] Figure 2 An example diagram illustrating a connection structure involved in a method for synchronously displaying multiple videos provided in an embodiment of the present application;

[0039] Figure 3 A synchronous display device for multiple video channels provided in an embodiment of the present application;

[0040] Figure 4 A schematic diagram of the structure of a video processing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical scheme and advantages of the present application clearer, the embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings. It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0042] When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are only examples of systems and methods consistent with some aspects of the present application as detailed in the attached claims.

[0043] In the description of the present application, it should be understood that the terms "first", "second", "third", etc. are only used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence, nor can they be understood as indicating or implying relative importance. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances. In addition, in the description of the present application, unless otherwise specified, "multiple" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship.

[0044] Figure 1 A flowchart of a method for synchronously displaying multiple videos provided in an embodiment of the present application. This embodiment is applicable to the case where multiple videos are synchronously displayed on a display screen. The method can be executed by a video processing device with video processing capabilities such as a server or a processing terminal, and in particular, by a processor based on the video processing device. The video processing device can be regarded as an execution terminal of the method for synchronously displaying multiple videos.

[0045] It should be noted that synchronous display of video data from different video sources in different display areas of a large screen is a common display requirement at present. In the existing technology for realizing synchronous display of multiple videos, the output video frames are often deleted or a certain video frame is repeatedly displayed to ensure display synchronization in terms of visual effects. However, if a special signal detection device is used for detection, the difference in display time of the display screen can still be found.

[0046] The method for synchronously displaying multiple videos provided in this embodiment can effectively solve the problems existing in the prior art.

[0047] In addition, it should be noted that the premise for each display area on the display screen to display video images synchronously is that the video data of multiple video sources can be output to the connected display areas through the video interface. In actual applications, each video source needs to correspond to a video interface, so multiple video sources need to be involved by multiple video interfaces.

[0048] Continuing with the above description, each video interface involved can be integrated on a video processing device, which is equivalent to a video processing device being able to access multiple video sources to receive video data from each video source. In this integrated case, it can be considered that one video processing device participates in the execution of the method provided in this embodiment. In another integrated implementation of the video interface, each video interface can be independently set on a different video processing device, which is equivalent to each video processing device being connected to a video source and directly receiving the video data of the connected video source. In this configuration implementation, it can be considered that the same number of video processing devices as the video sources participate in the execution of the method provided in this embodiment, and the method provided in this embodiment can be regarded as a set of execution logic that can be independently run on each video processing device, and when the video data of the video source connected to each video processing device needs to be synchronously displayed on the display screen, each video processing device needs to simultaneously execute the method provided in this embodiment.

[0049] Specifically, Figure 1 As shown, a method for synchronously displaying multiple videos provided in Embodiment 1 of the present application can be performed by each video processing device connected to one or more video sources, and may include the following operations:

[0050] S101. When receiving video data input from a connected video source, generate a video pixel clock using a received global clock signal relative to the video data, wherein the global clock signal acts on each channel of video data.

[0051] In this embodiment, the execution subject of the provided method receives the video data output by the connected video source, and as long as the video source continues to output the video data, the execution subject can continue to receive the video data. In this step, during the process of receiving the video data, the received global clock signal can be continuously used to generate the video pixel clock required for the video signal output relative to the received video data.

[0052] In this embodiment, the global clock signal can be considered as a reference clock signal required for generating a video pixel clock. It should be noted that video data is often output from a video interface to a connected display area in the form of a video signal in units of frames, and the output frequency of the video signal output through the video interface needs to be controlled according to the video drive timing. The determination of the video drive timing is related to the video pixel clock. In order to ensure that each channel of video data can be output from the corresponding video interface to the display area at the same time, this embodiment must ensure that the video drive timing corresponding to each channel of video data is the same, and the clock frequency of the video pixel clock must be the same. Considering that the clock frequency of the video pixel clock must be generated by the reference clock, in order to ensure the same clock frequency, this embodiment can use the same reference clock signal for each channel of video data through this step. This embodiment records the reference clock signal as a global clock signal.

[0053] In accordance with the above description, the video processing device executing this step can receive a global clock signal of the same frequency and apply the global clock signal to each connected video data. For multiple channels of video data that need to be synchronously displayed on the display area, whether each channel of video data is processed uniformly by one video processing device or is processed by one video processing device respectively, as long as the video processing device executes the method provided in this embodiment, it can be ensured that the global clock signal applied to each channel of video data for determining the video pixel clock is the same signal.

[0054] Among them, the global clock signal can be generated by a global crystal oscillator; the global crystal oscillator can be used as an external component, connected to the corresponding video processing device through the external interface on the video processing device connected to each video source, so as to send the global clock signal to each video processing device; or, the crystal oscillator can be used as an embedded component, pre-embedded in the video processing device integrating each video interface, so that the global clock signal acts on the video data transmitted by each video interface.

[0055] Specifically, in this embodiment, it can be considered that the global clock signal is generated by a crystal oscillator, and the crystal oscillator is recorded as a global crystal oscillator. When multiple video data need to be processed by multiple video processing devices, in order to ensure that each video processing device can receive the same global clock signal, it is necessary to ensure that the global crystal oscillator that generates the global clock signal can establish a connection with each video processing device. At this time, the global crystal oscillator can be regarded as an external component, and each video processing device can have an external interface for signal reception, so that each video processing device can establish a connection with the global crystal oscillator through the external interface.

[0056] When multiple channels of video data are uniformly processed by a video processing device including multiple video interfaces, the global crystal oscillator can be directly embedded in the video processing device so that the global clock signal generated by the panoramic crystal oscillator can act on the video data output by each video source connected to the video processing device.

[0057] In this embodiment, the video pixel clock generated by the global clock signal in this step can be generated by inputting the global clock signal into a pre-configured clock chip, and then combining the configuration information of the clock chip by the control unit in the video processing device to generate the video pixel clock; in addition, in another implementation method, the global clock signal can be directly used to generate the video pixel clock through a phase-locked loop or an analog clock manager.

[0058] S102: Generate a video driving timing of corresponding video data according to the video pixel clock.

[0059] In this embodiment, the video pixel clock can be specifically understood as a pixel clock on which the video drive timing generation depends, and the clock signal frequency of the pixel clock can be determined based on a global clock signal, wherein the clock signal frequency can be determined based on a global clock signal.

[0060] In this embodiment, the video driving timing includes the timing driving information for determining the generation and output of each video signal when the video data is represented in the form of a video signal, wherein the video signal involved may include a line synchronization signal, a field synchronization signal, and a data valid signal of the video data. In this embodiment, various signal driving information constituting the video driving timing can be generated by counting the video pixel clock when the clock signal is generated at the clock signal frequency.

[0061] In an optional implementation, generating the same video drive timing for each channel of video data based on the video pixel clock can be specifically optimized as follows: for each channel of video data, generating a line synchronization signal, a field synchronization signal and a data valid signal of the video data according to the clock signal frequency of the video pixel clock to constitute the video drive timing of the video data.

[0062] In this embodiment, the synchronization signal can be used to provide a signal with the same time reference to the execution subject (video processing device) that needs to synchronize the information. In this embodiment, the synchronization information is mainly used for the synchronization of video data. The synchronization signal can be a switch signal or a continuous pulse. In this embodiment, the continuous pulse is preferred.

[0063] In this embodiment, the display processing of video data to the display end involves a line synchronization signal and a field synchronization signal, and also involves a data valid signal for video data transmission. The line field synchronization signal can be understood as a pulse signal generated by the video signal transmitter (this execution device) to control the timing of video line field scanning in order to synchronize the line scanning and field scanning rules of the receiving end (display area) with it. The scanning of the video data content corresponding to the corresponding line (field) can be completed within the duration of the pulse signal. In addition, the data valid signal can be specifically understood as a pulse signal used to control the timing of sending the video content obtained by scanning to the display area side.

[0064] In this implementation, the calculation parameters of the video signal involved in the video data can be determined; then the line synchronization frequency multiples and the field synchronization frequency multiples can be obtained according to the video pixel clock and the calculation parameters, and the line synchronization pulse width multiples and the field synchronization pulse width multiples can be obtained; finally, the line synchronization signal can be obtained by counting the line synchronization frequency multiples and the line synchronization pulse width multiples, and the field synchronization signal can be obtained by counting the field synchronization frequency multiples and the field synchronization pulse width multiples. Similarly, the data valid signal can also be obtained using the above execution logic. In this step, the obtained line (field) synchronization signal and data valid signal can be used as the video drive timing of the video data.

[0065] S103 , according to the video driving timing, drive the corresponding video data to be output to the connected display area through the associated video interface for display.

[0066] In this embodiment, the determined video drive timing can drive the video data to generate relevant video signals at the appropriate execution time according to the timing control information contained therein. Ultimately, this step can control the various video signals generated relative to the video data to be output to the display area of ​​the video screen through the associated video interface.

[0067] It can be known that, for multiple video sources, each video source has a corresponding video interface required for video signal output, and the video signal generated by the video data of each video source in this step can be output to the display device through the corresponding video interface. The display device can be a large-sized liquid crystal display screen with display area division conditions.

[0068] In a preferred implementation, each of the display areas is connected to a video interface as an independent sub-display module, and each of the sub-display modules is spliced ​​to form a display screen. Specifically, the display screen in this case can be a light-emitting diode (LED) display screen, and the LED display screen can be formed by LED display units. Among them, each display area on the LED display screen can be an independent sub-display module composed of a group of display units, and after splicing the independent sub-display modules, a spliced ​​LED display screen can be formed.

[0069] In this embodiment, each display area on the display screen can be connected to a video interface of the video processing device, and the connected video interface can transmit the video signal generated by the video drive timing to the corresponding display area. The method provided in this embodiment can act on the video data of each video source through the video pixel clock generated by the same global clock signal, ensuring that the video pixel clock used when the video signal is generated by each video data is consistent, so that the video drive timing determined based on the consistent video pixel clock can also be consistent, which is equivalent to solving the current problem of asynchronous multi-channel video images from the root of the reference clock.

[0070] This embodiment provides a method for synchronizing multiple channels of video, which ensures that the same video drive timing can be used when each channel of video data is output by setting a global clock signal. Compared with the existing method of achieving video synchronization display by adding video frames or skipping frames, this technical solution uniformly uses the same global clock signal for each channel of video data to ensure video drive timing synchronization, which is equivalent to solving the root problem that causes asynchronous video display. Therefore, the technical solution of this embodiment can ensure effective synchronization of multiple channel video display.

[0071] As an optional embodiment of this embodiment, on the basis of the above embodiment, the method provided in this embodiment further includes: using a set global pulse signal to align the generation time of the video drive timing when generating the video drive timing of the corresponding video data according to the video pixel clock.

[0072] It can be understood that this optional embodiment is equivalent to further providing a method step for controlling the generation process of the video drive timing on the basis of the above-mentioned method. By controlling the generation process of the video drive timing, the alignment of the video drive timing of each channel of video data in the generation time can be achieved. In addition to ensuring that the video drive timing required for video data transmission is consistent through the above-mentioned method, this optional embodiment can also ensure that the video drive timing corresponding to each channel of video sources is consistent in the generation time by aligning the video drive timing corresponding to each channel of video sources. The method provided in this embodiment is equivalent to achieving dual synchronization in the timing generation start time and timing control.

[0073] Specifically, this embodiment can align the start generation time of the video drive timing corresponding to different video sources in the process of generating the video drive timing of the corresponding video data according to the video pixel clock by presetting a global pulse signal. In an alignment processing implementation, a reset control signal can be sent to each generation execution logic of the video drive timing based on the global pulse signal. As long as the reset control signal is received, the generated video drive timing can be released, so as to ensure that the generation execution logic of each video drive timing can maintain the same generation start time in this way.

[0074] In this optional embodiment, the global pulse signal can be further optimized to be generated by a pulse generating device; the pulse generating device is used as an external component, connected to the corresponding video processing device through an external interface on the video processing device to which each video source is connected, so as to send the global pulse signal to each video processing device; or, the pulse generating device is used as an embedded component, pre-embedded in the video processing device integrating each of the video interfaces, so that the global pulse signal acts on the video drive timing associated with each of the video interfaces.

[0075] In this embodiment, the global pulse signal is the same as the global clock signal, which is equivalent to the global signal required in the method provided by this embodiment. The global pulse signal can be generated by a pulse generating device. Similarly, the pulse generating device can also be connected to the execution subject (video processing device) of the method provided by this embodiment in the form of an external component or an embedded component.

[0076] Specifically, each video source can be connected to a different video processing device, and when the video interface on the corresponding video processing device is used to transmit video data, the pulse generating device can be used as an external component to connect to the video processing device through the external interface on each video processing device. In this connection mode, each video processing device can receive the global pulse signal generated by the external pulse generating device, so as to realize the processing of the video driving timing involved on different video processing devices by the same global pulse signal.

[0077] In addition, when each video source is connected to the same video processing device and multiple video interfaces on the video processing device are used to transmit corresponding video data, the pulse generating device can be directly used as an embedded component and built into the video processing device. In this connection mode, the video processing device can use the pulse signal generated by the pulse generating device as a global pulse signal to act on the video data of different video sources, and also realize the processing of the video drive timing involved in each video data.

[0078] Based on this optional embodiment, the alignment processing of the generation time of the video drive timing using the set global pulse signal can be further concretized as follows: when a reset control signal generated based on the global pulse signal is received, the generated video drive timing is released, and the video drive timing generation logic of the corresponding video data is returned to be re-executed.

[0079] In this embodiment, a reset control signal acting on the video drive timing generation logic can be generated under the control of the global pulse signal. When the video drive timing generation process receives the reset control signal, it is equivalent to the embodiment controlling the generation timing of the video drive timing. At this time, this step needs to release the video drive timing generated in the video drive timing generation process. This operation ensures that each video drive timing can be at the same generation starting point.

[0080] According to the above description, by releasing the generated video drive timing, it is possible to ensure that the video drive timing corresponding to each channel of video data remains aligned at the time of generation. Afterwards, each video drive timing generation process that is at the same generation starting point can be controlled to re-execute the video drive timing generation logic of the corresponding video data.

[0081] The above technical solution of this embodiment, under the premise of ensuring that the same global clock signal is used to generate the video pixel clock, further ensures the consistency of the timing of video drive timing generation by setting the same global pulse signal. This embodiment can fundamentally ensure the consistency of the timing of video data output from each channel by setting the same reference clock on which the video pixel clock depends and aligning the timing of video drive timing generation, thereby achieving the absolute effectiveness of synchronous display of multiple videos to the display area.

[0082] In order to better understand the source of the global clock signal and the global pulse signal in the method provided above in this embodiment, this embodiment provides the following exemplary structure for illustration. Specifically, Figure 2 An illustrative diagram of an example of a connection structure involved in a method for synchronously displaying multiple videos provided in an embodiment of the present application.

[0083] like Figure 2 As shown, taking each video source connected to a different video processing device as an example, each video processing device 11 is externally connected to the same global crystal oscillator 12 and the same pulse generating device 13, and each video processing device 11 can output the video data of the connected video source to the connected display area through the built-in video interface, wherein each display area can form a large display screen 14 by splicing. Figure 2 Under the connection structure shown, the video processing device can ensure the absolute synchronous display of each channel of video data to the corresponding display area by executing the method provided in this embodiment.

[0084] Figure 3 A synchronous display device for multiple videos is provided in an embodiment of the present application. The device is suitable for synchronously displaying multiple videos on a display screen. The device can be integrated in a video processing device having video processing capabilities such as a server or a processing terminal, such as Figure 3 As shown, the device includes: a pixel clock generating module 21, a driving timing generating module 22 and a video data driving module 23.

[0085] A pixel clock generating module 21 is used to generate a video pixel clock using a received global clock signal relative to the video data when receiving the video data inputted by the connected video source, wherein the global clock signal acts on each channel of video data;

[0086] A driving timing generation module 22, used for generating a video driving timing of corresponding video data according to the video pixel clock;

[0087] The video data driving module 23 is used to drive the corresponding video data to be output to the connected display area through the associated video interface for display according to the video driving timing.

[0088] The synchronous display device for multiple videos provided in this embodiment has a video source for each video corresponding to a video interface for video data output, each of the video interfaces is integrated in a video processing device, or is independently set on a video processing device, and the device is configured on the video processing device. A set global clock signal is used to ensure that the same video drive timing can be used when each video data is output. Compared with the existing method of achieving video synchronous display by adding video frames or skipping frames, this technical solution uniformly uses the same global clock signal for each video data to ensure video drive timing synchronization, which is equivalent to solving the root problem that causes asynchronous video display. Therefore, the technical solution of this embodiment can ensure effective synchronization of multi-channel video display.

[0089] Further, the global clock signal is generated by a global crystal oscillator;

[0090] The global crystal oscillator is used as an external component and is connected to the corresponding video processing device through the external interface on the video processing device to which each video source is connected, so as to send the global clock signal to each video processing device; or, the crystal oscillator is used as an embedded component and is pre-embedded in the video processing device integrating each video interface, so that the global clock signal acts on the video data transmitted by each video interface.

[0091] Furthermore, the driving timing generation module 22 can be specifically used for:

[0092] According to the clock signal frequency of the video pixel clock, a line synchronization signal, a field synchronization signal and a data valid signal of the video data are generated to form a video driving timing of the video data.

[0093] Furthermore, the device also includes: a timing alignment processing module, which is used to align the generation time of the video driving timing using a set global pulse signal when generating the video driving timing of the corresponding video data according to the video pixel clock.

[0094] Further, the global pulse signal is generated by a pulse generating device;

[0095] The pulse generating device is connected to the corresponding video processing device through the external interface on the video processing device connected to each video source to send the global pulse signal to each video processing device; or, the pulse generating device is pre-embedded in the video processing device integrating each video interface as an embedded component, so that the global pulse signal acts on the video driving timing associated with each video interface.

[0096] Furthermore, the timing alignment processing module can be specifically used for:

[0097] When a reset control signal generated based on the global pulse signal is received, the generated video drive timing is released, and the video drive timing generation logic of the corresponding video data is returned to be re-executed.

[0098] Furthermore, each of the display areas is connected to a video interface as an independent sub-display module, and each of the sub-display modules is spliced ​​to form a display screen.

[0099] Figure 4 The structure diagram of a video processing device provided in an embodiment of the present application is shown in FIG. Figure 4 As shown, the video processing device 30 may include: at least one video interface 300 , at least one processor 301 , at least one network interface 304 , a user interface 303 , a memory 305 , and at least one communication bus 302 .

[0100] The communication bus 302 is used to realize the connection and communication between these components.

[0101] The user interface 303 may include a display screen (Display) and a connection interface of a video acquisition device (Camera). Optionally, the user interface 303 may also include a standard wired interface and a wireless interface.

[0102] The network interface 304 may optionally include a standard wired interface or a wireless interface (such as a WI-FI interface).

[0103] Among them, the processor 301 may include one or more processing cores. The processor 301 uses various interfaces and lines to connect the various parts of the entire video processing device 30, and executes various functions and processes data of the video processing device 30 by running or executing instructions, programs, code sets or instruction sets stored in the memory 305, and calling data stored in the memory 305. Optionally, the processor 301 can be implemented in at least one hardware form of digital signal processing (Digital Signal Processing, DSP), field programmable gate array (Field-Programmable Gate Array, FPGA), and programmable logic array (Programmable Logic Array, PLA). The processor 301 can integrate one or a combination of a central processing unit (Central Processing Unit, CPU), a graphics processing unit (Graphics Processing Unit, GPU) and a modem. Among them, the CPU mainly processes the operation of the user interface and application programs; the GPU is responsible for rendering and drawing the content to be displayed on the display screen; the modem is used to process wireless communications. It can be understood that the above-mentioned modem may not be integrated into the processor 301, and can be implemented separately through a chip.

[0104] In this embodiment, the processor 301 runs the method for synchronously displaying multiple channels of video on the video processing device, and sends the video data of the connected video sources to the respective display areas through the video interface 300 .

[0105] in,

[0106] When receiving video data input from a connected video source, the processor 301 generates a video pixel clock using a received global clock signal relative to the video data, wherein the global clock signal acts on each channel of video data;

[0107] The processor 301 generates a video driving timing of corresponding video data according to the video pixel clock;

[0108] The processor 301 drives the corresponding video data to be output to the connected display area through the associated video interface for display according to the video driving timing;

[0109] Among them, the memory 305 in the video processing device 30 may include a random access memory (Random Access Memory, RAM) or a read-only memory (Read-Only Memory). Optionally, the memory 305 includes a non-transitory computer-readable storage medium. The memory 305 can be used to store instructions, programs, codes, code sets or instruction sets. The memory 305 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playback function, an image playback function, etc.), instructions for implementing the above-mentioned various method embodiments, etc.; the data storage area may store data involved in the above-mentioned various method embodiments, etc. The memory 305 may optionally be at least one storage device located away from the aforementioned processor 301. As Figure 4 As shown, the memory 305 as a computer storage medium may include an operating network communication module, a user interface module, and an operating application program of the video processing device. Figure 4 In the video processing device 30 shown, the user interface 303 is mainly used to provide an input interface for the user and obtain data input by the user; and the processor 301 can be used to call the operation application of the video processing device stored in the memory 305, and specifically perform the following operations:

[0110] In the case of receiving video data input from a connected video source, generating a video pixel clock relative to the video data using a received global clock signal, the global clock signal acting on each channel of video data;

[0111] Generate a video driving timing of corresponding video data according to the video pixel clock;

[0112] According to the video driving timing, the corresponding video data is driven to be output to the connected display area through the associated video interface for display.

[0113] Furthermore, the processor 301 calls the program in the memory 305 and can also specifically limit the global clock signal to be generated by a global crystal oscillator; the global crystal oscillator is used as an external component, and is connected to the corresponding video processing device through an external interface on the video processing device to which each video source is connected, so as to send the global clock signal to each video processing device; or, the crystal oscillator is used as an embedded component, and is pre-embedded in the video processing device that integrates each of the video interfaces, so that the global clock signal acts on the video data transmitted by each of the video interfaces.

[0114] Furthermore, the processor 301 calls the program in the memory 305 to specifically optimize the video drive timing for generating corresponding video data according to the video pixel clock as follows: according to the clock signal frequency of the video pixel clock, a line synchronization signal, a field synchronization signal and a data valid signal of the video data are generated to constitute the video drive timing of the video data.

[0115] Furthermore, the processor 301 calls the program in the memory 305 and can also specifically limit the global pulse signal to be generated by a pulse generating device; the pulse generating device is an external component, connected to the corresponding video processing device through the external interface on the video processing device to which each video source is connected, so as to send the global pulse signal to each video processing device; or, the pulse generating device is an embedded component, pre-embedded in the video processing device integrating each of the video interfaces, so that the global pulse signal acts on the video drive timing associated with each of the video interfaces.

[0116] Furthermore, the processor 301 calls the program in the memory 305 to optimize the alignment processing of the generation time of the video drive timing using the set global pulse signal as follows: when a reset control signal generated based on the global pulse signal is received, the generated video drive timing is released, and the video drive timing generation logic of the corresponding video data is returned to be re-executed.

[0117] Furthermore, the processor 301 calls the program in the memory 305 and can also specifically define each of the display areas as an independent sub-display module connected to a video interface, and each of the sub-display modules is spliced ​​to form a display screen.

[0118] When a video processing device provided in an embodiment of the present application executes the method for synchronously displaying multiple videos provided in the above embodiment, it has the functions and beneficial effects corresponding to the method for synchronously displaying multiple videos.

[0119] The present application also provides a computer storage medium, which can store multiple instructions.

[0120] The instructions are suitable for being loaded by a processor and executing the steps of the method provided in the above embodiment. The specific execution process can be found in the description of the above method embodiment, which will not be repeated here.

[0121] The device where the storage medium is located may be a video processing device that integrates a synchronous display method for multiple-channel videos.

[0122] Those skilled in the art should understand that the embodiments of the present application may be provided as methods or computer program products.

[0123] Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0124] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0125] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0126] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0127] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0128] Memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium. Computer-readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. The information can be computer-readable instructions, data structures, modules of programs or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include temporary computer-readable media (transitory media), such as modulated data signals and carrier waves. It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the presence of other identical elements in the process, method, commodity or device including the elements.

[0129] Note that the above are only preferred embodiments of the present application and the technical principles used. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present application. Therefore, although the present application is described in more detail through the above embodiments, the present application is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A method for synchronously displaying multiple video channels, characterized in that: The video source of each video channel corresponds to a video interface for outputting video data, each of the video interfaces is integrated in a video processing device, or is independently arranged on a video processing device, and the method is executed by the video processing device, including: In the case of receiving video data input from a connected video source, generating a video pixel clock relative to the video data using a received global clock signal, the global clock signal acting on each channel of video data; Generate a video driving timing of corresponding video data according to the video pixel clock; According to the video driving timing, the corresponding video data is driven to be output to the connected display area through the associated video interface for display.

2. The method according to claim 1, characterized in that: The global clock signal is generated by a global crystal oscillator; The global crystal oscillator is used as an external component and connected to the corresponding video processing device through the external interface on the video processing device connected to each video source, so as to send the global clock signal to each video processing device; or, The crystal oscillator is used as an embedded component and is pre-embedded in a video processing device integrating each of the video interfaces, so that the global clock signal acts on the video data transmitted by each of the video interfaces.

3. The method according to claim 1, characterized in that The video driving timing of generating corresponding video data according to the video pixel clock includes: According to the clock signal frequency of the video pixel clock, a line synchronization signal, a field synchronization signal and a data valid signal of the video data are generated to form a video driving timing of the video data.

4. The method according to claim 1, characterized in that When the video driving timing of the corresponding video data is generated according to the video pixel clock, it also includes: The generation time of the video driving timing is aligned using a set global pulse signal.

5. The method according to claim 4, characterized in that The global pulse signal is generated by a pulse generating device; The pulse generating device is an external component, connected to the corresponding video processing device through the external interface on the video processing device connected to each video source, so as to send the global pulse signal to each video processing device; or, The pulse generating device is pre-embedded as an embedded component in a video processing device integrating each of the video interfaces, so that the global pulse signal acts on the video driving timing associated with each of the video interfaces.

6. The method according to claim 4, characterized in that The aligning process of the generation time of the video driving timing by using the set global pulse signal includes: When a reset control signal generated based on the global pulse signal is received, the generated video drive timing is released, and the video drive timing generation logic of the corresponding video data is returned to be re-executed.

7. The method according to any one of claims 1 to 6, characterized in that: Each of the display areas is connected to a video interface as an independent sub-display module, and each of the sub-display modules is spliced ​​to form a display screen.

8. A synchronous display device for multiple video channels, characterized in that: The video source of each video channel corresponds to a video interface for outputting video data, each of the video interfaces is integrated in a video processing device, or is independently set on a video processing device, and the device is configured on the video processing device, including: A pixel clock generation module, for generating a video pixel clock using a received global clock signal relative to the video data when receiving video data inputted by the connected video source, wherein the global clock signal acts on each channel of video data; A driving timing generation module, used for generating a video driving timing of corresponding video data according to the video pixel clock; The video data driving module is used to drive the corresponding video data to be output to the connected display area for display via the associated video interface according to the video driving timing.

9. A video processing device, characterized in that: include: One or more processors and one or more video interfaces, wherein the processor runs a method for synchronously displaying multiple channels of video on the video processing device; wherein, The processor, when receiving video data inputted by the connected video source, generates a video pixel clock relative to the video data using a received global clock signal, wherein the global clock signal acts on each channel of video data; The processor generates a video driving timing of corresponding video data according to the video pixel clock; The processor drives the corresponding video data to be output to the connected display area through the associated video interface for display according to the video driving timing; The video processing device further includes: a memory for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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