Dynamic random access memory architecture and method of forming the same

Abstract

A dynamic random access memory architecture and a forming method thereof, wherein the forming method comprises: forming a substrate, the substrate having opposite first and second surfaces, the substrate comprising a plurality of active regions, the active regions comprising a plurality of word line regions; forming a word line gate trench in each word line region; forming two mutually separated word line gate structures in each word line gate trench; forming a plurality of bit line layers on the first surface; performing a source-drain ion implantation process on the substrate from the second surface to the first surface to form a second source-drain doped layer in each active region; and forming a plurality of capacitor structures on the second surface. By placing the process of forming the capacitor structures at the end, it can be ensured that the high-temperature process is normally used during the process before the capacitor structures are formed, without damaging the capacitor structures. The second source-drain doped layer is formed by implanting source-drain ions from the second surface to the first surface, which can effectively improve the uniformity of the distribution of source-drain ions in the second source-drain doped layer, thereby effectively improving the performance of the transistor.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and particularly relates to a dynamic random access memory architecture and a forming method thereof. BACKGROUND

[0002] With the rapid development of today's technology, semiconductor memories are widely used in electronic devices. Dynamic random access memory (DRAM) belongs to a volatile memory, and for the application of storing a large amount of data, dynamic random access memory is the most commonly used solution.

[0003] Generally, dynamic random access memory is composed of a plurality of memory cells, each of which is mainly composed of a transistor and a capacitor controlled by the transistor, and each of which is electrically connected to each other through a word line and a bit line.

[0004] However, the existing dynamic random access memory architecture still has many problems. SUMMARY

[0005] The technical problem solved by the present application is to provide a dynamic random access memory architecture and a forming method thereof, which ensures the normal use of high-temperature process and improves the performance of the transistor.

[0006] To solve the above problems, the technical scheme of the present application provides a forming method of a dynamic random access memory architecture, comprising: forming a substrate, the substrate having opposite first and second surfaces, the substrate comprising a plurality of active regions separated from each other and parallel to a first direction, and the plurality of active regions being arranged along a second direction, the active regions being separated from each other by first isolation grooves, the first isolation grooves extending along the first direction, the first direction being perpendicular to the second direction, each of the active regions comprising a plurality of word line regions and isolation regions separated from each other and arranged along the first direction; forming first isolation structures in the first isolation grooves; forming first source / drain doped layers in each of the active regions, the first surface exposing the first source / drain doped layers; forming word line gate grooves in each of the word line regions and second isolation grooves in each of the isolation regions, the word line gate grooves and the second isolation grooves extending from the first surface to the second surface, and the word line gate grooves and the second isolation grooves penetrating the active regions along the second direction; forming second isolation structures in each of the second isolation grooves; forming initial word line gate structures in each of the word line gate grooves; after forming the second isolation structures and the initial word line gate structures, forming a plurality of bit line layers parallel to the first direction on the first surface, each of the bit line layers being electrically connected to a plurality of the first source / drain doped layers in a corresponding one of the active regions; after forming the bit line layers, performing a first thinning process on the substrate from the second surface to the first surface; after the first thinning process, etching part of the initial word line gate structures from the first surface to the second surface, so that the initial word line gate structures form two word line gate structures separated from each other, the two word line gate structures being located on opposite sidewalls of the word line gate grooves along the first direction; after forming the word line gate structures, performing a source / drain ion implantation process on the substrate from the second surface to the first surface, so as to form second source / drain doped layers in each of the active regions, the second surface exposing the second source / drain doped layers; and after forming the second source / drain doped layers, forming a plurality of capacitor structures on the second surface, each of the capacitor structures being electrically connected to a corresponding one of the second source / drain doped layers.

[0007] Optionally, the second isolation structure is a conductive structure.

[0008] Optionally, the material of the conductive structure comprises titanium nitride.

[0009] Optionally, the second isolation structure is an insulating structure.

[0010] Optionally, the material of the insulating structure comprises silicon oxide or air.

[0011] Optionally, the method for forming the initial word line gate structure in each of the word line gate trenches comprises: forming a word line gate material layer on the sidewalls and bottom surface of the word line gate trenches; removing part of the word line gate material layer on the sidewalls of the word line gate trenches to form a first cut-off opening and a second cut-off opening, so that the word line gate material layer forms the initial word line gate structure.

[0012] Optionally, the first cut-off opening and the second cut-off opening are respectively located in the initial word line gate structure on the sidewalls of the word line gate trenches arranged opposite to each other along the first direction, and the first cut-off opening and the second cut-off opening are also respectively located on both sides of the initial word line gate structure along the second direction.

[0013] Optionally, after the formation of the bit line layer and before the first thinning process, the method further comprises: forming a bit line isolation structure between adjacent bit line layers.

[0014] Optionally, the bit line isolation structure is a cavity structure.

[0015] Optionally, the depth of the word line gate trench is less than the depth of the first isolation trench; the depth of the second isolation trench is less than the depth of the first isolation trench.

[0016] Optionally, the first thinning process exposes at least the first isolation structure.

[0017] Optionally, after the formation of the word line gate structure and before the formation of the second source / drain doped layer, the method further comprises: performing a second thinning process on the substrate from the direction of the second face to the first face, to expose at least the second isolation structure.

[0018] Optionally, the depth of the word line gate trench is equal to the depth of the first isolation trench; the depth of the second isolation trench is equal to the depth of the first isolation trench.

[0019] Optionally, the first thinning process exposes at least the first isolation structure, the second isolation structure and the initial word line gate structure.

[0020] Optionally, after the formation of the bit line layer and before the first thinning process, the method further comprises: providing a logic circuit wafer; and bonding the logic circuit wafer to the substrate towards the first face, so that the logic circuit wafer is electrically connected to the bit line layer and the initial word line gate structure.

[0021] Optionally, after the initial word line gate structure forms two mutually separated word line gate structures, the logic circuit wafer is electrically connected to the word line gate structures.

[0022] Optionally, the second isolation structure is a conductive structure, and the logic circuit wafer is electrically connected with the second isolation structure.

[0023] Optionally, along the first direction, a first conductive plug for electrically connecting the second isolation structure and the logic circuit wafer has a first central axis, and a second conductive plug for electrically connecting the initial word line gate structure and the logic circuit wafer has a second central axis, and the first central axis coincides with the second central axis.

[0024] Optionally, along the first direction, a first conductive plug for electrically connecting the second isolation structure and the logic circuit wafer has a first central axis, and a second conductive plug for electrically connecting the initial word line gate structure and the logic circuit wafer has a second central axis, and the first central axis does not coincide with the second central axis.

[0025] Optionally, in the process of etching part of the initial word line gate structure from the first face to the second face, part of the second isolation structure is also etched from the first face to the second face, so that a projection of the second isolation structure along the first direction is located within a projection range of the word line gate structure along the first direction.

[0026] Correspondingly, the technical scheme of the present application also provides a dynamic random access memory architecture formed by the forming method of any one of the technical schemes, the dynamic random access memory architecture comprising: a substrate having opposite first and second surfaces, the substrate comprising a plurality of active regions separated from each other and parallel to a first direction, and the plurality of active regions being arranged along a second direction, the active regions being separated from each other by first isolation grooves, the first isolation grooves extending along the first direction, the first direction being perpendicular to the second direction, each of the active regions comprising a plurality of word line regions and isolation regions separated from each other and arranged along the first direction; a first isolation structure located in the first isolation groove; a first source / drain doped layer located in each of the active regions, the first surface exposing the first source / drain doped layer; a word line gate groove located in each of the word line regions, the word line gate groove extending from the first surface to the second surface and penetrating the active region along the second direction; a second isolation groove located in each of the isolation regions, the second isolation groove extending from the first surface to the second surface and penetrating the active region along the second direction; a second isolation structure located in each of the second isolation grooves; two word line gate structures located in each of the word line gate grooves, the two word line gate structures being located on opposite sidewalls of the word line gate groove along the first direction; a plurality of bit line layers parallel to the first direction located on the first surface, each of the bit line layers being electrically connected to the plurality of first source / drain doped layers in the corresponding active region; a second source / drain doped layer located in each of the active regions, the second surface exposing the second source / drain doped layer; and a plurality of capacitor structures located on the second surface, each of the capacitor structures being electrically connected to the corresponding second source / drain doped layer.

[0027] Optionally, the second isolation structure is a conductive structure.

[0028] Optionally, the material of the conductive structure comprises titanium nitride.

[0029] Optionally, the second isolation structure is an insulating structure.

[0030] Optionally, the material of the insulating structure comprises silicon oxide or air.

[0031] Optionally, the dynamic random access memory architecture further comprises a bit line isolation structure located between adjacent bit line layers.

[0032] Optionally, the bit line isolation structure is a cavity structure.

[0033] Optionally, the memory device further comprises a logic circuit wafer, the logic circuit wafer is bonded to the substrate towards the first surface, and the logic circuit wafer is electrically connected to the bit line layer and the word line gate structure respectively.

[0034] Optionally, the second isolation structure is a conductive structure, and the logic circuit wafer is electrically connected to the second isolation structure.

[0035] Optionally, along the first direction, a first conductive plug for electrically connecting the second isolation structure and the logic circuit wafer has a first central axis, and a second conductive plug for electrically connecting the word line gate structure and the logic circuit wafer has a second central axis, and the first central axis coincides with the second central axis.

[0036] Optionally, along the first direction, a first conductive plug for electrically connecting the second isolation structure and the logic circuit wafer has a first central axis, and a second conductive plug for electrically connecting the word line gate structure and the logic circuit wafer has a second central axis, and the first central axis does not coincide with the second central axis.

[0037] Optionally, the two mutually separated word line gate structures are further located on the sidewalls of the word line gate trench opposite along the second direction, and the two second conductive plugs electrically connected to the two mutually separated word line gate structures are distributed on the two sides of the word line gate trench opposite along the second direction.

[0038] Optionally, a projection of the second isolation structure along the first direction is located within a projection range of the word line gate structure along the first direction.

[0039] Compared with the prior art, the technical scheme of the present application has the following advantages:

[0040] In the forming method of the dynamic random access memory architecture, the process of forming the capacitor structure is placed at the end, so that the high-temperature process can be normally used in the process before the capacitor structure is formed, without damaging the capacitor structure. In addition, the second source-drain doped layer is formed by implanting source-drain ions from the second surface to the first surface, which can effectively improve the uniformity of the distribution of source-drain ions in the second source-drain doped layer, thereby effectively improving the performance of the transistor.

[0041] Further, the second isolation structure is a conductive structure. By applying a negative voltage to the second isolation structure, adjacent memory cells arranged along the first direction can be effectively isolated, thereby reducing the impact of row hammer effect on the memory cells.

[0042] Further, the first cut-off opening and the second cut-off opening are respectively located in the initial word line gate structure on the sidewall of the word line gate trench arranged opposite along the first direction, and the first cut-off opening and the second cut-off opening are also respectively located in the two sides of the initial word line gate structure along the second direction. By retaining part of the initial word line gate structure on the opposite sidewall of the word line gate trench along the second direction, the second conductive plug subsequently formed on the opposite two sides of the initial word line gate structure along the second direction can be more in contact with the initial word line gate structure, thereby improving the electrical contact performance between the second conductive plug and the word line gate structure subsequently formed from the initial word line gate structure.

[0043] Further, the bit line isolation structure is a cavity structure. The cavity structure has a strong electrical isolation effect, thereby effectively reducing the crosstalk between adjacent bit line layers.

[0044] Further, the depth of the word line gate trench and the second isolation trench is less than the depth of the first isolation trench. After the first thinning process, the initial word line gate structure located in the word line gate trench is not exposed, thereby effectively reducing the process risk of metal exposure.

[0045] Further, along the first direction, the first conductive plug for electrically connecting the second isolation structure and the logic circuit wafer has a first central axis, and the second conductive plug for electrically connecting the initial word line gate structure and the logic circuit wafer has a second central axis, and the first central axis and the second central axis do not coincide. By arranging the first conductive plug and the second conductive plug staggered along the first direction, the exposure window for forming the first conductive plug and the second conductive plug can be further increased, thereby increasing the volume of the first conductive plug and the second conductive plug to improve the electrical conduction performance.

[0046] Further, in the process of etching part of the initial word line gate structure from the first face to the second face, it also includes etching part of the second isolation structure from the first face to the second face, so that the projection of the second isolation structure along the first direction is located in the projection range of the word line gate structure along the first direction, thereby reducing the influence of the second isolation structure on adjacent storage units when a negative voltage is applied.

[0047] In the dynamic random access memory architecture of the technical solution of the present application, the process of forming the capacitor structure is placed at the end, so that the normal high-temperature process can be used in the process before the capacitor structure is formed without damaging the capacitor structure. In addition, the second source / drain doped layer is formed by implanting source / drain ions from the second surface to the first surface, which can effectively improve the uniformity of the distribution of source / drain ions in the second source / drain doped layer, thereby effectively improving the performance of the transistor.

[0048] Further, the second isolation structure is a conductive structure. By applying a negative voltage to the second isolation structure, adjacent memory cells arranged in the first direction can be effectively isolated, thereby reducing the impact of row hammer effect on the memory cells.

[0049] Further, the bit line isolation structure is a cavity structure. The cavity structure has a strong electrical isolation effect, thereby effectively reducing the crosstalk between adjacent bit line layers.

[0050] Further, along the first direction, the first conductive plug for electrically connecting the second isolation structure and the logic circuit wafer has a first central axis, and the second conductive plug for electrically connecting the initial word line gate structure and the logic circuit wafer has a second central axis, and the first central axis and the second central axis do not coincide. By arranging the first conductive plug and the second conductive plug staggered in the first direction, the exposure window for forming the first conductive plug and the second conductive plug can be further increased, thereby increasing the volume of the first conductive plug and the second conductive plug to improve the electrical conduction performance.

[0051] Further, the two mutually separate word line gate structures are also located on the opposite sidewalls of the word line gate trench along the second direction; and the two second conductive plugs electrically connected with the two mutually separate word line gate structures are distributed on the two opposite sides of the word line gate trench along the second direction. In this way, the contact area between the second conductive plug and the corresponding word line gate structure is increased, and the electrical contact performance between the second conductive plug and the corresponding word line gate structure is improved.

[0052] Further, the projection of the second isolation structure along the first direction is located within the projection range of the word line gate structure along the first direction, thereby reducing the impact of the second isolation structure on adjacent memory cells when a negative voltage is applied. BRIEF DESCRIPTION OF DRAWINGS

[0053] Figures 1-39 is a schematic diagram of each step of a forming method of a dynamic random access memory architecture according to an embodiment of the present application;

[0054] Figure 40A structure diagram of a pillar-shaped capacitor in a dynamic random access memory architecture according to an embodiment of the present application;

[0055] Figure 41 A structure diagram of a cup-shaped capacitor in a dynamic random access memory architecture according to an embodiment of the present application;

[0056] Figure 42 A structure diagram of a cylinder-shaped capacitor in a dynamic random access memory architecture according to an embodiment of the present application;

[0057] Figure 43 A distribution diagram of a first conductive plug and a second conductive plug in a dynamic random access memory architecture according to another embodiment of the present application. DETAILED DESCRIPTION

[0058] As described in the background section, the existing dynamic random access memory architecture still has many problems. The following will be described in detail.

[0059] The dynamic random access memory architecture in the prior art is to make the capacitor structure first, and then make the back process, thereby causing that high-temperature process cannot be used in the back process, otherwise the high-K dielectric layer in the capacitor structure will be affected, thereby causing the failure of the capacitor structure. In addition, the back source-drain doped layer in the dynamic random access memory architecture is formed by ion implantation from the front surface, which easily causes poor ion distribution uniformity in the transistor, and reduces the performance of the transistor.

[0060] On this basis, the present application provides a dynamic random access memory architecture and a forming method thereof, by which the process of forming the capacitor structure is placed at the last, the high-temperature process can be normally used in the process before forming the capacitor structure, without causing damage to the capacitor structure. In addition, the second source-drain doped layer is formed by implanting source-drain ions from the second surface to the first surface, which can effectively improve the distribution uniformity of the source-drain ions in the second source-drain doped layer, thereby effectively improving the performance of the transistor.

[0061] In order to make the above-mentioned purpose, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0062] Figures 1-39 is a structure diagram of each step of a forming method of a dynamic random access memory architecture according to an embodiment of the present application; Figure 40 A structure diagram of a pillar-shaped capacitor in a dynamic random access memory architecture according to an embodiment of the present application; Figure 41 A structure diagram of a cup-shaped capacitor in a dynamic random access memory architecture according to an embodiment of the present application; Figure 42A structure diagram of a cylinder type capacitor in a dynamic random access memory architecture of an embodiment of the present application; Figure 43 A distribution diagram of a first conductive plug and a second conductive plug in a dynamic random access memory architecture of another embodiment of the present application.

[0063] Please refer to Figures 1-3 , Figure 2 is Figure 1 a sectional view along line A-A in FIG. 1, Figure 3 is Figure 1 a sectional view along line B-B in FIG. 1, a substrate 100 is formed, the substrate 100 has opposite first and second faces 100a and 100b, the substrate 100 includes a plurality of active regions 101 which are separate from each other and parallel to a first direction X, and the active regions 101 are arranged along a second direction Y, and a first isolation trench 102 is arranged between adjacent active regions 101, the first isolation trench 102 extends along the first direction X, and the first direction X is perpendicular to the second direction Y, each active region 101 includes a plurality of word line regions 1011 and isolation regions 1012 which are separate from each other and arranged along the first direction X.

[0064] In the embodiment, a forming method of the substrate 100 includes: providing an initial substrate (not shown); forming a first patterned layer (not shown) on the initial substrate; etching the initial substrate with the first patterned layer as a mask to form a plurality of first isolation trenches 102, and forming the substrate 100 from the initial substrate, and the active regions 101 are between adjacent first isolation trenches 102.

[0065] In the embodiment, a material of the substrate 100 is silicon.

[0066] In other embodiments, a material of the substrate 100 can also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0067] It should be noted that, in the embodiment, the first face 100a is a front face of a storage unit in a finally formed dynamic random access memory architecture, and the second face 100b is a back face of the storage unit in the finally formed dynamic random access memory architecture.

[0068] Please refer to Figure 4 and Figure 5 , Figure 5 is Figure 4 a sectional view along line C-C in FIG. 1, a first isolation structure 103 is formed in the first isolation trench 102.

[0069] In the embodiment, the forming method of the first isolation structure 103 includes: depositing an isolation material layer (not shown) which fills the first isolation trench 102 and is on the first surface 100a; planarizing the isolation material layer until the first surface 100a of the substrate 100 is exposed, thereby forming the first isolation structure 103.

[0070] In the embodiment, the material of the first isolation structure 103 is silicon oxide.

[0071] Please refer to the same view direction of Figure 6 , Figure 6 and Figure 5 , after forming the first isolation structure 103, a first source-drain doped layer 104 is formed in each of the active regions 101, and the first surface 100a exposes the first source-drain doped layer 104.

[0072] In the embodiment, the forming method of the first source-drain doped layer 104 includes: implanting source-drain ions into the substrate 100 from the first surface 100a to the second surface 100b, and annealing the implanted source-drain ions, thereby forming the first source-drain doped layer 104 in the active regions 101.

[0073] Please refer to the same view direction of Figures 7-9 , Figure 8 is Figure 7 , Figure 9 is Figure 7 , after forming the first source-drain doped layer 104, a word line gate trench (not shown) is formed in each of the word line regions 1011, and a second isolation trench (not shown) is formed in each of the isolation regions 1012, the word line gate trench and the second isolation trench extend from the first surface 100a to the second surface 100b, and the word line gate trench and the second isolation trench penetrate the active regions 101 along the second direction Y.

[0074] In the embodiment, the forming method of the word line gate trench and the second isolation trench includes: forming a second patterning layer (not shown) on the substrate 100; etching the word line regions 1011 and the first isolation structure 103 of the active regions 101 with the second patterning layer as a mask, thereby forming the word line gate trench; and etching the isolation regions 1012 and the first isolation structure 103 of the active regions 101 with the second patterning layer as a mask, thereby forming the second isolation trench.

[0075] In the embodiment, the depth of the word line gate trench is less than the depth of the first isolation trench 102; the depth of the second isolation trench is less than the depth of the first isolation trench 102.

[0076] In other embodiments, the depth of the word line gate trench can also be equal to the depth of the first isolation trench 102; the depth of the second isolation trench can also be equal to the depth of the first isolation trench 102.

[0077] Please continue to refer to Figures 7-9 After the word line gate trench and the second isolation trench are formed, the sacrificial layer 105 is filled in the word line gate trench and the second isolation trench.

[0078] It should be noted that in the embodiment, since different device structures are formed in the word line gate trench and the second isolation trench in subsequent processes, the word line gate trench and the second isolation trench are first filled with the sacrificial layer 105, and in subsequent processes, the sacrificial layer 105 in the corresponding trench is removed step by step to form the required device structure.

[0079] In the embodiment, the material of the sacrificial layer 105 is spin-on carbon.

[0080] Please refer to Figures 10-12 , Figure 11 is Figure 10 the cross-sectional view along F-F line in FIG. 1B, Figure 12 is Figure 10 the cross-sectional view along G-G line in FIG. 1B, after the formation of the sacrificial layer 105, a second isolation structure 106 is formed in each of the second isolation trenches.

[0081] It should be noted that in the embodiment, before the second isolation structure 106 is formed, the sacrificial layer 105 filled in the second isolation trench needs to be removed.

[0082] In the embodiment, the second isolation structure 106 is a conductive structure, and the material of the conductive structure is titanium nitride. Since the second isolation structure 106 is a conductive structure, a negative voltage can be applied to the second isolation structure 106, so that the second isolation structure 106 can effectively isolate adjacent storage units arranged along the first direction X, thereby reducing the impact of row hammer effect on the storage units.

[0083] It should be noted that, in the embodiment, a compact oxide layer (not shown) is formed on the surface of the second isolation trench before the second isolation structure 106 is formed, so as to repair the surface of the second isolation trench. The second isolation structure 106 does not fill the second isolation trench, and a protective layer 107 is formed on the second isolation structure 106 after the second isolation structure 106 is formed, so as to fill the second isolation trench. The purpose of that the second isolation structure 106 does not fill the second isolation trench is to reduce the height of the second isolation structure 106, so that the height of the second isolation structure 106 towards the first surface 100a cannot be higher than the height of the subsequently formed initial word line gate structure towards the first surface 100a, so as to ensure that the projection of the finally formed second isolation structure 106 along the first direction X is located in the projection range of the finally formed word line gate structure along the first direction X.

[0084] In other embodiments, the second isolation structure 106 can also be an insulating structure, and the material of the insulating structure can be silicon oxide or air. When the insulating structure is silicon oxide, only silicon oxide material needs to be deposited to fill the second isolation trench; when the insulating structure is air, by adjusting the parameters of the deposition process, the deposited material seals the opening of the second isolation trench, and the inside of the second isolation trench is air. The insulating isolation effect of air is strong, which can effectively improve the isolation effect of the second isolation structure 106.

[0085] Please refer to Figures 13-15 , Figure 13 is a top view of the word line gate trench in which the insulating material in the word line gate trench is omitted, Figure 14 is Figure 13 is a sectional view along the H-H line in Figure 15 is Figure 13 is a sectional view along the I-I line in, after the second isolation structure 106 is formed, an initial word line gate structure 108 is formed in each of the word line gate trenches.

[0086] It should be noted that, in the embodiment, before the initial word line gate structure 108 is formed, the sacrificial layer 105 filled in the word line gate trench needs to be removed, and the word line gate trench also needs to be lengthened to increase the volume of the word line gate trench.

[0087] Please refer to Figure 16 and Figure 17In this embodiment, the method of forming the initial word line gate structure 108 in each of the word line gate trenches includes: forming a word line gate material layer 109 on the sidewalls and bottom surface of the word line gate trench; removing part of the word line gate material layer 109 on the sidewalls of the word line gate trench to form a first cut-off opening 110 and a second cut-off opening 111, so that the word line gate material layer 109 forms the initial word line gate structure 108.

[0088] Please continue to refer to Figure 16 and Figure 17 In this embodiment, the first cut-off opening 110 and the second cut-off opening 111 are respectively located in the initial word line gate structure 108 on the sidewalls of the word line gate trench arranged in the first direction X, and the first cut-off opening 110 and the second cut-off opening 111 are also respectively located on both sides of the initial word line gate structure 108 in the second direction Y.

[0089] By retaining part of the initial word line gate structure 108 on the sidewalls of the word line gate trench in the second direction Y, the subsequent second conductive plug formed on the opposite sides of the initial word line gate structure 108 in the second direction Y can make more contact with the initial word line gate structure 108, thereby improving the electrical contact performance between the second conductive plug and the subsequent word line gate structure formed by the initial word line gate structure 108.

[0090] It should be noted that in this embodiment, before forming the initial word line gate structure 108, a dense oxide layer (not shown) is formed on the surface of the word line gate trench to repair the surface of the word line gate trench. Then the word line gate material layer 109 is formed on the sidewalls and bottom surface of the word line gate trench, wherein the word line gate material layer 109 includes a word line gate dielectric material layer (not shown) and a word line gate material layer (not shown). After forming the word line gate material layer 109, insulating material is deposited in the word line gate trench to fill the word line gate trench. Then the insulating material above the position where the word line gate material layer 109 needs to be cut off is removed, and then the first cut-off opening 110 and the second cut-off opening 111 are formed to form the word line gate material layer 109 into the initial word line gate structure 108. After forming the initial word line gate structure 108, insulating material is again deposited to fill the word line gate trench.

[0091] In this embodiment, the material of the word line gate dielectric material layer is silicon oxide, and the material of the word line gate material layer 109 is titanium nitride or tungsten.

[0092] In this embodiment, the second isolation structure 106 is formed before the initial word line gate structure 108 is formed. In this embodiment, the second isolation structure 106 is formed before the initial word line gate structure 108 is formed.

[0093] In other embodiments, the initial word line gate structure 108 can be formed first and then the second isolation structure 106.

[0094] Please refer to Figures 18-20 , Figure 19 is Figure 18 a cross-sectional view along the J-J line in FIG. 1C, and Figure 20 is Figure 18 a cross-sectional view along the K-K line in FIG. 1D, after the initial word line gate structure 108 is formed, a plurality of bit line layers 112 parallel to the first direction X are formed on the first surface 100a, and each of the bit line layers 112 is electrically connected to a plurality of the first source-drain doped layers 104 in the corresponding one of the active regions 101.

[0095] In the present embodiment, before the bit line layers 112 are formed, the first source-drain doped layers 104 exposed by the first surface 100a are subjected to a metallization process, so that part of the first source-drain doped layers 104 forms a metal silicide layer 113. By forming the metal silicide layer 113, the contact resistance between the bit line layers 112 and the first source-drain doped layers 104 can be effectively reduced.

[0096] In the present embodiment, the bit line layers 112 have a double-layer structure, and the bit line layers 112 include a first metal layer (not shown) and a second metal layer (not shown) on the first metal layer. The material of the first metal layer is titanium nitride, and the material of the second metal layer is tungsten.

[0097] Please refer to Figures 18-20 After the bit line layers 112 are formed, a bit line isolation structure 114 is formed between adjacent bit line layers 112.

[0098] In the present embodiment, the bit line isolation structure 114 has a cavity structure. The specific formation process is to adjust the parameters of the deposition process, so that the deposited silicon oxide material seals the opening between adjacent bit line layers 112, thereby forming a cavity structure between adjacent bit line layers 112. The cavity structure has a strong electrical isolation effect, thereby effectively reducing the crosstalk between adjacent bit line layers 112.

[0099] In other embodiments, the deposited silicon oxide material can also be directly filled into the gap between adjacent bit line layers 112 to serve as the bit line isolation structure 114.

[0100] Please refer to Figures 21-25 , Figure 21 is a top view of a dynamic random access memory architecture of a logic circuit wafer, Figure 22 is Figure 21 a cross-sectional view along the L-L line in FIG. 2C,Figure 23 is Figure 21 a cross-sectional view along line M-M in FIG. 1 1, Figure 24 is Figure 21 a cross-sectional view along line N-N in FIG. 1 1, Figure 25 is Figure 21 a cross-sectional view along line O-O in FIG. 1 1, after forming the bit line layer 1 12, a logic circuit wafer 200 is provided; the logic circuit wafer 200 is bonded to the substrate 100 towards the first surface 100a, and the logic circuit wafer 200 is electrically connected to the bit line layer 1 12 and the initial word line gate structure 108 respectively.

[0101] It should be noted that, in the embodiment, the logic circuit wafer 200 is bonded for logic control of reading, writing and refreshing of each memory cell.

[0102] In the embodiment, the second isolation structure 106 is a conductive structure, and the logic circuit wafer 200 is also electrically connected to the second isolation structure 106, and the logic circuit wafer 200 further includes an operation of applying a negative voltage to the second isolation structure 106.

[0103] In the embodiment, along the first direction X, a first conductive plug 1 15 for electrically connecting the second isolation structure 106 and the logic circuit wafer 200 has a first central axis S1, and a second conductive plug 1 16 for electrically connecting the initial word line gate structure 108 and the logic circuit wafer 200 has a second central axis S2, and the first central axis S1 coincides with the second central axis S2.

[0104] It should be noted that, in the embodiment, between forming the first conductive plug 1 15, the protective layer 107 covering the second isolation structure 106 needs to be removed. Between forming the second conductive plug 1 16, the insulating material covering the initial word line gate structure 108 needs to be removed.

[0105] Please refer to Figure 43 In other embodiments, along the first direction X, a first conductive plug 1 15 for electrically connecting the second isolation structure 106 and the logic circuit wafer 200 has a first central axis S1, and a second conductive plug 1 16 for electrically connecting the initial word line gate structure 108 and the logic circuit wafer 200 has a second central axis S2, and the first central axis S1 does not coincide with the second central axis S2. By staggering the first conductive plug 1 15 and the second conductive plug 1 16 along the first direction X, the exposure window for forming the first conductive plug 1 15 and the second conductive plug 1 16 can be further increased, and the volume of the first conductive plug 1 15 and the second conductive plug 1 16 can be further increased, so as to improve the electrical conduction performance.

[0106] In the embodiment, the logic circuit wafer 200 is electrically connected with the bit line layer 112 through the third conductive plugs 117.

[0107] In the embodiment, after the first surface 100a (i.e. the front surface) of the substrate 100 is bonded with the logic circuit wafer 200, the second surface 100b (i.e. the back surface) of the substrate 100 can be processed without the need of an additional temporary wafer to support the back surface processing of the substrate 100. Instead, the logic circuit wafer 200 can support the back surface processing of the substrate 100. Therefore, the process support can be simplified and the production cost can be reduced.

[0108] Please refer to Figures 26-29 , Figure 27 is Figure 26 a cross-sectional view along the P-P line in Figure 28 is Figure 26 a cross-sectional view along the Q-Q line in Figure 29 is Figure 26 a cross-sectional view along the R-R line in

[0109] In the embodiment, since the depth of the word line gate trench and the second isolation trench is less than the depth of the first isolation trench 102, the first thinning process can be performed until the first isolation structure 103 is exposed. In this way, the initial word line gate structure 108 in the word line gate trench will not be exposed after the first thinning process, thereby effectively reducing the process risk of metal exposure.

[0110] In other embodiments, when the depth of the word line gate trench and the second isolation trench is equal to the depth of the first isolation trench 102, the first thinning process can be performed until at least the first isolation structure 103, the second isolation structure 106 and the initial word line gate structure 108 are exposed.

[0111] The process of the first thinning process includes a physical and mechanical polishing process, a chemical and mechanical polishing process or a wet etching process.

[0112] In the embodiment, the process of the first thinning process adopts a chemical and mechanical polishing process.

[0113] Please refer to Figures 30-32 , Figure 30 and Figure 27 are consistent with the view direction of Figure 31 and Figure 28 are consistent with the view direction of Figure 32 andFigure 29 The view direction is consistent. After the first thinning process, part of the initial word line gate structure 108 is etched from the first surface 100a to the second surface 100b, so that the initial word line gate structure 108 forms two separate word line gate structures 118, and the two word line gate structures 118 are located on the opposite sidewalls of the word line gate trench along the first direction X.

[0114] It should be noted that in this embodiment, after the initial word line gate structure 108 forms two separate word line gate structures 118, the logic circuit wafer 200 is electrically connected to the word line gate structure 118.

[0115] In this embodiment, the purpose of forming two separate word line gate structures 118 from the initial word line gate structure 108 is to ensure that each word line gate trench has two word line gate structures 118 to control the channels on both sides of the word line gate trench.

[0116] It should be noted that in this embodiment, before etching the initial word line gate structure 108, the exposed first isolation structure 103 is etched until the initial word line gate structure 108 and the second isolation structure 106 are exposed. After the first isolation structure 103 exposes the bottom surface of the initial word line gate structure 108 and the second isolation structure 106, a wet etching process is used to etch and remove the bottom surface of the initial word line gate structure 108 and the second isolation structure 106. Because the wet etching process has the characteristic of isotropy, it can also remove the bottom surface of the initial word line gate structure 108 located in the active area 101, thereby ensuring that each initial word line gate structure 108 can form two separate word line gate structures 118. Moreover, the wet etching process needs to have a fast etching rate for the second isolation structure 106 to ensure that the height of the second isolation structure 106 after the final etching is lower than the height of the word line gate structure 108, that is, the projection of the second isolation structure 106 along the first direction X is located within the projection range of the word line gate structure 118 along the first direction X, so as to reduce the influence of the second isolation structure 106 on adjacent storage units when a negative voltage is applied. After wet etching, insulating material is deposited to fill the word line gate trench and the second isolation trench.

[0117] Please refer to Figure 33 and Figure 34 , Figure 33 In order to omit the dynamic random access memory architecture top view of the insulating material filled in the back surface to the word line gate trench and the second isolation trench, Figure 34 isFigure 33 Fig. 6 is a cross-sectional view along line S-S of Fig. 5, showing a second thinning process performed on the substrate 100 from the second surface 100b to the first surface 100a after forming the word line gate structure 118, so as to expose at least the second isolation structure 106.

[0118] The second thinning process includes a physical mechanical polishing process, a chemical mechanical polishing process, or a wet etching process.

[0119] In this embodiment, the second thinning process adopts a chemical mechanical polishing process.

[0120] In this embodiment, the second thinning process exposes the second isolation structure 106, so as to disconnect each active region 101 along the first direction X by the second isolation structure 106, thereby forming separate memory cells.

[0121] Fig. 7 is a cross-sectional view along line S-S of Fig. 5, showing a source-drain ion implantation process performed on the substrate 100 from the second surface 100b to the first surface 100a after the second thinning process, so as to form a second source-drain doped layer 119 in each active region 101, and the second surface 100b exposes the second source-drain doped layer 119. Figure 35 Figure 35 Fig. 8 is a top view of the substrate 100 omitting the bottom filling of the word line gate trench and the second isolation trench, Figure 34 Fig. 9 is a cross-sectional view along line T-T of Fig. 8, Fig. 10 is a cross-sectional view along line U-U of Fig. 8,

[0122] Fig. 11 is a cross-sectional view along line V-V of Fig. 8, showing a plurality of capacitor structures 120 formed on the second surface 100b after forming the second source-drain doped layer 119, and each capacitor structure 120 is electrically connected to a corresponding one of the second source-drain doped layers 119.

[0123] In this embodiment, after implanting the source-drain ions, an annealing process is further performed on the source-drain ions, thereby forming the second source-drain doped layer 119.

[0124] Fig. 8 is a top view of the substrate 100 omitting the bottom filling of the word line gate trench and the second isolation trench, Figures 36-39 Fig. 9 is a cross-sectional view along line T-T of Fig. 8, Figure 36 Fig. 10 is a cross-sectional view along line U-U of Fig. 8, Figure 37 Fig. 11 is a cross-sectional view along line V-V of Fig. 8, showing a plurality of capacitor structures 120 formed on the second surface 100b after forming the second source-drain doped layer 119, and each capacitor structure 120 is electrically connected to a corresponding one of the second source-drain doped layers 119. Figure 36 Figure 38 Figure 36 Figure 39 Figure 36 Fig. 11 is a cross-sectional view along line V-V of Fig. 8, showing a plurality of capacitor structures 120 formed on the second surface 100b after forming the second source-drain doped layer 119, and each capacitor structure 120 is electrically connected to a corresponding one of the second source-drain doped layers 119.

[0125] ​​​​By placing the process of forming the capacitor structure 120 at the end, it can be ensured that the high temperature process is normally used in the process before forming the capacitor structure 120, without causing damage to the capacitor structure 120.

[0126] In the embodiment, the capacitor structure 120 includes a pillar capacitor (as shown in Figure 40 ), a cup capacitor (as shown in Figure 41 ) or a cylinder capacitor (as shown in Figure 42 ).

[0127] In the embodiment, before forming the capacitor structure 120, a fourth conductive plug 121 is formed on the exposed second source / drain doped layer 119, and each capacitor structure 120 is electrically connected with the corresponding fourth conductive plug 121.

[0128] In other embodiments, the capacitor structure 120 can also be directly electrically connected with the corresponding second source / drain doped layer 119.

[0129] Correspondingly, the embodiment of the present application also provides a dynamic random access memory architecture, please continue to refer to Figures 36-39The dynamic random access memory architecture is formed by the forming method of any one of the above embodiments, and comprises: a substrate 100 having opposite first and second surfaces 100a and 100b, the substrate 100 comprising a plurality of active regions 101 separated from each other and parallel to a first direction X, and the plurality of active regions 101 being arranged along a second direction Y, and a first isolation groove 102 being between adjacent active regions 101 and extending along the first direction X, the first direction X being perpendicular to the second direction Y, each active region 101 comprising a plurality of word line regions 1011 and isolation regions 1012 separated from each other and arranged along the first direction X; a first isolation structure 103 in the first isolation groove 102; a first source / drain doped layer 104 in each active region 101, the first surface 100a exposing the first source / drain doped layer 104; a word line gate trench in each word line region 1011, the word line gate trench extending from the first surface 100a to the second surface 100b and penetrating the active region 101 along the second direction Y; a second isolation groove in each isolation region 1012, the second isolation groove extending from the first surface 100a to the second surface 100b and penetrating the active region 101 along the second direction Y; a second isolation structure 106 in each second isolation groove; two word line gate structures 118 separated from each other in each word line gate trench, the two word line gate structures 118 being located on opposite sidewalls of the word line gate trench along the first direction X; a plurality of bit line layers 112 parallel to the first direction X on the first surface 100a, each bit line layer 112 being electrically connected to a plurality of first source / drain doped layers 104 in a corresponding active region 101; a second source / drain doped layer 119 in each active region 101, the second surface 100b exposing the second source / drain doped layer 119; and a plurality of capacitor structures 120 on the second surface 100b, each capacitor structure 120 being electrically connected to a corresponding second source / drain doped layer 119.

[0130] By placing the process of forming the capacitor structures 120 at the end, it can be ensured that the high-temperature process is normally used during the process before the capacitor structures 120 are formed, without damaging the capacitor structures 120. In addition, the second source / drain doped layer 119 is formed by implanting source / drain ions from the second surface 100b to the first surface 100a, which can effectively improve the uniformity of the distribution of source / drain ions in the second source / drain doped layer 119, thereby effectively improving the performance of the transistor.

[0131] In the embodiment, the second isolation structure 106 is a conductive structure, and the material of the conductive structure is titanium nitride. Since the second isolation structure 106 is a conductive structure, a negative voltage can be applied to the second isolation structure 106 to effectively isolate adjacent memory cells arranged along the first direction X, thereby reducing the impact of row hammer on the memory cells.

[0132] In other embodiments, the second isolation structure 106 can also be an insulating structure, and the material of the insulating structure can be silicon oxide or air. When the insulating structure is silicon oxide, only the silicon oxide material needs to be deposited to fill the second isolation trench; when the insulating structure is air, by adjusting the parameters of the deposition process, the deposited material seals the opening of the second isolation trench, and the inside of the second isolation trench is air. The insulating isolation effect of air is strong, which can effectively improve the isolation effect of the second isolation structure 106.

[0133] In the embodiment, the dynamic random access memory architecture further includes a metal silicide layer 113 between the first source-drain doped layer 104 and the bit line layer 112. By forming the metal silicide layer 113, the contact resistance between the bit line layer 112 and the first source-drain doped layer 104 can be effectively reduced.

[0134] In the embodiment, the bit line layer 112 is a double-layer structure, and the bit line layer 112 includes a first metal layer and a second metal layer on the first metal layer. The material of the first metal layer is titanium nitride, and the material of the second metal layer is tungsten.

[0135] In the embodiment, the dynamic random access memory architecture further includes a bit line isolation structure 114 between adjacent bit line layers 112, and the bit line isolation structure 114 is a cavity structure. The specific forming process is to adjust the parameters of the deposition process so that the deposited silicon oxide material seals the opening between adjacent bit line layers 112, thereby forming a cavity structure between adjacent bit line layers 112. The cavity structure has a strong electrical isolation effect, thereby effectively reducing the crosstalk between adjacent bit line layers 112.

[0136] In the embodiment, the dynamic random access memory architecture further includes a logic circuit wafer 200, the logic circuit wafer 200 is bonded to the substrate 100 towards the first surface 100a, and the logic circuit wafer 200 is electrically connected to the bit line layer 112 and the word line gate structure 118, respectively.

[0137] It should be noted that in the present embodiment, the logic circuit wafer 200 is bonded for logic control of reading, writing and refreshing of each memory cell.

[0138] In the present embodiment, the second isolation structure 106 is a conductive structure, and the logic circuit wafer 200 is also electrically connected with the second isolation structure 106. The logic circuit wafer 200 further includes an operation of applying a negative voltage to the second isolation structure 106.

[0139] Please continue to refer to Figure 21 In the present embodiment, along the first direction X, the first conductive plug 115 for electrically connecting the second isolation structure 106 and the logic circuit wafer 200 has a first central axis S1, and the second conductive plug 116 for electrically connecting the word line gate structure 118 and the logic circuit wafer 200 has a second central axis S2, and the first central axis S1 coincides with the second central axis S2.

[0140] Please continue to refer to Figure 43 In other embodiments, along the first direction X, the first conductive plug 115 for electrically connecting the second isolation structure 106 and the logic circuit wafer 200 has a first central axis S1, and the second conductive plug 116 for electrically connecting the word line gate structure 118 and the logic circuit wafer 200 has a second central axis S2, and the first central axis S1 does not coincide with the second central axis S2. By arranging the first conductive plug 115 and the second conductive plug 116 staggered along the first direction X, the exposure window for forming the first conductive plug 115 and the second conductive plug 116 can be further increased, and thus the volume of the first conductive plug 115 and the second conductive plug 116 can be increased to improve the electrical conduction performance.

[0141] In the present embodiment, the logic circuit wafer 200 is electrically connected with the bit line layer 112 through a plurality of third conductive plugs 117.

[0142] In the present embodiment, the capacitor structure 120 includes a pillar capacitor (as shown in Figure 40 ), a cup capacitor (as shown in Figure 41 ) or a cylinder capacitor (as shown in Figure 42 ).

[0143] In the present embodiment, each capacitor structure 120 is electrically connected with the corresponding second source-drain doped layer 119 through a fourth conductive plug 121.

[0144] In other embodiments, the capacitor structure 120 can also be directly electrically connected with the corresponding second source-drain doped layer 119.

[0145] In this embodiment, the two mutually separated word line gate structures 118 are also located on the sidewalls opposite to each other along the second direction Y of the word line gate trench; and the two second conductive plugs 116 electrically connected with the two mutually separated word line gate structures 118 respectively are distributed on the two sides opposite to each other along the second direction Y of the word line gate trench. In this way, the contact area between the second conductive plug 116 and the corresponding word line gate structure 118 is increased, and the electrical contact performance between the second conductive plug 116 and the corresponding word line gate structure 118 is improved.

[0146] In this embodiment, the projection of the second isolation structure 106 along the first direction X is located in the projection range of the word line gate structure 118 along the first direction X, so as to reduce the influence of the second isolation structure 106 on the adjacent storage unit when a negative voltage is applied.

[0147] Although the present application has been disclosed as above, it is not limited to the above. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various changes and modifications, and therefore the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A method for forming a dynamic random access memory architecture, characterized in that, include: A substrate is formed having a first surface and a second surface opposite to each other. The substrate includes a plurality of mutually discrete active regions parallel to a first direction, and the plurality of active regions are arranged along a second direction. A first isolation trench is provided between adjacent active regions. The first isolation trench extends along the first direction and is perpendicular to the second direction. Each active region includes a plurality of mutually discrete word line regions and isolation regions, and the word line regions and isolation regions in each active region are arranged at intervals along the first direction. A first isolation structure is formed within the first isolation trench; A first source / drain doped layer is formed in each of the active regions, and the first surface exposes the first source / drain doped layer; A word line grid trench is formed in each of the word line regions, and a second isolation trench is formed in each of the isolation regions. The word line grid trench and the second isolation trench extend from the first surface to the second surface, and the word line grid trench and the second isolation trench penetrate the active region along the second direction. A second isolation structure is formed within each of the second isolation trenches; An initial word line grid structure is formed within each of the word line grid trenches; After forming the second isolation structure and the initial word line gate structure, a plurality of bit line layers parallel to the first direction are formed on the first surface, and each bit line layer is electrically connected to a plurality of the first source and drain doped layers in the corresponding active region. After the bit line layer is formed, the substrate is subjected to a first thinning process from the second surface to the first surface. After the first thinning process, a portion of the initial word line grid structure is etched from the first surface to the second surface, such that the initial word line grid structure forms two mutually independent word line grid structures, with the two word line grid structures located on opposite sidewalls of the word line grid trench along the first direction. After the word line gate structure is formed, source and drain ions are implanted into the substrate from the second surface to the first surface to form a second source and drain doped layer in each active region, and the second surface exposes the second source and drain doped layer. After the second source / drain doped layer is formed, a plurality of capacitor structures are formed on the second surface, and each capacitor structure is electrically connected to a corresponding second source / drain doped layer.

2. The method for forming a dynamic random access memory architecture as described in claim 1, characterized in that, The second isolation structure is a conductive structure.

3. The method for forming the dynamic random access memory architecture as described in claim 2, characterized in that, Materials used in conductive structures include titanium nitride.

4. The method for forming a dynamic random access memory architecture as described in claim 1, characterized in that, The second isolation structure is an insulating structure.

5. The method for forming the dynamic random access memory architecture as described in claim 4, characterized in that, The materials used for insulating structures include silicon dioxide or air.

6. The method for forming a dynamic random access memory architecture as described in claim 1, characterized in that, The method of forming the initial word grid structure in each of the word grid trenches includes: forming a word grid material layer on the sidewall and bottom surface of the word grid trench; removing a portion of the word grid material layer located on the sidewall of the word grid trench to form a first cutting opening and a second cutting opening, so that the word grid material layer forms the initial word grid structure.

7. The method for forming a dynamic random access memory architecture as described in claim 6, characterized in that, The first cutting opening and the second cutting opening are respectively located in the initial word grid structure on the sidewalls of the word grid grooves arranged opposite each other along the first direction, and the first cutting opening and the second cutting opening are also respectively located on both sides of the initial word grid structure along the second direction.

8. The method for forming a dynamic random access memory architecture as described in claim 1, characterized in that, After the bit line layer is formed and before the first thinning process is performed, the method further includes: forming a bit line isolation structure between adjacent bit line layers.

9. The method for forming the dynamic random access memory architecture as described in claim 8, characterized in that, The bit line isolation structure is a cavity structure.

10. The method for forming a dynamic random access memory architecture as described in claim 1, characterized in that, The depth of the word line grid trench is less than the depth of the first isolation trench; the depth of the second isolation trench is less than the depth of the first isolation trench.

11. The method for forming the dynamic random access memory architecture as described in claim 10, characterized in that, The first thinning process continues until the first isolation structure is exposed.

12. The method for forming a dynamic random access memory architecture as described in claim 11, characterized in that, After forming the word line gate structure and before forming the second source / drain doped layer, the method further includes: performing a second thinning process on the substrate from the second surface toward the first surface, until at least the second isolation structure is exposed.

13. The method for forming a dynamic random access memory architecture as described in claim 1, characterized in that, The depth of the word line grid trench is equal to the depth of the first isolation trench; the depth of the second isolation trench is equal to the depth of the first isolation trench.

14. The method for forming the dynamic random access memory architecture as described in claim 13, characterized in that, The first thinning process continues until at least the first isolation structure, the second isolation structure, and the initial word line gate structure are exposed.

15. The method for forming a dynamic random access memory architecture as described in claim 1, characterized in that, After forming the bit line layer and before performing the first thinning process, the method further includes: providing a logic circuit wafer; bonding the logic circuit wafer to the substrate with the first surface, wherein the logic circuit wafer is electrically connected to the bit line layer and the initial word line gate structure, respectively.

16. The method for forming the dynamic random access memory architecture as described in claim 15, characterized in that, After the initial word line gate structure forms two mutually independent word line gate structures, the logic circuit wafer is electrically connected to the word line gate structure.

17. The method for forming a dynamic random access memory architecture as described in claim 16, characterized in that, The second isolation structure is a conductive structure, and the logic circuit wafer is also electrically connected to the second isolation structure.

18. The method for forming a dynamic random access memory architecture as described in claim 17, characterized in that, Along the first direction, a first conductive plug for electrically connecting the second isolation structure and the logic circuit wafer has a first central axis, and a second conductive plug for electrically connecting the initial word line gate structure and the logic circuit wafer has a second central axis, the first central axis coinciding with the second central axis.

19. The method for forming a dynamic random access memory architecture as described in claim 17, characterized in that, Along the first direction, a first conductive plug for electrically connecting the second isolation structure and the logic circuit wafer has a first central axis, and a second conductive plug for electrically connecting the initial word line gate structure and the logic circuit wafer has a second central axis, wherein the first central axis and the second central axis do not coincide.

20. The method for forming a dynamic random access memory architecture as described in claim 1, characterized in that, During the process of etching a portion of the initial word line grid structure from the first surface to the second surface, the method further includes etching a portion of the second isolation structure from the first surface to the second surface, such that the projection of the second isolation structure along the first direction is located within the projection range of the word line grid structure along the first direction.

21. A dynamic random access memory architecture, characterized in that, The dynamic random access memory architecture is formed using the method described in any one of claims 1 to 20, and the dynamic random access memory architecture includes: A substrate having a first surface and a second surface opposite to each other, the substrate including a plurality of mutually discrete active regions parallel to a first direction, and the plurality of active regions arranged along a second direction, a first isolation trench between adjacent active regions, the first isolation trench extending along the first direction, the first direction being perpendicular to the second direction, each active region including a plurality of mutually discrete word line regions and isolation regions, and the word line regions and isolation regions in each active region being spaced apart along the first direction; The first isolation structure located within the first isolation trench; A first source / drain doped layer is located within each of the active regions, and the first surface exposes the first source / drain doped layer; A word line grid trench is located within each of the word line regions, the word line grid trench extends from the first surface to the second surface, and the word line grid trench penetrates the active region along the second direction; A second isolation trench is located within each of the isolation zones, the second isolation trench extends from the first surface to the second surface, and the second isolation trench penetrates the active zone along the second direction; A second isolation structure located within each of the second isolation trenches; Two mutually independent word line grid structures are located within each word line grid groove, and the two word line grid structures are respectively located on the opposite sidewalls of the word line grid groove along the first direction; A plurality of bit line layers are located on the first surface parallel to the first direction, and each bit line layer is electrically connected to a plurality of first source / drain doped layers in a corresponding active region. A second source / drain doped layer is located within each of the active regions, and the second surface exposes the second source / drain doped layer; A plurality of capacitor structures are located on the second surface, each of the capacitor structures being electrically connected to a corresponding second source / drain doped layer.

22. The dynamic random access memory architecture as described in claim 21, characterized in that, The second isolation structure is a conductive structure.

23. The dynamic random access memory architecture as described in claim 22, characterized in that, Materials used in conductive structures include titanium nitride.

24. The dynamic random access memory architecture as described in claim 21, characterized in that, The second isolation structure is an insulating structure.

25. The dynamic random access memory architecture as described in claim 24, characterized in that, The materials used for insulating structures include silicon dioxide or air.

26. The dynamic random access memory architecture as described in claim 21, characterized in that, Also includes: Bit line isolation structure located between adjacent bit line layers.

27. The dynamic random access memory architecture as described in claim 26, characterized in that, The bit line isolation structure is a cavity structure.

28. The dynamic random access memory architecture as described in claim 21, characterized in that, Also includes: A logic circuit wafer, wherein the logic circuit wafer is bonded to the substrate with the first surface, and the logic circuit wafer is electrically connected to the bit line layer and the word line gate structure respectively.

29. The dynamic random access memory architecture as described in claim 28, characterized in that, The second isolation structure is a conductive structure, and the logic circuit wafer is also electrically connected to the second isolation structure.

30. The dynamic random access memory architecture as described in claim 28, characterized in that, Along the first direction, a first conductive plug for electrically connecting the second isolation structure and the logic circuit wafer has a first central axis, and a second conductive plug for electrically connecting the word line gate structure and the logic circuit wafer has a second central axis, wherein the first central axis coincides with the second central axis.

31. The dynamic random access memory architecture as described in claim 28, characterized in that, Along the first direction, a first conductive plug for electrically connecting the second isolation structure and the logic circuit wafer has a first central axis, and a second conductive plug for electrically connecting the word line gate structure and the logic circuit wafer has a second central axis, wherein the first central axis and the second central axis do not coincide.

32. The dynamic random access memory architecture as described in claim 30 or 31, characterized in that, Two mutually independent word grid structures are also located on the opposite sidewalls of the word grid groove along the second direction; two second conductive plugs, which are electrically connected to the two mutually independent word grid structures, are distributed on opposite sides of the word grid groove along the second direction.

33. The dynamic random access memory architecture as described in claim 21, characterized in that, The projection of the second isolation structure along the first direction is located within the projection range of the word line grid structure along the first direction.

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