Dynamic random access memory architecture and method of forming the same

Abstract

A dynamic random access memory architecture and a forming method thereof, wherein the forming method comprises: forming a substrate and a bit line layer, the substrate having opposite first and second surfaces, the substrate comprising a plurality of active regions, the active regions comprising a plurality of word line regions, the bit line layer being located on the first surface; forming a word line gate trench in each word line region; forming two mutually separate word line gate structures in each word line gate trench; performing a source-drain ion implantation process on the substrate from the second surface to the first surface to form a second source-drain doped layer in each active region; and forming a plurality of capacitor structures on the second surface. By placing the process of forming the capacitor structures at the end, it is ensured that the high-temperature process is normally used during the process before the capacitor structures are formed, without damaging the capacitor structures. The second source-drain doped layer is formed by implanting source-drain ions from the second surface to the first surface, which can effectively improve the uniformity of the distribution of source-drain ions in the second source-drain doped layer, thereby effectively improving the performance of the transistor.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and particularly relates to a dynamic random access memory architecture and a forming method thereof. BACKGROUND

[0002] With the rapid development of today's technology, semiconductor memories are widely used in electronic devices. Dynamic random access memory (DRAM) belongs to a volatile memory, and for the application of storing a large amount of data, dynamic random access memory is the most commonly used solution.

[0003] Generally, dynamic random access memory is composed of a plurality of memory cells, each of which is mainly composed of a transistor and a capacitor controlled by the transistor, and each of which is electrically connected to each other through a word line and a bit line.

[0004] However, the existing dynamic random access memory architecture still has many problems. SUMMARY

[0005] The technical problem solved by the present application is to provide a dynamic random access memory architecture and a forming method thereof, which ensures the normal use of high-temperature process and improves the performance of the transistor.

[0006] To solve the above problems, the technical scheme of the present application provides a forming method of a dynamic random access memory architecture, comprising: forming a substrate and a plurality of bit line layers, the substrate having opposite first and second surfaces, the substrate comprising a plurality of active regions separated from each other and parallel to a first direction, and the plurality of active regions being arranged along a second direction, each of the active regions having a first source-drain doped layer, the first surface exposing the first source-drain doped layer, the active regions being separated by a first isolation trench, the first isolation trench having a first isolation structure, the first isolation trench extending along the first direction, the first direction being perpendicular to the second direction, each of the active regions comprising a plurality of word line regions and isolation regions separated from each other and arranged along the first direction, and each of the active regions having the word line regions and the isolation regions separated along the first direction, the plurality of bit line layers being parallel to the first direction and located on the first surface, each of the bit line layers being electrically connected to a plurality of the first source-drain doped layers in a corresponding one of the active regions; after forming the substrate and the bit line layers, performing a thinning process on the substrate from the second surface to the first surface until the first isolation structure is exposed; after the thinning process, forming a word line gate trench in each of the word line regions and a second isolation trench in each of the isolation regions, the word line gate trench and the second isolation trench extending from the first surface to the second surface and penetrating the active regions along the second direction; forming a second isolation structure in each of the second isolation trenches; forming two word line gate structures in each of the word line gate trenches, the two word line gate structures being located on opposite sidewalls of the word line gate trench along the first direction; after forming the word line gate structures, performing a source-drain ion implantation process on the substrate from the second surface to the first surface to form a second source-drain doped layer in each of the active regions, the second surface exposing the second source-drain doped layer; after forming the second source-drain doped layer, forming a plurality of capacitor structures on the second surface, each of the capacitor structures being electrically connected to a corresponding one of the second source-drain doped layers.

[0007] Optionally, the second isolation structure is a conductive structure.

[0008] Optionally, the material of the conductive structure comprises titanium nitride.

[0009] Optionally, the second isolation structure is an insulating structure.

[0010] Optionally, the material of the insulating structure comprises silicon oxide or air.

[0011] Optionally, the method for forming the substrate and the plurality of bit line layers comprises: providing an initial substrate, the initial substrate having opposite first and second surfaces; performing a patterned etching process on the initial substrate to form a plurality of first isolation trenches, the active regions being between adjacent first isolation trenches; forming the first isolation structures in the first isolation trenches; after forming the isolation structures, forming the first source / drain doped layers in the active regions to form the substrate; and after forming the substrate, forming the plurality of bit line layers.

[0012] Optionally, the method for forming the bit line layers comprises: performing a metallization process on the first source / drain doped layers exposed by the first surface, so that part of the first source / drain doped layers forms a metal silicide layer, and the metal silicide layer is used as the bit line layer.

[0013] Optionally, after forming the substrate and before forming the bit line layers, the method further comprises: etching part of the first isolation structures from the first surface to the second surface to form bit line isolation grooves between adjacent active regions; and forming bit line isolation structures in the bit line isolation grooves.

[0014] Optionally, the method for forming the substrate and the plurality of bit line layers comprises: providing an initial substrate, the initial substrate having opposite first and second surfaces; forming the first source / drain doped layers in the initial substrate; after forming the source / drain doped layers, forming a bit line material layer on the first surface; performing a patterned etching process on the bit line material layer and the initial substrate to form a plurality of first isolation trenches, the active regions being between adjacent first isolation trenches, and the bit line material layer forming the bit line layers; and after the patterned etching process, forming the first isolation structures in the first isolation trenches to form the substrate.

[0015] Optionally, after forming the substrate and the bit line layers, the method further comprises: etching part of the first isolation structures from the first surface to the second surface to form bit line isolation grooves between adjacent active regions; and forming bit line isolation structures in the bit line isolation grooves.

[0016] Optionally, the bit line isolation structures are cavity structures.

[0017] Optionally, after forming the bit line layers and before performing the thinning process, the method further comprises: providing a logic circuit wafer; and bonding the logic circuit wafer to the substrate towards the first surface, the logic circuit wafer being electrically connected to the bit line layers, respectively.

[0018] Optionally, after forming the word line gate structures, the logic circuit wafer is electrically connected to the word line gate structures.

[0019] Optionally, the method that the logic circuit wafer is electrically connected with the word line gate structure comprises: forming a plurality of first conductive plugs before bonding the logic circuit wafer and the substrate, the first conductive plugs being electrically connected with corresponding word line gate structures after forming the word line gate structure; after bonding the logic circuit wafer and the substrate, the logic circuit wafer is electrically connected with the first conductive plugs.

[0020] Optionally, the second isolation structure is a conductive structure, and the logic circuit wafer is electrically connected with the second isolation structure after forming the second isolation structure.

[0021] Optionally, the method that the logic circuit wafer is electrically connected with the second isolation structure respectively comprises: forming a plurality of second conductive plugs before bonding the logic circuit wafer and the substrate, the second conductive plugs being electrically connected with corresponding second isolation structures after forming the second isolation structure; after bonding the logic circuit wafer and the substrate, the logic circuit wafer is electrically connected with the second conductive plugs.

[0022] Optionally, along the first direction, the first conductive plugs have first central axes, and the second conductive plugs have second central axes, and the first central axes coincide with the second central axes.

[0023] Optionally, along the first direction, the first conductive plugs have first central axes, and the second conductive plugs have second central axes, and the first central axes do not coincide with the second central axes.

[0024] Optionally, the two mutually separate word line gate structures are also located on the sidewalls of the word line gate trench opposite along the second direction; and the two first conductive plugs electrically connected with the two mutually separate word line gate structures are distributed on the two sides of the word line gate trench opposite along the second direction.

[0025] Optionally, a projection of the second isolation structure along the first direction is located within a projection range of the word line gate structure along the first direction.

[0026] Correspondingly, the technical scheme of the present application also provides a dynamic random access memory architecture formed by the forming method of any one of the technical schemes, the dynamic random access memory architecture comprising: a substrate having opposite first and second surfaces, the substrate comprising a plurality of active regions separated from each other and parallel to a first direction, and the plurality of active regions being arranged along a second direction, the active regions being separated from each other by first isolation grooves, the first isolation grooves extending along the first direction, the first direction being perpendicular to the second direction, each of the active regions comprising a plurality of word line regions and isolation regions separated from each other and arranged along the first direction; a first isolation structure located in the first isolation groove; a first source / drain doped layer located in each of the active regions, the first surface exposing the first source / drain doped layer; a word line gate trench located in each of the word line regions, the word line gate trench extending from the first surface to the second surface and penetrating the active region along the second direction; a second isolation groove located in each of the isolation regions, the second isolation groove extending from the first surface to the second surface and penetrating the active region along the second direction; a second isolation structure located in each of the second isolation grooves; two word line gate structures located in each of the word line gate trenches, the two word line gate structures being located on opposite sidewalls of the word line gate trench along the first direction; a plurality of bit line layers parallel to the first direction located on the first surface, each of the bit line layers being electrically connected to the plurality of first source / drain doped layers in the corresponding active region; a second source / drain doped layer located in each of the active regions, the second surface exposing the second source / drain doped layer; and a plurality of capacitor structures located on the second surface, each of the capacitor structures being electrically connected to the corresponding second source / drain doped layer.

[0027] Optionally, the second isolation structure is a conductive structure.

[0028] Optionally, the material of the conductive structure comprises titanium nitride.

[0029] Optionally, the second isolation structure is an insulating structure.

[0030] Optionally, the material of the insulating structure comprises silicon oxide or air.

[0031] Optionally, the dynamic random access memory architecture further comprises a bit line isolation structure located between adjacent bit line layers.

[0032] Optionally, the bit line isolation structure is a cavity structure.

[0033] Optionally, the memory device further comprises a logic circuit wafer, the logic circuit wafer is bonded to the substrate towards the first surface, and the logic circuit wafer is electrically connected to the bit line layer and the word line gate structure respectively.

[0034] Optionally, the second isolation structure is a conductive structure, and the logic circuit wafer is electrically connected to the second isolation structure.

[0035] Optionally, along the first direction, a first conductive plug for electrically connecting the word line gate structure and the logic circuit wafer has a first central axis, and a second conductive plug for electrically connecting the second isolation structure and the logic circuit wafer has a second central axis, and the first central axis coincides with the second central axis.

[0036] Optionally, along the first direction, a first conductive plug for electrically connecting the word line gate structure and the logic circuit wafer has a first central axis, and a second conductive plug for electrically connecting the second isolation structure and the logic circuit wafer has a second central axis, and the first central axis does not coincide with the second central axis.

[0037] Optionally, the two mutually separated word line gate structures are also located on the sidewalls of the word line gate trench opposite to each other along the second direction, and the two first conductive plugs electrically connected to the two mutually separated word line gate structures are distributed on the two sides of the word line gate trench opposite to each other along the second direction.

[0038] Optionally, a projection of the second isolation structure along the first direction is located within a projection range of the word line gate structure along the first direction.

[0039] Compared with the prior art, the technical scheme of the present application has the following advantages:

[0040] In the forming method of the dynamic random access memory architecture, the process of forming the capacitor structure is placed at the end, so that the high-temperature process can be normally used in the process before the capacitor structure is formed, without damaging the capacitor structure. In addition, the second source-drain doped layer is formed by implanting source-drain ions from the second surface to the first surface, which can effectively improve the uniformity of the distribution of source-drain ions in the second source-drain doped layer, thereby effectively improving the performance of the transistor.

[0041] Further, the second isolation structure is a conductive structure. By applying a negative voltage to the second isolation structure, adjacent memory cells arranged along the first direction can be effectively isolated, thereby reducing the impact of row hammer effect on the memory cells.

[0042] Further, the bit line isolation structure is a cavity structure.

[0043] Further, along the first direction, the first conductive plug has a first central axis, and the second conductive plug has a second central axis, and the first central axis and the second central axis do not coincide. By arranging the first conductive plug and the second conductive plug staggered along the first direction, the exposure window for forming the first conductive plug and the second conductive plug can be further increased, thereby increasing the volume of the first conductive plug and the second conductive plug to improve the electrical conduction performance.

[0044] Further, the two mutually separate word line gate structures are also located on the side walls of the word line gate groove opposite along the second direction; and the two first conductive plugs electrically connected with the two mutually separate word line gate structures are distributed on the two sides of the word line gate groove opposite along the second direction. In this way, the contact area between the first conductive plug and the corresponding word line gate structure is increased, and the electrical contact performance between the first conductive plug and the corresponding word line gate structure is improved.

[0045] Further, a projection of the second isolation structure along the first direction is located in the projection range of the word line gate structure along the first direction, so as to reduce the influence of the second isolation structure on adjacent storage units when a negative voltage is applied.

[0046] In the dynamic random access memory architecture of the technical scheme of the present application, by placing the process of forming the capacitor structure at the end, it can be ensured that the high temperature process is normally used in the process before the capacitor structure is formed, without damaging the capacitor structure. In addition, the second source-drain doping layer is formed by implanting source-drain ions from the second surface to the first surface, which can effectively improve the uniformity of the distribution of source-drain ions in the second source-drain doping layer, thereby effectively improving the performance of the transistor.

[0047] Further, the second isolation structure is a conductive structure. By applying a negative voltage to the second isolation structure, adjacent storage units arranged along the first direction can be effectively isolated, thereby reducing the influence of row hammer effect on the storage units.

[0048] Further, the bit line isolation structure is a cavity structure. The cavity structure has a strong electrical isolation effect, thereby effectively reducing the crosstalk between adjacent bit line layers.

[0049] Further, along the first direction, the first conductive plug has a first central axis, and the second conductive plug has a second central axis, the first central axis and the second central axis are not coincident. By arranging the first conductive plug and the second conductive plug staggered along the first direction, the exposure window for forming the first conductive plug and the second conductive plug can be further increased, and thus the volume of the first conductive plug and the second conductive plug can be increased to improve the electrical conduction performance.

[0050] Further, the two mutually separate word line gate structures are also located on the side walls of the word line gate trench opposite along the second direction; and the two first conductive plugs electrically connected with the two mutually separate word line gate structures are distributed on the two sides of the word line gate trench opposite along the second direction. In this way, the contact area between the first conductive plug and the corresponding word line gate structure is increased, and the electrical contact performance between the first conductive plug and the corresponding word line gate structure is improved.

[0051] Further, the projection of the second isolation structure along the first direction is located in the projection range of the word line gate structure along the first direction, so as to reduce the influence of the second isolation structure on the adjacent storage unit when a negative voltage is applied. BRIEF DESCRIPTION OF DRAWINGS

[0052] Figures 1-30 is a structure schematic diagram of each step of a forming method of a dynamic random access memory architecture of an embodiment of the present application;

[0053] Figure 31 is a structure schematic diagram of a pillar-shaped capacitor in a dynamic random access memory architecture of an embodiment of the present application;

[0054] Figure 32 is a structure schematic diagram of a cup-shaped capacitor in a dynamic random access memory architecture of an embodiment of the present application;

[0055] Figure 33 is a structure schematic diagram of a cylinder-shaped capacitor in a dynamic random access memory architecture of an embodiment of the present application;

[0056] Figures 34-38 is a structure schematic diagram of each step of a forming method of a substrate and a bit line layer of a dynamic random access memory architecture in another embodiment of the present application;

[0057] Figure 39 is a distribution schematic diagram of a first conductive plug and a second conductive plug in a dynamic random access memory architecture of another embodiment of the present application. DETAILED DESCRIPTION

[0058] As described in the background, the existing dynamic random access memory architecture still has many problems. The following will be specifically described.

[0059] The prior art dynamic random access memory architecture is to make the capacitor structure first, then make the back process, thereby causing that high temperature process cannot be used in the back process, otherwise the high-K dielectric layer in the capacitor structure will be affected, thereby causing the failure of the capacitor structure. In addition, the back source-drain doped layer in the dynamic random access memory architecture is formed by ion implantation from the front surface, which easily causes poor ion distribution uniformity in the transistor, thereby reducing the performance of the transistor.

[0060] On this basis, the application provides a dynamic random access memory architecture and a forming method thereof. By placing the process of forming the capacitor structure at the end, the high temperature process can be normally used in the process before forming the capacitor structure, without damaging the capacitor structure. In addition, the second source-drain doped layer is formed by implanting source-drain ions from the second surface to the first surface, which can effectively improve the distribution uniformity of the source-drain ions in the second source-drain doped layer, thereby effectively improving the performance of the transistor.

[0061] In order to make the above-mentioned objects, features and advantages of the application more obvious and easy to understand, the specific embodiments of the application will be described in detail below with reference to the drawings.

[0062] Figures 1-30 is a forming method of a dynamic random access memory architecture according to an embodiment of the application; Figure 31 is a structure diagram of a pillar capacitor in the dynamic random access memory architecture according to an embodiment of the application; Figure 32 is a structure diagram of a cup capacitor in the dynamic random access memory architecture according to an embodiment of the application; Figure 33 is a structure diagram of a cylinder capacitor in the dynamic random access memory architecture according to an embodiment of the application; Figure 39 is a distribution diagram of the first conductive plug and the second conductive plug in the dynamic random access memory architecture according to another embodiment of the application.

[0063] Forming a substrate and a plurality of bit line layers, the substrate has opposite first and second faces, the substrate comprises a plurality of active regions which are mutually separated and parallel to a first direction, and the plurality of active regions are arranged along a second direction, each of the active regions has a first source-drain doped layer, the first face exposes the first source-drain doped layer, the active regions are separated by a first isolation trench, the first isolation trench has a first isolation structure, the first isolation trench extends along the first direction, and the first direction is perpendicular to the second direction, each of the active regions comprises a plurality of word line regions and isolation regions which are spaced apart along the first direction, and the plurality of bit line layers are parallel to the first direction on the first face, and each of the bit line layers is electrically connected to the plurality of first source-drain doped layers in the corresponding active region. The specific forming process of the substrate and the bit line layers can refer to Figures 1-7 .

[0064] Please refer to Figures 1-3 , Figure 2 is Figure 1 along the A-A line in FIG. 1, Figure 3 is Figure 1 along the B-B line in FIG. 1, an initial substrate 100 is provided, the initial substrate 100 has opposite first and second faces 100a and 100b; the initial substrate 100 is subjected to a patterned etching process to form a plurality of first isolation trenches 101, and the active regions 102 are formed between adjacent first isolation trenches 101.

[0065] In the embodiment, the plurality of active regions 102 extend along the first direction X and are arranged in parallel along the second direction Y, and the first direction X is perpendicular to the second direction Y.

[0066] In the embodiment, the word line regions 1021 and the isolation regions 1022 in each of the active regions 102 are spaced apart along the first direction X.

[0067] In the embodiment, the material of the initial substrate 100 is silicon.

[0068] In other embodiments, the material of the initial substrate 100 can also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

[0069] It should be noted that, in the embodiment, the first face 100a is the front face of the memory cell in the finally formed dynamic random access memory architecture, and the second face 100b is the back face of the memory cell in the finally formed dynamic random access memory architecture.

[0070] Please refer to Figure 4 andFigure 5 , Figure 5 is Figure 4 A cross-sectional view along the line C-C in the first isolation trench 101 in which the first isolation structure 103 is formed.

[0071] In this embodiment, the method for forming the first isolation structure 103 includes: depositing an isolation material layer (not shown) which fills the first isolation trench 101 and is on the first surface 100a, planarizing the isolation material layer until the first surface 100a of the substrate is exposed, and forming the first isolation structure 103.

[0072] In this embodiment, the material of the first isolation structure 103 is silicon oxide.

[0073] Please refer to Figure 6 , Figure 6 and Figure 5 The view direction is consistent, and after the first isolation structure 103 is formed, the first source / drain doped layer 104 is formed in each of the active regions 102, and the first surface 100a exposes the first source / drain doped layer 104.

[0074] In this embodiment, the method for forming the first source / drain doped layer 104 includes: implanting source / drain ions from the first surface 100a to the second surface 100b, and annealing the implanted source / drain ions to form the first source / drain doped layer 104 in the active region 102.

[0075] From this, the substrate 105 is formed.

[0076] Please refer to Figure 7 After the substrate 105 is formed, the bit line layer 106 is formed.

[0077] In this embodiment, the method for forming the bit line layer 106 includes: metallizing the first source / drain doped layer 104 exposed by the first surface 100a, so that part of the first source / drain doped layer 104 forms a metal silicide layer, and using the metal silicide layer as the bit line layer 106. By directly using the metal silicide layer as the bit line layer 106, the contact resistance between the bit line layer 106 and the first source / drain doped layer 104 can be effectively reduced.

[0078] In the embodiment, after forming the substrate 105 and before forming the bit line layer 106, further comprising: etching part of the first isolation structure 103 from the first surface 100a to the second surface 100b to form a bit line isolation groove (not shown) between adjacent active regions 102; and forming a bit line isolation structure 107 in the bit line isolation groove.

[0079] In the embodiment, the bit line isolation structure 107 is a cavity structure. The cavity structure is formed by adjusting the parameters of the deposition process so that the deposited silicon oxide material seals the opening between adjacent bit line layers 106, thereby forming a cavity structure between adjacent bit line layers 106. The cavity structure has a strong electrical isolation effect, thereby effectively reducing the crosstalk between adjacent bit line layers 106.

[0080] Please refer to Figures 8-12 , Figure 8 is a top view of a logic circuit wafer, Figure 9 is Figure 8 is a cross-sectional view along line D-D in Figure 10 is Figure 8 is a cross-sectional view along line E-E in Figure 11 is Figure 8 is a cross-sectional view along line F-F in Figure 12 is Figure 8 is a cross-sectional view along line G-G in

[0081] It should be noted that in the embodiment, the logic circuit wafer 200 is bonded for logic control of read, write, refresh and other operations of each memory cell.

[0082] In the embodiment, a plurality of first conductive plugs 108 are formed before bonding the logic circuit wafer 200 and the substrate 105. After forming the word line gate structure in the subsequent process, the first conductive plugs 108 are used to electrically connect with the corresponding word line gate structure. After bonding the logic circuit wafer 200 and the substrate 105, the logic circuit wafer 200 is electrically connected with the first conductive plugs 108.

[0083] In the embodiment, before the bonding of the logic circuit wafer 200 and the substrate 105, a plurality of second conductive plugs 109 are formed, and after the formation of the second isolation structure in the subsequent process, the second conductive plugs 109 are electrically connected with the corresponding second isolation structure; after the bonding of the logic circuit wafer 200 and the substrate 105, the logic circuit wafer 200 is electrically connected with the second conductive plugs 109.

[0084] In the embodiment, the method for electrically connecting the logic circuit wafer 200 with the bit line layer 106 respectively includes: before the bonding of the logic circuit wafer 200 and the substrate 105, a plurality of third conductive plugs 110 are formed, and the third conductive plugs 110 are electrically connected with the corresponding bit line layer 106; after the bonding of the logic circuit wafer 200 and the substrate 105, the logic circuit wafer 200 is electrically connected with the third conductive plugs 110.

[0085] In the embodiment, along the first direction X, the first conductive plug 108 has a first central axis S1, and the second conductive plug 109 has a second central axis S2, and the first central axis S1 coincides with the second central axis S2.

[0086] Please refer to Figure 39 In other embodiments, along the first direction X, the first conductive plug 108 has a first central axis S1, and the second conductive plug 109 has a second central axis S2, and the first central axis S1 does not coincide with the second central axis S2. By arranging the first conductive plug 108 and the second conductive plug 109 staggered along the first direction X, the exposure window for forming the first conductive plug 108 and the second conductive plug 109 can be further increased, and thus the volume of the first conductive plug 108 and the second conductive plug 109 can be increased to improve the electrical conduction performance.

[0087] In the embodiment, after the bonding of the first surface 100a (i.e. the front surface) of the substrate 105 and the logic circuit wafer 200, when the process of the second surface 100b (i.e. the back surface) of the substrate 105 is performed, there is no need to additionally provide a temporary wafer to support the back surface process of the substrate 105, and the back surface process of the substrate 105 can be supported by the logic circuit wafer 200, so that the process support can be simplified and the production cost can be reduced.

[0088] Please refer to Figures 13-16 , Figure 14 is Figure 13 the cross-sectional view along the H-H line in FIG. 8, Figure 15 is Figure 13 the cross-sectional view along the I-I line in FIG. 8, Figure 16is Figure 13 Fig. 2 is a cross-sectional view along line J-J of Fig. 1, showing a thinning process of the substrate 105 after the bonding of the logic circuit wafer 200 and the substrate 105, until the first isolation structure 103 is exposed.

[0089] The thinning process includes a physical mechanical polishing process, a chemical mechanical polishing process, or a wet etching process.

[0090] In this embodiment, the thinning process uses a chemical mechanical polishing process.

[0091] Please refer to Figures 17-19 , Figure 18 is Figure 17 Fig. 3 is a cross-sectional view along line K-K of Fig. 2, Figure 19 is Figure 17 Fig. 4 is a cross-sectional view along line L-L of Fig. 3, showing a formation of word line gate trenches (not shown) in each of the word line regions 1021 and a formation of second isolation trenches (not shown) in each of the isolation regions 1022 after the thinning process, the word line gate trenches and the second isolation trenches extending from the first surface 100a to the second surface 100b, and the word line gate trenches and the second isolation trenches penetrating the active region 102 along the second direction Y.

[0092] In this embodiment, the formation of the word line gate trenches and the second isolation trenches includes forming a patterned layer (not shown) on the substrate 105, etching the word line regions 1021 and the first isolation structure 103 of the active region 102 with the patterned layer as a mask to form the word line gate trenches, and etching the isolation regions 1022 and the first isolation structure 103 of the active region 102 with the second patterned layer as a mask to form the second isolation trenches.

[0093] It is noted that in this embodiment, the formed word line gate trenches need to expose the corresponding first conductive plugs 108, so that the word line gate structures subsequently formed in the word line gate trenches can be electrically connected with the first conductive plugs 108. The formed second isolation trenches need to expose the corresponding second conductive plugs 109, so that the second isolation structures subsequently formed in the second isolation trenches can be electrically connected with the second conductive plugs 109.

[0094] Please continue to refer to Figures 17-19 After the formation of the word line gate trenches and the second isolation trenches, the word line gate trenches and the second isolation trenches are filled with a sacrificial layer 111.

[0095] It should be noted that in the embodiment, the word line gate trench and the second isolation trench are filled with the sacrificial layer 111, and then the sacrificial layer 111 in the corresponding trench is removed in the subsequent process to form the required device structure.

[0096] In the embodiment, the material of the sacrificial layer 111 is spin-on carbon.

[0097] Please refer to Figure 20 and Figure 21 , Figure 20 and Figure 18 The view direction of Figure 21 and Figure 19 is consistent, and after the formation of the sacrificial layer 111, a second isolation structure 112 is formed in each of the second isolation trenches.

[0098] It should be noted that in the embodiment, the sacrificial layer 111 filled in the second isolation trench needs to be removed before the formation of the second isolation structure 112.

[0099] In the embodiment, the second isolation structure 112 is a conductive structure, and the material of the conductive structure is titanium nitride. Since the second isolation structure 112 is a conductive structure, a negative voltage can be applied to the second isolation structure 112 by the logic circuit wafer 200, so that the second isolation structure 112 can effectively isolate the adjacent storage units arranged along the first direction X, thereby reducing the impact of row hammer effect on the storage units.

[0100] It is to be noted that, in this embodiment, before forming the second isolation structure 112, a compact oxide layer (not shown) is formed on the surface of the second isolation trench to repair the surface of the second isolation trench, and then insulating material is filled in the second isolation trench to raise the second isolation structure 112, so as to ensure that the projection of the second isolation structure 112 along the first direction X is located in the projection range of the word line gate structure along the first direction X. The second isolation structure 112 is formed next, and the second isolation structure 112 does not fill the second isolation trench, so that the second isolation structure 112 is electrically connected with the corresponding second conductive plug 109, and thus the second isolation structure 112 is electrically connected with the logic circuit wafer 200. After forming the second isolation structure 112, a protective layer 113 is formed on the second isolation structure 112 to fill the second isolation trench. The purpose of not filling the second isolation trench with the second isolation structure 112 is to reduce the height of the second isolation structure 112, so that the height of the second isolation structure 112 towards the first surface 100a cannot be higher than the height of the subsequently formed initial word line gate structure towards the first surface 100a, so as to ensure that the projection of the second isolation structure 112 along the first direction X is located in the projection range of the word line gate structure along the first direction X.

[0101] In this embodiment, the insulating material deposited at the bottom of the second isolation trench is silicon oxide, and the material of the protective layer 113 is silicon nitride.

[0102] In other embodiments, the second isolation structure 112 can also be an insulating structure, and the material of the insulating structure can be silicon oxide or air. When the insulating structure is silicon oxide, only silicon oxide material needs to be deposited to fill the second isolation trench; when the insulating structure is air, by adjusting the parameters of the deposition process, the deposited material seals the opening of the second isolation trench, and the inside of the second isolation trench is air. The insulating isolation effect of air is strong, which can effectively improve the isolation effect of the second isolation structure 112.

[0103] Please refer to Figures 22-24 , Figure 23 is Figure 22 is a cross-sectional view along the M-M line in Figure 24 is Figure 17 is a cross-sectional view along the N-N line in

[0104] It is to be noted that, in the embodiment, before the word line gate structure 114 is formed, the sacrificial layer 111 filled in the word line gate trench needs to be removed, and the word line gate trench also needs to be extended to increase the volume of the word line gate trench.

[0105] Please continue to refer to Figure 22 In the embodiment, the method for forming the initial word line gate structure 114 in each word line gate trench includes: forming a word line gate dielectric material layer (not shown) on the sidewall and bottom surface of the word line gate trench; removing the word line gate dielectric material layer on the bottom surface of the word line gate trench; forming a word line gate material layer (not shown) on the surface of the word line gate dielectric material layer and the exposed bottom surface of the word line gate trench; removing the word line gate material layer on the bottom surface of the word line gate trench; and removing part of the word line gate material layer on the sidewall of the word line gate trench to form a first cut-off opening 115 and a second cut-off opening 116, thereby forming two separate word line gate structures 114.

[0106] Please continue to refer to Figure 22 In the embodiment, the two separate word line gate structures 114 are also located on the sidewalls of the word line gate trench opposite to each other along the second direction Y, and the two first conductive plugs 108 electrically connected to the two separate word line gate structures 114 are distributed on the two sides of the word line gate trench opposite to each other along the second direction Y. In this way, the contact area between the first conductive plug 108 and the corresponding word line gate structure 114 is increased, and the electrical contact performance between the first conductive plug 108 and the corresponding word line gate structure 114 is improved.

[0107] In the embodiment, the logic circuit wafer 200 is electrically connected to the word line gate structure 114 through the first conductive plug 108.

[0108] It is to be noted that, in the embodiment, before the word line gate structure 114 is formed, a dense oxide layer (not shown) is formed on the surface of the word line gate trench to repair the surface of the word line gate trench. After the word line gate structure 114 is formed, the word line gate trench is filled with insulating material again. Moreover, the insulating material filled in the word line gate trench needs to have a large etching selectivity with the material filled in the protection layer 113 of the second isolation trench, so as to prevent the etching damage to the protection layer 113 and the exposure of the second isolation structure 112 when the insulating material filled in the word line gate trench is etched back.

[0109] In the embodiment, the material of the word line gate dielectric material layer is silicon oxide, and the material of the word line gate material layer is titanium nitride or tungsten.

[0110] In the embodiment, the second isolation structure 112 is formed finally, and the projection of the second isolation structure 112 along the first direction X is located in the projection range of the word line gate structure 114 along the first direction X, so as to reduce the influence of the second isolation structure 112 on the adjacent storage unit when a negative voltage is applied. After wet etching, insulating material is deposited to fill the word line gate trench and the second isolation trench.

[0111] In the embodiment, the second isolation structure 112 is formed first, and then the initial word line gate structure 114 is formed.

[0112] In other embodiments, the initial word line gate structure 114 can also be formed first, and then the second isolation structure 112 is formed.

[0113] Please refer to Figures 25-26 , Figure 25 is a top view of omitting the insulating material filled in the top of the word line gate trench and omitting the protective layer 113 filled in the second isolation trench; Figure 26 is Figure 25 is a sectional view along the O-O line in FIG. 11, after the word line gate structure 114 is formed, the substrate 105 is subjected to a source-drain ion implantation process from the second surface 100b to the first surface 100a, and the second source-drain doped layer 117 is formed in each active region 102, and the second surface 100b exposes the second source-drain doped layer 117.

[0114] The second source-drain doped layer 117 is formed by implanting source-drain ions from the second surface 100b to the first surface 100a, which can effectively improve the uniformity of the distribution of source-drain ions in the second source-drain doped layer 117, and further effectively improve the performance of the transistor.

[0115] In the embodiment, after implanting the source-drain ions, an annealing process of the source-drain ions is further needed, and then the second source-drain doped layer 117 is formed.

[0116] Please refer to Figures 27-30 , Figure 27 is a top view of omitting the insulating material filled in the top of the word line gate trench and omitting the protective layer 113 filled in the second isolation trench, Figure 28 is Figure 27 is a sectional view along the P-P line in FIG. 12, Figure 29 is Figure 27 is a sectional view along the Q-Q line in FIG. 13, Figure 30 is Figure 27 is a sectional view along the R-R line in FIG. 14, after the second source-drain doped layer 117 is formed, a plurality of capacitor structures 118 are formed on the second surface 100b, and each capacitor structure 118 is electrically connected to a corresponding one of the second source-drain doped layers 117.

[0117] By placing the process of forming the capacitor structure 118 at the end, it can be ensured that the high temperature process is normally used during the process before the capacitor structure 118 is formed, without damaging the capacitor structure 118.

[0118] In the embodiment, the capacitor structure 118 includes a pillar capacitor (as shown in Figure 31 , a cup capacitor (as shown in Figure 32 , or a cylinder capacitor (as shown in Figure 33 ).

[0119] In the embodiment, before the capacitor structure 118 is formed, a fourth conductive plug 119 is formed on the exposed second source-drain doped layer 117, and the capacitor structure 118 is electrically connected to the corresponding fourth conductive plug 119.

[0120] In other embodiments, the capacitor structure 118 can also be directly electrically connected to the corresponding second source-drain doped layer 117.

[0121] Figures 34-38 is a schematic structural view of each step of the method for forming the substrate 105 and the bit line layer 106 of the dynamic random access memory architecture in another embodiment of the application.

[0122] Please refer to Figure 34 and Figure 35 , Figure 35 is Figure 34 a schematic view along the A-A line section, providing an initial substrate 300, the initial substrate 300 having opposite first and second surfaces 300a and 300b.

[0123] In the embodiment, the material of the initial substrate 300 is silicon.

[0124] In other embodiments, the material of the initial substrate 300 can also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

[0125] Please refer to Figure 36 , Figure 36 and Figure 35 , the first source-drain doped layer 301 is formed in the initial substrate 300.

[0126] In the embodiment, the method for forming the first source-drain doped layer 301 includes: performing a source-drain ion implantation process on the substrate 105 from the first surface 300a to the second surface 300b, and performing an annealing process on the implanted source-drain ions, to form the first source-drain doped layer 301 in the active region 102.

[0127] Please refer to Figure 37 After forming the first source-drain doped layer 301, a bit line material layer (not shown) is formed on the first surface 300a; the bit line material layer and the initial substrate 300 are subjected to a patterned etching process to form a plurality of first isolation trenches 302, the active region 303 between adjacent first isolation trenches 302, and the bit line material layer forms the bit line layer 304.

[0128] Please refer to Figure 38 After the patterned etching process, the first isolation structure 305 is formed in the first isolation trench 302, and the substrate 306 is formed.

[0129] In the embodiment, the method for forming the first isolation structure 305 includes: depositing an isolation material layer (not shown) that fills the first isolation trench 302 and is on the first surface 300a; performing a planarization process on the isolation material layer until the first surface 300a of the substrate 306 is exposed to form the first isolation structure 305.

[0130] Please refer to Figure 38 In the embodiment, after forming the substrate 306 and the bit line layer 304, the method further includes: etching part of the first isolation structure 305 from the first surface 300a to the second surface 300b to form a bit line isolation groove between adjacent active regions 303; and forming a bit line isolation structure 307 in the bit line isolation groove.

[0131] In the embodiment, the bit line isolation structure 307 is a cavity structure. The specific formation process is to adjust the parameters of the deposition process so that the deposited silicon oxide material seals the opening between adjacent bit line layers 304, thereby forming a cavity structure between adjacent bit line layers 304. The cavity structure has a strong electrical isolation effect, thereby effectively reducing the crosstalk between adjacent bit line layers 304.

[0132] Correspondingly, the embodiment of the application also provides a dynamic random access memory architecture, please refer to Figures 27-30The dynamic random access memory architecture is formed by the forming method of any one of the above embodiments, and comprises: a substrate 105 having opposite first and second surfaces 100a and 100b, the substrate 105 comprising a plurality of active regions 102 separated from each other and parallel to a first direction X, and the plurality of active regions 102 being arranged along a second direction Y, and a first isolation groove 101 being between adjacent active regions 102 and extending along the first direction X, the first direction X being perpendicular to the second direction Y, each active region 102 comprising a plurality of word line regions 1021 and isolation regions 1022 separated from each other and arranged along the first direction X; a first isolation structure 103 in the first isolation groove 101; a first source / drain doped layer 104 in each active region 102, the first surface 100a exposing the first source / drain doped layer 104; a word line gate trench in each word line region 1021, the word line gate trench extending from the first surface 100a to the second surface 100b and penetrating the active region 102 along the second direction Y; a second isolation groove in each isolation region 1022, the second isolation groove extending from the first surface 100a to the second surface 100b and penetrating the active region 102 along the second direction Y; a second isolation structure 112 in each second isolation groove; two word line gate structures 114 separated from each other in each word line gate trench, the two word line gate structures 114 being located on opposite sidewalls of the word line gate trench along the first direction X; a plurality of bit line layers 106 parallel to the first direction X on the first surface 100a, each bit line layer 106 being electrically connected to a plurality of first source / drain doped layers 104 in a corresponding active region 102; a second source / drain doped layer 117 in each active region 102, the second surface 100b exposing the second source / drain doped layer 117; and a plurality of capacitor structures 118 on the second surface 100b, each capacitor structure 118 being electrically connected to a corresponding second source / drain doped layer 117.

[0133] By placing the process of forming the capacitor structures 118 at the end, it can be ensured that the high-temperature process is normally used during the process before the capacitor structures 118 are formed, without damaging the capacitor structures 118. In addition, the second source / drain doped layer 117 is formed by implanting source / drain ions from the second surface 100b to the first surface 100a, which can effectively improve the uniformity of the distribution of source / drain ions in the second source / drain doped layer 117, thereby effectively improving the performance of the transistor.

[0134] In the embodiment, the second isolation structure 112 is a conductive structure, and the material of the conductive structure is titanium nitride. Since the second isolation structure 112 is a conductive structure, a negative voltage can be applied to the second isolation structure 112, so that the second isolation structure 112 can effectively isolate adjacent memory cells arranged along the first direction X, thereby reducing the impact of row hammer on the memory cells.

[0135] In other embodiments, the second isolation structure 112 can also be an insulating structure, and the material of the insulating structure can be silicon oxide or air. When the insulating structure is silicon oxide, only the silicon oxide material needs to be deposited to fill the second isolation trench; when the insulating structure is air, by adjusting the parameters of the deposition process, the deposited material seals the opening of the second isolation trench, and the inside of the second isolation trench is air. The insulating isolation effect of air is strong, which can effectively improve the isolation effect of the second isolation structure 112.

[0136] In the embodiment, the dynamic random access memory architecture further includes a metal silicide layer between the first source-drain doped layer 104 and the bit line layer 106. By forming the metal silicide layer, the contact resistance between the bit line layer 106 and the first source-drain doped layer 104 can be effectively reduced.

[0137] In the embodiment, the bit line layer 106 is a double-layer structure, and the bit line layer 106 includes a first metal layer and a second metal layer on the first metal layer. The material of the first metal layer is titanium nitride, and the material of the second metal layer is tungsten.

[0138] In the embodiment, the dynamic random access memory architecture further includes a bit line isolation structure 107 between adjacent bit line layers 106, and the bit line isolation structure 107 is a cavity structure. The specific forming process is to adjust the parameters of the deposition process, so that the deposited silicon oxide material seals the opening between adjacent bit line layers 106, thereby forming a cavity structure between adjacent bit line layers 106. The cavity structure has a strong electrical isolation effect, thereby effectively reducing the crosstalk between adjacent bit line layers 106.

[0139] In the embodiment, the dynamic random access memory architecture further includes a logic circuit wafer 200, the logic circuit wafer 200 is bonded to the substrate 105 towards the first surface 100a, and the logic circuit wafer 200 is electrically connected to the bit line layer 106 and the word line gate structure 114, respectively.

[0140] It should be noted that in the present embodiment, the logic circuit wafer 200 is bonded for logic control of reading, writing and refreshing of each memory cell.

[0141] In the present embodiment, the second isolation structure 112 is a conductive structure, the logic circuit wafer 200 is electrically connected with the second isolation structure 112, and the logic circuit wafer 200 further includes an operation of applying a negative voltage to the second isolation structure 112.

[0142] Please continue to refer to Figure 8 In the present embodiment, along the first direction X, the first conductive plug 108 for electrically connecting the word line gate structure 114 and the logic circuit wafer 200 has a first central axis S1, and the second conductive plug 109 for electrically connecting the second isolation structure 112 and the logic circuit wafer 200 has a second central axis S2, and the first central axis S1 coincides with the second central axis S2.

[0143] Please continue to refer to Figure 39 In other embodiments, along the first direction X, the first conductive plug 108 for electrically connecting the word line gate structure 114 and the logic circuit wafer 200 has a first central axis S1, and the second conductive plug 109 for electrically connecting the second isolation structure 112 and the logic circuit wafer 200 has a second central axis S2, and the first central axis S1 does not coincide with the second central axis S2. By arranging the first conductive plug 108 and the second conductive plug 109 staggered along the first direction X, the exposure window for forming the first conductive plug 108 and the second conductive plug 109 can be further increased, and thus the volume of the first conductive plug 108 and the second conductive plug 109 can be increased to improve the electrical conduction performance.

[0144] In the present embodiment, the logic circuit wafer 200 is electrically connected with the bit line layer 106 through a plurality of third conductive plugs 110.

[0145] In the present embodiment, the capacitor structure 118 includes a pillar capacitor (as shown in Figure 31 ), a cup capacitor (as shown in Figure 32 ) or a cylinder capacitor (as shown in Figure 33 ).

[0146] In the present embodiment, the capacitor structure 118 is electrically connected with the corresponding second source-drain doped layer 117 through a fourth conductive plug 119.

[0147] In other embodiments, the capacitor structure 118 can also be directly electrically connected with the corresponding second source-drain doped layer 117.

[0148] In this embodiment, the two mutually separated word line gate structures 114 are also located on the sidewalls opposite to each other along the second direction Y of the word line gate trench; and the two second conductive plugs 109 electrically connected with the two mutually separated word line gate structures 114 are distributed on the two sides opposite to each other along the second direction Y of the word line gate trench. In this way, the contact area between the second conductive plug 109 and the corresponding word line gate structure 114 is increased, and the electrical contact performance between the second conductive plug 109 and the corresponding word line gate structure 114 is improved.

[0149] In this embodiment, the projection of the second isolation structure 112 along the first direction X is located in the projection range of the word line gate structure 114 along the first direction X, so as to reduce the influence of the second isolation structure 112 on the adjacent storage unit when a negative voltage is applied.

[0150] Although the present application has been disclosed as above, it is not limited to the above. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various changes and modifications, and therefore the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A method of forming a dynamic random access memory architecture, comprising: The method comprises the following steps: forming a substrate and a plurality of bit line layers, the substrate has opposite first and second surfaces, the substrate comprises a plurality of active regions which are separated from each other and parallel to a first direction, and the active regions are arranged along a second direction, each of the active regions has a first source / drain doped layer, the first surface exposes the first source / drain doped layer, the active regions are separated by first isolation grooves, the first isolation grooves have first isolation structures, the first isolation grooves extend along the first direction, and the first direction is perpendicular to the second direction, each of the active regions comprises a plurality of word line regions and isolation regions which are separated from each other and arranged along the first direction, and the bit line layers are parallel to the first direction and located on the first surface, each of the bit line layers is electrically connected to the first source / drain doped layers in the corresponding active region; after the substrate and the bit line layers are formed, the substrate is thinned from the second surface to the first surface until the first isolation structures are exposed; after the thinning, word line gate grooves are formed in each of the word line regions, and second isolation grooves are formed in each of the isolation regions, the word line gate grooves and the second isolation grooves extend from the first surface to the second surface, and the word line gate grooves and the second isolation grooves penetrate the active regions along the second direction; second isolation structures are formed in each of the second isolation grooves; two word line gate structures are formed in each of the word line gate grooves, and the two word line gate structures are located on the opposite sidewalls of the word line gate groove along the first direction; after the word line gate structures are formed, source / drain ion implantation is performed on the substrate from the second surface to the first surface, and second source / drain doped layers are formed in each of the active regions, and the second surface exposes the second source / drain doped layers; after the second source / drain doped layers are formed, a plurality of capacitor structures are formed on the second surface, and each of the capacitor structures is electrically connected to the corresponding second source / drain doped layer.

2. The method of claim 1, wherein the DRAM architecture is formed by: The second isolation structure is a conductive structure. ​ 3. The method of claim 2, wherein the DRAM architecture is formed by: The material of the conductive structure comprises titanium nitride. ​ 4. The method of claim 1, wherein the DRAM architecture is formed by: The second isolation structure is an insulating structure. ​ 5. The method of claim 4, wherein the DRAM architecture is formed by: forming a first DRAM cell in the first memory cell region; and forming a second DRAM cell in the second memory cell region. The material of the insulating structure comprises silicon oxide or air.

6. The method of claim 1, wherein the DRAM architecture is formed by: forming a first DRAM cell in a first memory array; forming a second DRAM cell in a second memory array; and forming a third DRAM cell in a third memory array. The method for forming the substrate and the plurality of bit line layers comprises the following steps: providing an initial substrate, the initial substrate has opposite first and second surfaces; performing a patterned etching process on the initial substrate to form a plurality of first isolation grooves, and the active regions are between the adjacent first isolation grooves; forming the first isolation structures in the first isolation grooves; after the isolation structures are formed, forming the first source / drain doped layers in the active regions to form the substrate; and after the substrate is formed, forming the plurality of bit line layers.

7. The method of claim 6, wherein the DRAM architecture is formed by: forming a first DRAM cell in the first memory cell region; forming a second DRAM cell in the second memory cell region; and forming a third DRAM cell in the third memory cell region. The method for forming the bit line layer includes: performing a metallization process on the first source-drain doped layer exposed by the first surface, so that part of the first source-drain doped layer forms a metal silicide layer, and the metal silicide layer is used as the bit line layer.

8. The method of claim 7, wherein the DRAM architecture is formed by: forming a first DRAM cell in the first memory cell region; and forming a second DRAM cell in the second memory cell region. After the substrate is formed and before the bit line layer is formed, the method further includes: etching part of the first isolation structure from the first surface to the second surface to form a bit line isolation groove between adjacent active regions; and forming a bit line isolation structure in the bit line isolation groove.

9. The method of claim 1, wherein the DRAM architecture is formed by: The method for forming the substrate and the plurality of bit line layers includes: providing an initial substrate having opposite first and second surfaces; forming the first source-drain doped layer in the initial substrate; after forming the source-drain doped layer, forming a bit line material layer on the first surface; performing a patterned etching process on the bit line material layer and the initial substrate to form a plurality of first isolation trenches, with adjacent first isolation trenches forming the active regions therebetween, and with the bit line material layer forming the bit line layer; and after the patterned etching process, forming the first isolation structure in the first isolation trenches to form the substrate. ​ 10. The method of claim 9, wherein the DRAM architecture is formed by: After the substrate and the bit line layer are formed, the method further includes: etching part of the first isolation structure from the first surface to the second surface to form a bit line isolation groove between adjacent active regions; and forming a bit line isolation structure in the bit line isolation groove. ​ 11. The method of claim 8 or 10, wherein the dynamic random access memory architecture is formed by a process comprising: The bit line isolation structure is a cavity structure. ​ 12. The method of claim 1, wherein the DRAM architecture is formed by: After the bit line layer is formed and before the thinning process is performed, the method further includes: providing a logic circuit wafer; and bonding the logic circuit wafer to the substrate with the first surface facing the second surface, with the logic circuit wafer being electrically connected to the bit line layer. ​ 13. The method of claim 12, wherein the DRAM architecture is formed by: After the word line gate structure is formed, the logic circuit wafer is electrically connected to the word line gate structure. ​ 14. The method of claim 13, wherein the DRAM architecture is formed by: The method for electrically connecting the logic circuit wafer to the word line gate structure includes: forming a plurality of first conductive plugs before bonding the logic circuit wafer to the substrate, with the first conductive plugs being electrically connected to corresponding word line gate structures after the word line gate structure is formed; and after bonding the logic circuit wafer to the substrate, the logic circuit wafer is electrically connected to the first conductive plugs. ​ 15. The method of claim 14, wherein the DRAM architecture is formed by: The second isolation structure is a conductive structure, and after the second isolation structure is formed, the logic circuit wafer is electrically connected to the second isolation structure. ​ 16. The method of claim 15, wherein the DRAM architecture is formed by: The method for electrically connecting the logic circuit wafer to the second isolation structure includes: forming a plurality of second conductive plugs before bonding the logic circuit wafer to the substrate, with the second conductive plugs being electrically connected to corresponding second isolation structures after the second isolation structure is formed; and after bonding the logic circuit wafer to the substrate, the logic circuit wafer is electrically connected to the second conductive plugs.

17. The method of claim 16, wherein the DRAM architecture is formed by: In the first direction, the first conductive plugs have first central axes, and the second conductive plugs have second central axes, with the first central axes coinciding with the second central axes. ​ 18. The method of claim 16, wherein the DRAM architecture is formed by: In the first direction, the first conductive plug has a first central axis, and the second conductive plug has a second central axis, the first central axis and the second central axis are not coincident. ​ 19. The method of claim 14, wherein the DRAM architecture is formed by: The two mutually separated word line gate structures are also located on the opposite sidewalls of the word line gate trench along the second direction; and the two first conductive plugs electrically connected with the two mutually separated word line gate structures are distributed on the two sides of the word line gate trench along the second direction respectively. ​ 20. The method of claim 1, wherein the DRAM architecture is formed by: The projection of the second isolation structure along the first direction is located in the projection range of the word line gate structure along the first direction. ​ 21. A dynamic random access memory architecture, comprising: The dynamic random access memory architecture is formed by the method of any one of claims 1 to 20, and the dynamic random access memory architecture comprises: a substrate having opposite first and second surfaces, the substrate comprising a plurality of active regions separated from each other and parallel to a first direction, and a plurality of the active regions arranged along a second direction, the active regions being separated from each other by first isolation trenches extending along the first direction, the first direction being perpendicular to the second direction, each of the active regions comprising a plurality of word line regions and isolation regions separated from each other and arranged along the first direction; a first isolation structure located in the first isolation trench; a first source / drain doped layer located in each of the active regions, the first surface exposing the first source / drain doped layer; a word line gate trench located in each of the word line regions, the word line gate trench extending from the first surface to the second surface, and the word line gate trench extending through the active region along the second direction; a second isolation trench located in each of the isolation regions, the second isolation trench extending from the first surface to the second surface, and the second isolation trench extending through the active region along the second direction; a second isolation structure located in each of the second isolation trenches; two mutually separated word line gate structures located in each of the word line gate trenches, the two word line gate structures being located on opposite sidewalls of the word line gate trench along the first direction respectively; a plurality of bit line layers parallel to the first direction located on the first surface, each of the bit line layers being electrically connected with a plurality of the first source / drain doped layers in a corresponding one of the active regions; a second source / drain doped layer located in each of the active regions, the second surface exposing the second source / drain doped layer; a plurality of capacitor structures located on the second surface, each of the capacitor structures being electrically connected with a corresponding one of the second source / drain doped layers.

22. The DRAM architecture of claim 21, wherein, The second isolation structure is a conductive structure.

23. The DRAM architecture of claim 22, wherein, The material of the conductive structure comprises titanium nitride.

24. The DRAM architecture of claim 21, wherein, The second isolation structure is an insulating structure.

25. The DRAM architecture of claim 24, wherein, The material of the insulating structure comprises silicon oxide or air.

26. The DRAM architecture of claim 21, wherein, Further comprising: a bit line isolation structure located between adjacent bit line layers.

27. The DRAM architecture of claim 26, wherein, The bit line isolation structure is a cavity structure.

28. The DRAM architecture of claim 21, wherein, Further comprising: a logic circuit wafer bonded to the substrate towards the first surface, the logic circuit wafer being electrically connected with the bit line layers and the word line gate structures respectively.

29. The DRAM architecture of claim 28, wherein, The second isolation structure is a conductive structure, and the logic circuit wafer is electrically connected with the second isolation structure.

30. The DRAM architecture of claim 28, wherein, In the first direction, a first conductive plug for electrically connecting the word line gate structure and the logic circuit wafer has a first central axis, and a second conductive plug for electrically connecting the second isolation structure and the logic circuit wafer has a second central axis, and the first central axis coincides with the second central axis.

31. The DRAM architecture of claim 28, wherein, In the first direction, a first conductive plug for electrically connecting the word line gate structure and the logic circuit wafer has a first central axis, and a second conductive plug for electrically connecting the second isolation structure and the logic circuit wafer has a second central axis, and the first central axis does not coincide with the second central axis.

32. The DRAM architecture of claim 30, wherein, The two mutually separated word line gate structures are also located on the opposite sidewalls of the word line gate groove along the second direction; and the two first conductive plugs electrically connected with the two mutually separated word line gate structures are distributed on the two opposite sides of the word line gate groove along the second direction.

33. The DRAM architecture of claim 21, wherein, The projection of the second isolation structure along the first direction is located within the projection range of the word line gate structure along the first direction.

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