A memory chip, a logic chip, a chip stacking structure and a memory

Abstract

The present disclosure provides a memory chip, a logic chip, a chip stacking structure and a memory. In the memory chip, four first transmission structures are symmetrical about a first axis and a second axis; four second transmission structures in each second transmission structure group are symmetrical about the first axis and the second axis; the memory chip receives one first identification signal from each first transmission structure, and generates a chip position identification code based on the four first identification signals; the memory chip receives one second identification signal from each second transmission structure group, and generates a stacking position identification code based on B second identification signals.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a memory chip, a logic chip, a chip stacking structure, and a memory. Background Art

[0002] With the development of integrated circuit technology, the production process of semiconductor devices has made significant progress. However, in recent years, the development of two-dimensional semiconductor technology has encountered various challenges: physical limits, limits of existing development technology, and limits of storage electron density. In this context, in order to solve the difficulties encountered by two-dimensional semiconductor devices and pursue lower production costs per unit memory unit, bonding processes (such as hybrid bonding, bumping, and wire bonding) can be used to stack multiple chips to form three-dimensional semiconductor devices. However, for three-dimensional semiconductor devices, the connection structure between different chips still has problems such as large parasitic capacitance and large parasitic resistance, which affect the quality of signal transmission. Summary of the Invention

[0003] The present disclosure provides a memory chip, a logic chip, a chip stacking structure, and a memory.

[0004] The technical solution of the present disclosure is achieved as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a memory chip, wherein a top surface of the memory chip has a first axis and a second axis, the first axis and the second axis intersecting perpendicularly at the center of the top surface, the first axis being parallel to one edge of the top surface, and the second axis being parallel to another edge of the top surface; the memory chip includes four first transmission structures and B second transmission structure groups, where B is a natural number; the four first transmission structures are symmetrical about the first axis, and the four first transmission structures are symmetrical about the second axis; for each second transmission structure group, it includes four second transmission structures, the four second transmission structures are symmetrical about the first axis, and the four second transmission structures are symmetrical about the second axis; the memory chip receives one first identification signal from each first transmission structure and generates a chip position identification code based on the four first identification signals; the four second transmission structures in the same second transmission structure group transmit the same signal level, the memory chip receives one second identification signal from each second transmission structure group, and generates a stacking position identification code based on the B second identification signals; wherein the memory chip determines its own position number in the chip stacking structure to which it belongs based on the stacking position identification code and the chip position identification code.

[0006] In some embodiments, the memory chip also includes four first driving circuits and a first decoding circuit, and the four first driving circuits are coupled to the four first transmission structures one by one; the first decoding circuit is coupled to the four first driving circuits, and is configured to receive the four first identification signals via the four first driving circuits, and decode the received four first identification signals to generate the chip position identification code; wherein, the four memory chips are stacked to form a stacking unit, and the chip position identification code indicates the position number of the memory chip in the stacking unit to which it belongs.

[0007] In some embodiments, the memory chip further includes a comparison circuit, a logic processing circuit, and a logic operation circuit; the comparison circuit is coupled to the first decoding circuit and configured to generate a valid first control signal when the chip position identification code is the same as a preset chip position identifier; wherein the preset chip position identifier indicates that the memory chip is the last chip in the stacking unit to which it belongs; the logic processing circuit is coupled to B second transmission structure groups and configured to receive 1 second identification signal from each second transmission structure group, and generate the stacking position identification code based on the received B second identification signals; wherein a plurality of the stacking units are stacked to form a chip stacking structure, and the stacking position identification code indicates the position number of the stacking unit to which the memory chip belongs in the chip stacking structure to which it belongs; the logic operation circuit, It is coupled to the comparison circuit and the logic processing circuit respectively, and is configured to receive the first control signal and the stacking position identification code. When the first control signal is valid, the stacking position identification code is added by one to generate and output the second identification signal of the next storage chip; when the first control signal is invalid, the stacking position identification code of the storage chip is output as the second identification signal of the next storage chip; the logic processing circuit is also configured to receive the second identification signal of the next storage chip output by the logic operation circuit, and transmit it to the next storage chip through B second transmission structure groups; wherein the i-th second identification signal of the next storage chip is transmitted to the next storage chip through the i-th second transmission structure group, and i is a natural number less than or equal to B.

[0008] In some embodiments, each of the second transmission structures has conductive vias and contact structures arranged at intervals along a third direction, the conductive vias penetrate the substrate of the memory chip along the third direction, and the contact structures penetrate the top surface;

[0009] The logic processing circuit includes B second drive circuits and B third drive circuits; the i-th second drive circuit is coupled to the conductive through-hole of each second transmission structure in the i-th second transmission structure group; the i-th second drive circuit is also coupled to the logic operation circuit; i is a natural number, and i is less than or equal to B; the i-th third drive circuit is coupled to the contact structure of each second transmission structure in the i-th second transmission structure group; the i-th third drive circuit is also coupled to the logic operation circuit.

[0010] In some embodiments, the logic processing circuit is also coupled to the first decoding circuit and configured to receive the chip position identification code; when the chip position identification code indicates that the memory chip is in an even-numbered position, the second identification signal of the memory chip is received from the conductive through-hole of each second transmission structure in the corresponding second transmission structure group via the second driving circuit, and the generated stacking position identification code is sent to the logic operation circuit; and the second identification signal of the next memory chip output by the logic operation circuit is sent to the contact structure of each second transmission structure in the corresponding second transmission structure group via the third driving circuit; or, when the chip position identification code indicates that the memory chip is in an odd-numbered position, the second identification signal of the memory chip is received from the contact structure of each second transmission structure in the corresponding second transmission structure group via the third driving circuit, and the generated stacking position identification code is sent to the logic operation circuit, and the second identification signal of the next memory chip output by the logic operation circuit is sent to the conductive through-hole of each second transmission structure in the corresponding second transmission structure group via the second driving circuit.

[0011] In some embodiments, the second driving circuit includes a first OR logic circuit, an even driving input circuit, and an odd driving output circuit; the input end of the first OR logic circuit is coupled to the conductive through hole of each second transmission structure in the corresponding second transmission structure group, the even driving input circuit is coupled between the output end of the first OR logic circuit and the input end of the logic operation circuit, and the odd driving output circuit is coupled between the output end of the logic operation circuit and the conductive through hole of each second transmission structure in the corresponding second transmission structure group; the third driving circuit includes a second OR logic circuit, an even driving output circuit, and an odd driving input circuit; the input end of the second OR logic circuit is coupled to the contact structure of each second transmission structure in the corresponding second transmission structure group, and the odd driving input circuit is coupled to the Between the output end of the second OR logic circuit and the input end of the logic operation circuit, the even drive output circuit is coupled between the output end of the logic operation circuit and the contact structure of each second transmission structure in the corresponding second transmission structure group; wherein, the control end of the odd drive input circuit and the control end of the odd drive output circuit both receive a first odd switch signal; the control end of the even drive input circuit and the control end of the even drive output circuit both receive a first even switch signal; if the chip position identification code indicates that the memory chip is in an odd numbered position, the first odd switch signal is in an enabled state and the first even switch signal is in a disabled state; if the chip position identification code indicates that the memory chip is in an even numbered position, the first odd switch signal is in a disabled state and the first even switch signal is in an enabled state.

[0012] In some embodiments, the logic operation circuit includes: an adder and a selection circuit; the adder is configured to add one to the stacking position identification code and output a stacking code carry signal; the selection circuit is configured to output the stacking code carry signal as the second identification signal of the next storage chip if the first control signal is valid; if the first control signal is invalid, the stacking position identification code is directly output as the second identification signal of the next storage chip.

[0013] In some embodiments, the logic processing circuit further includes a weak drive circuit; the logic processing circuit is further configured to generate the second identification signal in a default state based on the weak drive circuit if the second transmission structure does not transmit a valid signal; and to generate the second identification signal based on the valid signal transmitted by the second transmission structure if the second transmission structure transmits a valid signal.

[0014] In some embodiments, the weak drive circuit includes B first logic devices and B second logic devices; each of the odd drive input circuits is coupled to one of the first logic devices; the odd drive input circuit includes a first inverting drive unit and a second inverting drive unit, and the output end of the second OR logic circuit is connected to the input end of the first inverting drive unit, the output end of the first inverting drive unit is connected to the input end of the second inverting drive unit, the output end of the second inverting drive unit is connected to the input end of the logic operation circuit, and the control end of the first inverting drive unit and the control end of the second inverting drive unit both receive the first odd switch signal; the output end of the first logic device is connected to the input end of the first inverting drive unit, the first input end of the first logic device receives a power-on indication signal, and the second input end of the first logic device is connected to the input end of the first inverting drive unit. The output end of the first inverting drive unit is connected; each of the even drive input circuits is coupled to one of the second logic devices; the even drive input circuit includes a third inverting drive unit and a fourth inverting drive unit, and the output end of the first OR logic circuit is connected to the input end of the third inverting drive unit, the output end of the third inverting drive unit is connected to the input end of the fourth inverting drive unit, the output end of the fourth inverting drive unit is connected to the input end of the logic operation circuit, and the control end of the third inverting drive unit and the control end of the fourth inverting drive unit both receive the first even switch signal; the output end of the second logic device is connected to the input end of the third inverting drive unit, the first input end of the second logic device receives a power-on indication signal, and the second input end of the second logic device is connected to the output end of the third inverting drive unit.

[0015] In some embodiments, the first logic device and the second logic device are both two-input NOR gates; after the memory chip is powered on, the power-on indication signal is at a high level; the second identification signal in the default state is at a low level; the first transmission structure is prepared by any one or more of the via-first, via-middle, via-last, and back side via-last processes; the conductive vias in the second transmission structure are prepared by any one or more of the via-first, via-middle, and back side via-last processes; different first transmission structures and different second transmission structures are electrically isolated from each other.

[0016] In a fourth aspect, an embodiment of the present disclosure provides a logic chip, wherein the top surface of the logic chip has a first axis and a second axis, the first axis and the second axis intersect perpendicularly at the center of the top surface, the first axis is parallel to one edge of the top surface, and the second axis is parallel to the other edge of the top surface; the logic chip includes 4 third transmission structures and B fourth transmission structure groups, where B is a natural number; the 4 third transmission structures are symmetrical about the first axis, and the 4 third transmission structures are symmetrical about the second axis; for each of the fourth transmission structure groups, it includes 4 fourth transmission structures, and the 4 fourth transmission structures are symmetrical about the first axis. The four fourth transmission structures are symmetrical about the second axis; the logic chip is configured to generate four first identification signals and transmit the four first identification signals to the four third transmission structures in a one-to-one correspondence; wherein the four first identification signals indicate the chip position identification code of the memory chip adjacent to the logic chip; the logic chip is further configured to receive one second identification signal from each of the fourth transmission structure groups during initialization, and generate a stacking position identification code based on B second identification signals; or, in a normal working stage, generate B second identification signals in a default state, and send one second identification signal to one of the fourth transmission structure groups.

[0017] In some embodiments, the logic chip also includes a first signal generating circuit and four fourth driving circuits, and the four fourth driving circuits are coupled to the four third transmission structures one by one; the first signal generating circuit is coupled to the four fourth driving circuits and is configured to generate four first identification signals during the initialization process, and the level state of the four first identification signals is a first combination value; during normal operation, four first identification signals are generated, and the level state of the four first identification signals is a second combination value; wherein, the first combination value and the second combination value are not exactly the same.

[0018] In some embodiments, the logic chip further includes a second signal generating circuit, B third OR logic circuits, B control input circuits, and B control output circuits; the second signal generating circuit is coupled to the B control output circuits and is configured to generate B second identification signals in a default state during a normal operation phase, and transmit the i-th second identification signal one-to-one to the input end of the i-th control output circuit; wherein the output end of the i-th control output circuit is coupled to each of the fourth transmission structures in the i-th fourth transmission structure group; i is a natural number less than or equal to B; each of the fourth transmission structures in the i-th fourth transmission structure group is coupled to the input end of the i-th third OR logic circuit, The output end of the third OR logic circuit is coupled to the input end of the i-th control output circuit, and the output end of the i-th control input circuit is coupled to the internal circuit of the logic chip; during the initialization process, the output end of the i-th control input circuit outputs the i-th second identification signal to the internal circuit of the logic chip; wherein, the control ends of the control output circuits all receive output enable signals, and the control ends of the control input circuits all receive input enable signals; if the logic chip is in a normal working stage, the input enable signal is in a non-enabled state, and the output enable signal is in an enabled state; if the logic chip is in an initialization process, the input enable signal is in an enabled state, and the output enable signal is in a non-enabled state.

[0019] In some embodiments, the third transmission structure or the fourth transmission structure is prepared by any one or more of the via-first, via-middle, via-last, and back side via-last processes; different third transmission structures and different fourth transmission structures are electrically isolated from each other.

[0020] In a fourth aspect, an embodiment of the present disclosure provides a chip stacking structure, the chip stacking structure comprising the logic chip according to the second aspect and at least one stacking unit, wherein the logic chip and the at least one stacking unit are stacked sequentially along a third direction; each stacking unit comprises a first memory chip, a second memory chip, a third memory chip, and a fourth memory chip stacked sequentially along the third direction, wherein the third direction is perpendicular to a top surface of each memory chip; the first memory chip, the second memory chip, the third memory chip, and the fourth memory chip are all the memory chips according to the first aspect;

[0021] The first memory chip and the second memory chip are stacked face to face, the second memory chip and the third memory chip are stacked back to back, and the third memory chip and the fourth memory chip are stacked face to face;

[0022] The logic chip and the first memory chip are stacked in a back-to-back manner; or, the logic chip and the first memory chip are stacked in a face-to-back manner.

[0023] In some embodiments, the top surface of the logic chip or each of the memory chips is divided into 2×2 signal areas, the first signal area and the second signal area are symmetrical along their own first axis, the first signal area and the fourth signal area are symmetrical along their own second axis, and the third signal area and the fourth signal area are symmetrical along their own first axis; the first axis of the logic chip and each of the memory chips are respectively aligned along a third direction, and the second axis of the logic chip and each of the memory chips are respectively aligned along the third direction; when the logic chip and the first memory chip are stacked back to back, the fourth signal area of ​​the logic chip, the first signal area of ​​the first memory chip, the second signal area of ​​the second memory chip, and the third signal area of ​​the third memory chip , the fourth signal area of ​​the fourth storage chip is aligned along the third direction; the third signal area of ​​the logic chip, the second signal area of ​​the first storage chip, the first signal area of ​​the second storage chip, the fourth signal area of ​​the third storage chip, and the third signal area of ​​the fourth storage chip are aligned along the third direction; the second signal area of ​​the logic chip, the third signal area of ​​the first storage chip, the fourth signal area of ​​the second storage chip, the first signal area of ​​the third storage chip, and the second signal area of ​​the fourth storage chip are aligned along the third direction; the first signal area of ​​the logic chip, the fourth signal area of ​​the first storage chip, the third signal area of ​​the second storage chip, the second signal area of ​​the third storage chip, and the first signal area of ​​the fourth storage chip are aligned along the third direction.

[0024] In some embodiments, for the four first transmission structures in each of the memory chips, the first transmission structure_0, the first transmission structure_1, the first transmission structure_2, and the first transmission structure_3 are located in the first signal area, the second signal area, the third signal area, and the fourth signal area in a one-to-one correspondence; for the four third transmission structures in the logic chip, the third transmission structure_0, the third transmission structure_1, the third transmission structure_2, and the third transmission structure_3 are located in the first signal area, the second signal area, the third signal area, and the fourth signal area in a one-to-one correspondence; the third transmission structure_3 of the logic chip, the first transmission structure_0 of the first memory chip, the first transmission structure_1 of the second memory chip, the first transmission structure_2 of the third memory chip, and the first transmission structure_3 of the fourth memory chip are aligned along a third direction and connected to form a signal transmission path; the third transmission structure_2 of the logic chip, the first transmission structure_1 of the first memory chip, the first transmission structure_0 of the second memory chip, and the third transmission structure_3 of the fourth memory chip are aligned along a third direction and connected to form a signal transmission path; The first transmission structure_3 and the first transmission structure_2 of the fourth storage chip are aligned along a third direction and connected to form a signal transmission path; the third transmission structure_1 of the logic chip, the first transmission structure_2 of the first storage chip, the first transmission structure_3 of the second storage chip, the first transmission structure_0 of the third storage chip, and the first transmission structure_1 of the fourth storage chip are aligned along the third direction and connected to form a signal transmission path; the third transmission structure_0 of the logic chip, the first transmission structure_3 of the first storage chip, the first transmission structure_2 of the second storage chip, the first transmission structure_1 of the third storage chip, and the first transmission structure_0 of the fourth storage chip are aligned along the third direction and connected to form a signal transmission path; wherein, each of the storage chips obtains the 0th first identification signal from the first transmission structure_0, each of the storage chips obtains the 1st first identification signal from the first transmission structure_1, each of the storage chips obtains the 2nd first identification signal from the first transmission structure_2, and each of the storage chips obtains the 3rd first identification signal from the first transmission structure_3.

[0025] In some embodiments, when B=2, for the two second transmission structure groups in each of the memory chips, the first second transmission structure group includes the second transmission structure _0 to the second transmission structure _3, and the second second transmission structure group includes the second transmission structure _4 to the second transmission structure _7; the second transmission structure _0 and the second transmission structure _4 are located in the first signal area, the second transmission structure _1 and the second transmission structure _5 are located in the second signal area, the second transmission structure _2 and the second transmission structure _6 are located in the third signal area, and the second transmission structure _3 and the second transmission structure _7 are located in the fourth signal area; for the logic chip, the first The fourth transmission structure group includes the fourth transmission structure _0 to the fourth transmission structure _3, and the second fourth transmission structure group includes the fourth transmission structure _4 to the fourth transmission structure _7; the fourth transmission structure _0 and the fourth transmission structure _4 are located in the first signal area, the fourth transmission structure _1 and the fourth transmission structure _5 are located in the fourth signal area, the fourth transmission structure _2 and the fourth transmission structure _6 are located in the third signal area, and the fourth transmission structure _3 and the fourth transmission structure _7 are located in the fourth signal area; the fourth transmission structure _3 of the logic chip, the second transmission structure _0 of the first memory chip, the second transmission structure _1 of the second memory chip, The second transmission structure _2 of the third storage chip and the second transmission structure _3 of the fourth storage chip are aligned along the third direction and connected to form a signal transmission channel; the fourth transmission structure _2 of the logic chip, the second transmission structure _1 of the first storage chip, the second transmission structure _0 of the second storage chip, the second transmission structure _3 of the third storage chip, and the second transmission structure _2 of the fourth storage chip are aligned along the third direction and connected to form a signal transmission channel; the fourth transmission structure _1 of the logic chip, the second transmission structure _2 of the first storage chip, the second transmission structure _3 of the second storage chip, the second transmission structure _0 of the third storage chip, and the fourth transmission structure _ The second transmission structure_1 is aligned along the third direction and connected to form a signal transmission channel; the fourth transmission structure_0 of the logic chip, the second transmission structure_3 of the first memory chip, the second transmission structure_2 of the second memory chip, the second transmission structure_1 of the third memory chip, and the second transmission structure_0 of the fourth memory chip are aligned along the third direction and connected to form a signal transmission channel; the fourth transmission structure_7 of the logic chip, the second transmission structure_4 of the first memory chip, the second transmission structure_5 of the second memory chip, the second transmission structure_6 of the third memory chip, and the second transmission structure_7 of the fourth memory chip are aligned along the third direction and connected to form a signal transmission channel;The fourth transmission structure_6 of the logic chip, the second transmission structure_5 of the first memory chip, the second transmission structure_4 of the second memory chip, the second transmission structure_7 of the third memory chip, and the second transmission structure_6 of the fourth memory chip are aligned along a third direction and connected to form a signal transmission channel. The fourth transmission structure_5 of the logic chip, the second transmission structure_6 of the first memory chip, the second transmission structure_7 of the second memory chip, the second transmission structure_4 of the third memory chip, and the second transmission structure_5 of the fourth memory chip are aligned along the third direction and connected to form a signal transmission channel. The fourth transmission structure_4 of the logic chip, the second transmission structure_7 of the first memory chip, the second transmission structure_6 of the second memory chip, the second transmission structure_5 of the third memory chip, and the second transmission structure_4 of the fourth memory chip are aligned along the third direction and connected to form a signal transmission channel.

[0026] In some embodiments, the top surface of the logic chip or each of the memory chips is divided into 2×2 signal areas, the first signal area and the second signal area are symmetrical along the first axis thereof, the first signal area and the fourth signal area are symmetrical along the second axis thereof, and the third signal area and the fourth signal area are symmetrical along the first axis thereof; the first axis of the logic chip and each of the memory chips are respectively aligned along a third direction, and the second axis of the logic chip and each of the memory chips are respectively aligned along a third direction; when the logic chip and the first memory chip are stacked back to back, the second signal area of ​​the logic chip, the first signal area of ​​the first memory chip, the second signal area of ​​the second memory chip, and the third signal area of ​​the third memory chip are respectively aligned along the third direction. , the fourth signal area of ​​the fourth storage chip is aligned along the third direction; the first signal area of ​​the logic chip, the second signal area of ​​the first storage chip, the first signal area of ​​the second storage chip, the fourth signal area of ​​the third storage chip, and the third signal area of ​​the fourth storage chip are aligned along the third direction; the fourth signal area of ​​the logic chip, the third signal area of ​​the first storage chip, the fourth signal area of ​​the second storage chip, the first signal area of ​​the third storage chip, and the second signal area of ​​the fourth storage chip are aligned along the third direction; the third signal area of ​​the logic chip, the fourth signal area of ​​the first storage chip, the third signal area of ​​the second storage chip, the second signal area of ​​the third storage chip, and the first signal area of ​​the fourth storage chip are aligned along the third direction.

[0027] In some embodiments, for the four first transmission structures in each of the memory chips, the first transmission structure_0, the first transmission structure_1, the first transmission structure_2, and the first transmission structure_3 are located in the first signal area, the second signal area, the third signal area, and the fourth signal area in a one-to-one correspondence; for the four third transmission structures in the logic chip, the third transmission structure_0, the third transmission structure_1, the third transmission structure_2, and the third transmission structure_3 are located in the first signal area, the second signal area, the third signal area, and the fourth signal area in a one-to-one correspondence; the third transmission structure_1 of the logic chip, the first transmission structure_0 of the first memory chip, the first transmission structure_1 of the second memory chip, the first transmission structure_2 of the third memory chip, and the first transmission structure_3 of the fourth memory chip are aligned along a third direction and connected to form a signal transmission path; the third transmission structure_0 of the logic chip, the first transmission structure_1 of the first memory chip, the first transmission structure_0 of the second memory chip, and the third transmission structure_3 of the third memory chip are aligned along a third direction and connected to form a signal transmission path; The first transmission structure_3 and the first transmission structure_2 of the fourth storage chip are aligned along a third direction and connected to form a signal transmission path; the third transmission structure_3 of the logic chip, the first transmission structure_2 of the first storage chip, the first transmission structure_3 of the second storage chip, the first transmission structure_0 of the third storage chip, and the first transmission structure_1 of the fourth storage chip are aligned along the third direction and connected to form a signal transmission path; the third transmission structure_2 of the logic chip, the first transmission structure_3 of the first storage chip, the first transmission structure_2 of the second storage chip, the first transmission structure_1 of the third storage chip, and the first transmission structure_0 of the fourth storage chip are aligned along the third direction and connected to form a signal transmission path; wherein, each of the storage chips obtains the 0th first identification signal from the first transmission structure_0, each of the storage chips obtains the 1st first identification signal from the first transmission structure_1, each of the storage chips obtains the 2nd first identification signal from the first transmission structure_2, and each of the storage chips obtains the 3rd first identification signal from the first transmission structure_3.

[0028] In some embodiments, when B=2, for the two second transmission structure groups in each of the memory chips, the first second transmission structure group includes the second transmission structure _0 to the second transmission structure _3, and the second second transmission structure group includes the second transmission structure _4 to the second transmission structure _7; the second transmission structure _0 and the second transmission structure _4 are located in the first signal area, the second transmission structure _1 and the second transmission structure _5 are located in the second signal area, the second transmission structure _2 and the second transmission structure _6 are located in the third signal area, and the second transmission structure _3 and the second transmission structure _7 are located in the fourth signal area; for the logic chip, the first The fourth transmission structure group includes the fourth transmission structure _0 to the fourth transmission structure _3, and the second fourth transmission structure group includes the fourth transmission structure _4 to the fourth transmission structure _7; the fourth transmission structure _0 and the fourth transmission structure _4 are located in the first signal area, the fourth transmission structure _1 and the fourth transmission structure _5 are located in the fourth signal area, the fourth transmission structure _2 and the fourth transmission structure _6 are located in the third signal area, and the fourth transmission structure _3 and the fourth transmission structure _7 are located in the fourth signal area; the fourth transmission structure _1 of the logic chip, the second transmission structure _0 of the first memory chip, the second transmission structure _1 of the second memory chip, The second transmission structure _2 of the third storage chip and the second transmission structure _3 of the fourth storage chip are aligned along the third direction and connected to form a signal transmission channel; the fourth transmission structure _0 of the logic chip, the second transmission structure _1 of the first storage chip, the second transmission structure _0 of the second storage chip, the second transmission structure _3 of the third storage chip, and the second transmission structure _2 of the fourth storage chip are aligned along the third direction and connected to form a signal transmission channel; the fourth transmission structure _3 of the logic chip, the second transmission structure _2 of the first storage chip, the second transmission structure _3 of the second storage chip, the second transmission structure _0 of the third storage chip, and the fourth transmission structure _ The second transmission structure_1 is aligned along the third direction and connected to form a signal transmission channel; the fourth transmission structure_2 of the logic chip, the second transmission structure_3 of the first memory chip, the second transmission structure_2 of the second memory chip, the second transmission structure_1 of the third memory chip, and the second transmission structure_0 of the fourth memory chip are aligned along the third direction and connected to form a signal transmission channel; the fourth transmission structure_5 of the logic chip, the second transmission structure_4 of the first memory chip, the second transmission structure_5 of the second memory chip, the second transmission structure_6 of the third memory chip, and the second transmission structure_7 of the fourth memory chip are aligned along the third direction and connected to form a signal transmission channel;The fourth transmission structure_4 of the logic chip, the second transmission structure_5 of the first memory chip, the second transmission structure_4 of the second memory chip, the second transmission structure_7 of the third memory chip, and the second transmission structure_6 of the fourth memory chip are aligned along a third direction and connected to form a signal transmission channel. The fourth transmission structure_7 of the logic chip, the second transmission structure_6 of the first memory chip, the second transmission structure_7 of the second memory chip, the second transmission structure_4 of the third memory chip, and the second transmission structure_5 of the fourth memory chip are aligned along the third direction and connected to form a signal transmission channel. The fourth transmission structure_6 of the logic chip, the second transmission structure_7 of the first memory chip, the second transmission structure_6 of the second memory chip, the second transmission structure_5 of the third memory chip, and the second transmission structure_4 of the fourth memory chip are aligned along the third direction and connected to form a signal transmission channel.

[0029] In some embodiments, for two chips connected face to face, the transmission structures aligned along the third direction in the two chips are electrically connected through a hybrid bonding process; for two chips connected back to back and for two chips connected back to face, the transmission structures aligned along the third direction in the two chips are electrically connected through a bump process; or, for the two chips connected face to face, for the two chips connected back to back and for the two chips connected back to face, the transmission structures aligned along the third direction in the two chips are electrically connected through a hybrid bonding process; or, for the two chips connected face to face, for the two chips connected back to back and for the two chips connected back to face, the transmission structures aligned along the third direction in the two chips are electrically connected through a bump process.

[0030] In a fourth aspect, an embodiment of the present disclosure provides a memory comprising the chip stacking structure as described in the third aspect.

[0031] The embodiments of the present disclosure provide a memory chip, a logic chip, a chip stacking structure and a memory, which not only reduces the number of drive circuits and data selectors, thereby reducing parasitic capacitance; in addition, the face-to-face (F2F) chip stacking structure formed by the memory chip realizes a signal rotation transmission effect through a direct connection configuration of a through hole, and also reduces parasitic resistance; at the same time, for the above-mentioned chip stacking structure, the present disclosure also utilizes fewer transmission structures to realize the transmission of chip position identification codes and stacking position identification codes, which not only has better transmission accuracy, but also can effectively reduce the chip area. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram of the structure of a chip;

[0033] Figure 2AA schematic diagram of signal transmission in a chip stacking structure;

[0034] Figure 2B A schematic diagram of signal transmission for another chip stacking structure;

[0035] Figure 3 A schematic diagram of the structure of a memory chip provided in an embodiment of the present disclosure Figure 1 ;

[0036] Figure 4 A second structural diagram of a memory chip provided in an embodiment of the present disclosure;

[0037] Figure 5 A schematic diagram of the structure of a memory chip provided in an embodiment of the present disclosure Figure 3 ;

[0038] Figure 6 A schematic diagram of a second transmission structure provided in an embodiment of the present disclosure;

[0039] Figure 7A A schematic diagram of a working scenario of a memory chip provided in an embodiment of the present disclosure;

[0040] Figure 7B A schematic diagram of another working scenario of a memory chip provided in an embodiment of the present disclosure;

[0041] Figure 8 A schematic diagram of the structure of a logic operation circuit provided in an embodiment of the present disclosure;

[0042] Figure 9 A schematic diagram of the structure of a memory chip provided in an embodiment of the present disclosure Figure 4 ;

[0043] Figure 10 A schematic diagram of the structure of a logic chip provided in an embodiment of the present disclosure Figure 1 ;

[0044] Figure 11 A second structural diagram of a logic chip provided in an embodiment of the present disclosure;

[0045] Figure 12 A schematic diagram of the structure of a logic chip provided in an embodiment of the present disclosure Figure 3 ;

[0046] Figure 13 A schematic diagram of a chip stacking structure provided in an embodiment of the present disclosure Figure 1 ;

[0047] Figure 14A A schematic diagram of signal transmission of a chip stacking structure provided in an embodiment of the present disclosure Figure 1 ;

[0048] Figure 14B A second schematic diagram of signal transmission of a chip stacking structure provided by an embodiment of the present disclosure;

[0049] Figure 15A A schematic diagram of signal transmission of another chip stacking structure provided in an embodiment of the present disclosure Figure 1 ;

[0050] Figure 15B A second schematic diagram of signal transmission of another chip stacking structure provided by an embodiment of the present disclosure;

[0051] Figure 16A A signal transmission diagram of another chip stacking structure provided in an embodiment of the present disclosure Figure 1 ;

[0052] Figure 16B A second signal transmission diagram of another chip stacking structure provided by an embodiment of the present disclosure;

[0053] Figure 17A A signal transmission diagram of another chip stacking structure provided in an embodiment of the present disclosure Figure 1 ;

[0054] Figure 17B A second schematic diagram of signal transmission of another chip stacking structure provided by an embodiment of the present disclosure;

[0055] Figure 18 A schematic diagram of the structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0056] The following, in conjunction with the accompanying drawings, provides a clear and complete description of the technical solutions in the embodiments of the present disclosure. It should be understood that the specific embodiments described herein are intended solely to illustrate the related applications and are not intended to limit those applications. It should also be noted that, for ease of description, only portions of the drawings related to the related applications are shown. Unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by those skilled in the art to which the present disclosure relates. The terms used herein are for the purpose of describing the embodiments of the present disclosure only and are not intended to limit the present disclosure. In the following description, references to "some embodiments" describe a subset of all possible embodiments. However, it should be understood that "some embodiments" may refer to the same or different subsets of all possible embodiments and may be combined with each other without conflict. It should be noted that the terms "first," "second," and "third" in the embodiments of the present disclosure are used solely to distinguish similar objects and do not represent a specific ordering of the objects. It should be understood that "first," "second," and "third" may be interchanged in a specific order or sequential order, where permitted, to enable the embodiments of the present disclosure described herein to be implemented in an order other than that illustrated or described.

[0057] Dynamic Random Access Memory (DRAM);

[0058] Synchronous Dynamic Random Access Memory (SDRAM);

[0059] Double Data Rate SDRAM (DDR);

[0060] Low Power DDR (LPDDR).

[0061] Before introducing the embodiments of the present disclosure, three directions that may be used to describe a three-dimensional structure in the plane involved in the following embodiments are defined. Taking the Cartesian coordinate system as an example, the three directions may include a first direction, a second direction, and a third direction.

[0062] See Figure 1 A semiconductor chip (specifically, a memory chip or a logic chip) may include a top surface on the front side and a bottom surface on the back side opposite the front side. Ignoring the flatness of the top and bottom surfaces, a direction intersecting (e.g., perpendicular) the top and bottom surfaces of the semiconductor chip is defined as a third direction. On the top surface of the semiconductor chip, two perpendicular directions, namely a first direction and a second direction, are defined, wherein the first direction is perpendicular to one edge of the semiconductor chip, and the second direction is perpendicular to the other edge of the semiconductor chip.

[0063] See Figure 1 A semiconductor chip includes a substrate. One side of the substrate used to make devices (such as transistors and capacitors) forms the active surface. Multiple metal layers, such as M1, M2, M3, etc., are distributed between the substrate and the top surface. Figure 1 Also shown are two types of transmission structures, which are used to implement signal connections between different stacked chips.

[0064] like Figure 1 As shown, for the type 1 transmission structure, it includes a conductive via extending along the third direction, the conductive via penetrates the bottom surface and the top surface at least along the third direction, and is connected to the internal circuit of the chip through the metal layer.

[0065] like Figure 1 As shown, for the transmission structure of type 2, it includes contact structures and conductive vias spaced apart along the third direction, the conductive vias penetrate the substrate along the third direction, and the contact structures penetrate the top surface along the third direction; the contact structures and the conductive vias are not directly electrically connected, but are indirectly electrically connected through the metal layer. For example: Figure 1 The contact structure is connected to the metal layer M4, and the conductive via is connected to the metal layer M1, thereby achieving electrical connection. Of course, in other embodiments, the contact structure and the conductive via can also be designed to be directly electrically connected.

[0066] Meanwhile, the types of transmission structures are not limited to the above two types, and any structure that can realize electrical connection between different stacked chips can be regarded as a transmission structure.

[0067] In particular, the illustrations presented in this disclosure are not meant to be actual views of any particular microelectronic device or its components, but are merely idealized representations used to describe illustrative embodiments.

[0068] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0069] In one embodiment, a memory chip and a logic chip are provided, each of which includes multiple transmission structures extending through the chip along a third direction, and the transmission structures are used to implement signal transmission between different chips. Exemplarily, the transmission structure can be a conductive through-hole (e.g., a through-silicon via). All transmission structures can be located at any position. In particular, every four transmission structures can be functionally regarded as a transmission structure group, but the positions of the four transmission structures are not limited.

[0070] In a specific embodiment, eight of the above-mentioned memory chips and one logic chip are stacked face-to-back to form a 3D memory device, and the transmission structures of the eight memory chips are aligned along a third direction, and the nine transmission structures aligned along the third direction are connected to form an electrical path. Figure 2A , which shows a schematic diagram of signal transmission of a chip stacking structure. Figure 2A As shown, the chip stacking structure includes memory chips 0 to 7 and a logic chip. Figure 2A Only four transmission structures T0 to T3 are shown for each memory chip, and these four transmission structures T0 to T3 belong to the same transmission structure group. At this time, the transmission structures T0 in the eight memory chips and one logic chip are all aligned to form one electrical path, and the transmission structures T1 in the eight memory chips and one logic chip are all aligned to form one electrical path... The remaining transmission structures are similar.

[0071] At the same time, each memory chip and logic chip is also provided with multiple driving circuits ( Figure 2A Only one driving circuit is shown in a dotted box, and the rest of the driving circuits are not framed), and each transmission structure is connected to a driving circuit; each memory chip is also provided with a plurality of data selectors (for example Figure 2A Each transmission structure group corresponds to a data selector. All transmission structures in a transmission structure group are connected to the data port of the data selector through their respective driver circuits. In other words, the data selector can select which transmission structure transmits the signal to output to the memory chip, or which transmission structure the memory chip outputs the signal to output to.

[0072] For the overall memory device, these 8 memory chips are divided into 4 channels (CH0, CH1, CH4, CH5) for management. The signal Signal_CH0 of channel CH0 is transmitted through the electrical path formed by "the transmission structure T0 in the logic chip, the transmission structure T0 in the memory chip 0 - the transmission structure T0 in the memory chip 1 - the transmission structure T0 in the memory chip 2 - the transmission structure T0 in the memory chip 3 - the transmission structure T0 in the memory chip 4 - the transmission structure T0 in the memory chip 5 - the transmission structure T0 in the memory chip 6 - the transmission structure T0 in the memory chip 7", and the selection signals of the data selector mux0 in the memory chip 0 and the data selector mux4 in the memory chip 4 are both SEL_C0, that is, the signal Signal_CH0 can enter the memory chip 0 and the memory chip 4 through the aforementioned electrical path; the signal output process can be understood similarly.

[0073] From the above, it can be seen that memory chip 0 only needs to obtain signals from transmission structure T0, memory chip 1 only needs to obtain signals from transmission structure T1... That is, each memory chip only needs to obtain signals from one of the transmission structures in a transmission structure group. It is worth noting that different memory chips may need to obtain signals from different transmission structures. However, since all memory chips need to be designed into exactly the same structure during process manufacturing (in order to maximize cost and manpower savings), all transmission structures in the memory chip need to be designed with corresponding drive structures and data selectors to achieve structural consistency. Further, when using Figure 1 In the chip stacking structure shown, each transmission structure corresponds to a driving circuit; during the operation of the chip stacking structure, it is necessary to drive all driving circuits in all storage chips in the same channel. The load is large and the parasitic capacitance is large, which seriously affects the performance of the chips, restricts the transmission efficiency and increases power consumption, and also restricts the number of chip stacks in the three-dimensional device.

[0074] In another embodiment, see Figure 2B , which shows another chip stacking structure signal transmission schematic. In particular, Figure 2B Only some transmission structures are marked (T0 to T3), and the others are omitted. Figure 2B For example, the identification of the transmission structures aligned along the third direction is the same. Figure 2B As shown, the chip stacking structure also includes 8 memory chips and 1 logic chip aligned along the third direction, but the transmission structure in each memory chip is rotationally connected to another transmission structure at a different position in another memory chip, and a spiral ascending connection is realized as a whole, that is, the signal Signal_CH0 of channel CH0 is transmitted through "the transmission structure T0 in the logic chip, the transmission structure T1 in the memory chip 0 - the transmission structure T2 in the memory chip 1 - the transmission structure T3 in the memory chip 2 - the transmission structure T0 in the memory chip 3 - the transmission structure T1 in the memory chip 4 - the transmission structure T2 in the memory chip 5 - the transmission structure T3 in the memory chip 6 - the transmission structure T0 in the memory chip 7", and the other signals are similar.

[0075] In this way, memory chip 0 can obtain signal Signal_CH0 through the output end of transmission structure T0 in the logic chip, memory chip 1 can obtain signal Signal_CH1 through the input end of transmission structure T0 in memory chip 0, memory chip 2 can obtain signal Signal_CH4 through the input end of transmission structure T0 in memory chip 1, memory chip 3 can obtain signal Signal_CH5 through the input end of transmission structure T0 in memory chip 2... For each memory chip, only one transmission structure is required in each transmission structure group to connect to the driving circuit, and no data selector is required, which can reduce the number of devices and thus reduce parasitic capacitance. However, compared to Figure 2A The transmission structure is directly connected. Figure 2B The process of rotating connection of the transmission structure is more complicated. Specifically, Figure 2B A horizontal interconnection structure needs to be set between adjacent transmission structures in each memory chip ( Figure 2B Only one of them is marked with a five-pointed star in the figure). The signal interconnection structure can be a metal interconnection line, a transmission structure, etc. To achieve the rotational connection of the transmission structure, the input signal signal_CH0 must first be transmitted upward from the transmission structure T0 of the logic chip to the interconnection structure below the transmission structure T0 of the memory chip 0 (not connected to the transmission structure T0 of the memory chip 0), and then horizontally transmitted from the interconnection structure below the transmission structure T0 of the memory chip 0 to the transmission structure T1 of the memory chip 0; that is: Figure 2B The structure shown in the figure also needs to pass through the interconnection structure in each memory chip during the signal process, and the output signal is similar, which will inevitably lead to an increase in parasitic resistance and also increase the complexity of the process.

[0076] In particular, Figure 2A and Figure 2B In the chip stacking structure, all chips are active-side up, that is, different memory chips are stacked back to face, and memory chips and logic chips are also stacked back to face, that is, the bottom surface of the upper chip contacts the top surface of the lower chip.

[0077] In general, on the one hand, Figure 2A The chip stacking structure requires more transmission structures to transmit the corresponding signals, coupled with the corresponding drive circuit and data selector, resulting in larger load and parasitic capacitance, but Figure 2B The chip stacking structure has a large parasitic resistance due to the rotation configuration; on the other hand, Figure 2A and Figure 2BThere are certain problems with stacking structures, and they cannot be directly applied to face-to-face stacking structures. Specifically, if you want to further realize the face-to-face chip stacking structure, one way is to use two sets of masks to make two different chips, one as the active-side-up chip and the other as the active-side-down chip. This method has high process complexity and uncontrollable costs. Another method is to make an additional set of transmission structures and connect both sets of transmission structures to the same drive circuit in the memory chip. However, this will lead to complex wiring inside the memory chip, which not only increases process complexity but also increases power consumption.

[0078] In another embodiment of the present disclosure, see Figure 3 , which shows a schematic structural diagram of a memory chip 10 provided by an embodiment of the present disclosure. The top surface of the memory chip 10 has a first axis AA' and a second axis BB', the first axis AA' and the second axis BB' perpendicularly intersect at the center of the top surface, the first axis AA' is parallel to one edge of the top surface, and the second axis BB' is parallel to the other edge of the top surface. Figure 3 In the embodiment, the first axis AA' extends along the first direction, and the second axis BB' extends along the second direction; however, this does not constitute a relevant limitation.

[0079] The memory chip 10 includes four first transmission structures (A0-A3) and B second transmission structure groups. Figure 3 Taking B=2 as an example, the first second transmission structure group is represented by B0 to B3, and the second second transmission structure group is represented by B4 to B7. It should be understood that Figure 3 This is just an example, and the specific positions of the first transmission structure and the second transmission structure group are not limited to Figure 3 In addition, the following descriptions are based on B=2, but B can also be other natural numbers. Please understand it adaptively.

[0080] See Figure 3 , the four first transmission structures are symmetrical about the first axis AA', and the four first transmission structures are symmetrical about the second axis BB'; for each second transmission structure group, it includes four second transmission structures, the four second transmission structures are symmetrical about the first axis AA', and the four second transmission structures are symmetrical about the second axis BB'.

[0081] The memory chip 10 receives one first identification signal from each first transmission structure and generates a chip location identification code CID based on the four first identification signals. The four second transmission structures in the same second transmission structure group transmit the same signal level. The memory chip 10 receives one second identification signal from each second transmission structure group and generates a stacking location identification code SID based on the B second identification signals.

[0082] Here, the memory chip 10 determines its position number in the chip stacking structure according to the stacking position identification code SID and the chip position identification code CID.

[0083] In a specific embodiment, four memory chips 10 are stacked to form a stack unit, and a logic chip and multiple stack units further form a chip stack structure. The chip position identification code CID indicates the position number of the memory chip 10 in the stack unit to which it belongs; the stack position identification code SID indicates the position number of the stack unit to which the memory chip 10 belongs in the chip stack structure to which it belongs.

[0084] Taking a chip stack unit consisting of one logic chip and eight memory chips (four memory chips per stack unit, for a total of two stack units) as an example, the CID has two sub-signals, CID<1:0>, and the SID has two sub-signals, SID<1:0>. During normal operation of memory chip 10, the chips are numbered from the logic chip side (i.e., bottom to top). The CID<1:0> and SID<1:0> of each chip are shown in Table 1. During the initialization phase of memory chip 10, the chips are numbered from the side away from the logic chip (i.e., top to bottom). The CID<1:0> and SID<1:0> of each chip are shown in Table 2.

[0085] Table 1

[0086] CID<1:0> SID<1:0> Memory chip 7 11 01 Memory chip 6 10 01 Memory chip 5 01 01 Memory chip 4 00 01 Memory chip 3 11 00 Memory chip 2 10 00 Memory chip 1 01 00 Memory chip 0 00 00 logic chip 00 00

[0087] Table 2

[0088] CID<1:0> SID<1:0> Memory chip 7 00 00 Memory chip 6 01 00 Memory chip 5 10 00 Memory chip 4 11 00 Memory chip 3 00 01 Memory chip 2 01 01 Memory chip 1 10 01 Memory chip 0 11 01 logic chip 11 10

[0089] In some embodiments, see Figure 4 The memory chip 10 further includes four first driving circuits 21 and a first decoding circuit 22. The four first driving circuits 21 are coupled to the four first transmission structures (A0 to A3) in a one-to-one correspondence. The first decoding circuit 22 is coupled to the four first driving circuits 21 and is configured to receive four first identification signals signalA<3:0> via the four first driving circuits 21 and decode the received four first identification signals signalA<3:0> to generate a chip location identification code CID<1:0>.

[0090] In some embodiments, see Figure 5 The memory chip 10 further includes a comparison circuit 31 , a logic processing circuit 32 and a logic operation circuit 33 .

[0091] First, the comparison circuit 31 is coupled to the first decoding circuit 22 and is configured to generate a valid first control signal when the chip position identification code CID<1:0> is the same as the preset chip position identifier; wherein the preset chip position identifier indicates that the memory chip 10 is the last chip in the stacking unit to which it belongs. For example, referring to Table 1 or Table 2, the preset chip position identifier = 11; for Table 1, that is, when the memory chips are numbered from bottom to top, the memory chip 3 and the memory chip 7 are the last chips in the stacking unit to which they belong; for Table 2, that is, when the memory chips are numbered from top to bottom, the memory chip 4 and the memory chip 0 are the last chips in the stacking unit to which they belong. Here, valid can refer to a high level state, invalid can refer to a low level state, or the reverse can be set.

[0092] Next, logic processing circuit 32 is coupled to the B second transmission structure groups and is configured to receive a second identification signal SignalB from each second transmission structure group and generate a stacking position identification code SID<1:0> based on the B received second identification signals SignalB<1:0> (using B=2 as an example). Here, the signals transmitted by the four second transmission structures in the same second transmission structure group are logically ORed to form a single second identification signal.

[0093] Again, the logic operation circuit 33 is coupled to the comparison circuit 31 and the logic processing circuit 32, respectively, and is configured to receive a first control signal and a stacking position identification code SignalB<1:0>. When the first control signal is valid, the stacking position identification code SignalB<1:0> is added by one to generate and output the second identification signal SignalB'<1:0> of the next memory chip 10; when the first control signal is invalid, the stacking position identification code SignalB<1:0> of the memory chip 10 is output as the second identification signal SignalB'<1:0> of the next memory chip 10.

[0094] Finally, the logic processing circuit 32 is further configured to receive the second identification signal SignalB'<1:0> of the next memory chip 10 output by the logic operation circuit 33, and transmit it to the next memory chip 10 through B second transmission structure groups; wherein the i-th second identification signal SignalB' of the next memory chip 10 is <i-1>The data is transmitted to the next memory chip 10 through the i-th second transmission structure group, where i is a natural number less than or equal to B.

[0095] It should be noted that the signal value of the second identification signal SignalB<1:0> is identical to the signal value of the stacking position identification code SID<1:0> in a one-to-one correspondence, but they are located in different circuit positions, and there may be signal transmission and enhancement in between.

[0096] In this way, for the first three memory chips 10 in each stacking unit, the stacking position identification code SID can be directly transmitted to the next memory chip 10; however, for the last memory chip 10 in each stacking unit, the stacking position identification code SID is incremented by one and then transmitted to the next memory chip 10.

[0097] In some embodiments, see Figure 5 Each second transmission structure (B0~B7) has conductive through holes (parts without pattern filling) and contact structures (parts filled with horizontal lines) arranged at intervals along the third direction, the conductive through holes penetrate the substrate of the memory chip 10 along the third direction, and the contact structures penetrate the top surface; and there is no direct contact between the conductive through holes and the contact structures along the third direction.

[0098] Just one example of a conductive via and contact structure: see Figure 6 , which shows a schematic diagram of the second contact structure in two memory chips 10 stacked face to face. Figure 6 As shown, the conductive vias penetrate the substrate (active surface of the chip) from the bottom surface upward and are coupled to the internal circuit of the memory chip 10 via the first metal layer M1; the contact structure penetrates the top surface from the fourth metal layer M4 and is coupled to the internal circuit of the memory chip 10 via the fourth metal layer M4; at the same time, the contact structure of the memory chip 10 is electrically connected to the contact structure of another memory chip 10 to achieve electrical connection between different memory chips 10. Figure 6 In the embodiment, each contact structure includes four sub-contact structures, but this does not constitute a relevant limitation, and the contact structure may include only one sub-contact structure.

[0099] See Figure 5 The logic processing circuit 32 includes B second drive circuits 321 and B third drive circuits 322. The i-th second drive circuit 321 is coupled to the conductive via of each second transmission structure in the i-th second transmission structure group. The i-th second drive circuit 321 is also coupled to the logic operation circuit 33. i is a natural number and i is less than or equal to B. The i-th third drive circuit 322 is coupled to the contact structure of each second transmission structure in the i-th second transmission structure group. The i-th third drive circuit 322 is also coupled to the logic operation circuit 33.

[0100] In some embodiments, the logic processing circuit 32 is also coupled to the first decoding circuit 22 (this part is not shown in the drawings, please refer to the text for understanding), and is configured to receive the chip position identification code CID<1:0>; when the chip position identification code CID<1:0> indicates that the memory chip 10 is in an even-numbered position, the second driving circuit 321 receives its own second identification signal SignalB<1:0> from the conductive through-hole of each second transmission structure in the corresponding second transmission structure group, and sends the generated stacking position identification code SID<1:0> to the logic operation circuit 33; and, the second identification signal SignalB'<1:0> of the next memory chip 10 output by the logic operation circuit 33 is sent to the contact structure of each second transmission structure in the corresponding second transmission structure group via the third driving circuit 322.

[0101] For example, see Figure 7A , the conductive vias B0 to B3 are all used to transmit the second identification signal SignalB <0> , the conductive vias B4 to B7 are all used to transmit the second identification signal SignalB <1> The first second driving circuit 321 receives SignalB from the conductive through-hole portion of B0-B3. <0> The second second driving circuit 321 receives SignalB from the conductive through-hole portion of B4 to B7. <1> ; Logic operation circuit 33 is based on SignalB<1:0> (ie Figure 7A The first third driving circuit 322 sends SignalB'0 to the contact structures B0 to B3, and the second third driving circuit 322 sends SignalB'1 to the contact structures B4 to B7.

[0102] At the same time, the logic processing circuit 32 is also configured to receive its own second identification signal SignalB<1:0> from the contact structure of each second transmission structure in the corresponding second transmission structure group via the third driving circuit 322 when the chip position identification code CID<1:0> indicates that the memory chip 10 is in an odd-numbered position, and send the generated stacking position identification code SID<1:0> to the logic operation circuit 33, and send the second identification signal SignalB'<1:0> of the next memory chip 10 output by the logic operation circuit 33 to the conductive through-hole of each second transmission structure in the corresponding second transmission structure group via the second driving circuit 321.

[0103] For example, see Figure 7B , the contact structures B0 to B3 are all used to transmit the second identification signal SignalB <0> The contact structures B4 to B7 are all used to transmit the second identification signal SignalB <1> The first third driving circuit 322 receives SignalB from the contact structure portion B0 to B3 <0> The second third driving circuit 322 receives SignalB from the contact structure portion of B4 to B7. <1> ; Logic operation circuit 33 is based on SignalB<1:0> (ie Figure 7B The first second driving circuit 321 generates the second identification signal SignalB'<1:0> of the next memory chip 10, and the first second driving circuit 321 generates the second identification signal SignalB'<1:0> of the next memory chip 10. <0> The second second driving circuit 321 sends SignalB' to the conductive vias B0-B3. <1> Sent to the conductive vias of B4 to B7.

[0104] In other words, the second transmission structure supports both top-down and bottom-up transmission, thereby implementing the two numbering mechanisms for the aforementioned initialization process and normal operation process. Specifically, the memory chips 10 provided in the embodiments of the present disclosure support face-to-face stacking. Referring to Tables 1 and 2 above, memory chips 0 and 1 are stacked face-to-face, memory chips 1 and 2 are stacked back-to-back, memory chips 2 and 3 are stacked face-to-face, and so on. In this way, when the signal is transmitted upward from the logic chip, memory chip 0, memory chip 2, memory chip 4, and memory chip 6 are facing upward, and it is necessary to obtain the second identification signal SignalB<1:0> from the conductive through-hole (second transmission structure) passing through the substrate, and send the newly generated second identification signal SignalB'<1:0> into the contact structure (second transmission structure) passing through the top surface; memory chip 1, memory chip 3, memory chip 5, and memory chip 7 are facing downward, and it is necessary to obtain the second identification signal SignalB<1:0> from the contact structure (second transmission structure) passing through the top surface, and send the newly generated second identification signal SignalB'<1:0> into the conductive through-hole. When transmitting from the top memory chip downward to the logic chip, the transmission direction of each memory chip is exactly opposite to the above description. Specifically, memory chip 0, memory chip 2, memory chip 4, and memory chip 6 are facing upward, and need to obtain the second identification signal SignalB<1:0> from the contact structure (second transmission structure) running through the top surface, and send the newly generated second identification signal SignalB'<1:0> into the conductive through-hole (second transmission structure) running through the substrate; memory chip 1, memory chip 3, memory chip 5, and memory chip 7 are facing downward, and need to obtain the second identification signal SignalB<1:0> from the conductive through-hole (second transmission structure) running through the substrate, and send the newly generated second identification signal SignalB'<1:0> into the contact structure (second transmission structure) running through the top surface.

[0105] Therefore, in some embodiments, see Figure 5 The second driving circuit 321 includes a first OR logic circuit 41, an even driving input circuit 42, and an odd driving output circuit 43; the input terminal of the first OR logic circuit 41 is coupled to the conductive via of each second transmission structure in the corresponding second transmission structure group, the even driving input circuit 42 is coupled between the output terminal of the first OR logic circuit 41 and the input terminal of the logic operation circuit 33, and the odd driving output circuit 43 is coupled between the output terminal of the logic operation circuit 33 and the conductive via of each second transmission structure in the corresponding second transmission structure group;

[0106] The third driving circuit 322 includes a second OR logic circuit 44, an even driving output circuit 46, and an odd driving input circuit 45; the input terminal of the second OR logic circuit 44 is coupled to the contact structure of each second transmission structure in the corresponding second transmission structure group, the odd driving input circuit 45 is coupled between the output terminal of the second OR logic circuit 44 and the input terminal of the logic operation circuit 33, and the even driving output circuit 46 is coupled between the output terminal of the logic operation circuit 33 and the contact structure of each second transmission structure in the corresponding second transmission structure group;

[0107] Among them, the control end of the odd drive input circuit 45 and the control end of the odd drive output circuit 43 both receive the first odd switch signal odd1; the control end of the even drive input circuit 42 and the control end of the even drive output circuit 46 both receive the first even switch signal even1; if the chip position identification code CID<1:0> indicates that the memory chip is in an odd-numbered position, the first odd switch signal odd1 is in an enabled state and the first even switch signal even1 is in a disabled state; if the chip position identification code CID<1:0> indicates that the memory chip is in an even-numbered position, the first odd switch signal odd1 is in a disabled state and the first even switch signal even1 is in an enabled state.

[0108] The specific code values ​​for odd-numbered positions should be determined based on the actual application scenario, while the specific code values ​​for even-numbered positions should be determined based on the actual application scenario. Specifically, the odd-numbered and even-numbered positions are not simply the parity of the actual chip positions. Even-numbered positions refer to the locations of the memory chips that require the second identification signal to be transmitted from the bottom surface to the top surface, while odd-numbered positions refer to the locations of the memory chips that require the second identification signal to be transmitted from the top surface to the bottom surface. Referring to Tables 1 and 2 above, when CID<1:0> = 00 / 10, it can be considered to be in an odd-numbered position; when CID<1:0> = 01 / 11, it can be considered to be in an even-numbered position.

[0109] So, see Figure 7A If the memory chip 10 is in an even-numbered position, the even-drive input circuit 42 and the even-drive output circuit 46 are turned on. The memory chip 10 receives the second identification signal signalB<1:0> from the conductive vias of the second transmission structure to generate its own stacking position identification code SID<1:0>, and transmits the newly generated second identification signal signalB'<1:0> through the contact structure of the second transmission structure, that is, the second identification signal is transmitted from the bottom surface to the top surface. Figure 7B If the memory chip 10 is in an odd-numbered position, the odd drive input circuit 45 and the odd drive output circuit 43 are turned on, and the memory chip 10 receives the second identification signal signalB<1:0> from the contact structure of the second transmission structure to generate its own stacking position identification code SID<1:0>, and sends the newly generated second identification signal signalB'<1:0> through the conductive through-hole of the second transmission structure, that is, the second identification signal is transmitted from the top surface to the bottom surface.

[0110] It should also be noted that the signals transmitted by the four second transmission structures generate corresponding second identification signals after OR logic, which has the following advantages: the signals transmitted by the four second transmission structures generate a second identification signal after OR logic. If the path corresponding to one of the second transmission structures is damaged, it will not affect the overall transmitted second identification signal. On the contrary, the other second transmission structures in the same group can still ensure the normal transmission of the second identification signal, thereby improving the memory chip's ability to resist damage.

[0111] In some embodiments, as Figure 8 As shown, the logic operation circuit 33 includes: an adder 331 and a selection circuit 332; the adder 331 is configured to add one to the stacking position identification code SID<1:0> and output a stacking code carry signal; the selection circuit 332 is configured to output the stacking code carry signal as the second identification signal signalB'<1:0> of the next memory chip 10 if the first control signal is valid; if the first control signal is invalid, the stacking position identification code SID is directly output as the second identification signal signalB'<1:0> of the next memory chip 10.

[0112] See Figure 8 In order to ensure delay consistency while ensuring signal strength and signal transmission delay, the stack position identification code SID<1:0> can be connected to the selection circuit 332 through a buffer (or driver).

[0113] Thus, for the last memory chip of each stacking unit, the stacking position identification code SID<1:0> is output to the next memory chip after adding one; for the other memory chips of each stacking unit, the stacking position identification code SID<1:0> is directly transmitted to the next memory chip.

[0114] In some embodiments, see Figure 9 , which shows a schematic diagram of signal transmission of the memory chip 10. Figure 9 As shown, the logic processing circuit 32 also includes a weak drive circuit (please refer to Figure 9 323 and 324);

[0115] The logic processing circuit 32 is further configured to generate a second identification signal signalB<1:0> in a default state based on the weak driving circuit if the second transmission structure does not transmit a valid signal; and to generate a second identification signal signalB<1:0> based on the valid signal transmitted by the second transmission structure if the second transmission structure transmits a valid signal.

[0116] Exemplarily, the default state is a low level. In simple terms, if there is no signal transmission in the second transmission structure (more precisely, when there is no external strong drive signal transmission in the second transmission structure), it is in a low level state. In this way, the weak drive circuit can enable the bottommost or topmost chip to generate the second identification signal signalB<1:0> in the default state. It is only necessary to change the transmission direction of the second identification signal to meet the bottom-up transmission during the initialization process or the top-down transmission during normal operation; in addition, as mentioned above, the signals transmitted by the four second transmission structures generate a second identification signal after the OR logic. If the path corresponding to one of the second transmission structures is damaged, the second transmission structure is in a low level state and will not affect the second identification signal transmitted as a whole.

[0117] In some embodiments, as Figure 9 As shown, the weak driving circuit includes B first logic devices 323 ( Figure 9 Only one is shown), B second logic units 324 ( Figure 9 Only 1 shown);

[0118] Each odd drive input circuit 45 is coupled to a first logic device 323; the odd drive input circuit 45 includes a first inverting drive unit 451 and a second inverting drive unit 452, and the output end of the second OR logic circuit 44 is connected to the input end of the first inverting drive unit 451, the output end of the first inverting drive unit 451 is connected to the input end of the second inverting drive unit 452, the output end of the second inverting drive unit 452 is connected to the input end of the logic operation circuit 33, and the control end of the first inverting drive unit 451 and the control end of the second inverting drive unit 452 both receive the first odd switching signal odd1; the output end of the first logic device 323 is connected to the input end of the first inverting drive unit 451, the first input end of the first logic device 323 receives the power-on indication signal poweron, and the second input end of the first logic device 323 is connected to the output end of the first inverting drive unit 451.

[0119] Each even drive input circuit 42 is coupled to a second logic device 324; the even drive input circuit 42 includes a third inverting drive unit 421 and a fourth inverting drive unit 422, and the output end of the first OR logic circuit 41 is connected to the input end of the third inverting drive unit 421, the output end of the third inverting drive unit 421 is connected to the input end of the fourth inverting drive unit 422, the output end of the fourth inverting drive unit 422 is connected to the input end of the logic operation circuit 33, and the control end of the third inverting drive unit 421 and the control end of the fourth inverting drive unit 422 both receive the first even switch signal even1; the output end of the second logic device 324 is connected to the input end of the third inverting drive unit 421, the first input end of the second logic device 324 receives the power-on indication signal poweron, and the second input end of the second logic device 324 is connected to the output end of the third inverting drive unit 421.

[0120] In a specific embodiment, the first logic unit 323 and the second logic unit 324 are both two-input NOR gates; after the memory chip 10 is powered on, the power-on indication signal poweron is high; and the second identification signal is low by default. However, this does not constitute a limitation.

[0121] In this way, after power-on, when the second identification signal is determined, the input and output level states of the weak drive circuit of the above structure remain locked, and there is no static current path, which effectively reduces circuit power consumption and avoids affecting other structures.

[0122] In another embodiment, the weak driving circuit may be implemented by a fixed resistor (with a relatively large resistance) connected to the ground, or by other methods not mentioned.

[0123] For example, the first transmission structure can be a conductive via extending through the entire chip along the third direction. Alternatively, the first transmission structure can be similar to the second transmission structure, consisting of a conductive via that does not extend through the entire memory chip and a contact structure. Here, the conductive via includes at least a through silicon via (TSV), specifically a vertical interconnect structure, or, in other embodiments, other conductive vias, without specific limitation.

[0124] Specifically, the first transmission structure is prepared by any one or more processes including the via-first, via-middle, via-last, and back side via-last processes; the conductive vias in the second transmission structure are prepared by any one or more processes including the via-first, via-middle, and back side via-last processes; different first transmission structures and different second transmission structures are electrically isolated from each other.

[0125] It should be noted that the "via-first" process refers to a through-hole process method that fabricates a through-hole structure before manufacturing the device structure of a device, such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET or MOS tube). The "intermediate" process is a through-hole structure formed during the manufacturing process flow, often after the device is formed and before the stack is manufactured. The "via-last" process is a manufacturing process that forms through-holes from the front side of the wafer after the back-end of line (BEOL) process is completed. The "back-end" process is a manufacturing process that forms through-holes from the back side of the wafer after the BEOL process is completed. In other words, the "via-first" process can refer to forming the through-hole first and then the circuit; the "intermediate" process can refer to forming the circuit and part of the metal layer first, then forming the through-hole, and finally the remaining through-hole; the "via-last" process and the "back-end" process can refer to forming the circuit and metal layer first and then the through-hole.

[0126] In addition, the contact structure may include at least one or more of the following structures: a copper pillar, a metal interconnection line, and a bump.

[0127] Thus, the embodiment of the present disclosure provides a memory chip 10, wherein the transmission structure has a four-quadrant symmetry (symmetrical about the first axis and about the second axis), which can be directly applied to face-to-face, back-to-back, and back-to-face stacking structures, and can be realized by physical direct connection. Figure 2B The rotating connection structure shown (see subsequent description for details) has relatively low parasitic capacitance and parasitic resistance. The invention also provides a transmission principle of the chip position identification code and the stacking position identification code, which has the following advantages: (1) the chip position identification code CID can be transmitted using only four first transmission structures, without the need to set up an independent transmission structure for the chip position identification code CID of each memory chip, which can reduce the number of first transmission structures and save chip area and cost; (2) the stacking position identification code SID is transmitted by the second transmission structure formed by the conductive through hole and the contact structure, and the last memory chip of each stacking unit is automatically added by one, so that only two second transmission structure groups (i.e., eight second transmission structures) are required to achieve it, and there is no need to set up an independent transmission structure for the chip position identification code SID of each memory chip, which can reduce the second transmission structure and save chip area and cost; (3) the second transmission structure can be transmitted from top to bottom or from bottom to top, so that the transmission logic can be well implemented when stacking face to face, and supports two numbering mechanisms during initialization and normal operation; (4) the second transmission structure group transmits one bit of the stacking position identification code SID together, and can still ensure correct transmission when some second transmission structures fail, thereby improving fault response performance.

[0128] In yet another embodiment of the present disclosure, see Figure 10 , which shows a logic chip 50 provided by an embodiment of the present disclosure. The top surface of the logic chip 50 has a first axis AA' and a second axis BB'. The first axis AA' and the second axis BB' intersect perpendicularly at the center of the top surface. The first axis AA' is parallel to one edge of the top surface, and the second axis BB' is parallel to the other edge of the top surface.

[0129] The logic chip 50 includes four third transmission structures (C0-C3) and B fourth transmission structure groups, where B is a natural number. Figure 10 Taking B=2 as an example, the first fourth transmission structure group is represented by D0-D3, and the second fourth transmission structure group is represented by D4-D7. The four third transmission structures are symmetrical about the first axis AA', and the four third transmission structures are symmetrical about the second axis BB'. Each fourth transmission structure group includes four fourth transmission structures, and the four fourth transmission structures are symmetrical about the first axis AA' and the four fourth transmission structures are symmetrical about the second axis BB'.

[0130] The logic chip 50 is configured to generate four first identification signals and transmit the four first identification signals to the four third transmission structures in a one-to-one correspondence; wherein the four first identification signals indicate the chip position identification code of the memory chip adjacent to the logic chip 50 (i.e., memory chip 0); the logic chip 50 is further configured to receive one second identification signal from each fourth transmission structure group during the initialization process and generate a stacking position identification code based on B second identification signals; or, in the normal operation stage, generate B second identification signals in a default state and send one second identification signal to one fourth transmission structure group, so that other memory chips receive corresponding second identification signals from their respective fourth transmission structure groups to generate their own stacking position identification codes.

[0131] In some embodiments, see Figure 11 The logic chip 50 also includes a first signal generating circuit 52 and four fourth driving circuits 51. The four fourth driving circuits 51 are coupled to the four third transmission structures C0~C3 in a one-to-one correspondence; the first signal generating circuit 52 is coupled to the four fourth driving circuits 51, and is configured to generate four first identification signals signalA<3:0> during the initialization process, and the level state of the four first identification signals signalA<3:0> is a first combination value; during the normal operation process, the four first identification signals signalA<3:0> are generated, and the level state of the four first identification signals is a second combination value; wherein the first combination value and the second combination value are not completely the same.

[0132] In particular, for the logic chip 50, the first identification signal signalA <0> It is not necessarily transmitted by the first transmission structure C0, but may also be transmitted by the first transmission structure C3 or the first transmission structure C2; ​​the remaining first identification signals signalA also have similar problems, and the stacking form of the logic chip 50 and the memory chip 10 needs to be considered. Here, you can further refer to the diagram of the chip stacking structure below for understanding.

[0133] For example, during normal operation, the four first identification signals signalA<3:0> = 0001, so that the CID<1:0> of logic chip 0 and memory chip 0 = 00, as shown in Table 1. During initialization, the four first identification signals signalA<3:0> = 1000, so that the CID<1:0> of logic chip 0 and memory chip 0 = 11, as shown in Table 2. Thus, for the chip stack structure 50, during normal operation, the numbering of each memory chip is counted starting from the side of logic chip 50 (e.g., Table 1), while during initialization, the numbering of each memory chip is counted starting from the side away from logic chip 50 (e.g., Table 2). For details, please refer to the subsequent description.

[0134] In some embodiments, please refer to Figure 12 , which is illustrated by taking B=2 as an example, the logic chip 50 further includes a second signal generating circuit 64, B third OR logic circuits 61, B control input circuits 62, and B control output circuits 63;

[0135] The second signal generating circuit 64 is coupled to the B control output circuits 63 and is configured to generate B second identification signals of a default state in a normal working phase and to convert the i-th second identification signal signalB <i-1>The output terminal of the i-th control output circuit 63 is coupled to each fourth transmission structure in the i-th fourth transmission structure group. i is a natural number less than or equal to B.

[0136] Each fourth transmission structure in the i-th fourth transmission structure group is coupled to an input terminal of the i-th third OR logic circuit 61, an output terminal of the third OR logic circuit 61 is coupled to an input terminal of the i-th control output circuit 63, and an output terminal of the i-th control input circuit 62 is coupled to an internal circuit of the logic chip 50;

[0137] During the initialization process, the output terminal of the i-th control input circuit 62 outputs the i-th second identification signal signalB to the internal circuit of the logic chip 50. <i-1>(Also equivalent to Figure 12 SID in <i-1>);

[0138] Among them, the control end of the control output circuit 63 receives the output enable signal Outen, and the control end of the control input circuit 62 receives the input enable signal Inen; if the logic chip 50 is in the normal working stage, the input enable signal Inen is in the non-enabled state, and the output enable signal Outen is in the enabled state; if the logic chip 50 is in the initialization process, the input enable signal Inen is in the enabled state, and the output enable signal Outen is in the non-enabled state.

[0139] In other embodiments, the second signal generating circuit 64 and the control output circuit 63 may not be provided, but a weak driving circuit similar to the above description may be provided to generate the second identification signal of the default state.

[0140] Thus, during the normal operation phase, the four first identification signals signalA<3:0>=0001, and the chip position identification code CID<1:0>=00 (even-numbered position), then the control output circuit 63 is in the enabled state (on), and the control input circuit 62 is in the disabled state (off). At this time, SID<1:0>=00 generated by the second signal generating circuit 64 is transmitted upward along the fourth transmission structure group as signglB<1:0>; taking the chip stacking structure formed by the logic chip 50 and 8 memory chips as an example, during the initialization process, the four first identification signals signalA<3:0>=1000 in the logic chip, and the chip position identification code CID<1:0>=11 (odd-numbered position), then the control output circuit 63 is in the disabled state, and the control input circuit 62 is in the enabled state. At this time, the logic chip 50 receives signglB<1:0>=10 from the fourth transmission structure group, that is, SID<1:0>=10.

[0141] In some embodiments, the third transmission structure or the fourth transmission structure is prepared by any one or more of the via-first, via-middle, via-last, and back side via-last processes; different third transmission structures and different fourth transmission structures are electrically isolated from each other.

[0142] That is, the third transmission structure and the fourth transmission structure may each be a conductive via penetrating the entire chip, or may be in the form of a conductive via that does not penetrate the entire chip + a contact structure, or may be other forms not mentioned.

[0143] In yet another embodiment of the present disclosure, see Figure 13 , which shows a chip stacking structure 70 provided by an embodiment of the present disclosure, the chip stacking structure 70 includes the aforementioned logic chip 50 and at least one stacking unit, and the logic chip 50 and the at least one stacking unit are stacked in sequence along a third direction; each stacking unit includes a first memory chip 11, a second memory chip 12, a third memory chip 13 and a fourth memory chip 14 stacked in sequence along the third direction, and the third direction is perpendicular to the top surface of each memory chip; the first memory chip 11, the second memory chip 12, the third memory chip 13, and the fourth memory chip 14 all adopt the structure of the aforementioned memory chip 10.

[0144] The first memory chip 11 and the second memory chip 12 are stacked face to face, the second memory chip 12 and the third memory chip 13 are stacked back to back, and the third memory chip 13 and the fourth memory chip 14 are stacked face to face; the logic chip 50 and the first memory chip 11 (in the first stacking unit) are stacked back to back; or, the logic chip 50 and the first memory chip 11 are stacked face to back.

[0145] It should be understood that Figure 13 In the figure, only four transmission structures are shown instead of all of them. These four transmission structures can be understood as four first transmission structures or as one second transmission structure group.

[0146] In the embodiments of the present disclosure, face-to-face stacking means that the top surfaces of two chips are approximately aligned along a third direction, and the center points, first axes, and second axes of the top surfaces of the two chips are all aligned along the third direction. Back-to-back stacking means that the top surfaces of two chips are approximately aligned along the third direction. Back-to-back stacking means that the top surface of one chip is approximately aligned with the bottom surface of another chip along the third direction. Unless logic chip or memory chip is specified, "chip" can refer to both logic chip and memory chip.

[0147] In some embodiments, it should be noted that, in one possibility, for two chips connected face to face, the bonding surfaces of the two (the positions where the conductive vias are aligned along the third direction) are electrically connected through a hybrid bonding structure (Hyperbonding, also known as bonding columns); for two chips connected back to back or for two chips connected face to back, the bonding surfaces of the two (the positions where the conductive vias are aligned along the third direction) are electrically connected through conductive bumps (UBumps, also known as microbumps).

[0148] In another possibility, for two chips connected face-to-face, or for two chips connected back-to-back, or for two chips connected face-to-back, the bonding surfaces of both chips (the locations where the middle conductive vias are aligned along the third direction) are connected via a hybrid bonding structure. In other words, the bonding surfaces between the two chips connected face-to-face (the locations where the middle conductive vias are aligned along the third direction) are electrically connected via a hybrid bonding structure, and the bonding surfaces between the two chips connected back-to-back (the locations where the middle conductive vias are aligned along the third direction) and the bonding surfaces between the two chips connected face-to-back (the locations where the middle conductive vias are aligned along the third direction) are also electrically connected via a hybrid bonding structure.

[0149] In another possibility, for two chips connected face to face or for two chips connected back to back, the bonding surfaces of both chips (the locations where the conductive vias / contact structures are aligned along the third direction) are connected via conductive bumps. In other words, the bonding surfaces between the two chips connected face to face (the locations where the conductive vias / contact structures are aligned along the third direction) are connected via conductive bumps, and the bonding surfaces between the two chips connected back to back (the locations where the conductive vias / contact structures are aligned along the third direction) and the bonding surfaces between the two chips connected face to back (the locations where the conductive vias / contact structures are aligned along the third direction) are also connected via conductive bumps.

[0150] Here, the above chip may refer to a logic chip 50 or a memory chip 10 .

[0151] It should be noted that, compared with the conductive bump process, the face-to-face connection using the hybrid bonding process can make the adjacent chips fit more closely, with basically no gaps, thereby greatly reducing the height of the chip stacking structure, which is also one of the advantages of face-to-face stacking. Of course, two chips connected back to back can also be connected through a hybrid bonding structure, but its connection performance is weaker than that of face-to-face connection. It should also be noted that when the transmission structure in the memory chip is a back through hole or a back through hole from the back of the wafer, the connection between the memory chips is a through hole connection; when the transmission structure in the memory chip is a first through hole or a middle through hole, for the two memory chips connected face to face, the positions of the conductive through holes in the bonding surfaces of the two chips aligned along the third direction can be electrically connected by a hybrid bonding process or a conductive bump bonding process.

[0152] It should be noted that each chip includes a high-order transmission area and a low-order transmission area. Figure 13 The arrows on each chip indicate the high-order transmission area. In particular, the high-order transmission area and the low-order transmission area in the embodiment of the present disclosure are merely two areas to distinguish the memory chips, and do not have any additional restrictions. They have nothing to do with the high-order data and low-order data commonly used in data transmission.

[0153] at the same time Figure 13 The first axis AA' is used as the dividing line between the high-level transmission area and the low-level transmission area for the schematic diagram. In other embodiments, the second axis BB' can also be used as the dividing line between the high-level transmission area and the low-level transmission area.

[0154] In some embodiments, see Figure 14A The top surface of the logic chip 50 or each memory chip is divided into 2×2 signal areas. The first signal area 70a and the second signal area 70b are symmetrical along their respective first axis AA', the first signal area 70a and the fourth signal area 70d are symmetrical along their respective second axis BB', and the third signal area 70c and the fourth signal area 70d are symmetrical along their respective first axis AA'. The first axis AA' of the logic chip 50 and the first axis AA' of each memory chip are aligned along a third direction, and the second axis BB' of the logic chip 50 and the second axis BB' of each memory chip are aligned along the third direction.

[0155] See Figure 14A , when the logic chip 50 and the first memory chip 11 are stacked back to back,

[0156] (1) The fourth signal area 70d of the logic chip 50, the first signal area 70a of the first memory chip 11, the second signal area 70b of the second memory chip 12, the third signal area 70c of the third memory chip 13, and the fourth signal area 70d of the fourth memory chip 14 are aligned along the third direction;

[0157] (2) The third signal area 70c of the logic chip 50, the second signal area 70b of the first memory chip 11, the first signal area 70a of the second memory chip 12, the fourth signal area 70d of the third memory chip 13, and the third signal area 70c of the fourth memory chip 14 are aligned along the third direction;

[0158] (3) The second signal area 70 b of the logic chip 50 , the third signal area 70 c of the first memory chip 11 , the fourth signal area 70 d of the second memory chip 12 , the first signal area 70 a of the third memory chip 13 , and the second signal area 70 b of the fourth memory chip 14 are aligned along the third direction;

[0159] (4) The first signal area 70a of the logic chip 50, the fourth signal area 70d of the first memory chip 11, the third signal area 70c of the second memory chip 12, the second signal area 70b of the third memory chip 13, and the first signal area 70a of the fourth memory chip 14 are aligned along the third direction.

[0160] In short, the placement of the logic chip 50 is the same as that of the fourth memory chip 14 .

[0161] It should be noted that due to process errors, the "alignment" in this embodiment is not an absolute alignment, and any deviation within a reasonable range can be considered as alignment.

[0162] It should be noted that the overall area of ​​the top surface of the logic chip 50 and the area of ​​the top surface of the memory chip 10 may or may not be completely consistent. If the top surface areas of the logic chip 50 and the memory chip 10 are different, the above-mentioned alignment of the signal areas should be adaptively understood as "alignment in orientation."

[0163] Please note that, see Figure 14A The transmission structure in the logic chip 50 or each memory chip is symmetrically distributed among four signal areas. Therefore, in some embodiments, for each memory chip, the four first transmission structures include the first transmission structure_0 (A0), the second transmission structure_1 (A1), the first transmission structure_2 (A2), and the first transmission structure_3 (A3); the first transmission structure_0 (A0) is located in the first signal area 70a, the first transmission structure_1 (A1) is located in the second signal area 70b, the first transmission structure_2 (A2) is located in the third signal area 70c, and the first transmission structure_3 (A3) is located in the fourth signal area 70d; for the logic chip 50, the four third transmission structures include the third transmission structure_0 (C0), the third transmission structure_1 (C1), the third transmission structure_2 (C2), and the third transmission structure_3 (C3); the third transmission structure_0 (C0) is located in the first signal area 70a, the third transmission structure_1 (C1) is located in the second signal area 70b, the third transmission structure_2 (C2) is located in the third signal area 70c, and the third transmission structure_3 (C3) is located in the fourth signal area 70d.

[0164] like Figure 14A As shown, the alignment relationship between the third transmission structure and the first transmission structure is as follows:

[0165] (1) The third transmission structure _3 (C3) of the logic chip 50, the first transmission structure _0 (A0) of the first memory chip 11, the first transmission structure _1 (A1) of the second memory chip 12, the first transmission structure _2 (A2) of the third memory chip 13, and the first transmission structure _3 (A3) of the fourth memory chip 14 are aligned along the third direction and connected to form a signal transmission path;

[0166] (2) The third transmission structure _2 (C2) of the logic chip 50, the first transmission structure _1 (A1) of the first memory chip 11, the first transmission structure _0 (A0) of the second memory chip 12, the first transmission structure _3 (A3) of the third memory chip 13, and the first transmission structure _2 (A2) of the fourth memory chip 14 are aligned along the third direction and connected to form a signal transmission path;

[0167] (3) The third transmission structure _1 (C1) of the logic chip 50, the first transmission structure _2 (A2) of the first memory chip 11, the first transmission structure _3 (A3) of the second memory chip 12, the first transmission structure _0 (A0) of the third memory chip 13, and the first transmission structure _1 (A1) of the fourth memory chip 14 are aligned along the third direction and connected to form a signal transmission path;

[0168] (4) The third transmission structure _0 (C0) of the logic chip 50, the first transmission structure _3 (A3) of the first memory chip 11, the first transmission structure _2 (A2) of the second memory chip 12, the first transmission structure _1 (A1) of the third memory chip 13, and the first transmission structure _0 (A0) of the fourth memory chip 14 are aligned along the third direction and connected to form a signal transmission path.

[0169] Each memory chip obtains the first identification signal signalA of the 0th bit from the first transmission structure_0 (A0) <0> Each of the memory chips obtains the first bit first identification signal signalA from the first transmission structure_1 (A1) <1> Each memory chip obtains the second first identification signal signalA from the first transmission structure_2 (A2) <2> Each of the memory chips obtains the third first identification signal signalA from the first transmission structure_3 (A3) <3> .

[0170] In this way, when the logic chip 50 transmits the first identification signal signalA<3:0> of the same combination value, the code values ​​of the first identification signal signalA<3:0> received by the memory chips at different positions in the same stack unit are different. There is no need to use a separate transmission structure to transmit the first identification signals of different memory chips, thereby reducing the chip area occupied and lowering costs.

[0171] In some embodiments, see Figure 14B , in the case of B=2, for each memory chip, the first second transmission structure group includes the second transmission structure_0 (B0) to the second transmission structure_3 (B3), and the second second transmission structure group includes the second transmission structure_4 (B4) to the second transmission structure_7 (B7); the second transmission structure_0 (B0) and the second transmission structure_4 (B4) are located in the first signal area 70a, the second transmission structure_1 (B1) and the second transmission structure_5 (B5) are located in the second signal area 70b, the second transmission structure_2 (B2) and the second transmission structure_6 (B6) are located in the third signal area 70c, and the second transmission structure_3 (B3) and the second transmission structure_7 (B7) are located in the fourth signal area Area 70d; for the logic chip 50, the first fourth transmission structure group includes the fourth transmission structure _0 (D0) to the fourth transmission structure _3 (D3), and the second fourth transmission structure group includes the fourth transmission structure _4 (D4) to the fourth transmission structure _7 (D7); the fourth transmission structure _0 (D0) and the fourth transmission structure _4 (D4) are located in the first signal area 70a, the fourth transmission structure _1 (D1) and the fourth transmission structure _5 (D5) are located in the second signal area 70b, the fourth transmission structure _2 (D2) and the fourth transmission structure _6 (D6) are located in the third signal area 70c, and the fourth transmission structure _3 (D3) and the fourth transmission structure _7 (D7) are located in the fourth signal area 70d.

[0172] like Figure 14B As shown, the alignment relationship between the fourth transmission structure and the second transmission structure is as follows:

[0173] (1) The fourth transmission structure _3 (D3) of the logic chip 50, the second transmission structure _0 (B0) of the first memory chip 11, the second transmission structure _1 (B1) of the second memory chip 12, the second transmission structure _2 (B2) of the third memory chip 13, and the second transmission structure _3 (B3) of the fourth memory chip 14 are aligned along the third direction and connected to form a signal transmission channel;

[0174] (2) The fourth transmission structure _2 (D2) of the logic chip 50, the second transmission structure _1 (B1) of the first memory chip 11, the second transmission structure _0 (B0) of the second memory chip 12, the second transmission structure _3 (B3) of the third memory chip 13, and the second transmission structure _2 (B2) of the fourth memory chip 14 are aligned along the third direction and connected to form a signal transmission channel;

[0175] (3) The fourth transmission structure _1 (D1) of the logic chip 50, the second transmission structure _2 (B2) of the first memory chip 11, the second transmission structure _3 (B3) of the second memory chip 12, the second transmission structure _0 (B0) of the third memory chip 13, and the second transmission structure _1 (B1) of the fourth memory chip 14 are aligned along the third direction and connected to form a signal transmission channel;

[0176] (4) The fourth transmission structure _0 (D0) of the logic chip 50, the second transmission structure _3 (B3) of the first memory chip 11, the second transmission structure _2 (B2) of the second memory chip 12, the second transmission structure _1 (B1) of the third memory chip 13, and the second transmission structure _0 (B0) of the fourth memory chip 14 are aligned along the third direction and connected to form a signal transmission channel;

[0177] (5) The fourth transmission structure _4 (D4) of the logic chip 50, the second transmission structure _4 (B4) of the first memory chip 11, the second transmission structure _5 (B5) of the second memory chip 12, the second transmission structure _6 (B6) of the third memory chip 13, and the second transmission structure _7 (B7) of the fourth memory chip 14 are aligned along the third direction and connected to form a signal transmission channel;

[0178] (6) The fourth transmission structure _5 (D5) of the logic chip 50, the second transmission structure _5 (B5) of the first memory chip 11, the second transmission structure _4 (B4) of the second memory chip 12, the second transmission structure _7 (B7) of the third memory chip 13, and the second transmission structure _6 (B6) of the fourth memory chip 14 are aligned along the third direction and connected to form a signal transmission channel;

[0179] (7) The fourth transmission structure _6 (D6) of the logic chip 50, the second transmission structure _6 (B6) of the first memory chip 11, the second transmission structure _7 (B7) of the second memory chip 12, the second transmission structure _4 (B4) of the third memory chip 13, and the second transmission structure _5 (B5) of the fourth memory chip 14 are aligned along the third direction and connected to form a signal transmission channel;

[0180] (8) The fourth transmission structure _7 (D7) of the logic chip 50, the second transmission structure _7 (B7) of the first memory chip 11, the second transmission structure _6 (B6) of the second memory chip 12, the second transmission structure _5 (B5) of the third memory chip 13, and the second transmission structure _4 (B4) of the fourth memory chip 14 are aligned along the third direction and connected to form a signal transmission channel.

[0181] It should be noted that the second transmission structure_0 (B0), the second transmission structure_1 (B1), the second transmission structure_2 (B2), and the second transmission structure_3 (B3) are all used to transmit the second identification signal signalB <0> , 4 signalB <0> Generate SID after OR logic <0> The second transmission structure _4 (B4), the second transmission structure _5 (B5), the second transmission structure _6 (B6), and the second transmission structure _7 (B7) are all used to transmit the second identification signal signalB <1> , 4 signalB <1> Generate SID after OR logic <1> .

[0182] It should be noted that in some work scenarios, Figure 14A and Figure 14B The oblique striped columns between the chips can be conductive bumps, hybrid bonding structures, etc.; or it can be understood as: Figure 14A and Figure 14B Essentially, it is used to emphasize the alignment relationship between signal areas, conductive vias, etc. along the third direction, but does not represent the physical structure, and no specific limitation is given to this.

[0183] In particular, for Figure 14A and Figure 14B For example, the first axis AA' is used as the dividing line between the high-order transmission area and the low-order transmission area. At this time, the directions of the logic chip 50, the first transmission chip 11, and the fourth transmission chip 14 (i.e., the high-order transmission area) are in the same orientation (this does not mean that the high-order transmission areas of these chips completely overlap, and there may be a mirror relationship along the horizontal direction); the directions of the second transmission chip 12 and the third transmission chip 13 (i.e., the high-order transmission area) are in the same orientation.

[0184] In other embodiments, the second axis BB' can also be used as the dividing line between the high-position transmission area and the low-position transmission area. In this case, the alignment relationship between the first transmission structure and the third transmission structure can be seen in FIG. Figure 15A For the alignment relationship between the second and fourth transmission structures, see Figure 15B At this time, the logic chip 50, the third transmission chip 13, and the fourth transmission chip 14 are oriented (i.e., the high-level transmission areas) in the same direction (this does not mean that the high-level transmission areas of these chips completely overlap); the first transmission chip 11 and the second transmission chip 12 are oriented (i.e., the high-level transmission areas) in the same direction.

[0185] In some other embodiments, see Figure 16A and Figure 16B , when the logic chip 50 and the first memory chip 11 are stacked back to back,

[0186] (1) The second signal area 70 b of the logic chip 50 , the first signal area 70 a of the first memory chip 11 , the second signal area 70 b of the second memory chip 12 , the third signal area 70 c of the third memory chip 13 , and the fourth signal area 70 d of the fourth memory chip 14 are aligned along a third direction;

[0187] (2) The first signal area 70 a of the logic chip 50 , the second signal area 70 b of the first memory chip 11 , the first signal area 70 a of the second memory chip 12 , the fourth signal area 70 d of the third memory chip 13 , and the third signal area 70 c of the fourth memory chip 14 are aligned along the third direction;

[0188] (3) the fourth signal area 70d of the logic chip 50, the third signal area 70c of the first memory chip 11, the fourth signal area 70d of the second memory chip 12, the first signal area 70a of the third memory chip 13, and the second signal area 70b of the fourth memory chip 14 are aligned along the third direction;

[0189] (4) The third signal area 70c of the logic chip 50, the fourth signal area 70d of the first memory chip 11, the third signal area 70c of the second memory chip 12, the second signal area 70b of the third memory chip 13, and the first signal area 70a of the fourth memory chip 14 are aligned along the third direction.

[0190] In short, the placement of the logic chip 50 is the same as that of the second memory chip 12 .

[0191] See Figure 16A , the alignment form of the third transmission structure and the first transmission structure is:

[0192] (1) The third transmission structure _1 (C1) of the logic chip 50, the first transmission structure _0 (A0) of the first memory chip 11, the first transmission structure _1 (A1) of the second memory chip 12, the first transmission structure _2 (A2) of the third memory chip 13, and the first transmission structure _3 (A3) of the fourth memory chip 14 are aligned along the third direction and connected to form a signal transmission path;

[0193] (2) The third transmission structure _0 (C0) of the logic chip 50, the first transmission structure _1 (A1) of the first memory chip 11, the first transmission structure _0 (A0) of the second memory chip 12, the first transmission structure _3 (A3) of the third memory chip 13, and the first transmission structure _2 (A2) of the fourth memory chip 14 are aligned along the third direction and connected to form a signal transmission path;

[0194] (3) The third transmission structure _3 (C3) of the logic chip 50, the first transmission structure _2 (A2) of the first memory chip 11, the first transmission structure _3 (A3) of the second memory chip 12, the first transmission structure _0 (A0) of the third memory chip 13, and the first transmission structure _1 (A1) of the fourth memory chip 14 are aligned along the third direction and connected to form a signal transmission path;

[0195] (4) The third transmission structure _2 (C2) of the logic chip 50, the first transmission structure _3 (A3) of the first memory chip 11, the first transmission structure _2 (A2) of the second memory chip 12, the first transmission structure _1 (A1) of the third memory chip 13, and the first transmission structure _0 (A0) of the fourth memory chip 14 are aligned along the third direction and connected to form a signal transmission path.

[0196] See him Figure 16B , the alignment form of the fourth transmission structure and the second transmission structure is:

[0197] (1) The fourth transmission structure _1 (D1) of the logic chip 50, the second transmission structure _0 (B0) of the first memory chip 11, the second transmission structure _1 (B1) of the second memory chip 12, the second transmission structure _2 (B2) of the third memory chip 13, and the second transmission structure _3 (B3) of the fourth memory chip 14 are aligned along the third direction and connected to form a signal transmission channel;

[0198] (2) The fourth transmission structure _2 (D2) of the logic chip 50, the second transmission structure _1 (B1) of the first memory chip 11, the second transmission structure _0 (B0) of the second memory chip 12, the second transmission structure _3 (B3) of the third memory chip 13, and the second transmission structure _2 (B2) of the fourth memory chip 14 are aligned along the third direction and connected to form a signal transmission channel;

[0199] (3) The fourth transmission structure _0 (D0) of the logic chip 50, the second transmission structure _2 (B2) of the first memory chip 11, the second transmission structure _3 (B3) of the second memory chip 12, the second transmission structure _0 (B0) of the third memory chip 13, and the second transmission structure _1 (B1) of the fourth memory chip 14 are aligned along the third direction and connected to form a signal transmission channel;

[0200] (4) The fourth transmission structure _3 (D3) of the logic chip 50, the second transmission structure _3 (B3) of the first memory chip 11, the second transmission structure _2 (B2) of the second memory chip 12, the second transmission structure _1 (B1) of the third memory chip 13, and the second transmission structure _0 (B0) of the fourth memory chip 14 are aligned along the third direction and connected to form a signal transmission channel;

[0201] (5) The fourth transmission structure _2 (D2) of the logic chip 50, the second transmission structure _4 (B4) of the first memory chip 11, the second transmission structure _5 (B5) of the second memory chip 12, the second transmission structure _6 (B6) of the third memory chip 13, and the second transmission structure _7 (B7) of the fourth memory chip 14 are aligned along the third direction and connected to form a signal transmission channel;

[0202] (6) The fourth transmission structure _5 (D5) of the logic chip 50, the second transmission structure _5 (B5) of the first memory chip 11, the second transmission structure _4 (B4) of the second memory chip 12, the second transmission structure _7 (B7) of the third memory chip 13, and the second transmission structure _6 (B6) of the fourth memory chip 14 are aligned along the third direction and connected to form a signal transmission channel;

[0203] (7) The fourth transmission structure _6 (D6) of the logic chip 50, the second transmission structure _6 (B6) of the first memory chip 11, the second transmission structure _7 (B7) of the second memory chip 12, the second transmission structure _4 (B4) of the third memory chip 13, and the second transmission structure _5 (B5) of the fourth memory chip 14 are aligned along the third direction and connected to form a signal transmission channel;

[0204] (8) The fourth transmission structure _7 (D7) of the logic chip 50, the second transmission structure _7 (B7) of the first memory chip 11, the second transmission structure _6 (B6) of the second memory chip 12, the second transmission structure _5 (B5) of the third memory chip 13, and the second transmission structure _4 (B4) of the fourth memory chip 14 are aligned along the third direction and connected to form a signal transmission channel.

[0205] In particular, for Figure 16A and Figure 16B For example, the first axis AA' is used as the dividing line between the high-level transmission area and the low-level transmission area. At this time, the directions of the logic chip 50, the second transmission chip 12, and the third transmission chip 13 (i.e., the high-level transmission area) are in the same orientation (which does not mean that the high-level transmission areas of these chips completely overlap); the directions of the first transmission chip 11 and the fourth transmission chip 14 (i.e., the high-level transmission area) are in the same orientation.

[0206] In other embodiments, the second axis BB' can also be used as the dividing line between the high-position transmission area and the low-position transmission area. In this case, the alignment relationship between the first transmission structure and the third transmission structure can be seen in FIG. Figure 17A For the alignment relationship between the second and fourth transmission structures, see Figure 17B At this time, the logic chip 50, the first transmission chip 11, and the second transmission chip 12 are oriented (i.e., the high-level transmission areas) in the same direction (this does not mean that the high-level transmission areas of these chips completely overlap); the third transmission chip 13 and the fourth transmission chip 14 are oriented (i.e., the high-level transmission areas) in the same direction.

[0207] From the above, it can be seen that for the chip stacking structure 70, the transmission structure along the third direction in different chips is different. Specifically, from a physical point of view, the conductive vias are still in a direct connection configuration, but from the absolute position of the conductive vias, the conductive vias can be regarded as a functional rotation configuration, that is, a similar direct connection configuration is achieved through the physical direct connection configuration. Figure 2B The signal transmission effect (i.e. the rotation transmission effect of transmission structure_0-transmission structure_1-transmission structure_2-transmission structure_3...). In simple terms, Figure 2B The chip stacking structure in the chip stacking process requires a physical spiral structure, in which there must be a horizontal interconnection structure. Figures 14A to 17B The chip stacking structure is physically a direct connection structure, which does not require a horizontal interconnection structure. The parasitic resistance is greatly reduced, and the transmission speed and transmission performance are greatly improved.

[0208] Combining the working principles of the comparison circuit, logic processing circuit, and logic operation circuit in each memory chip, the transmission principle of the SID and CID in the chip stack structure 70 is as follows:

[0209] Please refer to Table 3. During normal operation, the logic chip generates the initial combination of signalA<3:0>. After the transmission of the third transmission structure and the first transmission structure, the memory chip 0 and the memory chip 4 receive signalA<3:0>=0001, and the decoded CID<1:0>=00, which means that they are the 0th memory chip in the stacking unit. The memory chip 1 and the memory chip 5 receive signalA<3:0>=0010, and the decoded CID<1:0>=01 , indicating that it is the first memory chip in the stacking unit to which it belongs; memory chip 2 and memory chip 6 receive signalA<3:0>=0100, and thus decoded CID<1:0>=10, indicating that it is the second memory chip in the stacking unit to which it belongs; memory chip 3 and memory chip 7 receive signalA<3:0>=1000, and thus decoded CID<1:0>=11, indicating that it is the third memory chip in the stacking unit to which it belongs (i.e., the last memory chip in the stacking unit). At the same time, SID is transmitted from bottom to top, and the second signal generating circuit in the logic chip 50 makes its SID<1:0>=00. When SID<1:0> is transmitted upward to the memory chip 3, since the memory chip 3 is the last chip in the stacking unit, the memory chip 3 adds one to SID<1:0> and transmits it to the memory chip 4. The memory chip 4 receives SID<1:0>=01, so that the SID<1:0>=00 of the memory chip 0 to the memory chip 3, but the SID<1:0>=01 of the memory chip 4 to the memory chip 7.

[0210] Please refer to Table 4. During the initialization process, the logic chip generates an initial combination of signalA<3:0>. After transmission through the third transmission structure and the first transmission structure, memory chip 0 and memory chip 4 receive signalA<3:0>=1000, and the decoded CID<1:0>=11, indicating that they are the third memory chip in their stacking unit. Memory chip 1 and memory chip 5 receive signalA<3:0>=0100, and the decoded CID<1:0>=10, indicating that they are the second memory chip in their stacking unit. Memory chip 2 and memory chip 6 receive signalA<3:0>=0010, and the decoded CID<1:0>=01, indicating that they are the first memory chip in their stacking unit. Memory chip 3 and memory chip 7 receive signalA<3:0>=0001, and the decoded CID<1:0>=00, indicating that they are the zeroth memory chip in their stacking unit. At the same time, SID is transmitted from top to bottom. The weak drive circuit in memory chip 7 makes its SID<1:0>=00. When SID<1:0> is transmitted downward to memory chip 4, since memory chip 4 is the last chip in the stacking unit, memory chip 4 adds one to SID<1:0> and transmits it to memory chip 3. Memory chip 3 receives SID<1:0>=01, so that SID<1:0>=01 of memory chip 0 to memory chip 3, but SID<1:0>=00 of memory chip 4 to memory chip 7.

[0211] Table 3

[0212]

[0213] Table 4

[0214]

[0215] From the above, it can be seen that the embodiment of the present disclosure provides a chip stacking structure 70, in which the transmission structure has a four-quadrant symmetry (symmetrical about the first axis and about the second axis), which can be directly applied to face-to-face, back-to-back, and back-to-face stacking structures, and has the following advantages: (1) Only four first transmission structures are needed to realize the transmission of the chip position identification code CID, without the need to set four first transmission structures for each memory chip; in simple terms, for a chip stacking structure formed by eight memory chips and logic chips, only four first transmission structures need to be set, and the number of first transmission structures is small, saving chip area and cost; (2) By means of conductive through holes and contact structures, the chip position identification code CID can be transmitted. The second transmission structure formed together transmits the stacking position identification code SID, and the last memory chip performs an addition operation by itself, so that only two second transmission structure groups (i.e., eight second transmission structures) are needed to achieve the desired result. The number of second transmission structures is small, saving chip area and cost. (3) The second transmission structure can be transmitted from top to bottom or from bottom to top, so that the transmission logic can be well implemented when stacked face to face, and supports two numbering mechanisms during initialization and normal operation. (4) The second transmission structure group transmits one bit of the stacking position identification code SID as a whole, and can still ensure correct transmission when part of the second transmission structure fails, thereby improving fault response performance. In addition, the chip stacking structure formed by the memory chip 10 is compared with Figure 2A The memory chip 10 reduces parasitic capacitance, which not only saves circuit area but also reduces chip manufacturing cost; and the chip stacking structure formed by the memory chip 10 is compared with Figure 2B The memory chip 10 reduces the parasitic resistance (for specific reasons, please refer to the subsequent description).

[0216] In yet another embodiment of the present disclosure, see Figure 18 , which shows a schematic diagram of the structure of a memory 80 provided by an embodiment of the present disclosure. Figure 18 As shown, the memory 80 includes at least the aforementioned chip stack structure 70. The memory 80 can be, for example, a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), etc., and is not specifically limited here.

[0217] The above are only preferred embodiments of the present disclosure and are not intended to limit the scope of protection of the present disclosure. It should be noted that in the present disclosure, the terms "include", "comprise" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. The above serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments if there is no conflict. The features disclosed in the several product embodiments provided in the present disclosure can be arbitrarily combined to obtain new product embodiments if there is no conflict. The features disclosed in the several method or device embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments if there is no conflict. The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A memory chip, characterized in that: The top surface of the memory chip has a first axis and a second axis, the first axis and the second axis perpendicularly intersect the center of the top surface, the first axis is parallel to one edge of the top surface, and the second axis is parallel to the other edge of the top surface; The memory chip includes 4 first transmission structures and B second transmission structure groups, where B is a natural number; The four first transmission structures are symmetrical about the first axis, and the four first transmission structures are symmetrical about the second axis; Each second transmission structure group includes four second transmission structures, the four second transmission structures are symmetrical about the first axis, and the four second transmission structures are symmetrical about the second axis; The memory chip receives one first identification signal from each of the first transmission structures, and generates a chip position identification code based on four first identification signals; The four second transmission structures in the same second transmission structure group transmit the same signal level, the memory chip receives one second identification signal from each second transmission structure group, and generates a stacking position identification code based on B second identification signals; The memory chip determines its own position number in the chip stacking structure according to the stacking position identification code and the chip position identification code.

2. The memory chip according to claim 1, wherein: The memory chip further includes four first driving circuits and a first decoding circuit, and the four first driving circuits are coupled to the four first transmission structures in a one-to-one correspondence; The first decoding circuit is coupled to the four first driving circuits and configured to receive the four first identification signals via the four first driving circuits and decode the received four first identification signals to generate the chip position identification code; Wherein, four of the memory chips are stacked to form a stacking unit, and the chip position identification code indicates the position number of the memory chip in the stacking unit to which it belongs.

3. The memory chip according to claim 2, wherein: The memory chip further includes a comparison circuit, a logic processing circuit and a logic operation circuit; The comparison circuit is coupled to the first decoding circuit and configured to generate a valid first control signal when the chip position identification code is the same as a preset chip position identifier; wherein the preset chip position identifier indicates that the memory chip is the last chip in the stacking unit; The logic processing circuit is coupled to the B second transmission structure groups and configured to receive one second identification signal from each second transmission structure group and generate the stacking position identification code based on the received B second identification signals; wherein a plurality of the stacking units are stacked to form a chip stacking structure, and the stacking position identification code indicates a position number of the stacking unit to which the memory chip belongs in the chip stacking structure; The logic operation circuit is coupled to the comparison circuit and the logic processing circuit respectively, and is configured to receive the first control signal and the stacking position identification code, and when the first control signal is valid, perform an addition operation on the stacking position identification code to generate and output the second identification signal of the next memory chip; when the first control signal is invalid, output the stacking position identification code of the memory chip as the second identification signal of the next memory chip; The logic processing circuit is further configured to receive the second identification signal of the next memory chip output by the logic operation circuit, and transmit the second identification signal to the next memory chip through B groups of the second transmission structures; The i-th second identification signal of the next storage chip is transmitted to the next storage chip through the i-th second transmission structure group, where i is a natural number less than or equal to B.

4. The memory chip according to claim 3, wherein: Each of the second transmission structures has conductive through holes and contact structures arranged at intervals along a third direction, the conductive through holes penetrating the substrate of the memory chip along the third direction, and the contact structures penetrating the top surface; The logic processing circuit includes B second driving circuits and B third driving circuits; The i-th second driving circuit is coupled to the conductive through-hole of each second transmission structure in the i-th group of second transmission structures; The i-th second driving circuit is further coupled to the logic operation circuit; i is a natural number, and i is less than or equal to B; The i-th third driving circuit is coupled to the contact structure of each second transmission structure in the i-th group of second transmission structures; The i-th third driving circuit is further coupled to the logic operation circuit.

5. The memory chip according to claim 4, wherein: The logic processing circuit is further coupled to the first decoding circuit and configured to receive the chip position identification code; when the chip position identification code indicates that the memory chip is in an even-numbered position, receive the second identification signal from the conductive through-hole of each second transmission structure in the corresponding second transmission structure group via the second driving circuit, and send the generated stacking position identification code to the logic operation circuit; and sending the second identification signal of the next memory chip output by the logic operation circuit to the contact structure of each second transmission structure in the corresponding second transmission structure group via the third driving circuit; Alternatively, when the chip position identification code indicates that the memory chip is in an odd-numbered position, the second identification signal of the memory chip is received from the contact structure of each second transmission structure in the corresponding second transmission structure group via the third driving circuit, and the generated stacking position identification code is sent to the logic operation circuit, and the second identification signal of the next memory chip output by the logic operation circuit is sent to the conductive through-hole of each second transmission structure in the corresponding second transmission structure group via the second driving circuit.

6. The memory chip according to claim 5, wherein: The second driving circuit includes a first OR logic circuit, an even driving input circuit, and an odd driving output circuit; the input terminal of the first OR logic circuit is coupled to the conductive via of each second transmission structure in the corresponding second transmission structure group, the even driving input circuit is coupled between the output terminal of the first OR logic circuit and the input terminal of the logic operation circuit, and the odd driving output circuit is coupled between the output terminal of the logic operation circuit and the conductive via of each second transmission structure in the corresponding second transmission structure group; The third driving circuit includes a second OR logic circuit, an even driving output circuit and an odd driving input circuit; The input terminal of the second OR logic circuit is coupled to the contact structure of each second transmission structure in the corresponding second transmission structure group, the odd driving input circuit is coupled between the output terminal of the second OR logic circuit and the input terminal of the logic operation circuit, and the even driving output circuit is coupled between the output terminal of the logic operation circuit and the contact structure of each second transmission structure in the corresponding second transmission structure group; Wherein, the control end of the odd drive input circuit and the control end of the odd drive output circuit both receive a first odd switch signal; the control end of the even drive input circuit and the control end of the even drive output circuit both receive a first even switch signal; if the chip position identification code indicates that the memory chip is in an odd-numbered position, the first odd switch signal is in an enabled state and the first even switch signal is in a disabled state; if the chip position identification code indicates that the memory chip is in an even-numbered position, the first odd switch signal is in a disabled state and the first even switch signal is in an enabled state.

7. The memory chip according to claim 6, wherein: The logic operation circuit includes: an adder and a selection circuit; The adder is configured to add one to the stacking position identification code and output a stacking code carry signal; The selection circuit is configured to output the stacking code carry signal as the second identification signal of the next storage chip if the first control signal is valid; and directly output the stacking position identification code as the second identification signal of the next storage chip if the first control signal is invalid.

8. The memory chip according to claim 7, wherein: The logic processing circuit further includes a weak driving circuit; The logic processing circuit is further configured to generate the second identification signal of a default state based on the weak driving circuit if the second transmission structure does not transmit a valid signal; If the second transmission structure transmits a valid signal, the second identification signal is generated based on the valid signal transmitted by the second transmission structure.

9. The memory chip according to claim 8, wherein: The weak driving circuit includes B first logic units and B second logic units; Each of the odd-numbered drive input circuits is coupled to one of the first logic devices; the odd-numbered drive input circuit includes a first inverting drive unit and a second inverting drive unit, and the output end of the second OR logic circuit is connected to the input end of the first inverting drive unit, the output end of the first inverting drive unit is connected to the input end of the second inverting drive unit, the output end of the second inverting drive unit is connected to the input end of the logic operation circuit, and the control end of the first inverting drive unit and the control end of the second inverting drive unit both receive the first odd switching signal; the output end of the first logic device is connected to the input end of the first inverting drive unit, the first input end of the first logic device receives a power-on indication signal, and the second input end of the first logic device is connected to the output end of the first inverting drive unit; Each of the even drive input circuits is coupled to one of the second logic devices; the even drive input circuit includes a third inverting drive unit and a fourth inverting drive unit, and the output end of the first OR logic circuit is connected to the input end of the third inverting drive unit, the output end of the third inverting drive unit is connected to the input end of the fourth inverting drive unit, the output end of the fourth inverting drive unit is connected to the input end of the logic operation circuit, and the control end of the third inverting drive unit and the control end of the fourth inverting drive unit both receive the first even switch signal; the output end of the second logic device is connected to the input end of the third inverting drive unit, the first input end of the second logic device receives a power-on indication signal, and the second input end of the second logic device is connected to the output end of the third inverting drive unit.

10. The memory chip according to claim 9, wherein: The first logic unit and the second logic unit are both two-input NOR gates; after the memory chip is powered on, the power-on indication signal is at a high level; the second identification signal in a default state is at a low level; The first transmission structure is prepared by any one or more processes including the via-first, via-middle, via-last, and back side via-last processes; the conductive vias in the second transmission structure are prepared by any one or more processes including the via-first, via-middle, and back side via-last processes; different first transmission structures and different second transmission structures are electrically isolated from each other.

11. A logic chip, characterized in that: The top surface of the logic chip has a first axis and a second axis, the first axis and the second axis intersect perpendicularly at the center of the top surface, the first axis is parallel to one edge of the top surface, and the second axis is parallel to the other edge of the top surface; The logic chip includes 4 third transmission structures and B fourth transmission structure groups, where B is a natural number; The four third transmission structures are symmetrical about the first axis, and the four third transmission structures are symmetrical about the second axis; each of the fourth transmission structure groups includes four fourth transmission structures, the four fourth transmission structures are symmetrical about the first axis, and the four fourth transmission structures are symmetrical about the second axis; The logic chip is configured to generate four first identification signals and transmit the four first identification signals to four third transmission structures in a one-to-one correspondence; wherein the four first identification signals indicate chip location identification codes of memory chips adjacent to the logic chip; The logic chip is further configured to receive one second identification signal from each of the fourth transmission structure groups during the initialization process, and generate a stacking position identification code based on B second identification signals; or, during the normal operation phase, generate B second identification signals in a default state, and send one second identification signal to one of the fourth transmission structure groups.

12. The logic chip according to claim 11, wherein: The logic chip further includes a first signal generating circuit and four fourth driving circuits, and the four fourth driving circuits are coupled to the four third transmission structures in a one-to-one correspondence; The first signal generating circuit is coupled to the four fourth driving circuits and is configured to generate four first identification signals during an initialization process, wherein the level states of the four first identification signals are a first combination value; and to generate four first identification signals during a normal operation process, wherein the level states of the four first identification signals are a second combination value; The first combination value and the second combination value are not completely the same.

13. The logic chip according to claim 12, wherein: The logic chip further includes a second signal generating circuit, B third OR logic circuits, B control input circuits, and B control output circuits; The second signal generating circuit is coupled to the B control output circuits and is configured to, during a normal operation phase, generate B second identification signals in a default state and transmit the i-th second identification signal to the input terminal of the i-th control output circuit in a one-to-one correspondence; wherein the output terminal of the i-th control output circuit is coupled to each of the fourth transmission structures in the i-th fourth transmission structure group; i is a natural number less than or equal to B; Each of the fourth transmission structures in the i-th group of fourth transmission structures is coupled to an input terminal of the i-th third OR logic circuit, an output terminal of the third OR logic circuit is coupled to an input terminal of the i-th control output circuit, and an output terminal of the i-th control input circuit is coupled to an internal circuit of the logic chip; During the initialization process, the output end of the i-th control input circuit outputs the i-th second identification signal to the internal circuit of the logic chip; Among them, the control ends of the control output circuits all receive output enable signals, and the control ends of the control input circuits all receive input enable signals; if the logic chip is in a normal working stage, the input enable signal is in a non-enabled state, and the output enable signal is in an enabled state; if the logic chip is in an initialization process, the input enable signal is in an enabled state, and the output enable signal is in a non-enabled state.

14. The logic chip according to any one of claims 11 to 13, characterized in that: The third transmission structure or the fourth transmission structure is prepared by any one or more of a via-first process, a via-middle process, a via-last process, and a back side via-last process; Different third transmission structures and different fourth transmission structures are electrically isolated from each other.

15. A chip stacking structure, characterized in that: The chip stacking structure comprises the logic chip according to any one of claims 11 to 14 and at least one stacking unit, wherein the logic chip and the at least one stacking unit are stacked sequentially along a third direction; each of the stacking units comprises a first memory chip, a second memory chip, a third memory chip, and a fourth memory chip stacked sequentially along the third direction, wherein the third direction is perpendicular to a top surface of each of the memory chips; the first memory chip, the second memory chip, the third memory chip, and the fourth memory chip are all the memory chips according to any one of claims 1 to 10; The first memory chip and the second memory chip are stacked face to face, the second memory chip and the third memory chip are stacked back to back, and the third memory chip and the fourth memory chip are stacked face to face; The logic chip and the first memory chip are stacked back to back; Alternatively, the logic chip and the first memory chip are stacked in a face-to-back manner.

16. The chip stacking structure according to claim 15, wherein: The top surface of the logic chip or each of the memory chips is divided into 2×2 signal areas, the first signal area and the second signal area are symmetrical along the first axis thereof, the first signal area and the fourth signal area are symmetrical along the second axis thereof, and the third signal area and the fourth signal area are symmetrical along the first axis thereof; the first axes of the logic chip and each of the memory chips are respectively aligned along a third direction, and the second axes of the logic chip and each of the memory chips are respectively aligned along the third direction; When the logic chip and the first memory chip are stacked back to back, The fourth signal area of ​​the logic chip, the first signal area of ​​the first memory chip, the second signal area of ​​the second memory chip, the third signal area of ​​the third memory chip, and the fourth signal area of ​​the fourth memory chip are aligned along a third direction; The third signal area of ​​the logic chip, the second signal area of ​​the first memory chip, the first signal area of ​​the second memory chip, the fourth signal area of ​​the third memory chip, and the third signal area of ​​the fourth memory chip are aligned along a third direction; The second signal area of ​​the logic chip, the third signal area of ​​the first memory chip, the fourth signal area of ​​the second memory chip, the first signal area of ​​the third memory chip, and the second signal area of ​​the fourth memory chip are aligned along a third direction; The first signal area of ​​the logic chip, the fourth signal area of ​​the first memory chip, the third signal area of ​​the second memory chip, the second signal area of ​​the third memory chip, and the first signal area of ​​the fourth memory chip are aligned along a third direction.

17. The chip stacking structure according to claim 16, wherein: For the four first transmission structures in each of the memory chips, the first transmission structure_0, the first transmission structure_1, the first transmission structure_2, and the first transmission structure_3 are located in the first signal area, the second signal area, the third signal area, and the fourth signal area in a one-to-one correspondence; for the four third transmission structures in the logic chip, the third transmission structure_0, the third transmission structure_1, the third transmission structure_2, and the third transmission structure_3 are located in the first signal area, the second signal area, the third signal area, and the fourth signal area in a one-to-one correspondence; The third transmission structure_3 of the logic chip, the first transmission structure_0 of the first memory chip, the first transmission structure_1 of the second memory chip, the first transmission structure_2 of the third memory chip, and the first transmission structure_3 of the fourth memory chip are aligned along the third direction and connected to form a signal transmission path; The third transmission structure_2 of the logic chip, the first transmission structure_1 of the first memory chip, the first transmission structure_0 of the second memory chip, the first transmission structure_3 of the third memory chip, and the first transmission structure_2 of the fourth memory chip are aligned along the third direction and connected to form a signal transmission path; The third transmission structure_1 of the logic chip, the first transmission structure_2 of the first memory chip, the first transmission structure_3 of the second memory chip, the first transmission structure_0 of the third memory chip, and the first transmission structure_1 of the fourth memory chip are aligned along the third direction and connected to form a signal transmission path; The third transmission structure_0 of the logic chip, the first transmission structure_3 of the first memory chip, the first transmission structure_2 of the second memory chip, the first transmission structure_1 of the third memory chip, and the first transmission structure_0 of the fourth memory chip are aligned along a third direction and connected to form a signal transmission path; Among them, each of the memory chips obtains the 0th first identification signal from the first transmission structure_0, each of the memory chips obtains the 1st first identification signal from the first transmission structure_1, each of the memory chips obtains the 2nd first identification signal from the first transmission structure_2, and each of the memory chips obtains the 3rd first identification signal from the first transmission structure_3.

18. The chip stacking structure according to claim 17, wherein: In the case of B=2, for the two second transmission structure groups in each of the memory chips, the first second transmission structure group includes the second transmission structure_0 to the second transmission structure_3, and the second second transmission structure group includes the second transmission structure_4 to the second transmission structure_7; the second transmission structure_0 and the second transmission structure_4 are located in the first signal area, the second transmission structure_1 and the second transmission structure_5 are located in the second signal area, the second transmission structure_2 and the second transmission structure_6 are located in the third signal area, and the second transmission structure_3 and the second transmission structure_ 7 is located in the fourth signal area; for the logic chip, the first fourth transmission structure group includes fourth transmission structure_0 to fourth transmission structure_3, and the second fourth transmission structure group includes fourth transmission structure_4 to fourth transmission structure_7; the fourth transmission structure_0 and the fourth transmission structure_4 are located in the first signal area, the fourth transmission structure_1 and the fourth transmission structure_5 are located in the fourth signal area, the fourth transmission structure_2 and the fourth transmission structure_6 are located in the third signal area, and the fourth transmission structure_3 and the fourth transmission structure_7 are located in the fourth signal area; The fourth transmission structure_3 of the logic chip, the second transmission structure_0 of the first memory chip, the second transmission structure_1 of the second memory chip, the second transmission structure_2 of the third memory chip, and the second transmission structure_3 of the fourth memory chip are aligned along the third direction and connected to form a signal transmission channel; The fourth transmission structure_2 of the logic chip, the second transmission structure_1 of the first memory chip, the second transmission structure_0 of the second memory chip, the second transmission structure_3 of the third memory chip, and the second transmission structure_2 of the fourth memory chip are aligned along the third direction and connected to form a signal transmission channel; The fourth transmission structure_1 of the logic chip, the second transmission structure_2 of the first memory chip, the second transmission structure_3 of the second memory chip, the second transmission structure_0 of the third memory chip, and the second transmission structure_1 of the fourth memory chip are aligned along the third direction and connected to form a signal transmission channel; The fourth transmission structure_0 of the logic chip, the second transmission structure_3 of the first memory chip, the second transmission structure_2 of the second memory chip, the second transmission structure_1 of the third memory chip, and the second transmission structure_0 of the fourth memory chip are aligned along the third direction and connected to form a signal transmission channel; The fourth transmission structure _7 of the logic chip, the second transmission structure _4 of the first memory chip, the second transmission structure _5 of the second memory chip, the second transmission structure _6 of the third memory chip, and the second transmission structure _7 of the fourth memory chip are aligned along the third direction and connected to form a signal transmission channel; The fourth transmission structure _6 of the logic chip, the second transmission structure _5 of the first memory chip, the second transmission structure _4 of the second memory chip, the second transmission structure _7 of the third memory chip, and the second transmission structure _6 of the fourth memory chip are aligned along the third direction and connected to form a signal transmission channel; The fourth transmission structure _5 of the logic chip, the second transmission structure _6 of the first memory chip, the second transmission structure _7 of the second memory chip, the second transmission structure _4 of the third memory chip, and the second transmission structure _5 of the fourth memory chip are aligned along the third direction and connected to form a signal transmission channel; The fourth transmission structure _4 of the logic chip, the second transmission structure _7 of the first storage chip, the second transmission structure _6 of the second storage chip, the second transmission structure _5 of the third storage chip, and the second transmission structure _4 of the fourth storage chip are aligned along a third direction and connected to form a signal transmission channel.

19. The chip stacking structure according to claim 15, wherein: The top surface of the logic chip or each of the memory chips is divided into 2×2 signal areas, the first signal area and the second signal area are symmetrical along the first axis thereof, the first signal area and the fourth signal area are symmetrical along the second axis thereof, and the third signal area and the fourth signal area are symmetrical along the first axis thereof; the first axes of the logic chip and each of the memory chips are respectively aligned along a third direction, and the second axes of the logic chip and each of the memory chips are respectively aligned along the third direction; When the logic chip and the first memory chip are stacked back to back, The second signal area of ​​the logic chip, the first signal area of ​​the first memory chip, the second signal area of ​​the second memory chip, the third signal area of ​​the third memory chip, and the fourth signal area of ​​the fourth memory chip are aligned along a third direction; The first signal area of ​​the logic chip, the second signal area of ​​the first memory chip, the first signal area of ​​the second memory chip, the fourth signal area of ​​the third memory chip, and the third signal area of ​​the fourth memory chip are aligned along a third direction; The fourth signal area of ​​the logic chip, the third signal area of ​​the first memory chip, the fourth signal area of ​​the second memory chip, the first signal area of ​​the third memory chip, and the second signal area of ​​the fourth memory chip are aligned along a third direction; The third signal area of ​​the logic chip, the fourth signal area of ​​the first memory chip, the third signal area of ​​the second memory chip, the second signal area of ​​the third memory chip, and the first signal area of ​​the fourth memory chip are aligned along a third direction.

20. The chip stacking structure according to claim 19, wherein: For the four first transmission structures in each of the memory chips, the first transmission structure_0, the first transmission structure_1, the first transmission structure_2, and the first transmission structure_3 are located in the first signal area, the second signal area, the third signal area, and the fourth signal area in a one-to-one correspondence; for the four third transmission structures in the logic chip, the third transmission structure_0, the third transmission structure_1, the third transmission structure_2, and the third transmission structure_3 are located in the first signal area, the second signal area, the third signal area, and the fourth signal area in a one-to-one correspondence; The third transmission structure_1 of the logic chip, the first transmission structure_0 of the first memory chip, the first transmission structure_1 of the second memory chip, the first transmission structure_2 of the third memory chip, and the first transmission structure_3 of the fourth memory chip are aligned along the third direction and connected to form a signal transmission path; The third transmission structure_0 of the logic chip, the first transmission structure_1 of the first memory chip, the first transmission structure_0 of the second memory chip, the first transmission structure_3 of the third memory chip, and the first transmission structure_2 of the fourth memory chip are aligned along the third direction and connected to form a signal transmission path; The third transmission structure_3 of the logic chip, the first transmission structure_2 of the first memory chip, the first transmission structure_3 of the second memory chip, the first transmission structure_0 of the third memory chip, and the first transmission structure_1 of the fourth memory chip are aligned along the third direction and connected to form a signal transmission path; The third transmission structure_2 of the logic chip, the first transmission structure_3 of the first memory chip, the first transmission structure_2 of the second memory chip, the first transmission structure_1 of the third memory chip, and the first transmission structure_0 of the fourth memory chip are aligned along the third direction and connected to form a signal transmission path; Among them, each of the memory chips obtains the 0th first identification signal from the first transmission structure_0, each of the memory chips obtains the 1st first identification signal from the first transmission structure_1, each of the memory chips obtains the 2nd first identification signal from the first transmission structure_2, and each of the memory chips obtains the 3rd first identification signal from the first transmission structure_3.

21. The chip stacking structure according to claim 19, wherein: In the case of B=2, for the two second transmission structure groups in each of the memory chips, the first second transmission structure group includes the second transmission structure_0 to the second transmission structure_3, and the second second transmission structure group includes the second transmission structure_4 to the second transmission structure_7; the second transmission structure_0 and the second transmission structure_4 are located in the first signal area, the second transmission structure_1 and the second transmission structure_5 are located in the second signal area, the second transmission structure_2 and the second transmission structure_6 are located in the third signal area, and the second transmission structure_3 and the second transmission structure_ 7 is located in the fourth signal area; for the logic chip, the first fourth transmission structure group includes fourth transmission structure_0 to fourth transmission structure_3, and the second fourth transmission structure group includes fourth transmission structure_4 to fourth transmission structure_7; the fourth transmission structure_0 and the fourth transmission structure_4 are located in the first signal area, the fourth transmission structure_1 and the fourth transmission structure_5 are located in the fourth signal area, the fourth transmission structure_2 and the fourth transmission structure_6 are located in the third signal area, and the fourth transmission structure_3 and the fourth transmission structure_7 are located in the fourth signal area; The fourth transmission structure_1 of the logic chip, the second transmission structure_0 of the first memory chip, the second transmission structure_1 of the second memory chip, the second transmission structure_2 of the third memory chip, and the second transmission structure_3 of the fourth memory chip are aligned along the third direction and connected to form a signal transmission channel; The fourth transmission structure_0 of the logic chip, the second transmission structure_1 of the first memory chip, the second transmission structure_0 of the second memory chip, the second transmission structure_3 of the third memory chip, and the second transmission structure_2 of the fourth memory chip are aligned along the third direction and connected to form a signal transmission channel; The fourth transmission structure_3 of the logic chip, the second transmission structure_2 of the first memory chip, the second transmission structure_3 of the second memory chip, the second transmission structure_0 of the third memory chip, and the second transmission structure_1 of the fourth memory chip are aligned along the third direction and connected to form a signal transmission channel; The fourth transmission structure_2 of the logic chip, the second transmission structure_3 of the first memory chip, the second transmission structure_2 of the second memory chip, the second transmission structure_1 of the third memory chip, and the second transmission structure_0 of the fourth memory chip are aligned along the third direction and connected to form a signal transmission channel; The fourth transmission structure _5 of the logic chip, the second transmission structure _4 of the first memory chip, the second transmission structure _5 of the second memory chip, the second transmission structure _6 of the third memory chip, and the second transmission structure _7 of the fourth memory chip are aligned along the third direction and connected to form a signal transmission channel; The fourth transmission structure_4 of the logic chip, the second transmission structure_5 of the first memory chip, the second transmission structure_4 of the second memory chip, the second transmission structure_7 of the third memory chip, and the second transmission structure_6 of the fourth memory chip are aligned along the third direction and connected to form a signal transmission channel; The fourth transmission structure _7 of the logic chip, the second transmission structure _6 of the first memory chip, the second transmission structure _7 of the second memory chip, the second transmission structure _4 of the third memory chip, and the second transmission structure _5 of the fourth memory chip are aligned along the third direction and connected to form a signal transmission channel; The fourth transmission structure _6 of the logic chip, the second transmission structure _7 of the first storage chip, the second transmission structure _6 of the second storage chip, the second transmission structure _5 of the third storage chip, and the second transmission structure _4 of the fourth storage chip are aligned along the third direction and connected to form a signal transmission channel.

22. The chip stacking structure according to any one of claims 15 to 21, characterized in that: For two chips connected face to face, the transmission structures aligned along the third direction are electrically connected by a hybrid bonding process; for two chips connected back to back and two chips connected back to face, the transmission structures aligned along the third direction are electrically connected by a bump process; or For the two chips connected face to face, for the two chips connected back to back, and for the two chips connected back to face, the transmission structures aligned along the third direction in both are electrically connected by a hybrid bonding process; or, For the two chips connected face to face, for the two chips connected back to back, and for the two chips connected back to face, the transmission structures aligned along the third direction in both are electrically connected by a bump process.

23. A memory, characterized in that: The chip stacking structure comprises the chip stacking structure according to any one of claims 15 to 22.

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