Semiconductor device and method for manufacturing the same

Abstract

The present disclosure provides a semiconductor device and a method for manufacturing the same. The device includes: a substrate, in which spaced source regions and drain regions are included; a top surface of the substrate includes a gate structure located between the source regions and the drain regions, and the gate structure includes a gate dielectric layer, a composite work function layer, and a gate material layer sequentially stacked in a first direction away from the substrate. The composite work function layer at least includes a first work function adjustment structure and a second work function adjustment structure arranged in a second direction parallel to the substrate and having different work function values; wherein, the first work function adjustment structure and the second work function adjustment structure respectively include work function material stack structures with different numbers of stacked layers in the first direction. By making the composite work function layer have different work function values in different regions in the lateral direction, the semiconductor device has different electric field resistance strengths in the lateral direction, thereby improving the breakdown voltage of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly to a semiconductor device and a method for manufacturing the same. Background Art

[0002] With the technological iteration of CMOS, SiO2 gate dielectrics and polysilicon gate transistors have reached their physical limits. For example, excessive leakage current caused by the quantum tunneling effect and polysilicon depletion problems seriously affect the performance of the device. Therefore, the HKMG (High-k Metal Gate) process has been gradually introduced, which includes a metal gate, a high dielectric constant layer, and a metal work function layer. Due to the Fermi level pinning effect in the HKMG process, that is, the work function is pulled towards the center of the forbidden band, reducing the adjustment ability of the threshold voltage Vt and the gate control ability. Therefore, a metal work function layer must be added between the high dielectric constant layer and the metal gate to solve the Fermi level pinning effect.

[0003] The work functions of the metal work function layers are different, so the flat-band voltages of the devices are different, and the threshold voltages of the devices are also different. The metal work function layer of NMOS (N-Metal-Oxide-Semiconductor) is an N-type metal work function layer, and the work function of the N-type metal work function layer usually depletes the bottom of the conduction band of the substrate (such as a silicon substrate), thereby making the threshold voltage of the NMOS smaller, which is beneficial to improving the speed of the device and reducing power consumption. The metal work function layer of PMOS (P-Metal-Oxide-Semiconductor) is a P-type metal work function layer, and the work function of the P-type metal work function layer usually depletes the top of the valence band of the substrate such as a silicon substrate, thereby making the absolute value of the threshold voltage of the PMOS smaller, which is beneficial to improving the speed of the device and reducing power consumption. Summary of the Invention

[0004] Based on this, in view of the problems in the above background art, it is necessary to provide a semiconductor device whose gate structure includes a work function adjustment structure with different work function values to improve the breakdown voltage of the semiconductor device.

[0005] To achieve the above object and other related objects, one aspect of the present application provides a semiconductor device, including:

[0006] A substrate, which includes spaced source regions and drain regions therein;

[0007] The top surface of the substrate includes a gate structure located between the source region and the drain region. The gate structure includes a gate dielectric layer, a composite work function layer, and a gate material layer stacked in sequence in a first direction away from the substrate. The composite work function layer includes at least a first work function adjustment structure and a second work function adjustment structure arranged in a second direction parallel to the substrate and having different work function values.

[0008] Wherein, the first work function adjustment structure and the second work function adjustment structure respectively include a work function material stacked structure with different numbers of stacked layers in the first direction.

[0009] In one embodiment, the work function material stacked structure is formed by alternately stacking at least two work function materials, or each layer in the work function material stacked structure uses different work function materials.

[0010] In one embodiment, at the same height in the first direction, the work function materials of the first work function adjustment structure and the second work function adjustment structure are different; in the second direction, the end face of the first work function material of the first work function adjustment structure is joined to the end face of the second work function material of the second work function adjustment structure.

[0011] In one embodiment, the first work function adjustment structure includes a first TiN material layer, a first TiAl material layer, and a second TiN material layer alternately stacked in the first direction, and the second work function adjustment structure includes a second TiAl material layer and a third TiN material layer stacked in sequence in the first direction. Wherein, the first TiN material layer is joined to the second TiAl material layer, and the first TiAl material layer is joined to the third TiN material layer.

[0012] In one embodiment, the number of stacked layers of the first work function adjustment structure is greater than that of the second work function adjustment structure, and the work function value of the first work function adjustment structure is greater than that of the second work function adjustment structure.

[0013] In one embodiment, the composite work function layer includes a P-type work function part and an N-type work function part. The P-type work function part includes the first work function adjustment structure, and the N-type work function part includes the second work function adjustment structure.

[0014] In one embodiment, a bottom work function layer is further provided between the gate dielectric layer and the first work function adjustment structure and the second work function adjustment structure. The bottom work function layer includes a single-layer structure or a multi-layer structure, and the bottom work function layer includes a TiN material layer and a TaN material layer stacked in sequence in the first direction.

[0015] In one embodiment, the gate dielectric layer includes a high-K dielectric layer, and the gate material layer includes a metal gate.

[0016] Another aspect of the present application provides a method for manufacturing a semiconductor device, including the following steps:

[0017] Provide a substrate, which includes spaced source regions and drain regions therein;

[0018] Form a gate dielectric layer, a composite work function layer, and a gate material layer in sequence on the top surface of the substrate along a first direction away from the substrate. Among them, the composite work function layer at least includes a first work function adjustment structure and a second work function adjustment structure arranged along a second direction parallel to the substrate and having different work function values. The first work function adjustment structure and the second work function adjustment structure respectively include work function material stack structures with different numbers of stacked layers along the first direction.

[0019] In one embodiment, the substrate includes a first region for forming the first work function adjustment structure thereon and a second region for forming the second work function adjustment structure thereon.

[0020] Forming the first work function adjustment structure and the second work function adjustment structure includes:

[0021] Form a first work function material layer covering the first region and the second region of the substrate;

[0022] Etch away the first work function material layer covering the second region;

[0023] Form a second work function material layer covering the first region and the second region on the first work function material layer.

[0024] According to the semiconductor device and its manufacturing method provided by the present invention, the unexpected technical effect of the present application is that by forming a composite work function layer including a first work function adjustment structure and a second work function adjustment structure between the gate dielectric layer and the gate material layer, the composite work function layer has different work function values in different regions in the lateral direction, so that the semiconductor device has different electric field resistance strengths in the lateral direction, and the breakdown voltage of the semiconductor device is improved. Description of the Drawings

[0025] To better describe and illustrate the embodiments and / or examples of those applications disclosed here, one or more drawings can be referred to. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed applications, the currently described embodiments and / or examples, and the currently understood best mode of these applications.

[0026] Figure 1Schematic flow chart of a method for manufacturing a semiconductor device provided in an embodiment;

[0027] Figure 2 Schematic flow chart of forming a gate structure in a method for manufacturing a semiconductor device provided in an embodiment;

[0028] Figure 3 Schematic cross-sectional structure diagram of a substrate in a method for manufacturing a semiconductor device provided in an embodiment;

[0029] Figure 4 Schematic cross-sectional structure diagram of the structure after forming a dummy gate in a method for manufacturing a semiconductor device provided in an embodiment;

[0030] Figure 5 Schematic cross-sectional structure diagram of the obtained structure after forming a bottom work function layer in step S121 of a method for manufacturing a semiconductor device provided in an embodiment;

[0031] Figure 6 Schematic cross-sectional structure diagram of the structure after forming a first work function material layer in step S122 of a method for manufacturing a semiconductor device provided in an embodiment;

[0032] Figure 7 Schematic cross-sectional structure diagram of the structure after removing the first work function material layer covering the second region in step S123 of a method for manufacturing a semiconductor device provided in an embodiment;

[0033] Figure 8 Schematic cross-sectional structure diagram of the structure after forming a second work function material layer and a third work function material layer in step S124 of a method for manufacturing a semiconductor device provided in an embodiment;

[0034] Figure 9 Schematic cross-sectional structure diagram of the structure after forming a metal gate in step S125 of a method for manufacturing a semiconductor device provided in an embodiment;

[0035] Figure 10 Schematic cross-sectional structure diagram of the structure after forming a metal plug in a method for manufacturing a semiconductor device provided in an embodiment.

[0036] Description of reference numerals:

[0037] 200. Substrate; 210. Source region; 211. First high-voltage N-drift region; 212. First high-voltage P-drift region; 220. Drain region; 221. Second high-voltage N-drift region; 222. Second high-voltage P-drift region; 230. Gate dielectric layer; 240. Bottom work function layer; 241. First bottom work function layer; 242. Second bottom work function layer; 250. Pseudo gate material layer; 261. First work function material layer; 262. Second work function material layer; 263. Third work function material layer. Detailed implementation manners

[0038] For ease of understanding of this application, the following will describe this application more comprehensively with reference to the relevant drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of this application will be thorough and comprehensive.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used herein in the description of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the associated listed items.

[0040] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Thus, a first element, component, region, layer or part discussed below may be denoted as a second element, component, region, layer or part without departing from the teachings of this application.

[0041] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures with other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relationship terms are also intended to include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under other elements" or "beneath it" or "under it" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0042] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present application. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, identify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0043] Embodiments of the application are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present application. As such, variations from the shapes as illustrated, for example due to manufacturing techniques and / or tolerances, are to be expected. Accordingly, embodiments of the present application should not be limited to the particular shapes of regions shown herein, but rather include shape deviations due to, for example, manufacturing. The regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shape of regions of the device and are not intended to limit the scope of the present application.

[0044] It should be noted that the drawings provided in this embodiment only illustrate the basic concept of the present application schematically. Although only the components related to the present application are shown in the drawings, rather than being drawn according to the number, shape and size of the components in actual implementation, the types, numbers and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0045] The present invention provides a method for manufacturing a semiconductor device, as Figure 1 shown, comprising the following steps:

[0046] Step S110: providing a substrate, in which an active region and a drain region are formed;

[0047] Step S120: A gate dielectric layer, a composite work function layer, and a gate material layer are sequentially formed on the top surface of the substrate in a first direction away from the substrate. The composite work function layer at least includes a first work function adjustment structure and a second work function adjustment structure arranged in a second direction parallel to the substrate and having different work function values. The first work function adjustment structure and the second work function adjustment structure respectively include work function material stack structures with different stacking numbers in the first direction.

[0048] Further, the substrate includes a first region for forming the first work function adjustment structure thereon and a second region for forming the second work function adjustment structure thereon. Sequentially forming a gate dielectric layer, a composite work function layer, and a gate material layer on the substrate includes the following steps:

[0049] Step S121: Form a gate dielectric layer and a bottom work function layer covering the first region and the second region of the substrate;

[0050] Step S122: Form a first work function material layer covering the first region and the second region on the bottom work function layer;

[0051] Step S123: Etch and remove the first work function material layer covering the second region;

[0052] Step S124: Form a second work function material layer and a third work function material layer covering the first region and the second region on the first work function material layer. The first work function material layer, the second work function material layer, and the third work function material layer in the first region constitute the first work function adjustment structure, and the second work function material layer and the third work function material layer in the second region constitute the second work function adjustment structure;

[0053] Step S125: Form a gate material layer to fill the gate groove.

[0054] First, refer to Figure 3 As shown, perform Step S110 to provide a substrate 200, which includes spaced source regions 210 and drain regions 220. In one embodiment, the first direction away from the substrate 200 is longitudinal, the second direction parallel to the substrate 200 is transverse, and the second direction is parallel to the arrangement direction of the source regions 210 and the drain regions 220.

[0055] In one embodiment, the substrate 200 may be at least one of the materials mentioned below: silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanide on insulator (S-SiGeOI), silicon germanide on insulator (SiGeOI), and germanium on insulator (GeOI), etc. Preferably, the substrate 200 is a P-type substrate.

[0056] In one embodiment, the substrate includes spaced source region 210 and drain region 220, and a gate region located between the source region 210 and the drain region 220. Among them, the gate region is used to form a gate thereon, and the gate region further includes a first region for forming a first work function adjustment structure thereon, and a second region for forming a second work function adjustment structure thereon. Further, the areas of the first region and the second region can be set as needed. Preferably, the areas of the first region and the second region are equal. It should be noted that dividing the gate region into two regions is only exemplary, and the gate region can also be divided into more regions as needed, and each region is used to form a work function adjustment structure with different work function values thereon.

[0057] In one embodiment, the semiconductor device includes but is not limited to NMOS devices, PMOS devices, symmetric devices, asymmetric devices, high-voltage devices or low-voltage devices. Taking a high-voltage asymmetric NMOS device as an example, referring to Figure 3 As shown, between the gate region of the substrate and the first shallow trench isolation (STI), there are included a first high-voltage N drift region 211 and a first high-voltage P drift region 212: the gate region is directly adjacent to the first high-voltage N drift region 211, and no STI is provided therebetween; the first high-voltage P drift region 212 and the first high-voltage N drift region 211 are directly adjacent, and no STI is provided therebetween. Between the gate region and the second STI, there are included a second high-voltage N drift region 221 and a second high-voltage P drift region 222: a third STI is provided between the gate region and the second high-voltage N drift region 221; a fourth STI is provided between the second high-voltage P drift region 222 and the second high-voltage N drift region 221. Among them, the first high-voltage P drift region 212 and the second high-voltage P drift region 222 together form an annular high-voltage P drift region.

[0058] In one embodiment, the substrate 200 is etched to form four STI grooves, and isolation material is filled in the STI grooves to form four STIs; a mask layer is formed on the substrate, and with this mask layer as a mask, an N-type ion implantation process is performed to simultaneously form the first high-voltage N drift region 211 and the second high-voltage N drift region 221; the above mask layer is removed to form a new mask layer, and with this mask layer as a mask, a P-type ion implantation process is performed to simultaneously form the first high-voltage P drift region 212 and the second high-voltage P drift region 222.

[0059] In one embodiment, after forming the STIs and the drift regions, it further includes the step of etching back the gate region to form a groove, so that the top surface of the gate region of the substrate is lower than the top surface of the substrate 200. Then, a high-voltage gate oxide layer (HV GOX) is formed in the groove.

[0060] Then, referring to Figures 4 to 5As shown, step S121 is performed to form a gate dielectric layer 230 and a bottom work function layer 240 covering the first region and the second region of the substrate 200.

[0061] In one embodiment, after forming a high-voltage gate oxide layer (HV GOX), a gate dielectric layer 230, a first bottom work function layer 241, and a dummy gate material layer 250 are sequentially formed on the substrate 200. Specifically, the gate dielectric layer 230 is made of a high-K dielectric material, and the high-K dielectric material includes, but is not limited to, one or several of hafnium oxide, zirconium oxide, hafnium silicon oxynitride, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, or aluminum oxide. The first bottom work function layer 241 includes, but is not limited to, one or several of TiN, TaN, TiC, TiAl, TiAlC, or TaAlC, preferably TiN. The dummy gate material layer 250 is made of polysilicon material. The method for forming the gate dielectric layer 230, the first bottom work function layer 241, and the dummy gate material layer 250 can use chemical vapor deposition (CVD), such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD), and molecular beam epitaxy (MBE).

[0062] In one embodiment, the gate dielectric layer 230, the first bottom work function layer 241, and the dummy gate material layer 250 are etched to form a dummy gate structure. Specifically, a mask layer is formed on the dummy gate material layer 250, and the mask layer can include a nitride layer, an oxide layer, or a stacked structure of nitride and oxide. The method for etching the gate dielectric layer 230, the first bottom work function layer 241, and the dummy gate material layer 250 using the mask layer as a mask can be completed by a dry etching process or other process technologies familiar to those skilled in the art, which will not be elaborated here. Further, after forming the dummy gate, there is also a step of forming a gate sidewall, and the gate sidewall can include a nitride layer, an oxide layer, or a stacked structure of nitride and oxide.

[0063] In one embodiment, after forming the gate sidewall, it further includes the step of performing ion implantation on the drift region to form the source region 210 and the drain region 220. Specifically, after forming the patterned mask, a P-type ion implantation process is performed to simultaneously increase the P-type ion doping concentration in the top regions of the first high-voltage P drift region 212 and the second high-voltage P drift region 222, forming a P-type ion-doped region; the above mask is removed and a patterned mask is re-formed, and an N-type ion implantation process is performed to simultaneously increase the N-type ion doping concentration in the top regions of the first high-voltage N drift region 211 and the second high-voltage N drift region 221, respectively forming the source region 210 and the drain region 220. Among them, a part of the first high-voltage N drift region 211 is blocked by the gate sidewall, so the source region 210 is formed in the unblocked region of the upper part of the first high-voltage N drift region 211. Then, the mask is removed, and nickel silicide (NiSi) is formed on the exposed upper surface of the first high-voltage N drift region 211, the upper surface of the second high-voltage N drift region 221, and the upper surface of the second high-voltage P drift region 222 as a metal silicide layer.

[0064] Next, an etch stop layer (CESL) and an interlayer dielectric layer (ILD) are formed. The etch stop layer covers the upper surfaces of the source region 210 and the drain region 220, as well as the sidewalls of the gate sidewall. The upper surface of the interlayer dielectric layer is flush with the upper surface of the dummy gate material layer 250. The method of forming the etch stop layer and the interlayer dielectric layer can use chemical vapor deposition (CVD), such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), etc.

[0065] Next, the dummy gate material layer 250 is etched away to expose the first bottom work function layer 241, forming a gate trench. The removal of the dummy gate material layer 250 can use a combination of dry etching and wet etching to completely remove the polysilicon and expose the upper surface of the first bottom work function layer 241. Then, a second bottom work function layer 242 is formed. Specifically, the material of the second bottom work function layer 242 includes but is not limited to a tantalum nitride (TaN) layer. The second bottom work function layer 242 covers the interlayer dielectric layer, the bottom and sidewalls of the gate trench. The first bottom work function layer 241 and the second bottom work function layer 242 together constitute the bottom work function layer.

[0066] Next, referring to Figure 6 as shown, step S122 is performed to form a first work function material layer 261 covering the first region and the second region on the bottom work function layer.

[0067] In one embodiment, the material of the first work function material layer 261 includes but is not limited to titanium nitride (TiN). The method of forming the first work function material layer 261 can use one of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0068] Next, refer to Figure 7 shown in FIG. S123, and perform step S123 to etch and remove the first work function material layer 261 covering the second region.

[0069] In one embodiment, a photolithography process is performed to remove the first work function material layer 261 covering the second region. Specifically, a patterned mask layer is first formed, which includes a photoresist layer (PR) and a bottom anti-reflection coating (BARC). The patterned mask layer exposes the second region, and a dry etching process is performed to remove the exposed first work function material layer 261 until the second bottom work function layer 242 is exposed, and the second bottom work function layer 242 is used as an etching stop layer. The dry etching process includes, but is not limited to: reactive ion etching (RIE), ion beam etching, plasma etching, or laser ablation. A single etching method can be used, or more than one etching method can also be used.

[0070] Next, refer to Figure 8 shown in FIG. S124, and perform step S124 to form a second work function material layer 262 and a third work function material layer 263 covering the first region and the second region on the first work function material layer 261, where the first work function material layer, the second work function material layer, and the third work function material layer in the first region constitute the first work function adjustment structure, and the second work function material layer and the third work function material layer in the second region constitute the second work function adjustment structure.

[0071] Exemplarily, the first work function adjustment structure and the second work function adjustment structure respectively include a work function material stack structure with different stacking numbers in the first direction, where the work function material stack structure is formed by alternately stacking at least two work function materials. In one embodiment, the first work function material layer 261 and the third work function material layer 263 use the same work function material, such as titanium nitride (TiN). The second work function material layer 262 uses a work function material different from the first work function material layer 261, for example, the second work function material layer 262 uses titanium aluminide (TiAl). It should be noted that the use of a three-layer stack structure of TiN + TiAl + TiN for the first work function adjustment structure and a two-layer stack structure of TiAl + TiN for the second work function adjustment structure in this embodiment are only exemplary, and the stacking numbers of the first work function adjustment structure and the second work function adjustment structure can be set as needed, and the present application does not limit this.

[0072] Exemplarily, the first work function adjustment structure and the second work function adjustment structure respectively include work function material stack structures with different stacking numbers along a first direction, wherein different work function materials are used for each layer in the work function material stack structure. In one embodiment, the first work function material layer 261 uses titanium nitride (TiN), the second work function material layer 262 uses a work function material different from that of the first work function material layer 261, such as titanium aluminide (TiAl), and the third work function material layer 263 can use a work function material different from that of the first work function material layer 261 and the second work function material layer 262.

[0073] Exemplarily, at the same height in the first direction, the work function materials of the first work function adjustment structure and the second work function adjustment structure are different; in the second direction, the end face of the first work function material of the first work function adjustment structure is joined to the end face of the second work function material of the second work function adjustment structure. In one embodiment, the thicknesses of the layers in the work function material stack structure are the same. In this way, after removing the first work function material layer 261 in the second region, the first work function material layer (e.g., TiN material layer) in the first region is joined and flush with the second work function material layer (e.g., TiAl material layer) in the second region, and the second work function material layer (e.g., TiAl material layer) in the first region is joined and flush with the third work function material layer (e.g., TiN material layer) in the second region.

[0074] Exemplarily, the stacking number of the first work function adjustment structure is greater than that of the second work function adjustment structure, and the work function value of the first work function adjustment structure is greater than that of the second work function adjustment structure. In one embodiment, the first work function adjustment structure is a three-layer stack structure of TiN + TiAl + TiN, and the work function value is about 5.2 eV; the second work function adjustment structure is a two-layer stack structure of TiAl + TiN, and the work function value is about 4.2 eV.

[0075] Exemplarily, the composite work function layer includes a P-type work function portion and an N-type work function portion. The P-type work function portion includes the first work function adjustment structure, and the N-type work function portion includes the second work function adjustment structure. Among them, the work function of the N-type metal work function portion usually depletes the bottom of the conduction band of the substrate, thereby reducing the threshold voltage of the NMOS, which is beneficial to improving the speed of the device and reducing power consumption; the work function of the P-type metal work function layer usually depletes the top of the valence band of the substrate, thereby reducing the absolute value of the threshold voltage of the PMOS, which is beneficial to improving the speed of the device and reducing power consumption. In this embodiment, by making the composite work function layer include both a P-type work function portion and an N-type work function portion, the composite work function layer of the metal gate is different from that of the NMOS and the PMOS. Such a structure can adjust the threshold voltage Vt. Since the number of stacked layers and the total thickness of the N-type work function portion and the P-type work function portion are different, and their profiles are different, the strength of resisting the electric field in the lateral direction is different, which can improve the breakdown voltage (BVD) of the semiconductor device.

[0076] Through the method provided by the present invention, only by adding step S123 in the process of forming the work function stack structure, etching and removing the first work function material layer in the second region, the number of stacked layers and the total thickness of the work function stack structures formed in the first region and the second region can be made different, each having a different work function value, and the strength of the composite work function layer resisting the electric field in the lateral direction is different, thereby improving the breakdown voltage of the semiconductor device.

[0077] Next, refer to Figure 9 As shown, perform step S125 to form a gate material layer to fill the gate groove.

[0078] In one embodiment, after forming the first work function adjustment structure and the second work function adjustment structure, it further includes the step of forming a metal gate in the gate groove. In one embodiment, the material of the metal gate includes, but is not limited to, metal materials such as aluminum and copper. The method of forming the metal gate can be completed by process technologies familiar to those skilled in the art such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc., and will not be elaborated here.

[0079] Next, refer to Figure 10 As shown, after forming the metal gate, it further includes the steps of forming a contact plug (CT) and a metal wiring layer.

[0080] So far, the related steps of the preparation method of the semiconductor device according to the embodiment of the present invention have been introduced. It can be understood that the preparation method of the semiconductor device in this embodiment not only includes the above steps, but may also include other necessary steps before, during, or after the above steps, and all of them are included in the scope of this manufacturing method.

[0081] The present invention further provides a semiconductor device, as shown with reference to Figure 10 :

[0082] a substrate, in which spaced source region and drain region are included;

[0083] On the top surface of the substrate, there is a gate structure located between the source region and the drain region. The gate structure includes a gate dielectric layer, a composite work function layer, and a gate material layer stacked in sequence along a first direction away from the substrate. The composite work function layer at least includes a first work function adjustment structure and a second work function adjustment structure arranged along a second direction parallel to the substrate and having different work function values. Wherein, the first work function adjustment structure and the second work function adjustment structure respectively include work function material stack structures with different numbers of stacked layers along the first direction.

[0084] In one embodiment, the substrate includes spaced source region 210 and drain region 220, and a gate region located between source region 210 and drain region 220. In one embodiment, the first direction away from substrate 200 is the longitudinal direction, the second direction parallel to substrate 200 is the transverse direction, and the second direction is parallel to the arrangement direction of source region 210 and drain region 220. Wherein, the gate region is used to form a gate thereon, and the gate region further includes a first region for forming the first work function adjustment structure thereon, and a second region for forming the second work function adjustment structure thereon. Further, the areas of the first region and the second region can be set as required. Preferably, the areas of the first region and the second region are equal. It should be noted that dividing the gate region into two regions is only exemplary, and the gate region can also be divided into more regions as required, and each region is used to form a work function adjustment structure with a different work function value thereon.

[0085] In one embodiment, the semiconductor device includes, but is not limited to, an NMOS device, a PMOS device, a symmetric device, an asymmetric device, a high-voltage device, or a low-voltage device. Taking a high-voltage asymmetric NMOS device as an example, between the gate region (for forming a gate thereon) of the substrate and the first shallow trench isolation (STI), there are included a first high-voltage N drift region 211 and a first high-voltage P drift region 212: the gate region is directly adjacent to the first high-voltage N drift region 211, and no STI is provided therebetween; the first high-voltage P drift region 212 and the first high-voltage N drift region 211 are directly adjacent, and no STI is provided therebetween. Between the gate region and the second STI, there are included a second high-voltage N drift region 221 and a second high-voltage P drift region 222: a third STI is provided between the gate region and the second high-voltage N drift region 221; a fourth STI is provided between the second high-voltage P drift region 222 and the second high-voltage N drift region 221. Among them, the first high-voltage P drift region 212 and the second high-voltage P drift region 222 together form an annular high-voltage P drift region. Further, the top regions of the first high-voltage P drift region 212 and the second high-voltage P drift region 222 are P-type ion-doped regions, and the P-type ion doping concentration thereof is higher than the P-type ion doping concentration of the drift region; the portions of the first high-voltage N drift region 211 that do not overlap with the gate sidewalls and the top region of the second high-voltage N drift region 221 are the source region 210 and the drain region 220, and the N-type ion doping concentration of the source region 210 and the drain region 220 is higher than the N-type ion doping concentration of the drift region. Metal silicides are formed on the upper surfaces of the first high-voltage N drift region 211, the second high-voltage N drift region 221, and the second high-voltage P drift region 222, such as nickel silicide (NiSi).

[0086] In one embodiment, a high-voltage gate oxide layer (HV GOX) is formed on the top surface of the gate region of the substrate, and the top surface of the high-voltage gate oxide layer is flush with the top surfaces of the metal silicides of the source region 210 and the drain region 220. A gate dielectric layer 230 is formed on the high-voltage gate oxide layer, and the gate dielectric layer 230 uses a high-K dielectric material, and the high-K dielectric material includes, but is not limited to, one or several of hafnium oxide, zirconium oxide, hafnium silicon oxynitride, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, or aluminum oxide. A composite work function layer is formed on the gate dielectric layer 230, and the composite work function includes a bottom work function layer at the bottom. The bottom work function layer includes a single-layer structure or a multi-layer structure. Specifically, the bottom work function layer includes a first bottom work function layer 241 (for example, a TiN material layer) and a second bottom work function layer 242 (for example, a TaN material layer). Among them, the first bottom work function layer 241 only covers the bottom of the gate groove, and the second bottom work function layer 242 covers the bottom and sidewalls of the gate groove.

[0087] Exemplarily, the first work function adjustment structure and the second work function adjustment structure respectively include work function material stack structures with different numbers of stacked layers along a first direction, wherein the work function material stack structure is formed by alternately stacking at least two work function materials. In one embodiment, the first work function material layer 261 and the third work function material layer 263 employ the same work function material, such as titanium nitride (TiN). The second work function material layer 262 employs a work function material different from that of the first work function material layer 261, for example, the second work function material layer 262 employs titanium aluminide (TiAl). It should be noted that the use of a three-layer stack structure of TiN + TiAl + TiN for the first work function adjustment structure and a two-layer stack structure of TiAl + TiN for the second work function adjustment structure in this embodiment is merely exemplary, and the number of stacked layers of the first work function adjustment structure and the second work function adjustment structure can both be set as needed, and the present application places no restrictions thereon.

[0088] Exemplarily, the first work function adjustment structure and the second work function adjustment structure respectively include work function material stack structures with different numbers of stacked layers along a first direction, wherein each layer in the work function material stack structure employs a different work function material. In one embodiment, the first work function material layer 261 employs titanium nitride (TiN), the second work function material layer 262 employs a work function material different from that of the first work function material layer 261, such as titanium aluminide (TiAl), and the third work function material layer 263 employs a work function material different from that of the first work function material layer 261 and the second work function material layer 262.

[0089] Exemplarily, at the same height in the first direction, the work function materials of the first work function adjustment structure and the second work function adjustment structure are different; in the second direction, the end face of the first work function material of the first work function adjustment structure is joined to the end face of the second work function material of the second work function adjustment structure. In one embodiment, the thicknesses of the layers in the work function material stack structure are the same. Thus, after removing the first work function material layer 261 in the second region, the first work function material layer (e.g., TiN material layer) in the first region is joined and flush with the second work function material layer (e.g., TiAl material layer) in the second region, and the second work function material layer (e.g., TiAl material layer) in the first region is joined and flush with the third work function material layer (e.g., TiN material layer) in the second region.

[0090] Exemplarily, the number of stacked layers of the first work function adjustment structure is greater than that of the second work function adjustment structure, and the work function value of the first work function adjustment structure is greater than that of the second work function adjustment structure. In one embodiment, the first work function adjustment structure is a three-layer stacked structure of TiN+TiAl+TiN, and the work function value is about 5.2 eV; the second work function adjustment structure is a two-layer stacked structure of TiAl+TiN, and the work function value is about 4.2 eV.

[0091] Exemplarily, the composite work function layer includes a P-type work function part and an N-type work function part. The P-type work function part includes the first work function adjustment structure, and the N-type work function part includes the second work function adjustment structure. Among them, the work function of the N-type metal work function part usually depletes the bottom of the conduction band of the substrate, so that the threshold voltage of the NMOS becomes smaller, which is beneficial to improving the speed of the device and reducing the power consumption; the work function of the P-type metal work function layer usually depletes the top of the valence band of the substrate, so that the absolute value of the threshold voltage of the PMOS becomes smaller, which is beneficial to improving the speed of the device and reducing the power consumption. In this embodiment, by making the composite work function layer include both a P-type work function part and an N-type work function part, the composite work function layer of the metal gate is different from that of the NMOS and the PMOS. Such a structure can adjust the threshold voltage Vt. Since the number of stacked layers and the total thickness of the N-type work function part and the P-type work function part are different, their profiles are different, so the strength of resisting the electric field in the lateral direction is different, and the breakdown voltage of the semiconductor device can be improved.

[0092] In one embodiment, the material of the metal gate includes, but is not limited to, metal materials such as aluminum and copper. The semiconductor device further includes contact plugs (CT) and metal wiring layers, which will not be elaborated here.

[0093] According to the semiconductor device and its manufacturing method provided by the present invention, by forming a composite work function layer including a first work function adjustment structure and a second work function adjustment structure between the gate dielectric layer and the gate material layer, the composite work function layer has different work function values in different regions in the lateral direction, so that the semiconductor device has different strengths of resisting the electric field in the lateral direction, and the breakdown voltage of the semiconductor device is improved.

[0094] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation to the present application.

[0095] Each embodiment in this specification is described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0096] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0097] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A semiconductor device, characterized in that: include: A substrate, wherein the substrate includes a source region and a drain region separated from each other; The top surface of the substrate includes a gate structure located between the source region and the drain region, the gate structure includes a gate dielectric layer, a composite work function layer and a gate material layer stacked in sequence along a first direction away from the substrate, the composite work function layer includes a P-type work function portion and an N-type work function portion, the composite work function layer includes at least a first work function adjustment structure and a second work function adjustment structure arranged along a second direction parallel to the substrate and having different work function values, the P-type work function portion includes the first work function adjustment structure, and the N-type work function portion includes the second work function adjustment structure; Among them, the first work function adjustment structure and the second work function adjustment structure respectively include work function material stacking structures with different numbers of stacking layers along the first direction, and at the same height in the first direction, the work function materials of the first work function adjustment structure and the second work function adjustment structure are different.

2. The semiconductor device according to claim 1, wherein: The work function material stack structure is formed by alternately stacking at least two work function materials, or each layer in the work function material stack structure uses a different work function material.

3. The semiconductor device according to claim 2, characterized in that In the second direction, the first work function material end surface of the first work function adjustment structure is bonded to the second work function material end surface of the second work function adjustment structure.

4. The semiconductor device according to claim 3, characterized in that The first work function adjustment structure includes a first TiN material layer, a first TiAl material layer, and a second TiN material layer stacked in sequence along the first direction, and the second work function adjustment structure includes a second TiAl material layer and a third TiN material layer stacked in sequence along the first direction, wherein the first TiN material layer is bonded to the second TiAl material layer, and the first TiAl material layer is bonded to the third TiN material layer.

5. The semiconductor device according to claim 1, wherein: The number of stacked layers of the first work function adjustment structure is greater than the number of stacked layers of the second work function adjustment structure, and the work function value of the first work function adjustment structure is greater than the work function value of the second work function adjustment structure.

6. The semiconductor device according to claim 1, wherein: A bottom work function layer is also arranged between the gate dielectric layer and the first work function adjustment structure and the second work function adjustment structure. The bottom work function layer includes a single-layer structure or a multi-layer structure. The bottom work function layer includes a TiN material layer and a TaN material layer stacked in sequence along the first direction.

7. The semiconductor device according to claim 1, wherein: The gate dielectric layer includes a high-K dielectric layer, and the gate material layer includes a metal gate.

8. A method for preparing a semiconductor device, characterized in that: The following steps are involved: Providing a substrate, wherein the substrate includes a source region and a drain region separated from each other; A gate dielectric layer, a composite work function layer and a gate material layer are sequentially formed on the top surface of the substrate along a first direction away from the substrate, the composite work function layer includes a P-type work function portion and an N-type work function portion, wherein the composite work function layer at least includes a first work function adjustment structure and a second work function adjustment structure arranged along a second direction parallel to the substrate and having different work function values, the P-type work function portion includes the first work function adjustment structure, the N-type work function portion includes the second work function adjustment structure, the first work function adjustment structure and the second work function adjustment structure respectively include work function material stacking structures with different numbers of stacking layers along the first direction, and at the same height in the first direction, the work function materials of the first work function adjustment structure and the second work function adjustment structure are different.

9. The method for preparing a semiconductor device according to claim 8, characterized in that: The substrate includes a first region for forming the first work function regulating structure thereon and a second region for forming the second work function regulating structure thereon, Forming the first work function adjustment structure and the second work function adjustment structure includes: forming a first work function material layer covering the first region and the second region of the substrate; Etching and removing the first work function material layer covering the second region; A second work function material layer is formed on the first work function material layer and covers the first region and the second region.

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