Display device and repairing method thereof

Abstract

The invention relates to a display device and a method of repairing the same. The display device may include: a substrate; a first conductive pattern and a second conductive pattern on the substrate; a first electrode, a second electrode, a third electrode, and a fourth electrode on the first conductive pattern and the second conductive pattern; and a light emitting element on the first electrode and the second electrode. The first electrode may be electrically connected to the first conductive pattern, and the second electrode may be electrically connected to the second conductive pattern. The first conductive pattern may be electrically disconnected from the second electrode and the second conductive pattern, and the second conductive pattern may be electrically disconnected from the first electrode and the first conductive pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0136742 filed in the Korean Intellectual Property Office on October 13, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] Aspects of embodiments of the present disclosure relate to a display device and a repair method thereof. Background Art

[0004] Recently, as interest in information display increases, research and development of display devices have been continuously conducted. Summary of the invention

[0005] According to aspects of an embodiment of the present disclosure, there are provided a display device capable of improving reliability by preventing or substantially preventing a dark spot defect of a pixel and a repair method of the display device.

[0006] According to one or more embodiments of the present disclosure, a display device includes: a substrate; a first conductive pattern and a second conductive pattern, which are arranged on the substrate, and the first conductive pattern and the second conductive pattern are spaced apart from each other; a first electrode, a second electrode, a third electrode, and a fourth electrode, which are arranged on the first conductive pattern and the second conductive pattern, and the first electrode, the second electrode, the third electrode, and the fourth electrode are spaced apart from each other; and a light-emitting element, which is arranged on the first electrode and the second electrode, wherein the first electrode is electrically connected to the first conductive pattern, and the second electrode is electrically connected to the second conductive pattern, and wherein the first conductive pattern is electrically disconnected from the second electrode and the second conductive pattern, and the second conductive pattern is electrically disconnected from the first electrode and the first conductive pattern.

[0007] The first conductive pattern may overlap the first electrode, the second electrode, and the fourth electrode, and the second conductive pattern may overlap the first electrode, the second electrode, and the third electrode.

[0008] The first electrode and the third electrode may be integrally formed to be electrically connected to each other, and the second electrode and the fourth electrode may be integrally formed to be electrically connected to each other.

[0009] The display device may also include: a transistor, which is arranged on the substrate and is electrically connected to the first electrode and the third electrode; a common line, which is arranged on the substrate and is integrally formed with the second electrode and the fourth electrode to be electrically connected to the second electrode and the fourth electrode; and a power line, which is arranged on the substrate and is electrically connected to the common line, and the power line is provided with a low potential voltage.

[0010] The first electrode may include two or more first sub-electrodes spaced apart from each other, and the second electrode may include two or more second sub-electrodes spaced apart from each other. The first sub-electrodes may be electrically connected to each other, and the second sub-electrodes may be electrically connected to each other.

[0011] The display device may also include: a first connecting line, which is arranged on the first conductive pattern and the second conductive pattern, and the first connecting line is integrally formed with the first sub-electrode to be electrically connected to the first sub-electrode; and a second connecting line, which is arranged on the first conductive pattern and the second conductive pattern, and the second connecting line is integrally formed with the second sub-electrode to be electrically connected to the second sub-electrode.

[0012] The first conductive pattern may be electrically connected to at least one of the first sub-electrodes, and the second conductive pattern may be electrically connected to at least one of the second sub-electrodes.

[0013] The display device may further include an insulating layer disposed between the first conductive pattern and the second conductive pattern and the first to fourth electrodes, the insulating layer including a first contact portion exposing one end of the first conductive pattern and a second contact portion exposing one end of the second conductive pattern. At least one of the first sub-electrodes may be electrically connected to the first conductive pattern through the first contact portion, and at least one of the second sub-electrodes may be electrically connected to the second conductive pattern through the second contact portion.

[0014] The light emitting element may have a horizontal structure including a first end portion and a second end portion located on the same plane. The light emitting element may include: a semiconductor structure including a first semiconductor layer, an active layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the active layer; a first contact electrode disposed on the semiconductor structure, the first contact electrode being electrically connected to the first semiconductor layer, the first contact electrode being located at the second end portion; and a second contact electrode disposed on the semiconductor structure and spaced apart from the first contact electrode, the second contact electrode being electrically connected to the second semiconductor layer, the second contact electrode being located at the first end portion.

[0015] The first semiconductor layer may include an n-type semiconductor layer doped with an n-type dopant, and the second semiconductor layer may include a p-type semiconductor layer doped with a p-type dopant.

[0016] A first end portion of the light emitting element may be electrically connected to the first sub-electrode, and a second end portion of the light emitting element may be electrically connected to the second sub-electrode.

[0017] The first electrode may be an anode electrode, and the second electrode may be a cathode electrode.

[0018] According to one or more embodiments of the present disclosure, a display device includes: a substrate; a first conductive pattern and a second conductive pattern, which are arranged on the substrate, and the first conductive pattern and the second conductive pattern are spaced apart from each other; an insulating layer, which is arranged on the first conductive pattern and the second conductive pattern, and the insulating layer includes a first contact portion exposing a first end of the first conductive pattern, a second contact portion exposing the first end of the second conductive pattern, a third contact portion exposing the second end of the first conductive pattern, and a fourth contact portion exposing the second end of the second conductive pattern; a first electrode, which is arranged on the insulating layer, and the first electrode includes two or more first sub-electrodes; a second electrode, which is on the insulating layer, and the second electrode includes two or more second sub-electrodes; a third electrode, which is arranged to be spaced apart from the first electrode and the second electrode; a fourth electrode, which is arranged to be spaced apart from the first electrode to the third electrode; and a light-emitting element, which is arranged on the first electrode and the second electrode, wherein at least one of the first sub-electrodes is electrically connected to the first end of the first conductive pattern through the first contact portion, and the fourth electrode is electrically connected to the second end of the first conductive pattern through the third contact portion, and wherein at least one of the second sub-electrodes is electrically connected to the first end of the second conductive pattern through the second contact portion, and the third electrode is electrically connected to the second end of the second conductive pattern through the fourth contact portion.

[0019] The light emitting element may include a first end portion and a second end portion located on the same plane. The first end portion may be electrically connected to the second sub-electrode, and the second end portion may be electrically connected to the first sub-electrode. The p-type semiconductor layer may be located at the first end portion, and the n-type semiconductor layer may be located at the second end portion.

[0020] The display device may further include: a transistor disposed on the substrate, the transistor being electrically connected to the third electrode; a common line disposed on the substrate, the common line being integrally formed with the fourth electrode to be electrically connected to the fourth electrode; and a power line disposed on the substrate, the power line being electrically connected to the common line, the power line being provided with a low potential voltage. The first sub-electrode may be electrically connected to the fourth electrode through the first conductive pattern, and the second sub-electrode may be electrically connected to the third electrode through the second conductive pattern.

[0021] The first sub-electrode may be electrically disconnected from the third electrode, and the second sub-electrode may be electrically disconnected from the fourth electrode.

[0022] The first sub-electrode may correspond to a cathode electrode, and the second sub-electrode may correspond to an anode electrode.

[0023] According to one or more embodiments of the present disclosure, a method for repairing a display device is provided, wherein the display device includes: a substrate; a first conductive pattern and a second conductive pattern, which are arranged on the substrate, and the first conductive pattern and the second conductive pattern are spaced apart from each other; a first electrode, which is arranged on the first conductive pattern and the second conductive pattern, and the first electrode includes two or more first sub-electrodes, and the first electrode is electrically connected to a first end of the first conductive pattern; a second electrode, which is arranged on the first conductive pattern and the second conductive pattern, and the second electrode includes two or more second sub-electrodes, and the second electrode is electrically connected to a first end of the second conductive pattern; a third electrode, which is arranged on the second conductive pattern, and the third electrode is electrically connected to the first sub-electrode, and the third electrode overlaps with the second end of the second conductive pattern; a fourth electrode, which is arranged on the first conductive pattern, and the fourth electrode is electrically connected to the first sub-electrode. two sub-electrodes, the fourth electrode overlapping with the second end of the first conductive pattern; and a light-emitting element electrically connected to the first sub-electrode and the second sub-electrode, and wherein the method comprises: in the case where the light-emitting element is a defective light-emitting element, using a laser to electrically disconnect the first sub-electrode and the third electrode from each other and to electrically disconnect the second sub-electrode and the fourth electrode; and electrically connecting the second end of the first conductive pattern and the fourth electrode to each other by irradiating a laser onto the top of the overlapping area of ​​the first conductive pattern and the fourth electrode and then removing a portion of the insulating layer between the first conductive pattern and the fourth electrode, and electrically connecting the second end of the second conductive pattern and the third electrode to each other by irradiating a laser onto the top of the overlapping area of ​​the second conductive pattern and the third electrode and then removing another portion of the insulating layer between the second conductive pattern and the third electrode.

[0024] The defective light emitting element may include a first end portion and a second end portion located on the same plane. The first end portion may be electrically connected to the second sub-electrode and the fourth electrode, and the second end portion may be electrically connected to the first sub-electrode and the third electrode. The p-type semiconductor layer may be located at the first end portion, and the n-type semiconductor layer may be located at the second end portion.

[0025] The display device may further include: a transistor disposed on the substrate, the transistor being electrically connected to the third electrode; a common line disposed on the substrate, the common line being integrally formed with the fourth electrode to be electrically connected to the fourth electrode; and a power line disposed on the substrate, the power line being electrically connected to the common line, the power line being provided with a low potential voltage. The first sub-electrode may be electrically connected to the fourth electrode through the first conductive pattern, and the second sub-electrode may be electrically connected to the third electrode through the second conductive pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Some exemplary embodiments will now be described more fully herein with reference to the accompanying drawings; however, the present disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments to those skilled in the art.

[0027] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that where an element is referred to as being "between" two elements, it may be the only element between the two elements, or one or more intervening elements may also be present. The same reference numerals always represent the same elements.

[0028] Figure 1 is a schematic plan view showing a display device according to an embodiment of the present disclosure.

[0029] Figure 2 It is shown Figure 1 A schematic cross-sectional view of a display panel shown in FIG.

[0030] Figure 3 It is shown that the Figure 1 A schematic circuit diagram of the electrical connection relationship of the components in each of the pixels shown in FIG.

[0031] Figure 4 is a schematic plan view showing a sub-pixel according to an embodiment of the present disclosure.

[0032] Figure 5 It is along Figure 4 A schematic cross-sectional view taken along line II' shown in FIG.

[0033] Figure 6 It is along Figure 4 Schematic cross-sectional views taken along line II-II′ and line III-III′ shown in FIG.

[0034] Figure 7 It is shown in Figure 4 Schematic plan view of a state in which a light-emitting element is transferred in a sub-pixel shown in .

[0035] Figure 8 It is along Figure 7 A schematic cross-sectional view taken along line IV-IV' shown in FIG.

[0036] Fig. 9 It is shown Figure 8 Schematic cross-sectional view of a light emitting element shown in FIG.

[0037] Fig.10 A sub-pixel according to an embodiment of the present disclosure is shown and corresponds to Figure 7Schematic cross-sectional view along line IV-IV' shown in FIG.

[0038] Fig.11 A sub-pixel including a defective light-emitting element is shown, and corresponds to Figure 7 Schematic cross-sectional view along line IV-IV' shown in FIG.

[0039] Fig.12 and Fig.13 It shows the repair Fig.11 Schematic plan view of a method for removing a defective light-emitting element as shown in FIG.

[0040] Fig.14A It is along Fig.13 A schematic cross-sectional view taken along line V-V' shown in FIG.

[0041] Fig. 14B yes Fig.14A Schematic enlarged cross-sectional view of area “ EA1 ” shown in .

[0042] Fig.15A It is along Fig.13 A schematic cross-sectional view taken along line VI-VI' shown in FIG.

[0043] Fig. 15B yes Fig.15A A schematic enlarged cross-sectional view of the area “EA2” shown in FIG. DETAILED DESCRIPTION

[0044] The present disclosure may apply various changes and different shapes, and therefore, only some specific examples are shown herein. However, the embodiments are not limited to specific shapes, but are applicable to various changes and equivalent materials and replacements thereof. The included drawings may be shown so that the drawings are expanded for better understanding.

[0045] The same reference numerals always represent the same elements. In the accompanying drawings, for clarity, the thickness of a specific line, layer, component, element or feature may be exaggerated. It will be understood that although the terms "first", "second", etc. can be used herein to describe various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the "first" element discussed below may also be referred to as the "second" element. As used herein, the singular form is intended to also include the plural form, unless the context clearly indicates otherwise.

[0046] It will also be understood that the terms "comprises" and / or "includes" as used in this specification indicate the presence of the features, entities, steps, operations, elements and / or parts set forth, but do not exclude the presence and / or addition of one or more other features, entities, steps, operations, elements, parts and / or groups thereof. In addition, the statement that an element such as a layer, region, substrate or plate is placed "on" or "above" another element not only indicates the situation where the element is "directly" placed "on" or "directly above" another element, but also indicates the situation where another element is inserted between the element and the other element. In addition, the statement that an element such as a layer, region, substrate or plate is placed "below" or "below" another element not only indicates the situation where the element is "directly" placed "below" or "directly below" another element, but also indicates the situation where another element is inserted between the element and the other element.

[0047] Herein, some exemplary embodiments of the present disclosure and items required for those skilled in the art to easily understand the contents of the present disclosure will be described in more detail with reference to the accompanying drawings.In the following description, unless the context clearly indicates otherwise, the singular form in the present disclosure is intended to also include the plural form.

[0048] Figure 1 is a schematic plan view showing a display device DD according to an embodiment of the present disclosure. Figure 2 It is shown Figure 1 Schematic cross-sectional view of the display panel DP shown in FIG.

[0049] exist Figure 1 and Figure 2 , for convenience of description, the structure of the display device DD, for example, the display panel DP provided in the display device DD, is schematically illustrated based on a display area DA in which an image is displayed.

[0050] refer to Figure 1 and Figure 2 The display panel DP (or display device DD) according to an embodiment of the present disclosure may be provided in any of various shapes. For example, the display panel DP may be provided in a rectangular plate shape having two pairs of sides parallel to each other, but the present disclosure is not limited thereto. In the case where the display panel DP is provided in a rectangular plate shape, any pair of the two pairs of sides may be provided to be longer than the other pair of sides. Figure 1 , an extending direction of the long side is indicated as a second direction DR2, and an extending direction of the short side is indicated as a first direction DR1.

[0051] In an embodiment, at least a portion of the display panel DP may have flexibility and be folded at the portion having flexibility. However, the present disclosure is not limited thereto.

[0052] The display panel DP may display an image. A self-luminous display panel or a non-luminous display panel may be used as the display panel DP.

[0053] The display panel DP may include a substrate SUB and pixels PXL (or sub-pixels SPX) disposed on the substrate SUB.

[0054] The substrate SUB may include a transparent insulating material to allow light to pass therethrough, but the present disclosure is not limited thereto. The substrate SUB may be a rigid substrate or a flexible substrate.

[0055] The rigid substrate may be any one of, for example, a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystallized glass substrate.

[0056] The flexible substrate may be any one of a film substrate and a plastic substrate, which may include a polymer organic material. For example, the flexible substrate may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0057] One area of ​​the substrate SUB may be set as a display area DA so that the pixel PXL is disposed therein, and another area of ​​the substrate SUB may be set as a non-display area NDA. For example, the substrate SUB may include a display area DA including a pixel area in which a corresponding pixel PXL (or a corresponding sub-pixel SPX) is disposed, and a non-display area NDA disposed at the periphery of the display area DA (or adjacent to the display area DA).

[0058] The non-display area NDA may be positioned adjacent to the display area DA. The non-display area NDA may be disposed at least one side of the display area DA. For example, the non-display area NDA may surround the periphery (or edge) of the display area DA. A line unit connected to each pixel PXL and a driving unit connected to the line unit and driving the pixel PXL may be disposed in the non-display area NDA.

[0059] The pixel PXL may be disposed in the display area DA of the substrate SUB. The pixel PXL may include a light emitting element emitting white light and / or colored light and a pixel circuit for driving the light emitting element. The pixel circuit may include at least one transistor electrically connected to the light emitting element. The pixel PXL may emit light of one color among red, green and blue, but the present disclosure is not limited thereto. For example, the pixel PXL may emit light of one color among cyan, magenta, yellow and white.

[0060] In an embodiment, a plurality of pixels PXL may be arranged in a matrix form along rows extending in a first direction DR1 and columns extending in a second direction DR2 intersecting the first direction DR1. However, the arrangement form of the pixels PXL is not particularly limited, and the pixels PXL may be arranged in various forms. In some embodiments, in the case where each of the pixels PXL is arranged in plurality, the pixels PXL may be arranged in different areas (or sizes). For example, in the case where light of different colors is emitted from the pixels PXL, the pixels PXL may be arranged to have different areas (or sizes) or different shapes for different colors.

[0061] The driving unit may provide a signal (eg, a predetermined signal) and a voltage (eg, a predetermined voltage) to each pixel PXL through the line unit, thereby controlling driving of the pixel PXL.

[0062] The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, and an overcoat layer OC.

[0063] The pixel circuit layer PCL may be disposed on the substrate SUB and include transistors and signal lines connected to the transistors. For example, the transistor may have a form in which a semiconductor pattern and a gate electrode are sequentially stacked and an insulating layer is interposed therebetween. The semiconductor pattern may include amorphous silicon, polycrystalline silicon, low-temperature polycrystalline silicon, an organic semiconductor and / or an oxide semiconductor. The gate electrode may include any one of aluminum, copper, titanium and molybdenum, but the present disclosure is not limited thereto. In addition, the pixel circuit layer PCL may include at least one insulating layer.

[0064] The display element layer DPL may be disposed on the pixel circuit layer PCL. The display element layer DPL may include a light emitting element that emits light.

[0065] An overcoat layer OC may be selectively disposed on the display element layer DPL.

[0066] The overcoat layer OC may be provided to cover the display element layer DPL. Therefore, the overcoat layer OC may protect the display element layer DPL from external impact.

[0067] Figure 3 It is shown that the Figure 1 Schematic circuit diagram of the electrical connection relationship of components in each of the pixels PXL shown in FIG.

[0068] For ease of description, we will Figure 3 , a pixel PXL (or a sub-pixel SPX) located on the i-th pixel row (or i-th horizontal line) and the j-th pixel column is shown (i and j are natural numbers greater than 0).

[0069] refer to Figures 1 to 3, the pixel PXL (or sub-pixel SPX) may include a pixel circuit PXC and a light emitting unit EMU.

[0070] The light emitting unit EMU may include a light emitting element LD connected between a first power line PL1 and a second power line PL2, the first power line PL1 is provided with a voltage of a first driving power source VDD, and the second power line PL2 is provided with a voltage of a second driving power source VSS. For example, the light emitting unit EMU may include a first electrode EL1 connected to the first driving power source VDD via the pixel circuit PXC and the first power line PL1, a second electrode EL2 connected to the second driving power source VSS via the second power line PL2, and a light emitting element LD connected between the first electrode EL1 and the second electrode EL2. In an embodiment, the first electrode EL1 may be an anode electrode, and the second electrode EL2 may be a cathode electrode.

[0071] The light emitting element LD may include a first end portion EP1 electrically connected to the first electrode EL1 and a second end portion EP2 electrically connected to the second electrode EL2. The voltage of the first driving power supply VDD and the voltage of the second driving power supply VSS may have different potentials. For example, the voltage of the first driving power supply VDD may be a high potential voltage, and the voltage of the second driving power supply VSS may be a low potential voltage. During the emission period of the pixel PXL, the potential difference between the first driving power supply VDD and the second driving power supply VSS may be set to be equal to or higher than the threshold voltage of the light emitting element LD.

[0072] As described above, the light emitting element LD may constitute an effective light source of the light emitting unit EMU.

[0073] The light emitting element LD may emit light having a brightness corresponding to the driving current provided by the pixel circuit PXC. For example, the pixel circuit PXC may provide a driving current corresponding to the grayscale value of the corresponding frame data to the light emitting unit EMU during each frame period. The driving current provided to the light emitting unit EMU may flow through the light emitting element LD. Therefore, the light emitting unit EMU may emit light while the light emitting element LD emits light having a brightness corresponding to the driving current.

[0074] In the case where the pixel PXL (or subpixel SPX) is located in the i-th pixel row and the j-th pixel column in the display area DA, the pixel circuit PXC of the pixel PXL may be electrically connected to the i-th scan line Si and the j-th data line Dj.

[0075] The pixel circuit PXC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst.

[0076] The first transistor T1 is a driving transistor for controlling a driving current applied to the light emitting element LD, and may be electrically connected between a first power line PL1 to which a voltage of a first driving power source VDD is supplied and the light emitting element LD. A first terminal of the first transistor T1 may be electrically connected to the voltage of the first driving power source VDD through the first power line PL1, a second terminal of the first transistor T1 may be electrically connected to the light emitting element LD, and a gate electrode of the first transistor T1 may be electrically connected to a first node N1. The first transistor T1 may be turned on according to a voltage applied to the first node N1. The first transistor T1 may be designated as a driving transistor.

[0077] The second transistor T2 is a switching transistor for selecting the pixel PXL in response to the scan signal and activating the pixel PXL, and may be electrically connected between the j-th data line Dj and the first node N1. A first terminal of the second transistor T2 may be electrically connected to the j-th data line Dj, a second terminal of the second transistor T2 may be electrically connected to the first node N1 (or a gate electrode of the first transistor T1), and a gate electrode of the second transistor T2 may be electrically connected to the i-th scan line Si.

[0078] In the case where a scan signal having a gate-on voltage (e.g., a low level voltage) is provided from the i-th scan line Si, the second transistor T2 may be turned on to electrically connect the j-th data line Dj and the first node N1 to each other. The data signal of the corresponding frame may be provided to the j-th data line Dj. Therefore, the data signal may be transmitted to the first node N1. The data signal transmitted to the first node N1 may be charged into the storage capacitor Cst.

[0079] A first electrode of the storage capacitor Cst may be electrically connected to a node (or a first power line PL1) to which a voltage of a first driving power source VDD is supplied, and a second electrode of the storage capacitor Cst may be electrically connected to a first node N1. The storage capacitor Cst may charge a voltage corresponding to a data signal supplied to the first node N1 and maintain the charged voltage until a data signal of a next frame is supplied.

[0080] exist Figure 3, a pixel circuit PXC is shown, which includes a second transistor T2 for transmitting a data signal to a pixel PXL (or a sub-pixel SPX), a storage capacitor Cst for storing the data signal, and a first transistor T1 for providing a driving current corresponding to the data signal to the light-emitting element LD. However, the present disclosure is not limited thereto, and the structure of the pixel circuit PXC may be modified differently according to the embodiment. For example, the pixel circuit PXC may further include at least one transistor element, such as a transistor element for compensating for the threshold voltage of the first transistor T1, a transistor element for initializing the first node N1, and / or a transistor element for controlling the emission time of the light-emitting element LD, or may further include other circuit elements such as a boost capacitor for increasing the voltage of the first node N1.

[0081] In the embodiment, for convenience of description, a transverse direction on a plane is indicated as a first direction DR1, a longitudinal direction on a plane is indicated as a second direction DR2, and a direction on a cross section is indicated as a third direction DR3.

[0082] Figure 4 is a schematic plan view showing a sub-pixel SPX according to an embodiment of the present disclosure.

[0083] exist Figure 4 , for convenience of description, the first conductive pattern CP1 and the second conductive pattern CP2 among the components disposed under the third via layer VIA3 are illustrated.

[0084] refer to Figures 1 to 4 The subpixel SPX (or pixel PXL) may include a first electrode EL1, a second electrode EL2, a third electrode EL3, a fourth electrode EL4 and a common line COL disposed on the third via layer VIA3. In addition, the subpixel SPX may include a first conductive pattern CP1 and a second conductive pattern CP2 disposed under the third via layer VIA3.

[0085] In an embodiment, the common line COL may have a closed loop shape around the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 in the area of ​​the display area DA where the sub-pixel SPX is disposed (e.g., around the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4). However, the present disclosure is not limited thereto, and the common line COL may be provided in various shapes. The common line COL may be electrically connected to the reference Figure 3 Therefore, the voltage of the second driving power source VSS may be supplied to the common line COL.

[0086] The first electrode EL1 may be disposed to be spaced apart from the common line COL. The first electrode EL1 may be integrally formed with the third electrode EL3. The first electrode EL1 and the third electrode EL3 may be electrically connected to each other. In an embodiment, the first electrode EL1 may have a bar shape extending in the second direction DR2, but the present disclosure is not limited thereto.

[0087] In an embodiment, the first electrode EL1 may include at least two first sub-electrodes. For example, the first electrode EL1 may include four first sub-electrodes. The four first sub-electrodes may include a 1-1st sub-electrode SUE1_1, a 1-2nd sub-electrode SUE1_2, a 1-3rd sub-electrode SUE1_3, and a 1-4th sub-electrode SUE1_4. The 1-1st sub-electrode SUE1_1, the 1-2nd sub-electrode SUE1_2, the 1-3rd sub-electrode SUE1_3, and the 1-4th sub-electrode SUE1_4 may be arranged along the first direction DR1 and extend in the second direction DR2. The 1-1st sub-electrode SUE1_1, the 1-2nd sub-electrode SUE1_2, the 1-3rd sub-electrode SUE1_3, and the 1-4th sub-electrode SUE1_4 may be electrically connected to each other through the first connection line CNL1. The 1-1th sub-electrode SUE1_1, the 1-2th sub-electrode SUE1_2, the 1-3th sub-electrode SUE1_3, and the 1-4th sub-electrode SUE1_4 may have a bar shape extending from the first connection line CNL1 along the second direction DR2.

[0088] The first connection line CNL1 may extend in the first direction DR1 and be located between adjacent first sub-electrodes to electrically connect the first sub-electrodes to each other. The first connection line CNL1 may be located, for example, between the 1-1st sub-electrode SUE1_1 and the 1-2nd sub-electrode SUE1_2, between the 1-2nd sub-electrode SUE1_2 and the 1-3rd sub-electrode SUE1_3, and between the 1-3rd sub-electrode SUE1_3 and the 1-4th sub-electrode SUE1_4. In an embodiment, the first connection line CNL1 may be integrally formed with the 1-1st sub-electrode SUE1_1, the 1-2nd sub-electrode SUE1_2, the 1-3rd sub-electrode SUE1_3, and the 1-4th sub-electrode SUE1_4. In an embodiment, the first connection line CNL1 may be integrally formed with the first portion EL3a of the third electrode EL3.

[0089] In an embodiment, the 1-1st sub-electrode SUE1_1, the 1-2nd sub-electrode SUE1_2, the 1-3rd sub-electrode SUE1_3, and the 1-4th sub-electrode SUE1_4 may have the same width, but the present disclosure is not limited thereto. In some embodiments, the 1-1st sub-electrode SUE1_1, the 1-2nd sub-electrode SUE1_2, the 1-3rd sub-electrode SUE1_3, and the 1-4th sub-electrode SUE1_4 may have different widths. In an embodiment, the first connection line CNL1 may have a width different from that of the 1-1st sub-electrode SUE1_1 to the 1-4th sub-electrode SUE1_4.

[0090] The second electrode EL2 may be branched from the common line COL along the second direction DR2. In an embodiment, the second electrode EL2 may be formed integrally with the common line COL to be electrically connected to the common line COL. The second electrode EL2 may have a bar shape extending in the second direction DR2, but the present disclosure is not limited thereto. In an embodiment, the common line COL is electrically connected to the second power line PL2 through the second contact hole CH2, so that the second electrode EL2 may be electrically connected to the second power line PL2. In an embodiment, the second electrode EL2 may be a cathode electrode electrically connected to the second end portion EP2 of the light emitting element LD.

[0091] In an embodiment, the second electrode EL2 may include at least two second sub-electrodes. For example, the second electrode EL2 may include four second sub-electrodes. The four second sub-electrodes may include a 2-1st sub-electrode SUE2_1, a 2-2nd sub-electrode SUE2_2, a 2-3rd sub-electrode SUE2_3, and a 2-4th sub-electrode SUE2_4. The 2-1st sub-electrode SUE2_1, the 2-2nd sub-electrode SUE2_2, the 2-3rd sub-electrode SUE2_3, and the 2-4th sub-electrode SUE2_4 may be arranged along the first direction DR1 and electrically connected to each other through the second connection line CNL2.

[0092] The second connection line CNL2 may extend in the first direction DR1 and be located between adjacent second sub-electrodes to electrically connect the second sub-electrodes to each other. The second connection line CNL2 may be located, for example, between the 2-1st sub-electrode SUE2_1 and the 2-2nd sub-electrode SUE2_2, between the 2-2nd sub-electrode SUE2_2 and the 2-3rd sub-electrode SUE2_3, and between the 2-3rd sub-electrode SUE2_3 and the 2-4th sub-electrode SUE2_4. In an embodiment, the second connection line CNL2 may be integrally formed with the 2-1st sub-electrode SUE2_1, the 2-2nd sub-electrode SUE2_2, the 2-3rd sub-electrode SUE2_3, and the 2-4th sub-electrode SUE2_4.

[0093] In an embodiment, the 2-1st sub-electrode SUE2_1, the 2-2nd sub-electrode SUE2_2, the 2-3rd sub-electrode SUE2_3, and the 2-4th sub-electrode SUE2_4 may have the same width, but the present disclosure is not limited thereto. In some embodiments, the 2-1st sub-electrode SUE2_1, the 2-2nd sub-electrode SUE2_2, the 2-3rd sub-electrode SUE2_3, and the 2-4th sub-electrode SUE2_4 may have different widths. The second connection line CNL2 may have a width different from that of the 2-1st sub-electrode SUE2_1 to the 2-4th sub-electrode SUE2_4.

[0094] In a plan view, the 1-1th sub-electrode SUE1_1 and the 2-4th sub-electrode SUE2_4 may be disposed to face each other in the first direction DR1, but the present disclosure is not limited thereto.

[0095] The third electrode EL3 may be disposed to be spaced apart from the first electrode EL1, the second electrode EL2, the fourth electrode EL4, and the common line COL. The third electrode EL3 may be electrically connected to the first electrode EL1 through the first connection line CNL1. In an embodiment, the third electrode EL3, the first connection line CNL1, and the first electrode EL1 may be integrally formed.

[0096] The third electrode EL3 may be electrically connected to the reference electrode through the first contact hole CH1. Figure 3 Part of the pixel circuit PXC described, such as the first transistor T1. In an embodiment, the third electrode EL3 is electrically connected to the first electrode EL1 through the first connection line CNL1, so that the first electrode EL1 can be electrically connected to the pixel circuit PXC. In an embodiment, the first electrode EL1 can be an anode electrode electrically connected to the first end portion EP1 of the light emitting element LD.

[0097] The third electrode EL3 may include a first portion EL3a extending along the first direction DR1 and a second portion EL3b extending along the second direction DR2. In an embodiment, a width of the second portion EL3b may be greater than a width of the first sub-electrode, but the present disclosure is not limited thereto.

[0098] The fourth electrode EL4 may be disposed to be spaced apart from the first electrode EL1, the second electrode EL2, and the third electrode EL3. The fourth electrode EL4 may branch from the common line COL along the second direction DR2. In an embodiment, the common line COL, the second electrode EL2, and the fourth electrode EL4 may be integrally formed. The fourth electrode EL4 may be electrically connected to the second power line PL2.

[0099] In an embodiment, the fourth electrode EL4 may have a strip shape extending in the second direction DR2, but the present disclosure is not limited thereto. In an embodiment, the width of the fourth electrode EL4 may be greater than the width of the second sub-electrode, but the present disclosure is not limited thereto. In some embodiments, the width of each of the second sub-electrodes may be greater than the width of the fourth electrode EL4.

[0100] The first and second conductive patterns CP1 and CP2 may be disposed under the first to fourth electrodes EL1 to EL4 and the common line COL. For example, the first and second conductive patterns CP1 and CP2 may be disposed under the first to fourth electrodes EL1 to EL4 and the common line COL with the third via layer VIA3 interposed therebetween.

[0101] The first conductive pattern CP1 may extend in the first direction DR1 and be disposed to be spaced apart from the second conductive pattern CP2. The first conductive pattern CP1 may be used as a first bridge pattern to electrically connect the first electrode EL1 and the fourth electrode EL4 to each other by laser irradiation or the like in a process of repairing a dark spot defect of the sub-pixel SPX (which occurs when the light emitting element LD is connected in a reverse direction). In an embodiment, the first conductive pattern CP1 may be electrically connected to the first electrode EL1 through a first contact portion CNT1. For example, one end of the first conductive pattern CP1 (e.g., the "right end portion" in the plan view) may be electrically connected to the 1st-3rd sub-electrode SUE1_3 through the first contact portion CNT1 that passes through some insulating layers including the third via layer VIA3. The first conductive pattern CP1, the first electrode EL1 including the 1st-3rd sub-electrode SUE1_3, and the third electrode EL3 may be electrically connected to each other. In an embodiment, the first conductive pattern CP1 may overlap each of the first electrode EL1, the second electrode EL2, and the fourth electrode EL4. In an embodiment, the first conductive pattern CP1 may not overlap the third electrode EL3, but the present disclosure is not limited thereto. In some embodiments, the first conductive pattern CP1 may also overlap with the third electrode EL3 .

[0102] The second conductive pattern CP2 may extend in the first direction DR1 and be disposed to be spaced apart from the first conductive pattern CP1. The second conductive pattern CP2 may be used as a second bridge pattern electrically connecting the second electrode EL2 and the third electrode EL3 by laser irradiation or the like in a process of repairing a dark spot defect of the sub-pixel SPX (which occurs when the light emitting element LD is connected in a reverse direction). In an embodiment, the second conductive pattern CP2 may be electrically connected to the second electrode EL2 through a second contact portion CNT2. For example, one end of the second conductive pattern CP2 (e.g., the "left end portion" in the plan view) may be electrically connected to the 2-2 sub-electrode SUE2_2 of the second electrode EL2 through a second contact portion CNT2 that passes through some insulating layers including the third via layer VIA3. The second conductive pattern CP2, the second electrode EL2 including the 2-2 sub-electrode SUE2_2, the fourth electrode EL4, and the common line COL may be electrically connected to each other. In an embodiment, the second conductive pattern CP2 may overlap each of the first electrode EL1, the second electrode EL2, and the third electrode EL3. In an embodiment, the second conductive pattern CP2 may not overlap the fourth electrode EL4, but the present disclosure is not limited thereto. In some embodiments, the second conductive pattern CP2 may also overlap with the fourth electrode EL4.

[0103] In this article, we will mainly refer to Figure 5 and Figure 6 A stack structure (or a cross-sectional structure) of the sub-pixel SPX (or the pixel PXL) according to the above-described embodiment is described.

[0104] Figure 5 It is along Figure 4 A schematic cross-sectional view taken along line II' shown in FIG. Figure 6 It is along Figure 4 Schematic cross-sectional views taken along lines II-II′ and III-III′ shown in FIG.

[0105] exist Figure 5 and Figure 6 In the figure, for convenience of description, one sub-pixel SPX (or one pixel PXL) is shown, so that each electrode is shown as an electrode having a signal layer, and each insulating layer is shown as an insulating layer set as a single layer, but the present disclosure is not limited thereto.

[0106] refer to Figures 1 to 6 , the sub-pixel SPX (or the pixel PXL) may include a substrate SUB, a pixel circuit layer PCL disposed on the substrate SUB, and an electrode disposed on the pixel circuit layer PCL.

[0107] The substrate SUB may include a transparent insulating material to enable light to be transmitted therethrough. The substrate SUB may be a rigid substrate or a flexible substrate. The substrate SUB may include a first surface SF1 and a second surface SF2 facing each other in a third direction DR3. The first surface SF1 may be a mounting surface on which the light emitting element LD is mounted, and the second surface SF2 may be a surface on which an intermediate electrode CTE electrically connected to a flexible film (not shown) is provided.

[0108] In the sub-pixel SPX, a third passivation layer PAS3 , a fourth via layer VIA4 , and a fourth passivation layer PAS4 sequentially stacked in an opposite direction to the third direction DR3 may be disposed on the second surface SF2 of the substrate SUB.

[0109] The third passivation layer PAS3 may be located on the second surface SF2 of the substrate SUB, protect the second surface SF2 of the substrate SUB, and planarize the second surface SF2 of the substrate SUB. In an embodiment, the third passivation layer PAS3 may be an inorganic insulating layer including an inorganic material. In an embodiment, the third passivation layer PAS3 may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x ) at least one of.

[0110] The intermediate electrode CTE may be disposed on the third passivation layer PAS3. The intermediate electrode CTE may provide a voltage or signal received from the flexible film to a side surface connection line (not shown) through a lead. The intermediate electrode CTE may be electrically connected to the flexible film through a conductive member (or a connection film).

[0111] In an embodiment, the intermediate electrode CTE may include a first intermediate electrode CTE1 and a second intermediate electrode CTE2. The first intermediate electrode CTE1 may be disposed on a surface (or bottom surface) of the third passivation layer PAS3. The first intermediate electrode CTE1 may be a single layer or a multilayer, and may be made of any one of molybdenum, aluminum, chromium, gold, titanium, nickel, neodymium, copper, and any alloy thereof. The second intermediate electrode CTE2 may be disposed on a surface (or bottom surface) of the first intermediate electrode CTE1. The second intermediate electrode CTE2 may include a transparent conductive material (TCO), such as ITO or IZO.

[0112] The fourth via layer VIA4 may be disposed on the third passivation layer PAS3 and a portion of the intermediate electrode CTE. In an embodiment, the fourth via layer VIA4 may be an organic insulating layer including an organic material. In an embodiment, the fourth via layer VIA4 may include at least one of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and a benzocyclobutene resin. The fourth via layer VIA4 may planarize the second surface SF2 of the substrate SUB.

[0113] The fourth passivation layer PAS4 may be disposed on the fourth via layer VIA4 and the intermediate electrode CTE to protect the intermediate electrode CTE. In an embodiment, the fourth passivation layer PAS4 may include the same material as the third passivation layer PAS3 or include a suitable material among those described as constituting the third passivation layer PAS3.

[0114] The pixel circuit layer PCL may be disposed and / or formed on the first surface SF1 of the substrate SUB.

[0115] The pixel circuit PXC may be disposed in the pixel circuit layer PCL. The pixel circuit layer PCL may include at least one insulating layer disposed on the first surface SF1 of the substrate SUB. For example, the pixel circuit layer PCL may include a buffer layer BFL, a first gate insulating layer GI1, a second gate insulating layer GI2, an interlayer insulating layer ILD, a first via layer VIA1, a first passivation layer PAS1, a second via layer VIA2, a second passivation layer PAS2, and a third via layer VIA3, which are sequentially stacked on the first surface SF1 of the substrate SUB along a third direction DR3.

[0116] The buffer layer BFL may be disposed on the first surface SF1 of the substrate SUB. The buffer layer BFL may prevent or substantially prevent impurities from diffusing into the transistor T. In an embodiment, the buffer layer BFL may be an inorganic insulating layer including an inorganic material. For example, the buffer layer BFL may include silicon nitride (SiN x ), silicon oxide (SiO x ) and silicon oxynitride (SiO x N y ) or includes at least one of aluminum oxide (AlO x ) is at least one of the metal oxides of the substrate SUB. In an embodiment, the buffer layer BFL may be provided as a single layer, but may be provided as a multilayer including at least two layers. In the case where the buffer layer BFL is provided as a multilayer, the layers may be formed of the same material or of different materials. However, in an embodiment, the buffer layer BFL may be omitted depending on the material of the substrate SUB, process conditions, etc.

[0117] The first gate insulating layer GI1 may be disposed on the buffer layer BFL, but the present disclosure is not limited thereto. In some embodiments, the first gate insulating layer GI1 may be partially disposed on the buffer layer BFL. The first gate insulating layer GI1 may include the same material as the buffer layer BFL described above, or include, for example, an appropriate material among those materials described as materials constituting the buffer layer BFL.

[0118] The second gate insulating layer GI2 may be disposed on the first gate insulating layer GI1, but the present disclosure is not limited thereto. In some embodiments, the second gate insulating layer GI2 may be partially disposed on the first gate insulating layer GI1. In an embodiment, the second gate insulating layer GI2 may include the same material as the first gate insulating layer GI1. For example, the second gate insulating layer GI2 may be an inorganic insulating layer including an inorganic material.

[0119] An interlayer insulating layer ILD may be disposed and / or formed on the second gate insulating layer GI2. In an embodiment, the interlayer insulating layer ILD may include the same material as the second gate insulating layer GI2, or include an appropriate material, such as those constituting the second gate insulating layer GI2.

[0120] The first via layer VIA1 may be disposed and / or formed on the interlayer insulating layer ILD. The first via layer VIA1 may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. The inorganic insulating layer may include, for example, silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x ). The organic insulating layer may include, for example, at least one of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin. The first via layer VIA1 may have a flat surface to reduce a step difference caused by a component disposed thereunder. The first via layer VIA1 may be an organic insulating layer including an organic material.

[0121] In an embodiment, the first passivation layer PAS1 may be entirely disposed and / or formed on the first via layer VIA1. In an embodiment, the first passivation layer PAS1 may be an inorganic insulating layer including an inorganic material. The first passivation layer PAS1 may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x) at least one of.

[0122] In an embodiment, the second via layer VIA2 may be integrally disposed and / or formed on the first passivation layer PAS1. The second via layer VIA2 may include the same material as the first via layer VIA1, or include, for example, an appropriate material among the materials constituting the first via layer VIA1. For example, the second via layer VIA2 may be an organic insulating layer including an organic material.

[0123] In an embodiment, the second passivation layer PAS2 may be entirely disposed and / or formed on the second via layer VIA2. In an embodiment, the second passivation layer PAS2 may include the same material as the first passivation layer PAS1. The second passivation layer PAS2 may be an inorganic insulating layer including an inorganic material.

[0124] In an embodiment, the third via layer VIA3 may be entirely disposed and / or formed on the second passivation layer PAS2. In an embodiment, the third via layer VIA3 may include the same material as the first via layer VIA1. For example, the third via layer VIA3 may be an organic insulating layer including an organic material.

[0125] The pixel circuit layer PCL may include at least one conductive layer disposed between the insulating layers described above. For example, the pixel circuit layer PCL may include a first conductive layer disposed between the substrate SUB and the buffer layer BFL, a second conductive layer disposed between the first gate insulating layer GI1 and the second gate insulating layer GI2, a third conductive layer disposed between the interlayer insulating layer ILD and the first via layer VIA1, a fourth conductive layer disposed between the first passivation layer PAS1 and the second via layer VIA2, and a fifth conductive layer disposed between the second passivation layer PAS2 and the third via layer VIA3.

[0126] In an embodiment, the first conductive layer may be formed as a single layer including any one selected from the group consisting of copper, molybdenum, tungsten, neodymium, titanium, aluminum, silver, and any alloys thereof, or mixtures thereof. In another embodiment, the first conductive layer may be formed as a double or more layer structure including any one of molybdenum, titanium, copper, aluminum, and silver as a low resistance material to reduce wiring resistance. Each of the second to fifth conductive layers may include the same material as the first conductive layer, or include, for example, at least one suitable material among the materials constituting the first conductive layer. However, the present disclosure is not limited thereto.

[0127] The pixel circuit layer PCL may include a pixel circuit PXC, and a plurality of electrodes and a plurality of lines electrically connected to the pixel circuit PXC. For example, the pixel circuit layer PCL may include a bottom metal pattern BML, a transistor T, a connection electrode CCE, a second power line PL2, a first conductive pattern CP1, a second conductive pattern CP2, and a bridge pattern BRP, but the present disclosure is not limited thereto.

[0128] The bottom metal pattern BML may block light introduced into the pixel circuit PXC from the second surface SF2 of the substrate SUB. The bottom metal pattern BML may be a first conductive layer disposed between the substrate SUB and the buffer layer BFL. In some embodiments, the bottom metal pattern BML may be electrically connected to the transistor T. The driving range of the voltage (e.g., a predetermined voltage) supplied to the gate electrode GE of the transistor T may be widened. In the case where the bottom metal pattern BML is electrically connected to the transistor T, the channel region of the transistor T may be stabilized. When the bottom metal pattern BML is electrically connected to the transistor T, floating of the bottom metal pattern BML may be prevented or substantially prevented.

[0129] The transistor T may include a semiconductor pattern and a gate electrode GE overlapping a region of the semiconductor pattern. The transistor T may be, for example, a reference Figure 3 A first transistor T1 is described.

[0130] The semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include a channel region CHA, a first terminal TE1, and a second terminal TE2. In an embodiment, the first terminal TE1 and the second terminal TE2 may become conductors by annealing (or doping with high concentration impurities) the semiconductor pattern. For example, the semiconductor pattern may include polycrystalline silicon, single crystal silicon, low temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor. In another example, the semiconductor pattern may include a first active layer and a second active layer disposed in different layers. The first active layer may include polycrystalline silicon, single crystal silicon, low temperature polycrystalline silicon, or amorphous silicon, and the second active layer may include an oxide semiconductor.

[0131] The gate electrode GE may be disposed on the first gate insulating layer GI1. The gate electrode GE may be a second conductive layer disposed between the first gate insulating layer GI1 and the second gate insulating layer GI2. The gate electrode GE may overlap with the channel region CHA of the semiconductor pattern. The first gate insulating layer GI1 disposed between the semiconductor pattern and the gate electrode GE may insulate the channel region CHA of the semiconductor pattern and the gate electrode GE from each other.

[0132] The second conductive layer including the gate electrode GE may be configured as a single layer or a multi-layer. The second gate insulating layer GI2 may be disposed on the second conductive layer described above.

[0133] An interlayer insulating layer ILD may be disposed on the second gate insulating layer GI2 .

[0134] The connection electrode CCE may be disposed on the interlayer insulating layer ILD. The connection electrode CCE may be a third conductive layer located between the interlayer insulating layer ILD and the first via layer VIA1. The connection electrode CCE may be connected to the second terminal TE2 of the transistor T while passing through a contact hole of each of the interlayer insulating layer ILD, the second gate insulating layer GI2, and the first gate insulating layer GI1.

[0135] The second power line PL2 may be disposed on the interlayer insulating layer ILD. The second power line PL2 may be disposed on the interlayer insulating layer ILD to be spaced apart from the connection electrode CCE and configured as a third conductive layer.

[0136] The third conductive layer including the connection electrode CCE and the second power line PL2 may be configured as a single layer or a multi-layer.

[0137] The first via layer VIA1 may be disposed on the third conductive layer. The first via layer VIA1 may planarize a top of the third conductive layer.

[0138] The first passivation layer PAS1 may be disposed on the first via layer VIA1 .

[0139] The first and second conductive patterns CP1 and CP2 may be disposed on the first passivation layer PAS1. The first and second conductive patterns CP1 and CP2 may be a fourth conductive layer between the first passivation layer PAS1 and the second via layer VIA2.

[0140] The first conductive pattern CP1 may be electrically insulated from the second electrode EL2, the fourth electrode EL4, and the common line COL, except when a repair is performed when the light emitting element LD is connected to the first electrode EL1 and the second electrode EL2 in a reverse direction. The second conductive pattern CP2 may be electrically insulated from the first electrode EL1 and the third electrode EL3, except when a repair is performed when the light emitting element LD is connected to the first electrode EL1 and the second electrode EL2 in a reverse direction.

[0141] The fourth conductive layer including the first conductive pattern CP1 and the second conductive pattern CP2 may be configured as a single layer or a multi-layer.

[0142] The second via layer VIA2 may be disposed on the fourth conductive layer. The second via layer VIA2 may planarize a top of the fourth conductive layer.

[0143] The second passivation layer PAS2 may be disposed on the second via layer VIA2 .

[0144] The bridge pattern BRP may be disposed on the second passivation layer PAS2. The bridge pattern BRP may be a fifth conductive layer located between the second passivation layer PAS2 and the third via layer VIA3. The bridge pattern BRP may be electrically connected to the connection electrode CCE while passing through a contact hole of each of the second passivation layer PAS2, the second via layer VIA2, the first passivation layer PAS1, and the first via layer VIA1. The bridge pattern BRP may be electrically connected to the transistor T through the connection electrode CCE. The fifth conductive layer including the bridge pattern BRP may be configured as a single layer or multiple layers.

[0145] In addition, the first power line PL1 to which the voltage of the first driving power source VDD is applied may be disposed in the pixel circuit layer PCL. In an embodiment, the first power line PL1 may be located in the same layer as the second power line PL2, but the present disclosure is not limited thereto.

[0146] In the above-described embodiments, it has been described that the first conductive pattern CP1 and the second conductive pattern CP2 are disposed on the first passivation layer PAS1. However, the present disclosure is not limited thereto. The first conductive pattern CP1 and the second conductive pattern CP2 may be disposed on at least one insulating layer among the insulating layers included in the pixel circuit layer PCL. The first conductive pattern CP1 and the second conductive pattern CP2 may be disposed in the same layer, but the present disclosure is not limited thereto. In some embodiments, the first conductive pattern CP1 and the second conductive pattern CP2 may be disposed in different layers.

[0147] In an embodiment, the third via layer VIA3 may be entirely disposed on the fifth conductive layer described above. The third via layer VIA3 may planarize a top end of the fifth conductive layer. In an embodiment, the third via layer VIA3 may include a first contact hole CH1 exposing a portion of the bridge pattern BRP.

[0148] The sixth conductive layer may be disposed on the pixel circuit layer PCL having the configuration described above. The sixth conductive layer may include a first electrode EL1, a second electrode EL2, a third electrode EL3, a fourth electrode EL4, and a common line COL disposed on the third via layer VIA3 of the pixel circuit layer PCL. The sixth conductive layer may include, for example, an appropriate material among those described as materials constituting the first conductive layer, and may be configured as a single layer or multiple layers.

[0149] The first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 may be arranged on the third via layer VIA3 to be spaced apart from each other. In an embodiment, the first electrode EL1 and the third electrode EL3 may be integrally formed to be electrically connected to each other. In an embodiment, the second electrode EL2 and the fourth electrode EL4 may be integrally formed to be electrically connected to each other. The second electrode EL2 and the fourth electrode EL4 may be branched from the common line COL. In an embodiment, the second electrode EL2, the fourth electrode EL4, and the common line COL may be integrally formed to be electrically connected to each other.

[0150] In an embodiment, the first electrode EL1 may include four first sub-electrodes, and the second electrode EL2 may include four second sub-electrodes. For example, the first electrode EL1 may include a 1-1st sub-electrode SUE1_1, a 1-2nd sub-electrode SUE1_2, a 1-3rd sub-electrode SUE1_3, and a 1-4th sub-electrode SUE1_4. The second electrode EL2 may include a 2-1st sub-electrode SUE2_1, a 2-2nd sub-electrode SUE2_2, a 2-3rd sub-electrode SUE2_3, and a 2-4th sub-electrode SUE2_4.

[0151] The 1st-3rd sub-electrode SUE1_3 of the first electrode EL1 may be electrically connected to the first conductive pattern CP1 through the first contact portion CNT1 passing through the third via layer VIA3, the second passivation layer PAS2, and the second via layer VIA2. The 2nd-2nd sub-electrode SUE2_2 of the second electrode EL2 may be electrically connected to the second conductive pattern CP2 through the second contact portion CNT2 passing through the third via layer VIA3, the second passivation layer PAS2, and the second via layer VIA2.

[0152] The third electrode EL3 may be electrically connected to a portion of the pixel circuit layer PCL, for example, the transistor T, through the first contact hole CH1 of the third via layer VIA3.

[0153] The common line COL may be electrically connected to the second power line PL2 through a second contact hole CH2 passing through the third via layer VIA3 , the second passivation layer PAS2 , the second via layer VIA2 , the first passivation layer PAS1 , and the first via layer VIA1 .

[0154] In the above-described embodiments, the first electrode EL1 (or the first sub-electrode) may be an anode electrode electrically connected to the first end portion EP1 of the light emitting element LD, and the second electrode EL2 (or the second sub-electrode) may be a cathode electrode electrically connected to the second end portion EP2 of the light emitting element LD. In some embodiments, each of the first electrode EL1 and the second electrode EL2 may be a bonding electrode bonded to the light emitting element LD. Each of the first electrode EL1 and the second electrode EL2 may be bonded to the bonding electrode of the light emitting element LD, thereby electrically connecting the light emitting element LD and the pixel circuit PXC to each other.

[0155] In an implementation, the first electrode EL1 , the second electrode EL2 , the third electrode EL3 , the fourth electrode EL4 , and the common line COL may be formed in the same layer through the same process and include the same material.

[0156] The sixth conductive layer including the first electrode EL1, the second electrode EL2, the third electrode EL3, the fourth electrode EL4 and the common line COL may be located on the third via layer VIA3 and may be formed of a conductive material having a reflectivity that allows the light emitted from the light emitting element LD to advance in the image display direction (or forward direction) of the display device DD. In an embodiment, the conductive material may include an opaque metal that is suitable for reflecting the light emitted from the light emitting element LD in the image display direction (or desired direction) of the display device DD. The opaque material may include any one of metals such as silver, magnesium, aluminum, platinum, palladium, gold, nickel, neodymium, iridium, chromium, titanium and alloys thereof. In some embodiments, the sixth conductive layer may include a transparent conductive material (or substance). The transparent conductive material (or substance) may include any one of a conductive oxide (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO) or indium tin zinc oxide (ITZO)), a conductive polymer (such as poly (3,4-ethylenedioxythiophene) (PEDOT)), etc. In the case where the sixth conductive layer includes a transparent conductive material (or substance), a separate conductive layer formed of an opaque metal may be added for reflecting light emitted from the light emitting element LD in the image display direction of the display device DD. However, the material of the sixth conductive layer is not limited to the materials described above.

[0157] The sixth conductive layer may be formed as a single layer and / or multiple layers, but the present disclosure is not limited thereto. In some embodiments, the sixth conductive layer may be configured and / or formed as a multilayer in which at least two materials among metals, alloys, conductive oxides, and conductive polymers are stacked. The sixth conductive layer may be formed as a multilayer including at least two layers.

[0158] Reference Figures 7 to 9The sub-pixel SPX (or pixel PXL) including the light emitting element LD coupled to the first electrode EL1 and the second electrode EL2 is described in more detail.

[0159] Figure 7 It is shown in Figure 4 Schematic plan view of a state in which the light emitting element LD is transferred in the sub-pixel SPX shown in FIG. Figure 8 It is along Figure 7 A schematic cross-sectional view taken along line IV-IV' shown in FIG. Fig. 9 It is shown Figure 8 A schematic cross-sectional view of a light emitting element LD shown in FIG.

[0160] about Figures 7 to 9 The embodiment shown in FIG. 1 will mainly describe portions different from those of the embodiment described above to avoid redundancy.

[0161] refer to Figures 7 to 9 , the sub-pixel SPX (or pixel PXL) may include a substrate SUB, a pixel circuit layer PCL and a display element layer DPL.

[0162] The pixel circuit layer PCL may include a transistor T, a first conductive pattern CP1 , a second conductive pattern CP2 , and the like.

[0163] The display element layer DPL may include first to fourth electrodes EL1 to EL4, a common line COL, and a light emitting element LD. The sub-pixel SPX may include an emission area EMA in which light is emitted from the light emitting element LD and a non-emission area NEA located at the periphery of the emission area EMA. No light is emitted in the non-emission area NEA.

[0164] The first electrode EL1 to the fourth electrode EL4 may be disposed on the third via layer VIA3 of the pixel circuit layer PCL to be spaced apart from each other. The first electrode EL1 and the third electrode EL3 may be electrically connected to each other. The second electrode EL2, the fourth electrode EL4, and the common line COL may be electrically connected to each other. The first electrode EL1 may include a 1-1st sub-electrode SUE1_1 to a 1-4th sub-electrode SUE1_4, and the second electrode EL2 may include a 2-1st sub-electrode SUE2_1 to a 2-4th sub-electrode SUE2_4.

[0165] The common line COL may be provided in a form in which the common line COL surrounds the first to fourth electrodes EL1 to EL4 in a plan view and is electrically connected to the second power line PL2 through the second contact hole CH2 .

[0166] The light emitting element LD may be coupled to each of the first electrode EL1 and the second electrode EL2. The light emitting element LD may include a semiconductor structure 10, a first contact electrode 15, and a second contact electrode 16. In an embodiment, the semiconductor structure 10 may be formed by sequentially forming a first semiconductor layer 11, an active layer 12, and a second semiconductor layer 13 and then performing mesh etching, but the present disclosure is not limited thereto. The first contact electrode 15 and the second contact electrode 16 may be sequentially formed on the semiconductor structure 10, thereby forming the light emitting element LD in a package form. However, the present disclosure is not limited thereto.

[0167] Each of the length of the light emitting element LD in the longitudinal direction, the length of the light emitting element LD in the lateral direction, and the length of the light emitting element LD in the thickness direction may be several micrometers to hundreds of micrometers (μm).

[0168] In an embodiment, the light emitting element LD may be formed by growing on a semiconductor substrate such as a silicon wafer. The light emitting element LD may be directly transferred from the silicon wafer to the first electrode EL1 and the second electrode EL2 of the display element layer DPL. In another embodiment, the light emitting element LD may be transferred to the first electrode EL1 and the second electrode EL2 of the display element layer DPL by an electrostatic process using an electrostatic head or a stamping process using a polymer material having elasticity such as PDMS or silicon as a transfer substrate.

[0169] In an embodiment, the light emitting element LD may include a first end portion EP1 in contact with the first electrode EL1 (or the first sub-electrode) and a second end portion EP2 in contact with the second electrode EL2 (or the second sub-electrode). The light emitting element LD may include a light emitting element (or a light emitting diode) having a horizontal structure, and the first end portion EP1 and the second end portion EP2 thereof are located on the same plane. The second contact electrode 16 electrically connected to the second semiconductor layer 13 may be located at the first end portion EP1, and the first contact electrode 15 electrically connected to the first semiconductor layer 11 may be located at the second end portion EP2.

[0170] In an embodiment, in a plan view, the light emitting element LD may be disposed only on the first electrode EL1 and the second electrode EL2 located between the third electrode EL3 and the fourth electrode EL4. The first end portion EP1 of the light emitting element LD may be disposed on the first electrode EL1 (or the first sub-electrode) to be electrically connected to the first electrode EL1, and the second end portion EP2 of the light emitting element LD may be disposed on the second electrode EL2 (or the second sub-electrode) to be electrically connected to the second electrode EL2. The light emitting element LD is not disposed on the third electrode EL3 and the fourth electrode EL4, and may not overlap the third electrode EL3 and the fourth electrode EL4.

[0171] The semiconductor structure 10 may emit light when electrons and holes are recombined according to current flowing between the first contact electrode 15 and the second contact electrode 16. The semiconductor structure 10 may include a first semiconductor layer 11, an active layer 12, and a second semiconductor layer 13.

[0172] The first semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For example, the first semiconductor layer 11 may include at least one semiconductor material among InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and is an n-type semiconductor layer doped with a first conductive dopant (or n-type dopant) such as Si, Ge, or Sn. However, the material constituting the first semiconductor layer 11 is not limited thereto. In addition, the first semiconductor layer 11 may be configured with various materials. In an embodiment, the first semiconductor layer 11 may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or n-type dopant).

[0173] The active layer 12 (or light emitting layer) may be disposed on a portion of the surface of the first semiconductor layer 11. The active layer 12 may include a material having a single quantum well structure or a multiple quantum well structure. In the case where the active layer 12 may include a material having a multiple quantum well structure, the active layer 12 may have a structure in which a plurality of well layers and a plurality of barrier layers are alternately stacked. The well layer may be formed of InGaN, and the barrier layer may be formed of GaN or AlGaN. However, the present disclosure is not limited thereto. In another embodiment, the active layer 12 may be in a structure in which a semiconductor material having a high energy band gap and a semiconductor material having a low energy band gap are alternately stacked, and includes Group III to Group V semiconductor materials according to the wavelength band of the emitted light. The active layer 12 may include a first surface in contact with the first semiconductor layer 11 and a second surface in contact with the second semiconductor layer 13.

[0174] The second semiconductor layer 13 may be disposed on the surface of the active layer 12 and provide holes to the active layer 12. The second semiconductor layer 13 may include a semiconductor layer of a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 may include at least one semiconductor material among InAlGaN, GaN, AlGaN, InGaN, AlN and InN, and include a p-type semiconductor layer doped with a second conductive dopant (or p-type dopant), such as Mg, Zn, Ca, Sr or Ba. However, the material constituting the second semiconductor layer 13 is not limited thereto. In addition, the second semiconductor layer 13 may be configured with various materials. In an embodiment, the second semiconductor layer 13 may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or p-type dopant).

[0175] The first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 described above may be arranged in a structure in which the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 are sequentially stacked on a semiconductor substrate. The semiconductor substrate may include a semiconductor material, such as a sapphire substrate or a silicon substrate. The semiconductor substrate may be used as a substrate for growth, which is used to grow each of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, and then separated from the first semiconductor layer 11 by a substrate separation process. The substrate separation process may be laser lift-off (LLO), chemical lift-off (CLO), etc. Therefore, when the semiconductor substrate for growth is removed from the semiconductor structure 10, the semiconductor structure 10 may have a thin thickness. For example, the semiconductor structure 10 described above may have a small size of microscale (or micrometer), but the present disclosure is not limited thereto.

[0176] The first contact electrode 15 may be disposed and / or formed on the semiconductor structure 10. For example, the first contact electrode 15 may be disposed and / or formed on the first semiconductor layer 11 to be electrically separated (or electrically disconnected) from the active layer 12 and the second semiconductor layer 13. The first contact electrode 15 may be in ohmic contact with the first semiconductor layer 11. In an embodiment, the first contact electrode 15 may be located at the second end portion EP2 (or n-type end portion) of the light emitting element LD and contact the second bonding electrode BDE2 for bonding.

[0177] The second contact electrode 16 may be disposed and / or formed on the semiconductor structure 10. For example, the second contact electrode 16 may be disposed and / or formed on the second semiconductor layer 13. The second contact electrode 16 may be in ohmic contact with the second semiconductor layer 13. In an embodiment, the second contact electrode 16 may be located at the first end portion EP1 (or p-type end portion) of the light emitting element LD and contact the first bonding electrode BDE1 for bonding.

[0178] The first contact electrode 15 and the second contact electrode 16 may include a conductive material. For example, the first contact electrode 15 and the second contact electrode 16 may include an opaque metal using any one or a mixture of chromium, titanium, aluminum, gold, nickel, and any oxide or alloy thereof, but the present disclosure is not limited thereto. In some embodiments, the first contact electrode 15 and the second contact electrode 16 may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), or indium tin zinc oxide (ITZO). In some embodiments, the first contact electrode 15 and the second contact electrode 16 may be a solder bump.

[0179] In some embodiments, the light emitting element LD may further include an insulating film around the outer peripheral surface of the semiconductor structure 10 (eg, surrounding the outer peripheral surface of the semiconductor structure 10 ).

[0180] The light emitting element LD may be coupled to each of the first electrode EL1 and the second electrode EL2 via a coupling electrode. For example, the first end portion EP1 (or the p-type end portion) of the light emitting element LD may be coupled to the first electrode EL1 (or the first sub-electrode) via the first coupling electrode BDE1, and the second end portion EP2 (or the n-type end portion) of the light emitting element LD may be coupled to the second electrode EL2 (or the second sub-electrode) via the second coupling electrode BDE2. In an embodiment, each of the first coupling electrode BDE1 and the second coupling electrode BDE2 may be selected from gold, tin, and the like, which have excellent coupling strength (or bonding strength) to promote the generation and growth of intermetallic compounds. However, the present disclosure is not limited thereto. In some embodiments, the first coupling electrode BDE1 and the second coupling electrode BDE2 may be omitted.

[0181] The light emitting element LD may be disposed on the third via layer VIA3 such that the first end portion EP1 of the light emitting element LD (or the first combined electrode BDE1) is located on the first electrode EL1, and the second end portion EP2 of the light emitting element LD (or the second combined electrode BDE2) is located on the second electrode EL2. After the light emitting element LD transferred to the transfer base by the transfer device moves to the top of the first electrode EL1 and the second electrode EL2, the light emitting element LD may be re-transferred to the first electrode EL1 and the second electrode EL2.

[0182] In the case where the first end portion EP1 (or p-type end portion) of the light emitting element LD is electrically connected to the first electrode EL1 and the second end portion EP2 (or n-type end portion) of the light emitting element LD is electrically connected to the second electrode EL2, the light emitting element LD may be connected between the first electrode EL1 and the second electrode EL2 in a forward direction. In the case where a driving current flows from the first power line PL1 to the second power line PL2 through the transistor T, the driving current may flow into the third electrode EL3 and the first electrode EL1 electrically connected to the third electrode EL3 via the first contact hole CH1. Therefore, the light emitting element LD may emit light having a brightness corresponding to the driving current.

[0183] In an embodiment, since the first electrode EL1 electrically connected to the first end portion EP1 of the light emitting element LD (or the first combined electrode BDE1) while being in contact with the first end portion EP1 of the light emitting element LD includes a plurality of first sub-electrodes, and the second electrode EL2 electrically connected to the second end portion EP2 of the light emitting element LD (or the second combined electrode BDE2) while being in contact with the second end portion EP2 of the light emitting element LD includes a plurality of second sub-electrodes, a current path through which current flows in a direction from the first electrode EL1 to the second electrode EL2 can be set in plurality. Therefore, although the first end portion EP1 of the light emitting element LD is in contact with at least some of the first sub-electrodes, and the second end portion EP2 of the light emitting element LD is in contact with at least some of the second sub-electrodes, each end portion of the light emitting element LD and the corresponding electrode can be stably electrically connected to each other. Therefore, the reliability of the sub-pixel SPX (or the display device DD) can be improved.

[0184] After the light emitting element LD is transferred to the first electrode EL1 and the second electrode EL2, a light emitting test may be performed on the light emitting element LD. In the absence of any defects in the light emitting element LD, the sub-pixel SPX (or the display device DD) may be completed. However, in the case where the sub-pixel SPX becomes black due to the light emitting element LD not emitting light in the light emitting test described above, a repair process may be performed according to the type of defect of the light emitting element LD. For example, in the case where a dark spot defect occurs in the sub-pixel SPX when the light emitting element LD is connected between the first electrode EL1 and the second electrode EL2 in a reverse direction due to equipment conditions (e.g., alignment accuracy), the atmosphere of the environment in the equipment, etc. in the process of transferring the light emitting element LD to the first electrode EL1 and the second electrode EL2, a repair may be performed by changing the current direction of the sub-pixel SPX to a direction opposite to the current direction to allow current to flow through the light emitting element LD connected in the reverse direction. Reference will be made later to Figures 11 to 15B Repair of light emitting elements connected in the reverse direction is described in further detail.

[0185] Fig.10 The sub-pixel SPX according to the embodiment of the present disclosure is shown and is Figure 7 The schematic cross-sectional view corresponding to the line IV-IV' shown in FIG.

[0186] about Fig.10 The embodiment shown in FIG. 1 will mainly describe portions different from those of the embodiment described above to avoid redundancy.

[0187] refer to Figure 7 and Fig.10 , the sub-pixel SPX may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL and an overcoat layer OC.

[0188] The pixel circuit layer PCL may be located on the first surface SF1 of the substrate SUB and include a transistor T, a first conductive pattern CP1, and a second conductive pattern CP2.

[0189] The display element layer DPL may be located on the pixel circuit layer PCL, and include first to fourth electrodes EL1 to EL4 , a common line COL, a light emitting element LD, a cover layer CVL, and an optical layer OTL.

[0190] The cover layer CVL may be disposed on the sixth conductive layer including the first electrode EL1 to the fourth electrode EL4 and the common line COL and the light emitting element LD to cover the sixth conductive layer and the light emitting element LD. The cover layer CVL may be a packaging substrate or a packaging film formed as a multilayer. The cover layer CVL may prevent or substantially prevent external oxygen, external moisture, etc. from being introduced into the light emitting element LD and the pixel circuit layer PCL. In some embodiments, the cover layer CVL may be a planarization layer for reducing a step difference caused by a component disposed thereunder.

[0191] The optical layer OTL may be disposed on the cover layer CVL.

[0192] The optical layer OTL may convert the light emitted from the light emitting element LD into light having excellent color reproducibility, and then emit the converted light, thereby improving the luminous efficiency of each sub-pixel SPX (or each pixel PXL). The optical layer OTL may include a color filter layer including a color filter and a light blocking pattern. In some embodiments, the optical layer OTL may further include a color conversion layer including color conversion particles for converting the light emitted from the light emitting element LD into light of a specific color (or light having excellent color reproducibility).

[0193] The overcoat layer OC may be disposed on the optical layer OTL. The overcoat layer OC may cover the lower member including the optical layer OTL. The overcoat layer OC may protect the above-described lower member from foreign substances such as dust.

[0194] Fig.11 A sub-pixel SPX including a defective light emitting element LD′ is shown, and corresponds to Figure 7 Schematic cross-sectional view along line IV-IV' shown in FIG. Fig.12 and Fig.13 It shows the repair Fig.11 Schematic plan view of a method for producing a defective light emitting element LD′ shown in FIG. Fig.14A It is along Fig.13 A schematic cross-sectional view taken along line V-V' shown in FIG. Fig. 14B yes Fig.14A Schematic enlarged cross-sectional view of area “ EA1 ” shown in . Fig.15A It is along Fig.13 A schematic cross-sectional view taken along line VI-VI' shown in FIG. Fig. 15B yes Fig.15A A schematic enlarged cross-sectional view of the area “EA2” shown in FIG.

[0195] refer to Figure 7 and Figures 11 to 15B , the sub-pixel SPX (or the pixel PXL) may include a defective light emitting element LD' connected in a reverse direction between the first electrode EL1 and the second electrode EL2.

[0196] The defective light emitting element LD' may be as in the reference Figures 7 to 9 Described is a reverse light emitting element whose alignment direction is defective in a process of transferring a light emitting element LD onto a first electrode EL1 and a second electrode EL2, wherein a first end portion EP1 (or a first combined electrode BDE1) of the defective light emitting element LD' is electrically connected to the second electrode EL2 while in contact with the second electrode EL2, and a second end portion EP2 (or a second combined electrode BDE2) of the defective light emitting element LD' is electrically connected to the first electrode EL1 while in contact with the first electrode EL1. The defective light emitting element LD' is connected between the first electrode EL1 and the second electrode EL2 in a direction opposite to the alignment direction of the light emitting element LD, and the defective light emitting element LD' remains in an inactive state even when a specific driving voltage (e.g., a predetermined driving voltage) is applied between the first electrode EL1 and the second electrode EL2 (e.g., a driving voltage is applied in a forward direction), whereby any current does not substantially flow.

[0197] The sub-pixel SPX including the defective light emitting element LD' described above may become black, and a repair process for solving such a dark spot defect may be performed. For example, in the repair process, each of the electrical connection between the first electrode EL1 and the third electrode EL3 and the electrical connection between the second electrode EL2 and the fourth electrode EL4 may be cut using, for example, a laser, and by performing a bonding process using a laser, the corresponding electrodes and the corresponding conductive patterns may be electrically connected to each other.

[0198] like Fig.12As shown in , a laser may be used to remove a portion of the first connection line CNL1 in the first electrode separation area ESA1 between the first electrode EL1 (or a plurality of first sub-electrodes) and the third electrode EL3, thereby electrically separating the first electrode EL1 and the third electrode EL3 from each other. In addition, a laser may be used to remove a portion of the second electrode EL2 (or the second sub-electrode) in the second electrode separation area ESA2 between the second electrode EL2 (or the second sub-electrode) and the common line COL, thereby electrically separating the second electrode EL2 and the common line COL from each other. Therefore, the second electrode EL2 and the fourth electrode EL4 may be electrically disconnected from each other. The first electrode EL1 (or the first sub-electrode) electrically disconnected from the third electrode EL3 and the second electrode EL2 (or the second sub-electrode) electrically disconnected from the fourth electrode EL4 may be floated.

[0199] The first electrode EL1 electrically disconnected from the third electrode EL3 may be electrically connected to the first end (e.g., the "right end portion" in the plan view) of the first conductive pattern CP1 through the first contact portion CNT1. The second electrode EL2 electrically disconnected from the common line COL may be electrically connected to the first end (e.g., the "left end portion" in the plan view) of the second conductive pattern CP2 through the second contact portion CNT2.

[0200] As described above, after cutting the electrical connection between the electrodes using the laser, a process of electrically connecting the corresponding conductive patterns and the corresponding electrodes to each other through a laser bonding process may be performed. Fig.13 As shown in FIG, the third electrode EL3 and the second electrode EL2 may be electrically connected to each other through the second conductive pattern CP2, and the fourth electrode EL4 and the first electrode EL1 may be electrically connected to each other through the first conductive pattern CP1.

[0201] The laser bonding process performed after the first electrode EL1 and the third electrode EL3 are electrically disconnected from each other may mean a process in which a third contact portion CNT3 exposing the second end of the first conductive pattern CP1 is formed by strongly irradiating a laser onto the top of the fourth electrode EL4 overlapping the second end of the first conductive pattern CP1 (e.g., the "left end portion" on the plane) and then removing a portion of the insulating layer between the second end of the first conductive pattern CP1 and the fourth electrode EL4, so that the second end of the first conductive pattern CP1 and the fourth electrode EL4 are electrically connected to each other. In some embodiments, in the case where the first conductive pattern CP1 and the fourth electrode EL4 are formed of copper or gold, a laser bonding process using a laser having a wavelength of about 532nm or less may be performed. In the case where the first conductive pattern CP1 and the fourth electrode EL4 are formed of aluminum, a laser bonding process using a laser having a wavelength of about 750nm to about 900nm may be performed. In a plan view, the third contact portion CNT3 may be located in the first overlapping area OVA1, in which the second end of the first conductive pattern CP1 and the fourth electrode EL4 overlap each other.

[0202] In the case where the laser is irradiated on the top of the fourth electrode EL4 in the first overlapping area OVA1, the transmittance and / or absorptance of the laser beam may vary according to the material properties of each of the third via layer VIA3, the second passivation layer PAS2, and the second via layer VIA2 located between the first conductive pattern CP1 and the fourth electrode EL4. Therefore, the etching degree of each of the third via layer VIA3, the second passivation layer PAS2, and the second via layer VIA2 may vary. Therefore, the third contact portion CNT3 may have a Fig. 14B In addition, in some embodiments, a first groove portion HM1 may be formed at a second end of the first conductive pattern CP1 exposed by the third contact portion CNT3. The first groove portion HM1 may be formed when a portion of the first conductive pattern CP1 is melted from a surface (or upper surface) of the first conductive pattern CP1 in a direction opposite to the third direction DR3 by laser irradiated in a laser bonding process.

[0203] The third contact portion CNT3 can be formed when a portion of the insulating layer between the first conductive pattern CP1 and the fourth electrode EL4 is etched by the laser irradiated in the laser bonding process described above, and the first conductive pattern CP1 and the fourth electrode EL4 can be electrically connected to each other when the first conductive pattern CP1 and the fourth electrode EL4 are melted by the laser while the second end of the first conductive pattern CP1 is exposed to the outside through the third contact portion CNT3.

[0204] The laser bonding process performed after the second electrode EL2 and the common line COL are electrically disconnected from each other may mean a process in which a fourth contact portion CNT4 exposing the second end of the second conductive pattern CP2 is formed by strongly irradiating a laser onto the top of the third electrode EL3 overlapping the second end of the second conductive pattern CP2 (e.g., the "right end portion" on the plane) and then removing a portion of the insulating layer between the second end of the second conductive pattern CP2 and the third electrode EL3, so that the second end of the second conductive pattern CP2 and the third electrode EL3 are electrically connected to each other. In some embodiments, in the case where the second conductive pattern CP2 and the third electrode EL3 are formed of copper or gold, a laser bonding process using a laser having a wavelength of about 532nm or less may be performed. In the case where the second conductive pattern CP2 and the third electrode EL3 are formed of aluminum, a laser bonding process using a laser having a wavelength of about 750nm to about 900nm may be performed. In a plan view, the fourth contact portion CNT4 may be located in the second overlapping area OVA2, in which the second end of the second conductive pattern CP2 and the third electrode EL3 overlap each other.

[0205] In the case where the laser is irradiated on the top of the third electrode EL3 (or the first portion EL3a) in the second overlapping area OVA2, the transmittance and / or absorptance of the laser beam may vary according to the material properties of each of the third via layer VIA3, the second passivation layer PAS2, and the second via layer VIA2 located between the second conductive pattern CP2 and the third electrode EL3. Therefore, the etching degree of each of the third via layer VIA3, the second passivation layer PAS2, and the second via layer VIA2 may vary. Therefore, the fourth contact portion CNT4 may have a thickness of 0.04mm / s. Fig. 15B In addition, in some embodiments, a second groove portion HM2 may be formed at a second end of the second conductive pattern CP2 exposed by the fourth contact portion CNT4. The second groove portion HM2 may be formed when a portion of the second conductive pattern CP2 is melted from a surface (or upper surface) of the second conductive pattern CP2 in a direction opposite to the third direction DR3 by laser irradiated in a laser bonding process.

[0206] The fourth contact portion CNT4 can be formed when a portion of the insulating layer between the second conductive pattern CP2 and the third electrode EL3 is etched by the laser irradiated in the laser bonding process described above, and the second conductive pattern CP2 and the third electrode EL3 can be electrically connected to each other when the second conductive pattern CP2 and the third electrode EL3 are melted by the laser while the second end of the second conductive pattern CP2 is exposed to the outside through the fourth contact portion CNT4.

[0207] After performing the above-described laser bonding process, the third electrode EL3 may be electrically connected to the second end of the second conductive pattern CP2 through the fourth contact portion CNT4 , and the fourth electrode EL4 may be electrically connected to the second end of the first conductive pattern CP1 through the third contact portion CNT3 .

[0208] The first electrode EL1 (or the 1-3 sub-electrode SUE1_3) electrically connected to the first end of the first conductive pattern CP1 through the first contact portion CNT1 can be electrically connected to the fourth electrode EL4 through the first conductive pattern CP1. The second electrode EL2 (or the 2-2 sub-electrode SUE2_2) electrically connected to the first end of the second conductive pattern CP2 through the second contact portion CNT2 can be electrically connected to the third electrode EL3 through the second conductive pattern CP2. Therefore, the first electrode EL1 can be electrically connected to the second power line PL2 through the first conductive pattern CP1 and the fourth electrode EL4, and the second electrode EL2 can be electrically connected to the transistor T of the pixel circuit PXC through the second conductive pattern CP2 and the third electrode EL3. Therefore, current can flow between the second electrode EL2 and the first electrode EL1. Current can flow in the direction from the second electrode EL2 to the first electrode EL1 via the light emitting element LD. The second electrode EL2 can become an anode electrode, and the first electrode EL1 can become a cathode electrode. In this way, by repairing the sub-pixel SPX in which the dark spot defect occurs, the direction of the current flowing from the first electrode EL1 to the second electrode EL2 is changed to the direction from the second electrode EL2 to the first electrode EL1, so that the defective light-emitting element LD' can be connected between the second electrode EL2 and the first electrode EL1 in the forward direction. Therefore, the sub-pixel SPX in which the dark spot defect occurs is repaired by allowing the defective light-emitting element LD' to be driven as the light-emitting element LD, which is an effective light source, so that the reliability of the display device DD can be improved.

[0209] Generally, in the case where a dark spot defect occurs in the sub-pixel SPX due to a defective light emitting element LD' connected between the first electrode EL1 and the second electrode EL2 in a reverse direction, a repair process of removing the defective light emitting element LD' using a laser and then re-transferring another light emitting element LD on the first electrode EL1 and the second electrode EL2 is performed. The process of removing the defective light emitting element LD' and the process of re-transferring another light emitting element LD on the first electrode EL1 and the second electrode EL2 are added. Therefore, the manufacturing efficiency of the display device DD may be deteriorated, and the manufacturing cost of the display device DD may be increased due to unnecessary waste of the light emitting element LD.

[0210] In the above-described embodiment, after the light emitting element LD is transferred to the first electrode EL1 and the second electrode EL2, in the case where the light emitting element LD is determined to be a defective light emitting element LD' connected between the first electrode EL1 and the second electrode EL2 in the reverse direction, the electrical connection between the first electrode EL1 and the third electrode EL3 and the electrical connection between the second electrode EL2 and the fourth electrode EL4 are cut off, and the direction of the current flowing from the first electrode EL1 to the second electrode EL2 is changed to the direction from the second electrode EL2 to the first electrode EL1 using the first conductive pattern CP1 and the second conductive pattern CP2 provided under the first electrode EL1 to the fourth electrode EL4. Therefore, by allowing the defective light emitting element LD' to be driven as the light emitting element LD (which is an effective light source), the sub-pixel in which the dark spot defect occurs can be easily repaired. Therefore, in the above-described embodiment, the manufacturing efficiency of the display device DD can be improved, and the unnecessary waste of the light emitting element LD can be prevented or substantially prevented, thereby reducing the manufacturing cost of the display device.

[0211] In the display device and the repair method thereof according to the embodiment of the present disclosure, although a dark spot defect occurs in a sub-pixel, the sub-pixel can be easily repaired, thereby improving the reliability of the display device.

[0212] According to an embodiment of the present disclosure, without replacing a defective light-emitting element connected between electrodes in a reverse direction, a portion of the electrode is removed using a laser, and a conductive pattern under the electrode and the electrode are electrically connected to each other by performing a laser bonding process, so that the defective light-emitting element can be connected between the electrodes in a forward direction. Therefore, the defective light-emitting element is used as an effective light source, thereby preventing or substantially preventing the light-emitting element from being wasted unnecessarily, thereby reducing the manufacturing cost of the display device.

[0213] According to an embodiment of the present disclosure, a plurality of sub-electrodes electrically connected to each end portion of the light emitting element while being in contact with the end portion of the light emitting element are provided, thereby providing a plurality of current paths between the light emitting element and the sub-pixels, thereby improving the reliability of the display device.

[0214] Some exemplary embodiments have been disclosed herein, and although specific terms are used, they are used in a general and descriptive sense and will be interpreted in a general and descriptive sense, not for limiting purposes. In some cases, it will be apparent to one of ordinary skill in the art at the time of filing this application that, unless otherwise specifically indicated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A display device, comprising: substrate; a first conductive pattern and a second conductive pattern, the first conductive pattern and the second conductive pattern being spaced apart from each other on the substrate; a first electrode, a second electrode, a third electrode, and a fourth electrode, wherein the first electrode, the second electrode, the third electrode, and the fourth electrode are spaced apart from each other on the first conductive pattern and the second conductive pattern; as well as A light emitting element, on the first electrode and the second electrode, wherein the first electrode is electrically connected to the first conductive pattern, and the second electrode is electrically connected to the second conductive pattern, and wherein the first conductive pattern is electrically disconnected from the second electrode and the second conductive pattern, and The second conductive pattern is electrically disconnected from the first electrode and the first conductive pattern.

2. The display device according to claim 1, wherein: The first conductive pattern overlaps the first electrode, the second electrode, and the fourth electrode, and The second conductive pattern overlaps the first electrode, the second electrode, and the third electrode.

3. The display device according to claim 2, wherein: The first electrode and the third electrode are integrally formed to be electrically connected to each other, and The second electrode and the fourth electrode are integrally formed to be electrically connected to each other.

4. The display device according to claim 3, further comprising: a transistor, on the substrate, the transistor being electrically connected to the first electrode and the third electrode; a common line formed integrally with the second electrode and the fourth electrode on the substrate to be electrically connected to the second electrode and the fourth electrode; as well as A power line is provided on the substrate, the power line is electrically connected to the common line, and the power line is provided with a low potential voltage.

5. The display device according to claim 4, wherein: The first electrode includes two or more first sub-electrodes spaced apart from each other, and The second electrode includes two or more second sub-electrodes spaced apart from each other, and The first sub-electrodes are electrically connected to each other, and the second sub-electrodes are electrically connected to each other.

6. The display device according to claim 5, further comprising: a first connection line, on the first conductive pattern and the second conductive pattern, the first connection line being integrally formed with the first sub-electrode to be electrically connected to the first sub-electrode; as well as A second connection line is formed on the first conductive pattern and the second conductive pattern, the second connection line being integrally formed with the second sub-electrode to be electrically connected to the second sub-electrode.

7. The display device according to claim 6, wherein: The first conductive pattern is electrically connected to at least one of the first sub-electrodes, and The second conductive pattern is electrically connected to at least one of the second sub-electrodes.

8. The display device according to claim 7, further comprising an insulating layer between the first conductive pattern and the second conductive pattern and the first to fourth electrodes, the insulating layer comprising a first contact portion exposing one end of the first conductive pattern and a second contact portion exposing one end of the second conductive pattern, in, At least one of the first sub-electrodes is electrically connected to the first conductive pattern through the first contact portion, and At least one of the second sub-electrodes is electrically connected to the second conductive pattern through the second contact portion.

9. The display device according to claim 5, wherein: The light emitting element has a horizontal type structure including a first end portion and a second end portion located on the same plane, and Wherein, the light emitting element comprises: A semiconductor structure comprising a first semiconductor layer, an active layer on the first semiconductor layer, and a second semiconductor layer on the active layer; a first contact electrode on the semiconductor structure, the first contact electrode being electrically connected to the first semiconductor layer, the first contact electrode being located at the second end portion; and A second contact electrode is spaced apart from the first contact electrode on the semiconductor structure, the second contact electrode is electrically connected to the second semiconductor layer, and the second contact electrode is located at the first end portion.

10. The display device according to claim 9, wherein: The first semiconductor layer includes an n-type semiconductor layer doped with an n-type dopant, and the second semiconductor layer includes a p-type semiconductor layer doped with a p-type dopant.

11. The display device according to claim 10, wherein: The first end portion of the light emitting element is electrically connected to the first sub-electrode, and The second end portion of the light emitting element is electrically connected to the second sub-electrode.

12. The display device according to claim 11, wherein: The first electrode is an anode electrode, and the second electrode is a cathode electrode.

13. A display device comprising: substrate; a first conductive pattern and a second conductive pattern, the first conductive pattern and the second conductive pattern being spaced apart from each other on the substrate; an insulating layer, on the first conductive pattern and the second conductive pattern, the insulating layer comprising a first contact portion exposing a first end of the first conductive pattern, a second contact portion exposing a first end of the second conductive pattern, a third contact portion exposing a second end of the first conductive pattern, and a fourth contact portion exposing a second end of the second conductive pattern; a first electrode, on the insulating layer, the first electrode comprising two or more first sub-electrodes; a second electrode, on the insulating layer, the second electrode comprising two or more second sub-electrodes; a third electrode spaced apart from the first electrode and the second electrode; a fourth electrode, spaced apart from the first electrode to the third electrode; as well as A light emitting element, on the first electrode and the second electrode, wherein at least one of the first sub-electrodes is electrically connected to the first end of the first conductive pattern through the first contact portion, and the fourth electrode is electrically connected to the second end of the first conductive pattern through the third contact portion, and At least one of the second sub-electrodes is electrically connected to the first end of the second conductive pattern through the second contact portion, and the third electrode is electrically connected to the second end of the second conductive pattern through the fourth contact portion.

14. The display device according to claim 13, wherein: The light emitting element includes a first end portion and a second end portion located on the same plane, wherein the first end portion is electrically connected to the second sub-electrode, and the second end portion is electrically connected to the first sub-electrode, and Wherein, a p-type semiconductor layer is located at the first end portion, and an n-type semiconductor layer is located at the second end portion.

15. The display device according to claim 14, further comprising: a transistor, on the substrate, the transistor being electrically connected to the third electrode; a common line, on the substrate, the common line being integrally formed with the fourth electrode to be electrically connected to the fourth electrode; as well as a power line on the substrate, the power line being electrically connected to the common line, the power line being provided with a low potential voltage, wherein the first sub-electrode is electrically connected to the fourth electrode through the first conductive pattern, and The second sub-electrode is electrically connected to the third electrode through the second conductive pattern.

16. The display device according to claim 15, wherein: The first sub-electrode is electrically disconnected from the third electrode, and the second sub-electrode is electrically disconnected from the fourth electrode.

17. The display device according to claim 15, wherein: The first sub-electrode corresponds to a cathode electrode, and the second sub-electrode corresponds to an anode electrode.

18. Method for repairing a display device, in, The display device comprises: substrate; a first conductive pattern and a second conductive pattern, the first conductive pattern and the second conductive pattern being spaced apart from each other on the substrate; a first electrode on the first conductive pattern and the second conductive pattern, the first electrode including two or more first sub-electrodes, the first electrode being electrically connected to a first end of the first conductive pattern; a second electrode on the first conductive pattern and the second conductive pattern, the second electrode comprising two or more second sub-electrodes, the second electrode being electrically connected to a first end of the second conductive pattern; a third electrode, on the second conductive pattern, the third electrode being electrically connected to the first sub-electrode, and the third electrode overlapping the second end of the second conductive pattern; a fourth electrode on the first conductive pattern, the fourth electrode being electrically connected to the second sub-electrode, the fourth electrode overlapping the second end of the first conductive pattern; and A light emitting element is electrically connected to the first sub-electrode and the second sub-electrode, and the method includes: In a case where the light emitting element is a defective light emitting element, electrically disconnecting the first sub-electrode and the third electrode from each other and electrically disconnecting the second sub-electrode and the fourth electrode using laser; and The second end of the first conductive pattern and the fourth electrode are electrically connected to each other by irradiating laser onto the top of the overlapping area of ​​the first conductive pattern and the fourth electrode and then removing a portion of the insulating layer between the first conductive pattern and the fourth electrode, and the second end of the second conductive pattern and the third electrode are electrically connected to each other by irradiating laser onto the top of the overlapping area of ​​the second conductive pattern and the third electrode and then removing another portion of the insulating layer between the second conductive pattern and the third electrode.

19. The method according to claim 18, wherein: The defective light emitting element includes a first end portion and a second end portion located on the same plane, wherein the first end portion is electrically connected to the second sub-electrode and the fourth electrode, and the second end portion is electrically connected to the first sub-electrode and the third electrode, and Wherein, a p-type semiconductor layer is located at the first end portion, and an n-type semiconductor layer is located at the second end portion.

20. The method according to claim 18, wherein: The display device further includes: a transistor, on the substrate, the transistor being electrically connected to the third electrode; a common line formed integrally with the fourth electrode on the substrate to be electrically connected to the fourth electrode; and a power line on the substrate, the power line being electrically connected to the common line, the power line being provided with a low potential voltage, wherein the first sub-electrode is electrically connected to the fourth electrode through the first conductive pattern, and The second sub-electrode is electrically connected to the third electrode through the second conductive pattern.

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