Amplification circuit and communication device

Abstract

The amplifier circuit (1) receives a plurality of discrete power supply voltages. A peak amplifier (22); a synthesis circuit (40) that synthesizes a high-frequency signal output from the carrier amplifier (12) and a high-frequency signal output from the peak amplifier (22); a bias circuit (50) that supplies a first bias current to the peak amplifier (22); and digital control terminals (140, 150) that receive a digital control signal based on an envelope signal. And a switch (23) that is connected to the digital control terminals (140, 150) and that switches between the connection and disconnection of the bias circuit (50) and the peak amplifier (22). The carrier amplifier (12) and the peak amplifier (22) each include a plurality of amplification elements that are cascode-connected.

Description

Technical Field

[0001] The invention relates to an amplifier circuit and a communication device. Background Art

[0002] In recent years, the efficiency (power added efficiency) has been improved by applying envelope tracking (ET) to power amplifier circuits. A digital ET technology for supplying a power supply voltage having a plurality of discrete voltage levels in an ET system has been disclosed.

[0003] Patent Document 1 discloses a power supply modulation circuit (envelope tracking system) that supplies a power supply voltage to an amplifier circuit based on an envelope signal. The power supply modulation circuit includes a switched capacitor circuit that generates a plurality of voltages having different voltage levels, and an output switch circuit that selects and outputs at least one of the plurality of voltages.

[0004] Prior Art Literature

[0005] Patent Literature

[0006] Patent Document 1: U.S. Patent No. 9755672 Summary of the invention

[0007] Problem that the invention aims to solve

[0008] However, when a high-frequency signal is amplified by an amplifier circuit using the digital ET disclosed in Patent Document 1, it is assumed that the efficiency of the amplifier circuit deteriorates as the frequency of the high-frequency signal increases.

[0009] Therefore, the present invention provides an amplifier circuit and a communication device in which efficiency degradation is suppressed when digital ET is used.

[0010] Technical solutions to solve problems

[0011] An amplifier circuit involved in one embodiment of the present invention is an amplifier circuit that receives multiple discrete power supply voltages and includes: a carrier amplifier; a first peak amplifier; a synthesis circuit that synthesizes a high-frequency signal output from the carrier amplifier and a high-frequency signal output from the first peak amplifier; a bias circuit that supplies a first bias current to the first peak amplifier; a digital control terminal that receives a digital control signal based on an envelope signal; and a first switch that is connected to the digital control terminal and switches between connection and non-connection of the bias circuit and the first peak amplifier, wherein the carrier amplifier and the first peak amplifier each include multiple amplifier elements that are connected in a common source and common gate manner.

[0012] Effects of the Invention

[0013] According to the present invention, it is possible to provide an amplifier circuit and a communication device in which efficiency degradation is suppressed when digital ET is used. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1A This is a graph showing an example of the transition of the power supply voltage in the average power tracking mode.

[0015] Figure 1B This is a graph showing an example of the transition of the power supply voltage in the analog envelope tracking mode.

[0016] Figure 1C This is a graph showing an example of transition of the power supply voltage in the digital envelope tracking mode.

[0017] Figure 2A It is a circuit configuration diagram of an amplifier circuit and a communication device according to an embodiment.

[0018] Figure 2B It is a diagram showing a logic value table of a logic circuit according to an embodiment and a relationship between a high-frequency signal and a power supply voltage value.

[0019] Figure 3A This is a circuit configuration diagram of an amplifier circuit and a communication device according to Modification 1.

[0020] Figure 3B 1 is a diagram showing a logic value table of a logic circuit according to Modification 1 and a relationship between a high-frequency signal and a power supply voltage value.

[0021] Figure 4 This is a circuit configuration diagram of an amplifier circuit and a communication device according to Modification Example 2.

[0022] Figure 5A This is a circuit configuration diagram of an amplifier circuit and a communication device according to Modification 3.

[0023] Figure 5B 1 is a diagram showing a logic value table of a logic circuit according to Modification 3 and a relationship between a high-frequency signal and a power supply voltage value.

[0024] Fig. 6A This is a circuit state diagram when the input power of the amplifier circuit according to Modification 3 is a third power value.

[0025] Figure 6B This is a circuit state diagram when the input power of the amplifier circuit according to Modification 3 is the second power value.

[0026] Figure 6C This is a circuit state diagram when the input power of the amplifier circuit according to Modification 3 is a first power value.

[0027] Figure 7: is a graph showing the relationship between the output power and the gain of the amplifier circuit according to the third modification. DETAILED DESCRIPTION

[0028] The following are detailed descriptions of the embodiments of the present disclosure using the accompanying drawings. In addition, the embodiments described below are all general or specific examples. The numerical values, shapes, materials, components, configurations of components, and connection methods shown in the following embodiments are examples, and the main purpose is not to limit the present invention.

[0029] In addition, each figure is a schematic diagram that appropriately emphasizes, omits, or adjusts the ratio in order to illustrate the present invention, and is not necessarily strictly illustrated, and sometimes differs from the actual shape, positional relationship, and ratio. In each figure, the same reference numerals are marked for substantially the same structure, and repeated descriptions are sometimes omitted or simplified.

[0030] In the circuit structure of the present disclosure, the so-called "connection" includes not only the case of direct connection through connection terminals and / or wiring conductors, but also the case of electrical connection via other circuit elements. The so-called "connected between A and B" means connected between A and B to both A and B.

[0031] In the present disclosure, a “signal path” means a transmission line composed of a wiring that propagates a high-frequency signal, an electrode directly connected to the wiring, and a terminal directly connected to the wiring or the electrode.

[0032] First, as a technique for efficiently amplifying a high-frequency signal, a tracking mode in which a variable power supply voltage dynamically adjusted over time based on the high-frequency signal is supplied to a power amplifier is described. The so-called tracking mode is a mode in which the power supply voltage applied to the amplifier circuit is dynamically adjusted. There are several types of tracking modes, but here, while referring to Figure 1A to Figure 1C , while explaining the average power tracking (APT: Average Power Tracking) mode and the envelope tracking (ET: Envelope Tracking) mode (including analog ET mode and digital ET mode). Figure 1A to Figure 1C In the figure, the horizontal axis represents time and the vertical axis represents voltage. In addition, the thick solid line represents the power supply voltage and the thin solid line (waveform) represents the modulation wave.

[0033] Figure 1AThis is a graph showing an example of the transition of the power supply voltage in the APT mode. In the APT mode, the power supply voltage is varied to a plurality of discrete voltage levels in units of one frame. As a result, the power supply voltage signal forms a rectangular wave. In the APT mode, the voltage level of the power supply voltage is determined based on the average output power. In addition, in the APT mode, the voltage level may also vary in units smaller than one frame (e.g., subframes, time slots, or symbols). APT in which the voltage level varies in units of symbols is sometimes called symbol power tracking (SPT: Symbol Power Tracking).

[0034] A frame is a unit of a high frequency signal having a length of 10 milliseconds, including 10 subframes. A subframe is a unit of a high frequency signal having a length of 1 millisecond, including 2 slots. A slot is a unit of a high frequency signal having a length of 0.5 milliseconds, including 6 symbols. A symbol is a unit of a high frequency signal having a length of 71 microseconds, including a cyclic prefix (CP).

[0035] In the SPT mode, the power supply voltage level is modulated in units of one symbol. At this time, the voltage level is changed in the CP interval. For example, in the first symbol, the CP is changed to a higher voltage level, and in the second symbol, the CP is changed to a lower voltage level. In addition, in subsequent symbols, the voltage level may not be changed. The power supply voltage level can be modulated based on the data signal in each symbol interval.

[0036] Figure 1B 1 is a graph showing an example of the transition of the power supply voltage in the simulated ET mode. The simulated ET mode is an example of the conventional ET mode. Figure 1B As shown, in the analog ET mode, the power supply voltage is continuously varied to track the envelope of the modulation wave. In the analog ET mode, the power supply voltage is determined based on the envelope signal.

[0037] The so-called envelope signal is a signal showing the envelope of the modulated wave. The envelope value is represented by the square root of (I2+Q2), for example. Here, (I, Q) represents a constellation point. The so-called constellation point is a point on the constellation diagram that represents a signal modulated by digital modulation. (I, Q) is determined by BBIC (Base Band Integrated Circuit) based on the transmission information, for example.

[0038] Figure 1C 2 is a graph showing an example of the transition of the power supply voltage in the digital ET mode. Figure 1CAs shown in FIG. 1 , in the digital ET mode, the power supply voltage is varied to a plurality of discrete voltage levels within one frame to track the envelope of the modulation wave. As a result, the power supply voltage signal forms a rectangular wave. In the digital ET mode, the power supply voltage level is selected or set from a plurality of discrete voltage levels based on the envelope signal.

[0039] (Implementation Method)

[0040] [1 Configuration of Amplifier Circuit 1 and Communication Device 4]

[0041] One side reference Figure 2A Next, the amplifier circuit 1 and the communication device 4 according to the present embodiment will be described.

[0042] Figure 2A 1 is a circuit diagram of an amplifier circuit 1 and a communication device 4 according to an embodiment. The communication device 4 according to this embodiment is equivalent to a user terminal (UE: User Equipment) in a cellular network, and is typically a mobile phone, a smart phone, a tablet computer, a wearable device, etc. In addition, the communication device 4 may also be an IoT (Internet of Things) sensor device, a medical / health care device, a car, an unmanned aerial vehicle (UAV: Unmanned Aerial Vehicle) (so-called drone), or an unmanned guided vehicle (AGV: Automated Guided Vehicle).

[0043] First, the circuit structure of the communication device 4 is described. Figure 2A As shown, the communication device 4 according to the present embodiment includes an amplifier circuit 1 , a tracker circuit 2 , and a signal processing circuit 3 .

[0044] The signal processing circuit 3 is an example of a signal processing circuit that processes a high-frequency signal. The signal processing circuit 3 has a control unit that controls the amplifier circuit 1 and the tracker circuit 2. Specifically, the signal processing circuit 3 performs signal processing on the transmission signal by up-conversion, etc., and outputs the high-frequency transmission signal generated by the signal processing to the amplifier circuit 1. In addition, the signal processing circuit 3 outputs a signal showing the envelope of the modulation wave of the high-frequency signal, that is, an envelope signal, to the tracker circuit 2. In addition, part or all of the functions of the control unit of the signal processing circuit 3 can also be installed outside the signal processing circuit 3, for example, can also be installed in the amplifier circuit 1 and the tracker circuit 2.

[0045] The tracker circuit 2 can supply a plurality of discrete power supply voltages based on a tracking mode to the amplifier circuit 1. As the tracking mode, a digital ET mode can be used, but the present invention is not limited thereto. The tracker circuit 2 includes a discrete voltage generating circuit 60, a voltage selecting circuit 70, and a digital control circuit 80.

[0046] The discrete voltage generating circuit 60 is configured to generate a plurality of discrete voltages each having a plurality of discrete voltage levels. The discrete voltage generating circuit 60 is, for example, a switched capacitor circuit including a plurality of capacitors and a plurality of switches.

[0047] The voltage selection circuit 70 is configured to selectively output at least one of the plurality of discrete voltages generated by the discrete voltage generation circuit 60 to the amplifier circuit 1 based on the envelope signal. The voltage selection circuit 70 is controlled based on a digital control signal output from the digital control circuit 80 .

[0048] The digital control circuit 80 can control the voltage selection circuit 70 and the amplifier circuit 1 based on the envelope signal from the signal processing circuit 3. Specifically, the digital control circuit 80 generates digital logic (DCL: Digital Control Logic / Line) signals (V1_EN, V2_EN) based on the envelope signal received from the signal processing circuit 3.

[0049] In addition, the digital control circuit 80 may be included in the signal processing circuit 3 instead of being included in the tracker circuit 2 .

[0050] The amplifier circuit 1 includes carrier amplifiers 11 and 12, peak amplifiers 21 and 22, switches 13 and 23, logic circuits 14 and 24, a phase shift circuit 30, a synthesizing circuit 40, a bias circuit 50, a signal input terminal 110, a signal output terminal 120, a power supply voltage terminal 130, and digital control terminals 140 and 150.

[0051] The signal input terminal 110 is connected to the signal processing circuit 3 and the phase shift circuit 30, and transmits the high-frequency signal output from the signal processing circuit 3 to the phase shift circuit 30. The signal output terminal 120 is connected to the synthesizing circuit 40 and an antenna (not shown), and outputs the high-frequency signal amplified by the amplifier circuit 1 to the antenna.

[0052] The power supply voltage terminal 130 is connected to the tracker circuit 2, the carrier amplifiers 11 and 12, and the peak amplifiers 21 and 22, and transmits a plurality of discrete power supply voltages based on the envelope signal generated by the tracker circuit 2 to the carrier amplifiers 11 and 12, and the peak amplifiers 21 and 22. The amplifier circuit 1 receives a plurality of discrete power supply voltages from the tracker circuit 2 via the power supply voltage terminal 130.

[0053] The digital control terminals 140 and 150 receive a digital control signal based on the envelope signal generated by the tracker circuit 2 .

[0054] The carrier amplifiers 11 and 12 and the peak amplifiers 21 and 22 each include an amplifier transistor. The amplifier transistor is, for example, a bipolar transistor such as a heterojunction bipolar transistor (HBT) or a field effect transistor such as a MOSFET.

[0055] The carrier amplifiers 11 and 12 are class A (or class AB) amplifier circuits capable of amplifying all power levels of high-frequency signals, and in particular, are capable of amplifying with high efficiency in low output and medium output regions. In addition, the carrier amplifiers 11 and 12 are not limited to carrier amplifiers as long as they are class A (or class AB) amplifier circuits.

[0056] The peak amplifiers 21 and 22 are class C amplifier circuits that can perform amplification in a region where the power level of the high-frequency signal is high. A bias voltage lower than the bias voltage applied to the amplifier transistors of the carrier amplifiers 11 and 12 is applied to the amplifier transistors of the peak amplifiers 21 and 22, so that the higher the power level of the high-frequency signal becomes, the lower the output impedance becomes. As a result, the peak amplifiers 21 and 22 can perform low-distortion amplification in a high-output region. In addition, the peak amplifiers 21 and 22 can be any class C amplifier circuit and are not limited to peak amplifiers.

[0057] The carrier amplifier 11 includes transistors 111 and 112, and a resistor 113. The transistors 111 and 112 are, for example, n-type bipolar transistors (amplifying elements). The base of the transistor 111 is connected to the phase shift circuit 30 via a capacitor, the emitter of the transistor 111 is connected to the ground, and the collector of the transistor 111 is connected to the emitter of the transistor 112. The base of the transistor 112 is connected to the bias circuit 50 via the resistor 113 and the switch 13. In addition, the base of the transistor 112 is connected to the ground via a capacitor and is grounded at high frequency. The collector of the transistor 112 is connected to the power supply voltage terminal 130. That is, the carrier amplifier 11 includes the transistors 111 and 112 that are cascode-connected.

[0058] The carrier amplifier 12 includes transistors 121 (first amplifier element) and 122 (second amplifier element), and a resistor 123. The transistors 121 and 122 are, for example, n-type bipolar transistors (amplifier elements). The base (first control terminal) of the transistor 121 is connected to the phase shift circuit 30 via the capacitor and the carrier amplifier 11, the emitter (first terminal) of the transistor 121 is connected to the ground, and the collector (second terminal) of the transistor 121 is connected to the emitter (third terminal) of the transistor 122. The base (second control terminal) of the transistor 122 is connected to the bias circuit 50 via the resistor 123 and the switch 13. In addition, the base of the transistor 122 is connected to the ground via the capacitor and is grounded at high frequency. The collector (fourth terminal) of the transistor 122 is connected to the power supply voltage terminal 130, and is also connected to the synthesizing circuit 40. That is, the carrier amplifier 12 includes the transistors 121 and 122 connected in a cascode manner.

[0059] In addition, the amplifier circuit 1 may not include the carrier amplifier 11. In addition, the amplifier circuit 1 may include three or more carrier amplifiers including the carrier amplifier 12 connected in cascade.

[0060] The peak amplifier 21 includes transistors 211 and 212, and a resistor 213. The transistors 211 and 212 are, for example, n-type bipolar transistors (amplifying elements). The base of the transistor 211 is connected to the phase shift circuit 30 via a capacitor, the emitter of the transistor 211 is connected to the ground, and the collector of the transistor 211 is connected to the emitter of the transistor 212. The base of the transistor 212 is connected to the bias circuit 50 via the resistor 213 and the switch 23. In addition, the base of the transistor 212 is connected to the ground via a capacitor and is grounded at high frequency. The collector of the transistor 212 is connected to the power supply voltage terminal 130. That is, the peak amplifier 21 includes the transistors 211 and 212 connected in common source and gate.

[0061] The peak amplifier 22 is an example of a first peak amplifier, and includes transistors 221 (third amplifying element) and 222 (fourth amplifying element), and a resistor 223. The transistors 221 and 222 are, for example, n-type bipolar transistors (amplifying elements). The base (third control terminal) of the transistor 221 is connected to the phase shift circuit 30 via the capacitor and the peak amplifier 21, the emitter (fifth terminal) of the transistor 221 is connected to the ground, and the collector (sixth terminal) of the transistor 221 is connected to the emitter (seventh terminal) of the transistor 222. The base (fourth control terminal) of the transistor 222 is connected to the bias circuit 50 via the resistor 223 and the switch 23. In addition, the base of the transistor 222 is connected to the ground via the capacitor and is grounded at high frequency. The collector (eighth terminal) of the transistor 222 is connected to the power supply voltage terminal 130, and is also connected to the synthesizing circuit 40. That is, the peak amplifier 22 includes transistors 221 and 222 connected in a cascode manner.

[0062] In addition, the amplifier circuit 1 may not include the peak amplifier 21. In addition, the amplifier circuit 1 may include three or more peak amplifiers including the peak amplifier 22 connected in cascade.

[0063] The carrier amplifiers 11 and 12 and the peak amplifiers 21 and 22 have a cascode connection structure, respectively. Thus, the amplifier circuit 1 can ensure a high amplification gain even for high-frequency signals in the millimeter wave band and the sub-terahertz band.

[0064] The phase shift circuit 30 is configured to distribute the high frequency signal input from the signal input terminal 110 and output the distributed signal to the carrier amplifier 11 and the peak amplifier 21. The phase shift circuit 30 adjusts the phase of the distributed signal.

[0065] The synthesizing circuit 40 is configured to synthesize the high frequency signal output from the carrier amplifier 12 and the high frequency signal output from the peak amplifier 22, and output the synthesized high frequency signal to the signal output terminal 120. The synthesizing circuit 40 may be a voltage synthesizing circuit using a transformer or a current synthesizing circuit using a phase shifting line.

[0066] The bias circuit 50 is configured to supply bias currents to the carrier amplifiers 11 and 12 and the peak amplifiers 21 and 22. The first bias current is supplied to the peak amplifiers 21 and 22 via the switch 23, and the bias current is supplied to the carrier amplifiers 11 and 12 via the switch 13.

[0067] The switch 13 is connected to the digital control terminals 140 and 150, and switches the connection and disconnection between the bias circuit 50 and the carrier amplifiers 11 and 12. Specifically, the switch 13 has a control terminal and two terminals, the control terminal is connected to the digital control terminals 140 and 150 via the logic circuit 14, one terminal is connected to the bias circuit 50, and the other terminal is connected to the carrier amplifiers 11 and 12.

[0068] The switch 23 is an example of a first switch, and is connected to the digital control terminals 140 and 150, and switches the connection and disconnection between the bias circuit 50 and the peak amplifiers 21 and 22. Specifically, the switch 23 has a control terminal and two terminals, the control terminal is connected to the digital control terminals 140 and 150 via the logic circuit 24, one terminal is connected to the bias circuit 50, and the other terminal is connected to the peak amplifiers 21 and 22.

[0069] The logic circuit 14 is connected between the digital control terminals 140 and 150 and the switch 13. The logic circuit 24 is connected between the digital control terminals 140 and 150 and the switch 23. Digital logic (DCL: Digital Control Logic / Line) signals (V1_EN, V2_EN) generated by the digital control circuit 80 of the tracker circuit 2 are applied to the digital control terminals 140 and 150, for example.

[0070] In addition, the digital control signal supplied to the digital control terminals 140 and 150 is not a serial data signal like a source synchronous digital control signal, but a parallel data signal. By supplying the DCL signals V1_EN and V2_EN in parallel to the digital control terminals 140 and 150, respectively, it is possible to perform high-speed variable supply of the power supply voltage and high-speed on-off switching of the peak amplifiers 21 and 22. Therefore, it is possible to cope with wide channel bandwidths of high-frequency signals in the millimeter wave band and the sub-terahertz band.

[0071] In addition, the so-called serial data signal refers to a data signal that is transmitted one bit at a time in one signal line or line, and the so-called parallel data signal refers to a data signal that is transmitted in parallel in a plurality of signal lines or lines at the same time.

[0072] Figure 2B1 is a diagram showing a logic value table of the logic circuits 14 and 24 according to the embodiment, and a relationship between a high-frequency signal and a power supply voltage value. In (a) of the figure, a power supply voltage (V1 or V2) applied to the power supply voltage terminal 130 corresponding to the DCL signal (V1_EN, V2_EN) is shown, and a gate signal (Vg_C) output from the logic circuit 14 and a gate signal (Vg_P) output from the logic circuit 24 corresponding to the DCL signal (V1_EN, V2_EN) are shown. In addition, in (b) of the figure, a power supply voltage (V1 or V2) supplied to the amplifier circuit 1 in response to the envelope of the high-frequency signal input to the amplifier circuit 1 is shown.

[0073] like Figure 2B As shown, when the DCL signal V1_EN=1 and the DCL signal V2_EN=0, the voltage selection circuit 70 outputs the power supply voltage V1 to the power supply voltage terminal 130, the logic circuit 14 outputs the gate signal (Vg_C=1) for setting the switch 13 to the conductive state, and the logic circuit 24 outputs the gate signal (Vg_P=0) for setting the switch 23 to the non-conductive state. In addition, when the DCL signal V1_EN=0 and the DCL signal V2_EN=1, the voltage selection circuit 70 outputs the power supply voltage V2 to the power supply voltage terminal 130, the logic circuit 14 outputs the gate signal (Vg_C=1) for setting the switch 13 to the conductive state, and the logic circuit 24 outputs the gate signal (Vg_P=1) for setting the switch 23 to the conductive state.

[0074] That is, when the envelope value (I 2 +Q 2 ) is relatively large (when a large signal is input: the second power value), the amplifier circuit 1 receives a power supply voltage V2 greater than the power supply voltage V1, and the carrier amplifiers 11 and 12 and the peak amplifiers 21 and 22 that receive the bias current from the bias circuit 50 are turned on. In this case, the output impedance of the load side viewed from the output terminals of the carrier amplifier 12 and the peak amplifier 22 is set to R L .

[0075] In addition, when the envelope value (I 2 +Q 2 ) is relatively small (when a small signal is input: the first power value), the amplifier circuit 1 receives the power supply voltage V1, the carrier amplifiers 11 and 12 that receive the bias current from the bias circuit 50 are turned on, and the peak amplifiers 21 and 22 that do not receive the bias current from the bias circuit 50 are turned off. In this case, the impedance of the load side viewed from the output terminal of the carrier amplifier 12 becomes 2R LIn addition, at this time, the impedance on the load side viewed from the output terminal of the peak amplifier 22 is in an open circuit state.

[0076] As described above, when a small signal is input, the impedance of the load side viewed from the carrier amplifier 12 becomes twice as large as when a large signal is input. That is, when a small signal is input, since the peak amplifiers 21 and 22 are in the cut-off state, the impedance of the load side viewed from the carrier amplifier 12 becomes high, so that the amplifier circuit 1 can operate with high efficiency.

[0077] On the other hand, when a large signal is input, since the carrier amplifiers 11, 12 and the peak amplifiers 21 and 22 operate under a high power supply voltage, a high-power signal can be output, and since the impedance of the load side viewed from the peak amplifier 22 is low, signal distortion can be suppressed.

[0078] According to this, the supply of the first bias current to the peak amplifiers 21 and 22 is controlled based on the envelope signal, so that the efficiency is optimized according to the output power of the amplifier circuit 1. In addition, the supply of the power supply voltage and the turning on and off of the peak amplifiers 21 and 22 are performed based on the envelope signal, so the efficiency of the amplifier circuit 1 is optimized with high accuracy.

[0079] In addition, a bias current is supplied to the bases of the transistor 112 of the carrier amplifier 11 and the transistor 122 of the carrier amplifier 12 according to the conduction and non-conduction of the switch 13. In addition, a bias current is supplied to the bases of the transistor 212 of the peak amplifier 21 and the transistor 222 of the peak amplifier 22 according to the conduction and non-conduction of the switch 23. In contrast, a bias current is continuously supplied to the bases of the transistor 111 of the carrier amplifier 11, the transistor 121 of the carrier amplifier 12, the transistor 211 of the peak amplifier 21, and the transistor 221 of the peak amplifier 22, regardless of the conduction and non-conduction of the switches 13 and 23.

[0080] [2 Configuration of Amplifier Circuit 1A and Communication Device 4A According to Modification 1]

[0081] Figure 3A 1 is a circuit diagram of an amplifier circuit 1A and a communication device 4A according to variant example 1. The communication device 4A according to this variant example includes an amplifier circuit 1A, a tracker circuit 2A, and a signal processing circuit 3. The communication device 4A according to this variant example is different in structure from the communication device 4 according to the embodiment in that the logic circuit does not exist in the amplifier circuit 1A but exists in the tracker circuit 2A. In the following, regarding the communication device 4A according to this variant example, the description of the same structure as the communication device 4 according to the embodiment is omitted, and the description will be centered on the different structures.

[0082] The tracker circuit 2A includes a discrete voltage generating circuit 60 , a voltage selecting circuit 70 , and a digital control circuit 80 .

[0083] The voltage selection circuit 70 is configured to selectively output at least one of the plurality of discrete voltages generated by the discrete voltage generation circuit 60 to the amplifier circuit 1A based on the envelope signal. The voltage selection circuit 70 includes a logic circuit 74 and is controlled based on a digital control signal output from the digital control circuit 80 .

[0084] The digital control circuit 80 generates a DCL signal (Vc_EN, Vp_EN) based on the envelope signal received from the signal processing circuit 3 .

[0085] In addition, the digital control circuit 80 may be included in the signal processing circuit 3 instead of being included in the tracker circuit 2A.

[0086] The amplifier circuit 1A includes carrier amplifiers 11 and 12 , peak amplifiers 21 and 22 , switches 13 and 23 , a phase shift circuit 30 , a synthesizing circuit 40 , a bias circuit 50 , a signal input terminal 110 , a signal output terminal 120 , a power supply voltage terminal 130 , and digital control terminals 140 and 150 .

[0087] The digital control terminals 140 and 150 receive a digital control signal based on the envelope signal generated by the tracker circuit 2A.

[0088] The switch 13 is connected to the digital control terminals 140 and 150, and switches the connection and non-connection between the bias circuit 50 and the carrier amplifiers 11 and 12. Specifically, the switch 13 has a control terminal and two terminals, the control terminal is connected to the digital control terminal 140, one terminal is connected to the bias circuit 50, and the other terminal is connected to the carrier amplifiers 11 and 12.

[0089] The switch 23 is an example of a first switch, and is connected to the digital control terminals 140 and 150, and switches the connection and disconnection between the bias circuit 50 and the peak amplifiers 21 and 22. Specifically, the switch 23 has a control terminal and two terminals, the control terminal is connected to the digital control terminal 150, one terminal is connected to the bias circuit 50, and the other terminal is connected to the peak amplifiers 21 and 22.

[0090] The logic circuit 74 is included in the voltage selection circuit 70. The DCL signal (Vc_EN, Vp_EN) generated by the digital control circuit 80 of the tracker circuit 2A, for example, is applied to the digital control terminals 140 and 150.

[0091] Figure 3B1 is a diagram showing a logic value table of a logic circuit 74 according to Modification 1 and a relationship between a high-frequency signal and a power supply voltage value. In (a) of the figure, a power supply voltage (V1 or V2) applied to the power supply voltage terminal 130 corresponding to a DCL signal (Vc_EN, Vp_EN) is shown. In addition, in (b) of the figure, a power supply voltage (V1 or V2) supplied to the amplifier circuit 1A in response to the envelope of the high-frequency signal input to the amplifier circuit 1A is shown.

[0092] like Figure 3B As shown, when DCL signal Vc_EN=1 and DCL signal Vp_EN=1, voltage selection circuit 70 outputs power supply voltage V2 greater than power supply voltage V1 to power supply voltage terminal 130. In addition, switch 13 is turned on by DCL signal Vc_EN=1, and switch 23 is turned on by DCL signal Vp_EN=1.

[0093] That is, when the envelope value (I 2 +Q 2 ) is relatively large (when a large signal is input: the second power value), the amplifier circuit 1A receives the power supply voltage V2, and the carrier amplifiers 11 and 12 and the peak amplifiers 21 and 22 that receive the bias current from the bias circuit 50 are turned on. In this case, the impedance of the load side viewed from the output terminals of the carrier amplifier 12 and the peak amplifier 22 is set to R L .

[0094] In addition, when the envelope value (I 2 +Q 2 ) is relatively small (when a small signal is input: the first power value), the amplifier circuit 1A receives the power supply voltage V1, the carrier amplifiers 11 and 12 that receive the bias current from the bias circuit 50 are turned on, and the peak amplifiers 21 and 22 that do not receive the bias current from the bias circuit 50 are turned off. In this case, the impedance of the load side viewed from the output terminal of the carrier amplifier 12 becomes 2R L In addition, at this time, the impedance on the load side viewed from the output terminal of the peak amplifier 22 is in an open circuit state.

[0095] As described above, when a small signal is input, the impedance of the load side viewed from the carrier amplifier 12 becomes twice as large as when a large signal is input. That is, when a small signal is input, since the peak amplifiers 21 and 22 are in the off state, the impedance of the load side viewed from the carrier amplifier 12 becomes high, and the amplifier circuit 1A can operate with high efficiency.

[0096] On the other hand, when a large signal is input, since the carrier amplifiers 11, 12 and the peak amplifiers 21 and 22 operate under a high power supply voltage, a high-power signal can be output, and since the impedance of the load side viewed from the peak amplifier 22 is low, signal distortion can be suppressed.

[0097] According to this, the supply of the first bias current to the peak amplifiers 21 and 22 is controlled based on the envelope signal, so that the efficiency is optimized according to the output power of the amplifier circuit 1A. In addition, the supply of the power supply voltage and the turning on and off of the peak amplifiers 21 and 22 are performed based on the envelope signal, so the efficiency of the amplifier circuit 1A is optimized with high accuracy.

[0098] [3. Configuration of Amplifier Circuit 1B and Communication Device 4B According to Modification 2]

[0099] Figure 4 1 is a circuit diagram of an amplifier circuit 1B and a communication device 4B according to a second modification. The communication device 4B according to this modification includes an amplifier circuit 1B, a tracker circuit 2B, and a signal processing circuit 3. The communication device 4B according to this modification differs from the communication device 4 according to the embodiment in that the structure of the digital control circuit 80 is different, and there is no logic circuit in the amplifier circuit 1B. Hereinafter, the communication device 4B according to this modification will be described with the focus on the different structures, while the description will be given below.

[0100] The tracker circuit 2B includes a discrete voltage generating circuit 60 , a voltage selecting circuit 70 , and a digital control circuit 80 .

[0101] The digital control circuit 80 generates DCL signals ( V1_EN, V2_EN, Vc_EN, Vp_EN) based on the envelope signal received from the signal processing circuit 3 .

[0102] In addition, the digital control circuit 80 may be included in the signal processing circuit 3 instead of being included in the tracker circuit 2B.

[0103] The amplifier circuit 1B includes carrier amplifiers 11 and 12 , peak amplifiers 21 and 22 , switches 13 and 23 , a phase shift circuit 30 , a synthesizing circuit 40 , a bias circuit 50 , a signal input terminal 110 , a signal output terminal 120 , a power supply voltage terminal 130 , and digital control terminals 140 and 150 .

[0104] The digital control terminals 140 and 150 receive a digital control signal based on the envelope signal generated by the tracker circuit 2B.

[0105] The switch 13 is connected to the digital control terminals 140 and 150, and switches the connection and non-connection between the bias circuit 50 and the carrier amplifiers 11 and 12. Specifically, the switch 13 has a control terminal and two terminals, the control terminal is connected to the digital control terminal 140, one terminal is connected to the bias circuit 50, and the other terminal is connected to the carrier amplifiers 11 and 12.

[0106] The switch 23 is an example of a first switch, and is connected to the digital control terminals 140 and 150, and switches the connection and disconnection between the bias circuit 50 and the peak amplifiers 21 and 22. Specifically, the switch 23 has a control terminal and two terminals, the control terminal is connected to the digital control terminal 150, one terminal is connected to the bias circuit 50, and the other terminal is connected to the peak amplifiers 21 and 22.

[0107] For example, DCL signals (Vc_EN, Vp_EN) generated by the digital control circuit 80 are applied to the digital control terminals 140 and 150 . In addition, DCL signals (V1_EN, V2_EN) generated by the digital control circuit 80 are applied to the voltage selection circuit 70 .

[0108] When the DCL signal Vc_EN=1, the switch 13 is turned on. When the DCL signal Vp_EN=1, the switch 23 is turned on. When the DCL signal V1_EN=1, the voltage selection circuit 70 outputs the power supply voltage V1 to the power supply voltage terminal 130. When the DCL signal V2_EN=1, the voltage selection circuit 70 outputs the power supply voltage V2 to the power supply voltage terminal 130.

[0109] The envelope value (I 2 +Q 2 ) is relatively large (when a large signal is input: the second power value), the digital control circuit 80 outputs the DCL signals V2_EN=1, V1_EN=0, Vc_EN=1, and Vp_EN=1. As a result, the amplifier circuit 1B receives the power supply voltage V2 greater than the power supply voltage V1, and the carrier amplifiers 11 and 12 and the peak amplifiers 21 and 22 that receive the bias current from the bias circuit 50 are turned on. In this case, the impedance of the load side viewed from the output terminals of the carrier amplifier 12 and the peak amplifier 22 is set to R L .

[0110] In addition, when the envelope value (I 2 +Q 2) is relatively small (when a small signal is input: the first power value), the digital control circuit 80 outputs the DCL signals V2_EN=0, V1_EN=1, Vc_EN=1, and Vp_EN=0. As a result, the amplifier circuit 1B receives the power supply voltage V1, and the carrier amplifiers 11 and 12 that receive the bias current from the bias circuit 50 are turned on, and the peak amplifiers 21 and 22 that do not receive the bias current from the bias circuit 50 are turned off. In this case, the impedance of the load side viewed from the output terminal of the carrier amplifier 12 becomes 2R L In addition, at this time, the impedance on the load side viewed from the output terminal of the peak amplifier 22 is in an open circuit state.

[0111] As described above, when a small signal is input, the output impedance of the load side viewed from the carrier amplifier 12 is doubled compared to when a large signal is input. That is, when a small signal is input, since the peak amplifiers 21 and 22 are in the off state, the impedance of the load side viewed from the carrier amplifier 12 becomes higher, and the amplifier circuit 1B can operate with high efficiency.

[0112] On the other hand, when a large signal is input, since the carrier amplifiers 11, 12 and the peak amplifiers 21 and 22 operate under a high power supply voltage, a high-power signal can be output, and since the impedance of the load side viewed from the peak amplifier 22 is low, signal distortion can be suppressed.

[0113] According to this, the supply of the first bias current to the peak amplifiers 21 and 22 is controlled based on the envelope signal, so that the efficiency is optimized according to the output power of the amplifier circuit 1B. In addition, the supply of the power supply voltage and the turning on and off of the peak amplifiers 21 and 22 are performed based on the envelope signal, so the efficiency of the amplifier circuit 1B is optimized with high accuracy.

[0114] [4. Configuration of Amplifier Circuit 1C and Communication Device 4C According to Modification 3]

[0115] Figure 5A 1 is a circuit structure diagram of an amplifier circuit 1C and a communication device 4C involved in modification example 3. The communication device 4C involved in this modification example includes an amplifier circuit 1C, a tracker circuit 2C, and a signal processing circuit 3. The communication device 4C involved in this modification example is different from the communication device 4 involved in the embodiment mainly in that the amplifier structure of the amplifier circuit 1C is different. Hereinafter, regarding the communication device 4C involved in this modification example, the description of the same structure as the communication device 4 involved in the embodiment is omitted, and the description is centered on the different structures.

[0116] The tracker circuit 2C can supply a plurality of discrete power supply voltages to the amplifier circuit 1C based on the tracking mode. As the tracking mode, a digital ET mode can be used, but the present invention is not limited thereto. The tracker circuit 2C includes a discrete voltage generation circuit 60 , a voltage selection circuit 70 , and a digital control circuit 80 .

[0117] The digital control circuit 80 can control the voltage selection circuit 70 and the amplifier circuit 1C based on the envelope signal from the signal processing circuit 3 . Specifically, the digital control circuit 80 generates DCL signals ( V1_EN, V2_EN, V3_EN) based on the envelope signal received from the signal processing circuit 3 .

[0118] In addition, the digital control circuit 80 may be included in the signal processing circuit 3 instead of being included in the tracker circuit 2C.

[0119] The amplifier circuit 1C includes carrier amplifiers 11 and 12, peak amplifiers 21, 22, 31 and 32, switches 13, 23 and 33, logic circuits 14C, 24C and 34C, a phase shift circuit 30, a synthesizing circuit 40, a bias circuit 50, a signal input terminal 110, a signal output terminal 120, a power supply voltage terminal 130, and digital control terminals 140, 150 and 160.

[0120] The power supply voltage terminal 130 is connected to the tracker circuit 2C, the carrier amplifiers 11 and 12, and the peak amplifiers 21, 22, 31, and 32, and transmits a plurality of discrete power supply voltages based on the envelope signal generated by the tracker circuit 2C to the carrier amplifiers 11 and 12, and the peak amplifiers 21, 22, 31, and 32. The amplifier circuit 1C receives a plurality of discrete power supply voltages from the tracker circuit 2C via the power supply voltage terminal 130.

[0121] The digital control terminals 140 , 150 , and 160 receive digital control signals based on the envelope signal generated by the tracker circuit 2C.

[0122] The carrier amplifiers 11 and 12 and the peak amplifiers 21, 22, 31 and 32 each include an amplifier transistor. The amplifier transistor is, for example, a bipolar transistor such as HBT or a field effect transistor such as MOSFET.

[0123] The peak amplifiers 21 and 22 are class C amplifier circuits that can perform amplification in a region where the power level of the high-frequency signal is high. A bias voltage lower than the bias voltage applied to the amplifier transistors of the carrier amplifiers 11 and 12 is applied to the amplifier transistors of the peak amplifiers 21 and 22, so that the higher the power level of the high-frequency signal becomes, the lower the output impedance becomes. As a result, the peak amplifiers 21 and 22 can perform low-distortion amplification in a medium output region. In addition, the peak amplifiers 21 and 22 can be any class C amplifier circuit and are not limited to peak amplifiers.

[0124] The peak amplifiers 31 and 32 are class C amplifier circuits that can perform amplification in a region where the power level of the high-frequency signal is high. A bias voltage lower than the bias voltage applied to the amplifier transistors of the carrier amplifiers 11 and 12 is applied to the amplifier transistors of the peak amplifiers 31 and 32, so that the higher the power level of the high-frequency signal becomes, the lower the output impedance becomes. As a result, the peak amplifiers 31 and 32 can perform low-distortion amplification in a high-output region. In addition, the peak amplifiers 31 and 32 can be any class C amplifier circuit and are not limited to peak amplifiers.

[0125] The peak amplifier 31 includes transistors 311 and 312, and a resistor 313. The transistors 311 and 312 are, for example, n-type bipolar transistors (amplification elements). The base of the transistor 311 is connected to the phase shift circuit 30 via a capacitor, the emitter of the transistor 311 is connected to the ground, and the collector of the transistor 311 is connected to the emitter of the transistor 312. The base of the transistor 312 is connected to the bias circuit 50 via the resistor 313 and the switch 33. In addition, the base of the transistor 312 is connected to the ground via a capacitor and is grounded at high frequency. The collector of the transistor 312 is connected to the power supply voltage terminal 130. That is, the peak amplifier 31 includes the transistors 311 and 312 connected in common source and common gate.

[0126] The peak amplifier 32 is an example of a second peak amplifier, and includes transistors 321 and 322, and a resistor 323. The transistors 321 and 322 are, for example, n-type bipolar transistors (amplification elements). The base of the transistor 321 is connected to the phase shift circuit 30 via the capacitor and the peak amplifier 31, the emitter of the transistor 321 is connected to the ground, and the collector of the transistor 321 is connected to the emitter of the transistor 322. The base of the transistor 322 is connected to the bias circuit 50 via the resistor 323 and the switch 33. In addition, the base of the transistor 322 is connected to the ground via the capacitor and is grounded at high frequency. The collector of the transistor 322 is connected to the power supply voltage terminal 130, and is also connected to the synthesizing circuit 40. That is, the peak amplifier 32 includes transistors 321 and 322 connected in common source and common gate.

[0127] In addition, the amplifier circuit 1C may not include the peak amplifier 31. In addition, the amplifier circuit 1C may include three or more peak amplifiers including the peak amplifier 32 connected in cascade.

[0128] The carrier amplifiers 11 and 12 and the peak amplifiers 21 , 22 , 31 and 32 respectively have a common source and common gate connection structure, so that the amplifier circuit 1C can ensure high amplification gain even for high frequency signals in the millimeter wave band and the sub-terahertz band.

[0129] The phase shift circuit 30 is configured to distribute the high frequency signal input from the signal input terminal 110 and output the distributed signal to the carrier amplifier 11 and the peak amplifiers 21 and 31. The phase shift circuit 30 adjusts the phase of the distributed signal at this time.

[0130] The synthesizing circuit 40 is configured to synthesize the high frequency signal output from the carrier amplifier 12 , the high frequency signal output from the peak amplifier 22 , and the high frequency signal output from the peak amplifier 32 , and output the synthesized high frequency signal to the signal output terminal 120 .

[0131] The bias circuit 50 is configured to supply bias currents to the carrier amplifiers 11 and 12 and the peak amplifiers 21, 22, 31, and 32. The first bias current is supplied to the peak amplifiers 21 and 22 via the switch 23, the second bias current is supplied to the peak amplifiers 31 and 32 via the switch 33, and the bias current is supplied to the carrier amplifiers 11 and 12 via the switch 13.

[0132] The switch 13 is connected to the digital control terminals 140, 150, and 160, and switches the connection and disconnection between the bias circuit 50 and the carrier amplifiers 11 and 12. Specifically, the switch 13 has a control terminal and two terminals, the control terminal is connected to the digital control terminals 140, 150, and 160 via the logic circuit 14C, one terminal is connected to the bias circuit 50, and the other terminal is connected to the carrier amplifiers 11 and 12.

[0133] The switch 23 is an example of a first switch, and is connected to the digital control terminals 140, 150, and 160, and switches the connection and disconnection between the bias circuit 50 and the peak amplifiers 21 and 22. Specifically, the switch 23 has a control terminal and two terminals, the control terminal is connected to the digital control terminals 140, 150, and 160 via the logic circuit 24C, one terminal is connected to the bias circuit 50, and the other terminal is connected to the peak amplifiers 21 and 22.

[0134] The switch 33 is an example of a second switch, and is connected to the digital control terminals 140, 150, and 160, and switches the connection and disconnection between the bias circuit 50 and the peak amplifiers 31 and 32. Specifically, the switch 33 has a control terminal and two terminals, the control terminal is connected to the digital control terminals 140, 150, and 160 via the logic circuit 34C, one terminal is connected to the bias circuit 50, and the other terminal is connected to the peak amplifiers 31 and 32.

[0135] The logic circuit 14C is connected between the digital control terminals 140, 150, and 160 and the switch 13. The logic circuit 24C is connected between the digital control terminals 140, 150, and 160 and the switch 23. The logic circuit 34C is connected between the digital control terminals 140, 150, and 160 and the switch 33. The DCL signals (V1_EN, V2_EN, V3_EN) generated by, for example, the digital control circuit 80 of the tracker circuit 2C are applied to the digital control terminals 140, 150, and 160.

[0136] In addition, the digital control signals supplied to the digital control terminals 140, 150, and 160 are not serial data signals like source synchronous digital control signals, but parallel data signals. By supplying the DCL signals V1_EN, V2_EN, and V3_EN in parallel to the digital control terminals 140, 150, and 160, respectively, it is possible to perform high-speed variable supply of the power supply voltage and high-speed on-off switching of the peak amplifiers 21, 22, 31, and 32. Therefore, it is possible to cope with wide channel bandwidths of high-frequency signals in the millimeter wave band and the sub-terahertz band.

[0137] Figure 5B This is a diagram showing a logic value table of logic circuits 14C, 24C, and 34C involved in Modification Example 3 and a relationship between a high-frequency signal and a power supply voltage value. In (a) of the figure, a power supply voltage (V1, V2, or V3) applied to the power supply voltage terminal 130 corresponding to the DCL signal (V1_EN, V2_EN, V3_EN) is shown, and a gate signal (Vg_C) output from the logic circuit 14C, a gate signal (Vg_P1) output from the logic circuit 24C, and a gate signal (Vg_P2) output from the logic circuit 34C corresponding to the DCL signal (V1_EN, V2_EN, V3_EN) are shown. In addition, in (b) of the figure, a power supply voltage (V1, V2, or V3) supplied to the amplifier circuit 1C in response to the envelope of the high-frequency signal input to the amplifier circuit 1C is shown.

[0138] like Figure 5BAs shown, when the DCL signal V1_EN=1, the DCL signal V2_EN=0, and the DCL signal V3_EN=0, the voltage selection circuit 70 outputs the power supply voltage V1 to the power supply voltage terminal 130, the logic circuit 14C outputs a gate signal (Vg_C=1) for setting the switch 13 to the on state, the logic circuit 24C outputs a gate signal (Vg_P1=0) for setting the switch 23 to the non-conducting state, and the logic circuit 34C outputs a gate signal (Vg_P2=0) for setting the switch 33 to the non-conducting state.

[0139] In addition, when the DCL signal V1_EN=0, the DCL signal V2_EN=1, and the DCL signal V3_EN=0, the voltage selection circuit 70 outputs the power supply voltage V2 greater than the power supply voltage V1 to the power supply voltage terminal 130, the logic circuit 14C outputs the gate signal (Vg_C=1) for setting the switch 13 to the on state, the logic circuit 24C outputs the gate signal (Vg_P1=1) for setting the switch 23 to the on state, and the logic circuit 34C outputs the gate signal (Vg_P2=0) for setting the switch 33 to the non-conducting state.

[0140] In addition, when the DCL signal V1_EN=0, the DCL signal V2_EN=0, and the DCL signal V3_EN=1, the voltage selection circuit 70 outputs the power supply voltage V3 greater than the power supply voltage V2 to the power supply voltage terminal 130, the logic circuit 14C outputs the gate signal (Vg_C=1) for setting the switch 13 to the on state, the logic circuit 24C outputs the gate signal (Vg_P1=1) for setting the switch 23 to the on state, and the logic circuit 34C outputs the gate signal (Vg_P2=1) for setting the switch 33 to the on state.

[0141] Fig. 6A 1C is a circuit state diagram when the input power of the amplifier circuit 1C according to the modification example 3 is the third power value. As shown in the figure, when the envelope value (I 2 +Q 2 ) is relatively large (when a large signal is input: the third power value), the amplifier circuit 1C receives the power supply voltage V3, and the switches 13, 23, and 33 are turned on. As a result, the carrier amplifiers 11 and 12 and the peak amplifiers 21, 22, 31, and 32 that receive the bias current from the bias circuit 50 are turned on. In this case, the impedance of the load side viewed from the output terminals of the carrier amplifiers 12 and the peak amplifiers 22 and 32 is set to R L .

[0142] Figure 6B1 is a circuit state diagram when the input power of the amplifier circuit 1C according to the modification example 3 is the second power value. As shown in the figure, when the envelope value (I 2 +Q 2 ) is less than the third power value (when the medium signal is input: the second power value), the amplifier circuit 1C receives the power supply voltage V2, switches 13 and 23 are turned on, and switch 33 is turned off. As a result, the carrier amplifiers 11 and 12 and the peak amplifiers 21 and 22 that receive the bias current from the bias circuit 50 are turned on, and the peak amplifiers 31 and 32 that do not receive the bias current from the bias circuit 50 are turned off. In this case, the impedance of the load side viewed from the output terminals of the carrier amplifier 12 and the peak amplifier 22 becomes 2R L In addition, at this time, the impedance on the load side viewed from the output terminal of the peak amplifier 32 is in an open circuit state.

[0143] Figure 6C 1 is a circuit state diagram when the input power of the amplifier circuit 1C according to the modification example 3 is the first power value. As shown in the figure, when the envelope value (I 2 +Q 2 ) is less than the second power value (when a small signal is input: the first power value), the amplifier circuit 1C receives the power supply voltage V1, the switch 13 becomes conductive, and the switches 23 and 33 become non-conductive. As a result, the carrier amplifiers 11 and 12 that receive the bias current from the bias circuit 50 become conductive, and the peak amplifiers 21, 22, 31, and 32 that do not receive the bias current from the bias circuit 50 become non-conductive. In this case, the impedance of the load side viewed from the output terminal of the carrier amplifier 12 becomes 3R L In addition, at this time, the impedance on the load side viewed from the output terminals of the peak amplifiers 22 and 32 is in an open circuit state.

[0144] As described above, when the power level of the high-frequency input signal drops from the third power value (when a large signal is input) to the second power value (when a medium signal is input), the impedance of the load side viewed from the on-state carrier amplifier 12 and the peak amplifier 22 increases. Therefore, when a medium signal is input, the efficiency becomes higher than when the carrier amplifier 12 and the peak amplifiers 22 and 32 operate in the on-state.

[0145] Furthermore, when the power level of the high-frequency input signal drops from the second power value (when a medium signal is input) to the first power value (when a small signal is input), the impedance of the load side viewed from the on-state carrier amplifier 12 further increases. Therefore, when a small signal is input, the efficiency is higher than when the carrier amplifier 12 and the peak amplifier 22 operate in the on-state.

[0146] That is, when the input signal changes from large to small, the peak amplifier 32 and the peak amplifier 22 are turned off in sequence, and the impedance of the load side viewed from the carrier amplifier 12 (and the peak amplifier) ​​in the on state becomes higher, so that the amplifier circuit 1C can operate with high efficiency in the low output region (and the medium output region). In addition, the peak amplifiers 22 and 32 change to the off state in stages, so that the power difference between the output power when the peak amplifiers 22 and 32 are in the on state and the output power when the peak amplifiers 22 and 32 are in the off state, that is, the backoff amount, can be ensured to be large.

[0147] On the other hand, when a large signal is input, the carrier amplifiers 11 and 12 and the peak amplifiers 21, 22, 31 and 32 operate in a state where the power supply voltage is large (V3), thereby being able to output a high-power signal, and since the impedance of the load side viewed from the peak amplifiers 22 and 32 is low, signal distortion can be suppressed.

[0148] According to this, the supply of the first bias current to the peak amplifiers 21 and 22 and the supply of the second bias current to the peak amplifiers 31 and 32 are controlled based on the envelope signal, so that the efficiency is optimized according to the output power of the amplifier circuit 1C. In addition, the supply of the power supply voltage and the turning on and off of the peak amplifiers 21, 22, 31, and 32 are performed based on the envelope signal, so the efficiency of the amplifier circuit 1C is optimized with high accuracy.

[0149] In addition, a bias current is supplied to the bases of the transistor 112 of the carrier amplifier 11 and the transistor 122 of the carrier amplifier 12 according to the conduction and non-conduction of the switch 13. In addition, a bias current is supplied to the bases of the transistor 212 of the peak amplifier 21 and the transistor 222 of the peak amplifier 22 according to the conduction and non-conduction of the switch 23. In addition, a bias current is supplied to the bases of the transistor 312 of the peak amplifier 31 and the transistor 322 of the peak amplifier 32 according to the conduction and non-conduction of the switch 33. In contrast, a bias current is continuously supplied to the bases of the transistor 111 of the carrier amplifier 11, the transistor 121 of the carrier amplifier 12, the transistor 211 of the peak amplifier 21, the transistor 221 of the peak amplifier 22, the transistor 311 of the peak amplifier 31, and the transistor 321 of the peak amplifier 32, regardless of the conduction and non-conduction of the switches 13, 23, and 33.

[0150] exist Figure 7 In (b), a graph showing the relationship between the output power and the gain of the amplifier circuit 1C according to the modification example 3 is shown. Figure 7 (a) shows the gain characteristics of the Doherty-type amplifier circuit with respect to the output power without applying digital ET. In the Doherty-type amplifier circuit, as the input changes from a large signal to a small signal, the output impedance of the amplifier in the on state increases, so the efficiency and gain increase. On the other hand, in the amplifier circuit with the application of digital ET, as the input changes from a small signal to a large signal, the gain increases, and the gain deviation with respect to the output power increases. That is, in the amplifier circuit 1C involved in this modification, as Figure 7 As shown in (b), by synthesizing the gain characteristic obtained in the amplifier circuit to which digital ET is applied and the gain characteristic obtained in the Doherty-type amplifier circuit, it is possible to ensure a large back-off amount and reduce gain deviation with respect to output power.

[0151] Similarly, in the amplifier circuits according to the present embodiment and Modifications 1 to 3, by applying digital ET to the Doherty amplifier circuit, gain fluctuations with respect to output power can be suppressed, and thus gain variations can be reduced.

[0152] [5 Effects, etc.]

[0153] As described above, the amplifier circuit 1 involved in this embodiment is an amplifier circuit that receives a plurality of discrete power supply voltages, and includes a carrier amplifier 12, a peak amplifier 22, a synthesis circuit 40 that synthesizes a high-frequency signal output from the carrier amplifier 12 and a high-frequency signal output from the peak amplifier 22, a bias circuit 50 that supplies a first bias current to the peak amplifier 22, digital control terminals 140 and 150 that receive a digital control signal based on an envelope signal, and a switch 23 that is connected to the digital control terminals 140 and 150 and switches between connection and non-connection between the bias circuit 50 and the peak amplifier 22, and the carrier amplifier 12 and the peak amplifier 22 each include a plurality of amplifier elements that are cascade-connected.

[0154] According to this, when the input of a large signal changes to that of a small signal, the peak amplifier 22 is turned off, and the impedance of the carrier amplifier 12 turned on becomes high, so that the amplifier circuit 1 can operate with high efficiency in the low output region. On the other hand, when a large signal is input, the carrier amplifier 12 and the peak amplifier 22 operate in a state where the power supply voltage is large, so that a high-power signal can be output, and since the impedance of the load side viewed from the peak amplifier 22 is low, signal distortion can be suppressed. At this time, the supply of the first bias current to the peak amplifier 22 is controlled based on the envelope signal, so that the efficiency is optimized according to the output power of the amplifier circuit 1, and by applying digital ET to the Doherty-type amplifier circuit 1, the gain deviation with respect to the output power can be reduced.

[0155] Furthermore, for example, in the amplifier circuit 1 , the digital control signal may be a digital signal different from the serial data signal.

[0156] Thus, by supplying digital control signals in parallel, it is possible to perform high-speed variable supply of power supply voltage and high-speed on / off switching of peak amplifier 22. Therefore, it is possible to cope with wide channel bandwidths of high-frequency signals in the millimeter wave band and sub-terahertz band.

[0157] Furthermore, for example, the amplifier circuit 1 may receive a plurality of discrete power supply voltages based on the envelope signal.

[0158] According to this, the supply of the power supply voltage and the turning on and off of the peak amplifier 22 are both performed based on the envelope signal, so the efficiency of the amplifier circuit 1 is optimized with high accuracy.

[0159] In addition, for example, in the amplifier circuit 1, when the power level of the high-frequency signal input to the amplifier circuit 1 is a first power value, the switch 23 may be in a non-conducting state, and when the power level of the high-frequency signal input to the amplifier circuit 1 is a second power value greater than the first power value, the switch 23 may be in a conducting state.

[0160] As a result, at the first power value, the peak amplifier 22 is turned off, and the impedance of the carrier amplifier 12 becomes relatively large. Therefore, at the first power value, the efficiency of the amplifier circuit 1 is improved.

[0161] In addition, for example, the amplifier circuit 1 further includes a signal input terminal 110 to which a high-frequency signal is input, a power supply voltage terminal 130 to which a power supply voltage based on an envelope signal is input, and digital control terminals 140 and 150 connected to the switch 23 and to which a digital control signal is input. The carrier amplifier 12 includes transistors 121 and 122, the base of the transistor 121 is connected to the signal input terminal 110, the emitter of the transistor 121 is connected to the ground, the collector of the transistor 121 is connected to the emitter of the transistor 122, the collector of the transistor 122 is connected to the power supply voltage terminal 130 and the synthesizing circuit 40, and the base of the transistor 122 is connected to the bias circuit 50. The peak amplifier 22 has transistors 221 and 222, the base of the transistor 221 is connected to the signal input terminal 110, the emitter of the transistor 221 is connected to the ground, the collector of the transistor 221 is connected to the emitter of the transistor 222, the collector of the transistor 222 is connected to the power supply voltage terminal 130 and the synthesis circuit 40, and the base of the transistor 222 is connected to the switch 23.

[0162] In addition, for example, the amplifier circuit 1 may further include logic circuits 14 and 24 connected between the digital control terminals 140 and 150 and the switch 23 .

[0163] This allows the digital control signal to be converted into a gate signal that controls conduction and non-conduction of the switch 23 .

[0164] Furthermore, for example, in the amplifier circuit 1 , the bias current may be supplied to the bases of the transistors 121 and 221 in both the conductive state and the non-conductive state of the switch 23 .

[0165] According to this, the on-state and off-state of the carrier amplifier 12 are controlled only by the presence or absence of the bias current supplied to the transistor 122, and the on-state and off-state of the peak amplifier 22 are controlled only by the presence or absence of the bias current supplied to the transistor 222. Therefore, the control signal can be simplified.

[0166] In addition, for example, the amplifier circuit 1C involved in the modified example 3 may also include a peak amplifier 32 and a switch 33 connected to the digital control terminals 140, 150 and 160 and switching the connection and non-connection between the bias circuit 50 and the peak amplifier 32 relative to the amplifier circuit 1, the synthesis circuit 40 synthesizes the high-frequency signal output from the carrier amplifier 12, the high-frequency signal output from the peak amplifier 22 and the high-frequency signal output from the peak amplifier 32, the bias circuit 50 supplies a first bias current to the peak amplifier 22 and supplies a second bias current to the peak amplifier 32, and the carrier amplifier 12, the peak amplifiers 22 and 32 respectively include a plurality of amplifier elements connected in common source and gate.

[0167] According to this, when the input of a large signal changes to the input of a small signal, the peak amplifiers 32 and 22 are successively turned off, and the impedance on the load side viewed from the carrier amplifier 12 (and the peak amplifier) ​​in the on state becomes high, so that the amplifier circuit 1C can operate with high efficiency in the low output region (and the medium output region). In addition, the peak amplifiers 22 and 32 change to the off state in stages, so that the power difference between the output power when the peak amplifiers 22 and 32 are in the on state and the output power when the peak amplifiers 22 and 32 are in the off state, that is, the back-off amount, can be ensured to be large. On the other hand, when a large signal is input, since the carrier amplifier 12, the peak amplifiers 22 and 32 operate in a state where the power supply voltage is large, a high-power signal can be output, and since the impedance on the load side viewed from the peak amplifiers 22 and 32 is low, signal distortion can be suppressed. Thus, the supply of the first bias current to the peak amplifier 22 and the supply of the second bias current to the peak amplifier 32 are controlled based on the envelope signal, so that the efficiency is optimized according to the output power of the amplifier circuit 1C. By applying digital ET to the Doherty-type amplifier circuit 1C, the gain deviation relative to the output power can be reduced.

[0168] In addition, for example, in the amplifier circuit 1C, when the power level of the high-frequency signal input to the amplifier circuit 1C is a first power value, switches 23 and 33 are placed in a non-conducting state; when the power level of the high-frequency signal input to the amplifier circuit 1C is a second power value greater than the first power value, switch 23 is placed in a conducting state and switch 33 is placed in a non-conducting state; and when the power level of the high-frequency signal input to the amplifier circuit 1C is a third power value greater than the second power value, switches 23 and 33 are placed in a conducting state.

[0169] Accordingly, in the case of the second power value, the peak amplifier 32 is in the off state, and the impedance on the load side viewed from the carrier amplifier 12 and the peak amplifier 22 becomes relatively large. In addition, in the case of the first power value, the peak amplifiers 22 and 32 are in the off state, and the impedance on the load side viewed from the carrier amplifier 12 becomes relatively large. Therefore, at the first power value and the second power value, the efficiency of the amplifier circuit 1C is improved.

[0170] Furthermore, the communication device 4 according to the present embodiment includes the signal processing circuit 3 that processes a high-frequency signal, and the amplifier circuit 1 that transmits the high-frequency signal between the signal processing circuit 3 and an antenna.

[0171] According to this, the effect of the amplifier circuit 1 can be realized in the communication device 4.

[0172] In addition, for example, the communication device 4 may also include a tracker circuit 2 that supplies a power supply voltage to the amplifier circuit 1, and the tracker circuit 2 may include a discrete voltage generating circuit 60 that is configured to generate a plurality of discrete voltages, a voltage selecting circuit 70 that is configured to selectively output at least one of the plurality of discrete voltages to the amplifier circuit 1 based on an envelope signal, and a digital control circuit 80 that outputs a digital control signal to the voltage selecting circuit 70 and the switch 23.

[0173] (Other Implementations)

[0174] The amplifier circuit and the communication device according to the present invention have been described above based on the embodiments and the modified examples, but the amplifier circuit and the communication device according to the present invention are not limited to the above-mentioned embodiments and the modified examples. Other embodiments implemented by combining any constituent elements in the above-mentioned embodiments and the modified examples, modified examples obtained by applying various modifications that can be conceived by those skilled in the art to the above-mentioned embodiments and the modified examples without departing from the gist of the present invention, and various devices in which the above-mentioned amplifier circuit and the communication device are built-in are also included in the present invention.

[0175] For example, in the circuit configurations of the amplifier circuits and communication devices according to the above-described embodiments and modifications, another circuit element or wiring may be inserted between paths connecting the circuit elements and signal paths disclosed in the drawings.

[0176] Features of the amplifier circuit and the communication device described in the above-mentioned embodiment and modified examples are described below.

[0177] <1>

[0178] An amplifier circuit is an amplifier circuit that accepts multiple discrete power supply voltages and has:

[0179] Carrier amplifier;

[0180] 1st peak amplifier;

[0181] A synthesis circuit synthesizes the high frequency signal output from the carrier amplifier and the high frequency signal output from the first peak amplifier;

[0182] A bias circuit for supplying a first bias current to the first peak amplifier;

[0183] a digital control terminal receiving a digital control signal based on the envelope signal; and

[0184] a first switch connected to the digital control terminal and switching between connection and non-connection between the bias circuit and the first peak amplifier;

[0185] The carrier amplifier and the first peak amplifier each include a plurality of cascode-connected amplification elements.

[0186] <2>

[0187] exist <1> In the amplifier circuit described,

[0188] The digital control signal is a digital signal different from the serial data signal.

[0189] <3>

[0190] exist <1> In the amplifier circuit described,

[0191] The amplifier circuit receives the plurality of discrete power supply voltages based on the envelope signal.

[0192] <4>

[0193] exist <1> ~ <3> In the amplifier circuit described in any one of the above,

[0194] When the power level of the high frequency signal input to the amplifier circuit is a first power value, the first switch is in a non-conductive state.

[0195] When the power level of the high-frequency signal input to the amplifier circuit is a second power value greater than the first power value, the first switch is turned on.

[0196] <5>

[0197] exist <1> ~ <4> In the amplifier circuit described in any one of the above,

[0198] The amplifier circuit also has:

[0199] A signal input terminal, into which a high-frequency signal is input;

[0200] a power supply voltage terminal to which a power supply voltage based on the envelope signal is input; and

[0201] a digital control terminal connected to the first switch and receiving the digital control signal;

[0202] The carrier amplifier has:

[0203] a first amplifying element having a first control terminal, a first terminal, and a second terminal; and

[0204] The second amplifier element has a second control terminal, a third terminal and a fourth terminal,

[0205] The first control terminal is connected to the signal input terminal,

[0206] The first terminal is connected to the ground.

[0207] The second terminal is connected to the third terminal,

[0208] The fourth terminal is connected to the power supply voltage terminal and the synthesis circuit.

[0209] The second control terminal is connected to the bias circuit.

[0210] The first peak amplifier comprises:

[0211] a third amplifying element having a third control terminal, a fifth terminal, and a sixth terminal; and

[0212] The fourth amplifier element has a fourth control terminal, a seventh terminal and an eighth terminal,

[0213] The third control terminal is connected to the signal input terminal.

[0214] The fifth terminal is connected to the ground.

[0215] The sixth terminal is connected to the seventh terminal,

[0216] The eighth terminal is connected to the power supply voltage terminal and the synthesis circuit.

[0217] The fourth control terminal is connected to the first switch.

[0218] <6>

[0219] exist <5> In the amplifier circuit described,

[0220] The amplifier circuit further includes a logic circuit connected between the digital control terminal and the first switch.

[0221] <7>

[0222] exist <5> or <6> In the amplifier circuit described,

[0223] In both the conducting state and the non-conducting state of the first switch, a bias current is supplied to the first control terminal and the third control terminal.

[0224] <8>

[0225] exist <1> ~ <7> In the amplifier circuit described in any one of the above,

[0226] The amplifier circuit also has:

[0227] a second peak amplifier; and

[0228] a second switch connected to the digital control terminal and switching between connection and non-connection of the bias circuit and the second peak amplifier;

[0229] The synthesizing circuit synthesizes the high frequency signal output from the carrier amplifier, the high frequency signal output from the first peak amplifier, and the high frequency signal output from the second peak amplifier.

[0230] The bias circuit supplies the first bias current to the first peak amplifier and supplies the second bias current to the second peak amplifier.

[0231] The carrier amplifier, the first peak amplifier, and the second peak amplifier each include a plurality of cascode-connected amplification elements.

[0232] <9>

[0233] exist <8> In the amplifier circuit described,

[0234] When the power level of the high frequency signal input to the amplifier circuit is a first power value, the first switch and the second switch are in a non-conductive state.

[0235] When the power level of the high frequency signal input to the amplifier circuit is a second power value greater than the first power value, the first switch is turned on and the second switch is turned off.

[0236] When the power level of the high-frequency signal input to the amplifier circuit is a third power value greater than the second power value, the first switch is turned on and the second switch is turned on.

[0237] <10>

[0238] A communication device, comprising:

[0239] A signal processing circuit for processing high frequency signals; and

[0240] <1> ~ <9> The amplifier circuit described in any one of the above transmits the high-frequency signal between the signal processing circuit and the antenna.

[0241] <11>

[0242] exist <10> In the communication device described,

[0243] The communication device further includes a tracker circuit that supplies a power supply voltage to the amplifier circuit.

[0244] The tracker circuit has:

[0245] A discrete voltage generating circuit configured to generate a plurality of discrete voltages;

[0246] a voltage selection circuit configured to selectively output at least one of the plurality of discrete voltages to the amplifier circuit based on an envelope signal; and

[0247] The digital control circuit outputs the digital control signal to the voltage selection circuit and the first switch.

[0248] Industrial Applicability

[0249] The present invention can be widely used in communication equipment such as mobile phones as a power amplifier circuit or a communication device arranged in a front end portion that supports multiple frequency bands.

[0250] Description of Reference Numerals

[0251] 1. 1A, 1B, 1C amplifier circuit

[0252] 2.2A, 2B, 2C Tracker Circuit

[0253] 3 Signal Processing Circuit

[0254] 4, 4A, 4B, 4C Communication device

[0255] 11, 12 Carrier amplifier

[0256] 13, 23, 33 switch

[0257] 14, 14C, 24, 24C, 34C, 74 logic circuits

[0258] 21, 22, 31, 32 Peak Amplifier

[0259] 30 Phase shift circuit

[0260] 40 Synthetic Circuit

[0261] 50 Bias Circuit

[0262] 60 Discrete Voltage Generator Circuit

[0263] 70 Voltage selection circuit

[0264] 80 Digital Control Circuit

[0265] 110 Signal input terminal

[0266] 111, 112, 121, 122, 211, 212, 221, 222, 311, 312, 321, 322 transistors

[0267] 113, 123, 213, 223, 313, 323 resistors

[0268] 120 Signal output terminal

[0269] 130 Supply voltage terminal

[0270] 140, 150, 160 digital control terminals.

Claims

1. An amplifier circuit is an amplifier circuit that receives a plurality of discrete power supply voltages, and has: Carrier amplifier; 1st peak amplifier; A synthesis circuit synthesizes the high frequency signal output from the carrier amplifier and the high frequency signal output from the first peak amplifier; A bias circuit for supplying a first bias current to the first peak amplifier; A digital control terminal receives a digital control signal based on an envelope signal; and a first switch connected to the digital control terminal and switching between connection and non-connection between the bias circuit and the first peak amplifier; The carrier amplifier and the first peak amplifier each include a plurality of cascode-connected amplification elements.

2. The amplifier circuit according to claim 1, wherein: The digital control signal is a digital signal different from the serial data signal.

3. The amplifier circuit according to claim 1, wherein: The amplifier circuit receives the plurality of discrete power supply voltages based on the envelope signal.

4. The amplifier circuit according to any one of claims 1 to 3, wherein: When the power level of the high frequency signal input to the amplifier circuit is a first power value, the first switch is in a non-conductive state. When the power level of the high-frequency signal input to the amplifier circuit is a second power value greater than the first power value, the first switch is turned on.

5. The amplifier circuit according to claim 1, wherein: The amplifier circuit also has: a signal input terminal to which a high frequency signal is input; and a power supply voltage terminal to which a power supply voltage based on the envelope signal is input, The carrier amplifier has: a first amplifying element having a first control terminal, a first terminal, and a second terminal; and The second amplifier element has a second control terminal, a third terminal and a fourth terminal, The first control terminal is connected to the signal input terminal, The first terminal is connected to the ground. The second terminal is connected to the third terminal, The fourth terminal is connected to the power supply voltage terminal and the synthesis circuit. The second control terminal is connected to the bias circuit. The first peak amplifier comprises: a third amplifying element having a third control terminal, a fifth terminal, and a sixth terminal; and The fourth amplifier element has a fourth control terminal, a seventh terminal and an eighth terminal, The third control terminal is connected to the signal input terminal. The fifth terminal is connected to the ground. The sixth terminal is connected to the seventh terminal, The eighth terminal is connected to the power supply voltage terminal and the synthesis circuit. The fourth control terminal is connected to the first switch.

6. The amplifier circuit according to claim 5, wherein: The amplifier circuit further includes a logic circuit connected between the digital control terminal and the first switch.

7. The amplifier circuit according to claim 5 or 6, wherein: In both the conducting state and the non-conducting state of the first switch, a bias current is supplied to the first control terminal and the third control terminal.

8. The amplifier circuit according to any one of claims 1 to 7, wherein: The amplifier circuit also has: a second peak amplifier; and a second switch connected to the digital control terminal and switching between connection and non-connection of the bias circuit and the second peak amplifier; The synthesizing circuit synthesizes the high frequency signal output from the carrier amplifier, the high frequency signal output from the first peak amplifier, and the high frequency signal output from the second peak amplifier. The bias circuit supplies the first bias current to the first peak amplifier and supplies the second bias current to the second peak amplifier. The carrier amplifier, the first peak amplifier, and the second peak amplifier each include a plurality of cascode-connected amplification elements.

9. The amplifier circuit according to claim 8, wherein: When the power level of the high frequency signal input to the amplifier circuit is a first power value, the first switch and the second switch are in a non-conductive state. When the power level of the high frequency signal input to the amplifier circuit is a second power value greater than the first power value, the first switch is turned on and the second switch is turned off. When the power level of the high-frequency signal input to the amplifier circuit is a third power value greater than the second power value, the first switch is turned on and the second switch is turned on.

10. A communication device comprising: A signal processing circuit for processing high frequency signals; and The amplifier circuit according to any one of claims 1 to 9, wherein the high-frequency signal is transmitted between the signal processing circuit and an antenna.

11. The communication device according to claim 10, wherein: The communication device further includes a tracker circuit that supplies a power supply voltage to the amplifier circuit. The tracker circuit has: A discrete voltage generating circuit configured to generate a plurality of discrete voltages; a voltage selection circuit configured to selectively output at least one of the plurality of discrete voltages to the amplifier circuit based on an envelope signal; and The digital control circuit outputs the digital control signal to the voltage selection circuit and the first switch.

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