Multiplexer and communication equipment

Abstract

The embodiment of the invention discloses a multiplexer and communication equipment. The multiplexer comprises a transmitting port, at least one receiving port, at least one antenna port, a filter bank and a switch. The fixed end of the switch is connected with the first TDD filter in the filter bank, the first free end of the switch is connected with the output end of the second TDD filter in the filter bank, and the second free end of the switch is connected with one of the receiving ports; the transmitting port is connected with the input end of the FDD transmitting filter in the filter bank and the input end of the second TDD filter, and the output end of the FDD receiving filter in the filter bank is connected with one of the receiving ports; the output end of the FDD transmitting filter, the input end of the FDD receiving filter and the first TDD filter are respectively connected with one antenna port. By adopting the embodiment of the invention, the port multiplexing rate can be improved and the circuit area can be reduced on the premise of ensuring the reliable work of the FDD and the TDD.

Description

Multiplexer and communication device Technical Field

[0001] The embodiments of the present application relate to the field of communication technology, and in particular to a multiplexer and communication equipment. Background Art

[0002] Full-duplex technology is divided into time division duplexing (TDD) and frequency division duplexing (FDD). In devices that support both TDD and FDD, the FDD and TDD systems are prone to mutual interference, especially in the TDD receive time slot. Since the FDD transmit (TX) channel continues to work, the nonlinear spurious signals generated by the FDD transmit signal are likely to interfere with the TDD receive frequency band, thereby affecting the normal operation of the TDD receiver (RX). Therefore, in order to avoid the impact of FDD transmission on TDD reception, it is often necessary to suppress the signals of the corresponding frequency bands through multiple filters in the multiplexer. In addition, the multiplexer also needs to provide different transmit ports for FDD and TDD systems to improve the isolation between TDD and FDD, so that in the TDD receive time slot, the FDD transmit spurious signals will not leak into the TDD receive path and affect the TDD receive signal.

[0003] However, setting up two different transmission ports for TDD and FDD systems can easily lead to excessive circuit interfaces, increased circuit connections, and increased circuit area, thereby increasing the production and manufacturing costs of the equipment.

[0004] Therefore, how to improve the multiplexing rate of the transmission port and reduce the circuit area while ensuring the reliable operation of FDD and TDD is an urgent problem to be solved.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a multiplexer and a communication device, which can improve the multiplexing rate of the transmission port and reduce the circuit area while ensuring the reliable operation of FDD and TDD.

[0007] In a first aspect, an embodiment of the present application provides a multiplexer, comprising a transmitting port, at least one receiving port, at least one antenna port, a filter group and a switch; the filter group comprises a frequency division duplex (FDD) transmitting filter, an FDD receiving filter, a first time division duplex (TDD) filter and a second TDD filter; wherein the fixed end of the switch is connected to the first TDD filter, the first free end of the switch is connected to the output end of the second TDD filter, and the second free end of the switch is connected to one of the at least one receiving port; the transmitting port is connected to the input end of the FDD transmitting filter and the input end of the second TDD filter, and the output end of the FDD receiving filter is connected to one of the at least one receiving port; the output end of the FDD transmitting filter, the input end of the FDD receiving filter and the first TDD filter are respectively connected to one of the at least one antenna port.

[0008] In an embodiment of the present application, the conventional multiplexer structure is improved. The multiplexer in the embodiment of the present application is provided with only one transmit port, so that the transmit paths of the TDD and FDD systems can share one transmit port. In addition, the multiplexer in the embodiment of the present application further adds a switch between the TDD transmit path and the TDD receive path. The switch may include a fixed end and two free ends (e.g., a first free end and a second free end), and the first free end and the second free end may be located in the TDD transmit path and the TDD receive path, respectively. By switching the fixed end of the switch between the first free end and the second free end, the switching of TDD transmission and reception can be achieved. Based on the above-mentioned multiplexer architecture, when the TDD is in the transmit time slot, the second free end of the switch is connected to the fixed end. At this time, due to the physical isolation between the first free end and the second free end, a series of nonlinear spurious signals generated by the FDD transmit signal at the transmit port cannot leak into the TDD receive path, thereby avoiding the influence of FDD transmission on TDD reception. At the same time, considering that the switching frequency of the switch is high in actual applications, that is, the fixed end will quickly switch back and forth between the first free end and the second free end, there is a certain possibility that the FDD transmission spurious signal will leak into the TDD receiving path through the first free end and the second free end. Therefore, the multiplexer in the embodiment of the present application is also provided with an additional TDD filter (such as a second TDD filter) between the first free end and the transmitting port to suppress signals outside the TDD frequency band and avoid the possibility that the FDD transmission signal generated by the transmitting port will go into the TDD transmission path. In this way, compared with the solution in the prior art where TDD and FDD cannot share the transmitting port, resulting in too many interfaces, complex circuits, and large circuit area, the embodiment of the present application can improve the structure of the multiplexer to ensure that both FDD and TDD work reliably, so that the FDD and TDD systems share one transmitting port, thereby improving the multiplexing rate of the transmitting port, reducing circuit connections and circuit area, further reducing production costs, and meeting user needs.

[0009] In one possible embodiment, when the first free end of the switch is connected to the fixed end: the second TDD filter is used to receive the TDD transmit signal output by the transmit port, and to suppress signals outside the TDD transmit frequency band, and output the TDD transmit signal to the first TDD filter; the first TDD filter is used to suppress signals outside the TDD transmit frequency band, and output the TDD transmit signal to the antenna port; the frequency band of the TDD transmit signal is within the TDD transmit frequency band; when the second free end of the switch is connected to the fixed end: the first TDD filter is used to receive the TDD receive signal input by the antenna port, and to suppress signals outside the TDD receive frequency band, and output the TDD receive signal to the receive port; the frequency band of the TDD receive signal is within the TDD receive frequency band.

[0010] In an embodiment of the present application, the switching of TDD transmission and reception can be achieved by switching the fixed end of the switch between the first free end and the second free end. When the first free end is connected to the fixed end, the TDD system is in the transmission time slot. At this time, the second TDD filter can receive the TDD transmission signal output by the transmission port, suppress the signal outside the TDD transmission frequency band, and output the TDD transmission signal to the first TDD filter via the first free end and the fixed end. Subsequently, the first TDD filter suppresses the signal outside the TDD transmission frequency band and finally outputs it to the corresponding antenna port for transmission. When the second free end of the switch is connected to the fixed end, the TDD system is in the reception time slot. At this time, the first TDD filter receives the TDD reception signal input by the antenna port, suppresses the signal outside the TDD reception frequency band, and outputs the TDD reception signal to the corresponding reception port via the fixed end and the second free end. In this way, the embodiment of the present application can achieve reliable operation of TDD transmission and reception when the FDD and TDD systems share a transmission port by improving the multiplexer architecture, thereby meeting user needs.

[0011] In one possible embodiment, the second TDD filter is specifically used to suppress signals in the first frequency band and output the TDD transmit signal to the first TDD filter; the first TDD filter is specifically used to suppress signals in the second and third frequency bands and output the TDD transmit signal to the antenna port; the first frequency band, the second frequency band and the third frequency band are all outside the TDD transmit frequency band.

[0012] In the embodiment of the present application, both the first TDD filter and the second TDD filter in the multiplexer can suppress signals outside the TDD transmission frequency band, and the frequency bands suppressed by the two filters can be different. In this way, the embodiment of the present application can respectively suppress multiple interference signals outside the TDD transmission frequency band through multiple TDD filters, thereby ensuring the suppression effect of the interference signals, thereby ensuring the normal operation of TDD transmission, and reducing the difficulty of implementing a single filter.

[0013] In a possible implementation, the filter group further includes a third TDD filter; an input end of the third TDD filter is connected to the second free end of the switch, and an output end of the third TDD filter is connected to one of the at least one receiving port.

[0014] The first TDD filter is specifically used to suppress signals in the second frequency band and the third frequency band, and output the TDD receive signal to the third TDD filter; the third TDD filter is used to suppress signals in the fourth frequency band and output the TDD receive signal to the receive port; the second frequency band, the third frequency band and the fourth frequency band are all outside the TDD receive frequency band.

[0015] In an embodiment of the present application, in addition to the first TDD filter, an additional TDD filter (e.g., a third TDD filter) may be provided in the TDD receiving path. The input end of the third TDD filter is connected to the second free end of the switch, and the output end is connected to the corresponding receiving port. Both the first TDD filter and the third TDD filter can suppress signals outside the TDD receiving frequency band, and the frequency bands suppressed by the two may be different. In this way, the embodiment of the present application can suppress interference signals outside the TDD receiving frequency band respectively through multiple TDD filters, thereby ensuring the suppression effect on the interference signal, thereby ensuring the normal operation of the TDD reception, and reducing the difficulty of implementing a single filter.

[0016] In some possible embodiments, the second TDD filter and the third TDD filter may be bandpass filters or bandstop filters. A bandpass filter is a filter that passes frequency components within a certain range but attenuates most other frequency components to extremely low levels, as opposed to a bandstop filter. A bandstop filter is a filter that passes most frequency components but attenuates frequency components within a certain range to extremely low levels, as opposed to a bandpass filter.

[0017] In a possible implementation manner, the number of the at least one receiving port is one, and the receiving port is respectively connected to the output end of the FDD receiving filter and the second free end of the switch.

[0018] The receiving port is used to receive the FDD receiving signal output by the FDD receiving filter; when the second free end of the switch is connected to the fixed end, the receiving port is also used to receive the TDD receiving signal output by the first TDD filter.

[0019] In an embodiment of the present application, the multiplexer may include only one receive port, which may be connected to the FDD receive filter and the second free end of the switch, respectively. This receive port may be used to receive the FDD receive signal output by the FDD filter and the TDD receive signal output by the first TDD filter. Thus, in this embodiment of the present application, while achieving transmit port sharing, further improves the multiplexer structure to achieve sharing of TDD and FDD receive ports while ensuring reliable operation of FDD and TDD, thereby increasing the multiplexing rate of the receive ports and further reducing circuit wiring and circuit area.

[0020] In a possible implementation manner, the number of the at least one receiving port is one, and the receiving port is connected to the output end of the FDD receiving filter and the output end of the third TDD filter respectively.

[0021] The receiving port is used to receive the FDD receiving signal output by the FDD receiving filter; when the second free end of the switch is connected to the fixed end, the receiving port is also used to receive the TDD receiving signal output by the third TDD filter.

[0022] In an embodiment of the present application, the multiplexer may include only one receive port, which may be connected to the FDD receive filter and the third TDD filter, respectively. This receive port may be used to receive the FDD receive signal output by the FDD filter and the TDD receive signal output by the third TDD filter. Thus, in this embodiment of the present application, while achieving transmit port sharing, further improves the multiplexer structure to achieve sharing of TDD and FDD receive ports while ensuring reliable operation of FDD and TDD, thereby increasing the multiplexing rate of the receive ports and further reducing circuit wiring and circuit area.

[0023] In a possible implementation, the at least one receiving port includes an FDD receiving port and a TDD receiving port, the FDD receiving port is connected to the output end of the FDD receiving filter, and the TDD receiving port is connected to the second free end of the switch.

[0024] The FDD receiving port is used to receive the FDD receiving signal output by the FDD receiving filter; when the second free end of the switch is connected to the fixed end, the TDD receiving port is used to receive the TDD receiving signal output by the first TDD filter.

[0025] In an embodiment of the present application, the multiplexer may include two receive ports: an FDD receive port connected to the FDD receive filter, and a TDD receive port connected to the second free end. The FDD receive port is used to receive the FDD receive signal output by the FDD filter, and the TDD receive port is used to receive the TDD receive signal output by the first TDD filter. In this way, by providing two independent receive ports, the embodiment of the present application can increase the isolation between TDD transmission and FDD reception, thereby preventing interference of the TDD transmission signal with the FDD receive signal.

[0026] In a possible implementation, the at least one receiving port includes an FDD receiving port and a TDD receiving port, the FDD receiving port is connected to the output end of the FDD receiving filter, and the TDD receiving port is connected to the output end of the third TDD filter.

[0027] The FDD receiving port is used to receive the FDD receiving signal output by the FDD receiving filter; when the second free end of the switch is connected to the fixed end, the TDD receiving port is used to receive the TDD receiving signal output by the third TDD filter.

[0028] In an embodiment of the present application, the multiplexer may include two receive ports: an FDD receive port connected to an FDD receive filter, and a TDD receive port connected to a third TDD filter. The FDD receive port is used to receive the FDD receive signal output by the FDD filter, and the TDD receive port is used to receive the TDD receive signal output by the third TDD filter. In this way, by providing two independent receive ports, the embodiment of the present application can increase the isolation between TDD transmission and FDD reception, thereby preventing interference of the TDD transmission signal with the FDD reception signal.

[0029] In a possible implementation manner, the number of the at least one antenna port is one, and the antenna port is respectively connected to the output end of the FDD transmit filter, the input end of the FDD receive filter, and the first TDD filter.

[0030] In an embodiment of the present application, the multiplexer may include an antenna port, which may be connected to an FDD transmit filter, an FDD receive filter, and a first TDD filter, respectively, to transmit corresponding FDD transmit signals and TDD transmit signals, and to receive FDD receive signals and TDD receive signals. Thus, in addition to achieving transmit port sharing, the embodiment of the present application further achieves sharing of TDD and FDD antenna ports, thereby improving the reuse rate of the antenna ports and further reducing circuit connections and circuit area.

[0031] In one possible implementation, the at least one antenna port includes a first antenna port and a second antenna port; the first antenna port is connected to the output of the FDD transmit filter and the input of the FDD receive filter, and the second antenna port is connected to the first TDD filter.

[0032] In an embodiment of the present application, the multiplexer may include two antenna ports, namely a first antenna port and a second antenna port. The first antenna port may be connected to an FDD transmit filter and an FDD receive filter for transmitting FDD transmit signals and receiving FDD receive signals. The second antenna port is connected to a first TDD filter for transmitting TDD transmit signals and receiving TDD receive signals. In this way, the embodiment of the present application can increase the isolation between TDD and FDD by setting two independent antenna ports, ensuring normal transmission and reception of TDD and FDD, while also reducing the suppression degree and implementation difficulty of the filter.

[0033] In one possible implementation, the at least one antenna port includes a first antenna port and a second antenna port; the first antenna port is connected to the output end of the FDD transmit filter and the first TDD filter, and the second antenna port is connected to the input end of the FDD receive filter.

[0034] In an embodiment of the present application, the multiplexer may include two antenna ports, namely a first antenna port and a second antenna port. The first antenna port may be connected to an FDD transmit filter and a first TDD filter for transmitting FDD transmit signals, TDD transmit signals, and receiving TDD receive signals. The second antenna port is connected to an FDD receive filter for receiving FDD receive signals. In this way, the embodiment of the present application may increase the isolation between TDD and FDD by providing two independent antenna ports, thereby ensuring normal transmission and reception of TDD and FDD, while also reducing the suppression degree and implementation difficulty of the filter.

[0035] In one possible implementation, the at least one antenna port includes a first antenna port and a second antenna port; the first antenna port is connected to the output end of the FDD transmit filter, and the second antenna port is connected to the input end of the FDD receive filter and the first TDD filter.

[0036] In an embodiment of the present application, the multiplexer may include two antenna ports, namely a first antenna port and a second antenna port. The first antenna port may be connected to an FDD transmit filter for transmitting an FDD transmit signal. The second antenna port is connected to an FDD receive filter and a first TDD filter for receiving FDD receive signals, TDD receive signals, and transmitting TDD transmit signals. In this way, the embodiment of the present application can increase the isolation between TDD and FDD by setting two independent antenna ports, thereby ensuring normal transmission and reception of TDD and FDD, while also reducing the suppression degree and implementation difficulty of the filter.

[0037] In one possible implementation, the FDD transmit filter is used to receive the FDD transmit signal output by the transmit port, and to suppress signals outside the FDD transmit frequency band, and output the FDD transmit signal to the antenna port; the frequency band of the FDD transmit signal is within the FDD transmit frequency band; the FDD receive filter is used to receive the FDD receive signal input by the antenna port, and to suppress signals outside the FDD receive frequency band, and output the FDD receive signal to the receive port; the frequency band of the FDD receive signal is within the FDD receive frequency band.

[0038] In the embodiment of the present application, regardless of how the switches in the multiplexer are turned on, the FDD system can always transmit and receive normally. Thus, by improving the multiplexer architecture, the embodiment of the present application can achieve the sharing of a single transmit port for the FDD and TDD systems while ensuring reliable operation of both FDD and TDD. Furthermore, the FDD and TDD systems can share a single transmit port, or even a single antenna port, significantly reducing circuit wiring and circuit area, lowering manufacturing costs, and meeting user needs.

[0039] In a second aspect, an embodiment of the present application provides a communication device, which includes a transmitting circuit, a receiving circuit, an antenna system, and a multiplexer described in any one of the first aspects above; the transmitting circuit is connected to the transmitting port in the multiplexer, the receiving circuit is connected to at least one receiving port in the multiplexer, and the antenna system is connected to at least one antenna port in the multiplexer.

[0040] In a possible implementation, the antenna system includes one antenna, the number of the at least one antenna port is one, and the antenna is connected to the antenna port.

[0041] In a possible implementation, the antenna system includes a first antenna and a second antenna, and the at least one antenna port includes a first antenna port and a second antenna port; the first antenna is connected to the first antenna port, and the second antenna is connected to the second antenna port.

[0042] It should be understood that the communication device provided in the second aspect of this application is consistent with the technical solution of the first aspect of this application. Its specific content and beneficial effects can be referred to the multiplexer provided in the first aspect above, and will not be described in detail here. The communication device can be a base station with the above-mentioned structure and functions, or it can also be a terminal device, such as a smart wearable device, a smart phone, a tablet computer, a laptop computer, etc. Alternatively, the communication device can also be part of a base station and a terminal device. For example, it can be a part consisting of a transceiver and an antenna in a base station and a terminal device, etc., and the embodiments of this application do not specifically limit this.

[0043] In a third aspect, an embodiment of the present application provides a communication method, which is applied to a communication device, wherein the communication device includes a multiplexer, the multiplexer includes a transmitting port, at least one receiving port, at least one antenna port, a filter group and a switch; the filter group includes a frequency division duplex (FDD) transmitting filter, an FDD receiving filter, a first time division duplex (TDD) filter and a second TDD filter; wherein the fixed end of the switch is connected to the first TDD filter, the first free end of the switch is connected to the output end of the second TDD filter, and the second free end of the switch is connected to one of the at least one receiving port; the transmitting port is connected to the input end of the FDD transmitting filter and the input end of the second TDD filter, and the output end of the FDD receiving filter is connected to one of the at least one receiving port; the output end of the FDD transmitting filter, the input end of the FDD receiving filter and the first TDD filter are respectively connected to one of the at least one antenna port.

[0044] Controlling the first free end of the switch to be conductive with the fixed end:

[0045] receiving, through the second TDD filter, a TDD transmit signal output by the transmit port, suppressing signals outside the TDD transmit frequency band, and outputting the TDD transmit signal to the first TDD filter;

[0046] Suppressing signals outside the TDD transmit frequency band through the first TDD filter, and outputting the TDD transmit signal to the antenna port; the frequency band of the TDD transmit signal is within the TDD transmit frequency band;

[0047] Controlling the second free end of the switch to be conductive with the fixed end:

[0048] The first TDD filter receives the TDD receive signal input by the antenna port, suppresses signals outside the TDD receive frequency band, and outputs the TDD receive signal to the receive port; the frequency band of the TDD receive signal is within the TDD receive frequency band.

[0049] It should be understood that the method flow provided in the third aspect of this application is consistent with the technical solution of the first aspect of this application. Its specific content and beneficial effects can be referred to the multiplexer provided in the above-mentioned first aspect, and will not be repeated here.

[0050] In a fourth aspect, an embodiment of the present application provides a communication device, which may include: a processor and a memory, wherein the memory is used to store program code, and the processor is used to call the program code to implement the functions involved in the communication method process provided in the third aspect above. The communication device may also include a communication interface for the communication device to communicate with other devices or a communication network.

[0051] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the functions involved in the communication method process provided in the third aspect above.

[0052] In a sixth aspect, an embodiment of the present application provides a computer program, which includes instructions. When the instructions are executed by a computer, the computer can perform the functions involved in the communication method process provided in the third aspect above.

[0053] In the seventh aspect, an embodiment of the present application provides a chip, which includes a processor and a communication interface, and the processor is used to call and run instructions from the communication interface. When the processor executes the instructions, the chip performs the functions involved in a communication method process provided in the third aspect above.

[0054] In an eighth aspect, an embodiment of the present application provides a chip system, comprising the multiplexer described in any one of the first aspects above, for implementing the functions involved in the communication method process provided in the third aspect above. In one possible design, the chip system further includes a memory, which is used to store program instructions and data necessary for the communication method. The chip system can be composed of a chip or can include a chip and other discrete components. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments of the present application or the background technology will be described below.

[0056] FIG1 is a schematic diagram of a TDD operation provided in an embodiment of the present application.

[0057] FIG2 is a schematic diagram of an FDD operation according to an embodiment of the present application.

[0058] FIG3 is a schematic diagram of TDD transceiver duplexing provided in an embodiment of the present application.

[0059] FIG4 is a schematic diagram of FDD transceiver duplexing provided in an embodiment of the present application.

[0060] FIG5 a is a schematic diagram of FDD transmit / receive isolation provided in an embodiment of the present application.

[0061] FIG5 b is a schematic diagram of another FDD transmit / receive isolation provided in an embodiment of the present application.

[0062] FIG6 is a schematic diagram of the structure of a multiplexer with a common transmit port for TDD and FDD provided in an embodiment of the present application.

[0063] FIG7 is a schematic diagram of interference in a TDD receiving time slot provided in an embodiment of the present application.

[0064] FIG8 is a schematic diagram of a multiplexer structure in which TDD and FDD do not share a common antenna, provided in an embodiment of the present application.

[0065] FIG9 is a schematic diagram of a multiplexer structure with a shared antenna for TDD and FDD provided in an embodiment of the present application.

[0066] FIG10 is a schematic diagram of a system architecture provided in an embodiment of the present application.

[0067] FIG11 is a schematic structural diagram of a multiplexer provided in an embodiment of the present application.

[0068] FIG12 is a schematic structural diagram of another multiplexer provided in an embodiment of the present application.

[0069] FIG13 is a schematic structural diagram of another multiplexer provided in an embodiment of the present application.

[0070] FIG14 is a schematic structural diagram of another multiplexer provided in an embodiment of the present application.

[0071] FIG15 is a schematic structural diagram of another multiplexer provided in an embodiment of the present application.

[0072] FIG16 a is a schematic structural diagram of another multiplexer provided in an embodiment of the present application.

[0073] FIG16 b is a schematic structural diagram of another multiplexer provided in an embodiment of the present application.

[0074] FIG17 a is a schematic structural diagram of another multiplexer provided in an embodiment of the present application.

[0075] FIG17 b is a schematic structural diagram of another multiplexer provided in an embodiment of the present application.

[0076] FIG18 a is a schematic structural diagram of another multiplexer provided in an embodiment of the present application.

[0077] FIG18 b is a schematic structural diagram of another multiplexer provided in an embodiment of the present application.

[0078] FIG19 a is a schematic structural diagram of another multiplexer provided in an embodiment of the present application.

[0079] FIG19 b is a schematic structural diagram of another multiplexer provided in an embodiment of the present application.

[0080] FIG20 a is a schematic structural diagram of another multiplexer provided in an embodiment of the present application.

[0081] FIG20 b is a schematic structural diagram of another multiplexer provided in an embodiment of the present application.

[0082] FIG21 a is a schematic structural diagram of another multiplexer provided in an embodiment of the present application.

[0083] FIG21 b is a schematic structural diagram of another multiplexer provided in an embodiment of the present application.

[0084] Figure 22 is a structural diagram of a communication device provided in an embodiment of the present application.

[0085] Figure 23 is a flow chart of a communication method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0086] The embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0087] The terms "first," "second," "third," and "fourth," as well as "first," "second," "third," and "fourth" in the specification and claims of this application and the accompanying drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to the process, method, product, or apparatus.

[0088] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0089] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present invention. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute a separate or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0090] As used in this specification, the terms "component," "module," "system," and the like are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. By way of illustration, both an application running on a computing device and a computing device can be a component. One or more components can reside in a process and / or an execution thread, and a component can be located on a computer and / or distributed between two or more computers. In addition, these components can be executed from various computer-readable media having various data structures stored thereon. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0091] First, some terms in this application are explained to facilitate understanding by those skilled in the art.

[0092] (1) Full-duplex refers to simultaneous two-way communication. Both parties can send and receive data at the same time. Full-duplex technology is further divided into time division duplexing (TDD) and frequency division duplexing (FDD).

[0093] (2) Time Division Duplex. By allocating different time slots, the TDD system can use a single frequency band for transmission and reception operations. Please refer to Figure 1, which is a schematic diagram of the operation of TDD provided by an embodiment of the present application. As shown in Figure 1, the frequency bands of the uplink (i.e., transmission) and the downlink (i.e., reception) can be the same, but there is a certain time slot interval between the uplink and downlink. In some TDD systems, the uplink and downlink can be allocated equal time slots, but in actual applications, the uplink and downlink time slots can also be asymmetric.

[0094] (3) Frequency Division Duplex. The FDD system has two independent communication channels, and there needs to be sufficient spacing between the two channels to ensure that the transmission and reception do not interfere with each other. The FDD system must filter or shield the signal to ensure that the signal transmitter does not affect the adjacent receiver. Please refer to Figure 2, which is a schematic diagram of the working of FDD provided in an embodiment of the present application. As shown in Figure 2, the FDD system can transmit and receive simultaneously through two communication channels, but the frequency bands of transmission and reception are different, and there is a certain degree of isolation between the two frequency bands.

[0095] (4) Multiplexer. A component that enables multiple channels to share a single port is called a "multiplexer." Duplexers, triplexers, and quadplexers can all be collectively referred to as "multiplexers." For example, a component that enables two channels to share a single port is called a "duplexer" (e.g., one transmitter and one receiver), while a component that enables four channels to share a single port is called a "quadplexer" (e.g., two transmitters and two receivers).

[0096] It should be noted that a typical multiplexer includes a single input port and multiple output ports. However, the multiplexer provided in the embodiments of the present application combines multiple filters to support simultaneous operation of multiple frequency bands and multiple standards. Its implementation can be single-input multiple-output, multiple-input multiple-output, etc. Furthermore, the multiplexer provided in the embodiments of the present application includes a set of non-overlapping filters, which are combined in a manner that ensures that they do not load each other and have a high degree of isolation between their outputs. That is, the frequency bands suppressed by the multiple filters are different, and the frequency bands of the output signals are different.

[0097] Please refer to Figure 3, which is a schematic diagram of a TDD transceiver duplex system provided in an embodiment of the present application. As shown in Figure 3, in a TDD system, the duplexer may include a filter, an antenna (ANT) port, and a TX / RX port (TX and RX are common ports for TDD). The filter is connected to the antenna port and the TX / RX port, respectively. As shown in Figure 3, the TDD system also includes a circulator and a switch. The circulator is connected to the TX / RX port, the power amplifier (PA) in the TDD transmit channel, and one end of the switch, respectively. The other end of the switch is connected to the low noise amplifier (LNA) in the TDD receive channel. The switch is mainly used to switch between the TX and RX channels, thereby achieving time division duplexing. Exemplarily, when the switch is closed, the TDD system is in a receive time slot, and the TDD receive signal received by the antenna is filtered by the filter and then enters the LNA. Exemplarily, when the switch is open, the TDD system is in a transmit time slot, and the TDD transmit signal output by the PA is filtered by the filter and then sent out via the antenna. As mentioned above, the TDD receive signal and the TDD transmit signal have the same frequency band. The filter shown in FIG3 is used to suppress signals outside the TDD transmit / receive frequency band to ensure normal operation of transmission and reception.

[0098] Please refer to Figure 4, which is a schematic diagram of an FDD transceiver duplex provided in an embodiment of the present application. Compared with TDD, duplexers are generally used in FDD radio applications. As shown in Figure 4, in an FDD system, the duplexer is composed of two filters, filter 1 and filter 2, which are combined. The duplexer also includes an antenna port, a TX port and an RX port. Among them, filter 1 is a receiving filter and filter 2 is a transmitting filter. The input end of filter 1 is connected to the antenna port, and the output end of filter 1 is connected to the RX port. The RX port is used to connect to a receiver, for example, to an LNA in an FDD receiving channel. The output end of filter 2 is connected to the antenna port, and the input end of filter 2 is connected to the TX port. The TX port is used to connect to a transmitter, for example, to a PA in an FDD transmitting channel via a circulator. As shown in Figure 4, filter 1 and filter 2 share a common node (i.e., antenna port), allowing the device to transmit and receive simultaneously. For example, as shown in Figure 4, the FDD transmit signal output by the PA is filtered by filter 2 and sent out via the antenna. For example, as shown in Figure 4, the FDD receive signal received by the antenna is filtered by filter 1 and then enters the LNA. As mentioned above, the frequency bands of the FDD receive signal and the FDD transmit signal are different. Therefore, in the FDD system, the design of the duplexer needs to ensure that the passband of each filter does not load the other filter. In particular, the transmit filter needs to have a large suppression of the receive frequency band to ensure that the nonlinear spurious output of the PA does not interfere with the receive frequency band. This isolation is often referred to as transmit-receive isolation at the transmit frequency. For example, filter 1 shown in Figure 4 needs to suppress signals outside the FDD receive frequency band (especially suppress the FDD transmit frequency band) and output the FDD receive signal. Filter 2 needs to suppress signals outside the FDD transmit frequency band (especially suppress the FDD receive frequency band) and output the FDD transmit signal, thereby ensuring the normal operation of FDD transmission and reception.

[0099] Please refer to Figure 5a, which is a schematic diagram of FDD transmit / receive isolation provided by an embodiment of the present application. As shown in Figure 5a, if the FDD system does not include the aforementioned filters 1 and 2, the nonlinear spurious signals generated by the FDD transmission cannot be effectively suppressed. The power attenuation of the spurious signals IM3, IM5, and IM7 compared to the FDD transmission signal is only 45dB, 50dB, and 55dB, respectively. The frequency band of the spurious signal IM7 hits the FDD receiving band, thereby affecting the FDD receiving signal and interfering with the normal operation of the FDD reception.

[0100] Please refer to Figure 5b, which is another schematic diagram of FDD transmit-receive isolation provided in an embodiment of the present application. As shown in Figure 5b, when the FDD system includes the above-mentioned filter 1 and filter 2, the nonlinear spurious generated by the FDD transmission can be well suppressed by filter 1, and the spurious signals IM3, IM5, and IM7 shown in Figure 5b have been further significantly attenuated compared to Figure 5a. Among them, the power attenuation of the spurious signal IM7 compared to the FDD transmit signal is reduced by 155dB, which has almost no effect on the FDD receive signal, ensuring the normal operation of the FDD reception. Generally speaking, traditional FDD base stations require a transmit-receive isolation of more than 150dBc, especially the signal in the transmit frequency band appearing in the output of the receive filter needs to be significantly attenuated to avoid overdrive of the receive front end.

[0101] Furthermore, when a device supports both TDD and FDD, a triplexer is often required. The triplexer is composed of three filters combined, and the passband loading and isolation targets of the triplexer are the same as those of the duplexer. Please refer to Figure 6, which is a schematic diagram of the structure of a multiplexer with a common transmit port for TDD and FDD provided in an embodiment of the present application. As shown in Figure 6, the triplexer includes filter 1, filter 2, and filter 3, and adopts a traditional FDD solution to use one TX port, that is, TDD and FDD share one TX and one PA. Under the multiplexer structure shown in Figure 6, if TDD is in the receiving time slot (switch closed), the FDD system continues to work, and the PA cannot be turned off, then the nonlinear spurious output of the PA will leak into the TDD receiving path through the closed switch, affecting the normal operation of TDD reception and failing to meet the system application requirements. For example, please refer to Figure 7, which is an interference schematic diagram of a TDD receiving time slot provided in an embodiment of the present application. As shown in Figure 7, the nonlinear spurious signals of the PA can be seen as IM3, IM5, and IM7. Since there is no filter between the PA and the receiving path, IM3, IM5, and IM7 are not well suppressed. The frequency band of IM7 hits the TDD frequency band, and IM7 is not significantly attenuated. This can easily lead to an increase in the TDD uplink noise floor, affecting TDD RX operation.

[0102] Therefore, in practical applications, since FDD and TDD systems easily interfere with each other, especially in the TDD receive time slot, FDD transmit spurious signals will interfere with the TDD receive frequency band, so the total isolation between FDD TX and TDD RX often needs to meet certain requirements before it can be used. In order to facilitate the understanding of the embodiments of the present application, the technical problems to be specifically solved by this application are further analyzed and proposed. In the prior art, there are a variety of technical solutions for the multiplexer structure in the TDD+FDD scenario. The following exemplifies the two commonly used solutions.

[0103] Option 1:

[0104] Please refer to Figure 8, which is a schematic diagram of the structure of a multiplexer for TDD and FDD that do not share a common antenna, provided in an embodiment of the present application. As shown in Figure 8, the multiplexer (or triplexer) includes filter 1, filter 2, and filter 3, as well as two TX ports (TX1 and TX2), two RX ports (RX1 and RX2), and two antenna ports (ANT1 and ANT 2). Among them, ANT1 is connected to filter 1 and filter 2 in the FDD system, and ANT2 is connected to filter 3 in the TDD system. The output end of filter 1 is connected to LNA1 in the FDD receive channel via the RX1 port, the input end of filter 2 is connected to PA1 in the FDD transmit path via the TX1 port and circulator 1, and filter 3 is connected to PA2 in the TDD transmit path and LNA2 in the TDD receive path via TX2 / RX2 and circulator 2 respectively. As shown in Figure 8, in the TDD receive time slot (switch closed), PA2 stops working and will not generate spurious signals that affect TDD reception. At the same time, since there is sufficient isolation between PA1 and the TDD receive path, it will not affect TDD reception. In this way, Solution 1 ensures the normal operation of the TDD receiving time slot by setting different TX ports for the FDD and TDD systems.

[0105] Option 2:

[0106] Please refer to Figure 9, which is a schematic diagram of the structure of a multiplexer with a shared antenna for TDD and FDD provided in an embodiment of the present application. As shown in Figure 9, the multiplexer 9 includes filter 1, filter 2 and filter 3, as well as two TX ports (TX1 and TX2), two RX ports (RX1 and RX2) and an antenna port. Among them, ANT is connected to filter 1 and filter 2 in FDD and filter 3 in TDD. The specific structure of Figure 9 can refer to the description in the corresponding embodiment of Figure 8 above, and will not be repeated here. As shown in Figure 9, in the TDD receiving time slot (switch closed), PA2 stops working and will not generate spurious signals to affect TDD reception. At the same time, since there is sufficient isolation between PA1 and the TDD receiving path, it will not affect TDD reception. In this way, Solution 2 ensures the normal operation of the TDD receiving time slot by setting different TX ports for FDD and TDD systems.

[0107] Both Option 1 and Option 2 have the following disadvantages:

[0108] (1) The FDD and TDD systems each have a PA inputting two different TX ports, which cannot be reused. This results in excessive circuit interfaces and a complex system. Furthermore, the two independent PAs prevent power sharing between the FDD and TDD systems, resulting in poor flexibility.

[0109] (2) FDD and TDD systems have different RX ports, which cannot be reused, resulting in too many circuit interfaces and complex systems.

[0110] Therefore, to address the problem that the current multiplexer structure in the TDD+FDD scenario does not meet actual business needs, the technical problems actually to be solved by this application include the following aspects: By improving the multiplexer structure, while ensuring the reliable operation of FDD and TDD, FDD and TDD can share a single transmit port. Furthermore, FDD and TDD can also share a single receive port, thereby achieving sharing of the PA and LNA, greatly reducing circuit interfaces and connections, thereby reducing circuit area and lowering manufacturing costs.

[0111] Please refer to Figure 10, which is a schematic diagram of a system architecture provided in an embodiment of the present application. As shown in Figure 10, the system architecture may include a baseband 21, a transceiver 22, and an antenna system 23, which are connected in sequence. As shown in Figure 10, the transceiver 22 may include a multiplexer 10. The multiplexer 10 may include only one transmit port, which is connected to the output of the PA and is used to receive the FDD transmit signal and the TDD transmit signal output by the PA, thereby implementing a shared transmit port for FDD and TDD. Furthermore, the multiplexer 10 may also include a receive port, which is connected to the input of the LNA and is used to input the FDD receive signal and the TDD receive signal to the LNA, thereby implementing a shared receive port for FDD and TDD. As shown in Figure 10, in some implementations, the input of the PA is connected to a digital-to-analog (DA) conversion module, and the output of the LNA is connected to an analog-to-digital (AD) conversion module.

[0112] Optionally, the multiplexer 10 may also include multiple receiving terminals, which can be connected one-to-one with the input terminals of multiple LNAs to achieve sufficient isolation between FDD and TDD reception. For details, please refer to the following embodiments and will not be described in detail here. In addition, as shown in Figure 10, the multiplexer 10 may also include one or more antenna ports, which can be connected one-to-one with one or more antennas in the antenna system 23 to receive FDD receive signals and TDD receive signals, and send FDD transmit signals and TDD transmit signals through the corresponding antennas.

[0113] It should be noted that the multiplexer 10 provided in the embodiments of the present application can be applied in the field of wireless communications, specifically in communication devices such as base stations and terminal devices. The terminal devices may be, for example, smart wearable devices, smartphones, tablet computers, laptops, in-vehicle computers, servers, server clusters consisting of multiple servers, or a cloud computing service center, etc., which are not specifically limited in the embodiments of the present application. The multiplexer 10 provided in the embodiments of the present application is suitable for communication devices that need to support both TDD and FDD standards. As shown in FIG10 , the multiplexer 10 can be located at the end of the transceiver 22 in the communication device, and is used to connect the antenna system 23 with the PA, LNA, etc. By improving the multiplexer structure, the embodiments of the present application can achieve the multiplexing of a single transmit port for FDD and TDD systems while ensuring reliable operation of FDD and TDD, simplifying hardware implementation, reducing circuit area, and lowering power consumption and cost. Furthermore, the multiplexer 10 can also achieve the multiplexing of a single receive port for FDD and TDD systems, thereby significantly reducing circuit interfaces and circuit area.

[0114] Please refer to Figure 11, which is a schematic diagram of the structure of a multiplexer provided in an embodiment of the present application. As shown in Figure 11, the multiplexer 10 includes a transmitting port, at least one receiving port and at least one antenna port, and can specifically include a transmitting port 101, N receiving ports 102 and M antenna ports 103, where N and M are integers greater than or equal to 1. As shown in Figure 11, the multiplexer 10 also includes a filter group and a switch 108. The filter group can specifically include an FDD transmitting filter 104, an FDD receiving filter 105, a first TDD filter 106 and a second TDD filter 107. The switch 108 can include a fixed end (i.e., end A shown in Figure 11), a first free end (i.e., end B shown in Figure 11) and a second free end (i.e., end C shown in Figure 11). Exemplarily, the switch 108 can be a single-pole double-throw switch.

[0115] As shown in Figure 11, terminal A of switch 108 is connected to first TDD filter 106, terminal B of switch 108 is connected to the output of second TDD filter 107, and terminal C of switch 108 is connected to one of N receive ports 102. Transmit port 101 is connected to the input of FDD transmit filter 104 and the input of second TDD filter 107. The output of FDD receive filter 105 is connected to one of N receive ports 102. The output of FDD transmit filter 104, the input of FDD receive filter 105, and first TDD filter 106 are each connected to one of M antenna ports 103.

[0116] The FDD transmit filter 104 is configured to receive the FDD transmit signal output by the transmit port 101, suppress signals outside the FDD transmit frequency band, and output the FDD transmit signal to the antenna port 103. The frequency band of the FDD transmit signal is within the FDD transmit frequency band. For example, if the FDD transmit frequency band is 1-2 GHz, the frequency band of the FDD transmit signal is within the 1-2 GHz frequency band. The FDD transmit filter 104 suppresses other signals outside the 1-2 GHz frequency band. Other signals (e.g., 3-4 GHz signals, or 2-3 GHz signals, such as TDD transmit signals) are significantly attenuated after passing through the FDD transmit filter 104.

[0117] The FDD receive filter 105 is used to receive the FDD receive signal input by the antenna port 103, suppress signals outside the FDD receive frequency band, and output the FDD receive signal to the receive port 102. The frequency band of the FDD receive signal is within the FDD receive frequency band. For example, if the FDD receive frequency band is 3-4 GHz, then the frequency band of the FDD receive signal is within the 3-4 GHz frequency band. The FDD receive filter 105 will suppress other signals outside the 3-4 GHz frequency band. Other signals (such as 1-2 GHz signals, or 2-3 GHz signals, such as TDD transmit signals) will be significantly attenuated after passing through the FDD receive filter 105.

[0118] When the A and B terminals of the switch 108 are turned on:

[0119] The second TDD filter 107 is configured to receive the TDD transmit signal outputted by the transmit port 101 , suppress signals outside the TDD transmit frequency band, and output the TDD transmit signal to the first TDD filter 106 .

[0120] The first TDD filter 106 is used to suppress signals outside the TDD transmit frequency band and output the TDD transmit signal to the antenna port 103. The frequency band of the TDD transmit signal is within the TDD transmit frequency band. For example, if the TDD transmit frequency band is 2-3 GHz, the frequency band of the TDD transmit signal is within the 2-3 GHz frequency band. The second TDD filter 107 and the first TDD filter 106 will suppress other signals outside the 2-3 GHz frequency band. Other signals (for example, 1-1.5 GHz signals, or 3-4 GHz signals, such as FDD transmit signals) will be significantly attenuated after passing through the second TDD filter 107 and the first TDD filter 106. The second TDD filter is mainly used to separate the FDD transmit signal and the TDD transmit signal output by the transmit port 101, specifically by suppressing the FDD transmit signal to prevent the FDD transmit signal from flowing into the TDD transmit path.

[0121] Optionally, the second TDD filter 107 can be used to suppress signals outside the first frequency band, and the first TDD filter 106 can be used to suppress signals outside the second frequency band and the third frequency band. The first frequency band, the second frequency band, and the third frequency band are all outside the above-mentioned TDD transmission frequency band. For example, if the TDD transmission frequency band is 2-3 GHz, then the first frequency band can be 0-1.5 GHz, the second frequency band can be 1.5-2 GHz, and the third frequency band can be 3-3.5 GHz. In this way, the embodiment of the present application can suppress interference signals outside multiple TDD transmission frequency bands respectively through multiple TDD filters, thereby ensuring the suppression effect of the interference signal, thereby ensuring the normal operation of TDD transmission, and reducing the difficulty of implementing a single filter.

[0122] When the A terminal and the C terminal of the switch 108 are turned on:

[0123] The first TDD filter 106 is used to receive the TDD receive signal input by the antenna port 103, suppress signals outside the TDD receive frequency band, and output the TDD receive signal to the receive port 102. The frequency band of the TDD receive signal is within the TDD receive frequency band. As mentioned above, the TDD transmit frequency band is the same as the TDD receive frequency band. Taking 2-3 GHz as an example, the frequency band of the TDD receive signal is within the 2-3 GHz frequency band. The first TDD filter 106 will suppress other signals outside the 2-3 GHz frequency band. Other signals (for example, 1-1.5 GHz signals, or 3-4 GHz signals, etc., such as FDD transmit signals) will be significantly attenuated after passing through the first TDD filter 106.

[0124] Optionally, the switch 108 can be connected to a corresponding control circuit (not shown in the figure), which is used to output a control signal. Under the action of the control signal, the switch 108 can connect the A end and the B end, or connect the A end and the C end, thereby realizing the switching of TDD transmission and reception.

[0125] As described above, by selectively conducting the switch 108 between the B end and the C end, the isolation between the FDD and TDD systems is increased. Especially in the TDD receiving time slot (i.e., when the A end and the C end are turned on), the physical isolation between the B end and the C end can be used to effectively prevent the FDD transmission spurious signals from leaking into the TDD receiving path, thereby preventing the normal operation of the TDD reception from being affected. In addition, considering that the switching frequency of the switch 108 is relatively high in actual applications, there is a certain possibility that the FDD transmission signal and its corresponding transmission spurious signals may leak into the TDD receiving path where the C end is located via the B end of the switch 108. Therefore, the multiplexer 10 provided in the embodiment of the present application is further provided with a second TDD filter 107 between the transmitting port 101 and the B end of the switch. The second TDD filter 107 suppresses the FDD transmission signal, thereby preventing the FDD transmission signal and its corresponding transmission spurious signals from flowing into the TDD transmission path and leaking into the TDD receiving path via the B end and the C end, thereby fully ensuring the normal operation of the TDD reception.

[0126] In summary, the multiplexer 10 provided in the embodiment of the present application can enable the FDD and TDD systems to share one transmit port while ensuring the reliable operation of FDD and TDD, thereby improving the multiplexing rate of the transmit port, reducing circuit connections and circuit area, further reducing production costs, and meeting user needs.

[0127] Based on the above description of the embodiment corresponding to FIG. 11 , various possible structures of the multiplexer 10 will be described in detail below with reference to the accompanying drawings.

[0128] Embodiment 1: The multiplexer 10 includes a single transmitting port, dual receiving ports and a single antenna port.

[0129] Please refer to Figure 12, which is a schematic diagram of the structure of another multiplexer provided in an embodiment of the present application. As shown in Figure 12, the multiplexer 10 includes a transmit port, two receive ports, and an antenna port, specifically including a transmit port 101, a TDD receive port 1021, an FDD receive port 1022, and an antenna port 103. As shown in Figure 12, the multiplexer 10 also includes a filter group and a switch 108. The filter group specifically may include an FDD transmit filter 104, an FDD receive filter 105, a first TDD filter 106, and a second TDD filter 107. The switch 108 may include an A terminal, a B terminal, and a C terminal. Exemplarily, the switch 108 may be a single-pole double-throw switch.

[0130] As shown in Figure 12, terminal A of switch 108 is connected to first TDD filter 106, terminal B of switch 108 is connected to the output of second TDD filter 107, and terminal C of switch 108 is connected to TDD receive port 1021. Transmit port 101 is connected to the input of FDD transmit filter 104 and the input of second TDD filter 107. The output of FDD receive filter 105 is connected to FDD receive port 1022. The output of FDD transmit filter 104, the input of FDD receive filter 105, and first TDD filter 106 are respectively connected to antenna port 103.

[0131] Furthermore, as shown in FIG12 , the input of transmit port 101 is connected to the output of the PA, the output of TDD receive port 1021 is connected to the input of the LNA-TDD (i.e., the LNA in the TDD receive path), the output of FDD receive port 1022 is connected to the input of the LNA-FDD (i.e., the LNA in the FDD receive path), and antenna port 103 is connected to antenna 109. FDD transmit signals and TDD transmit signals of corresponding power generated by the PA can be input into the FDD transmit path and the TDD transmit path via transmit port 101.

[0132] The FDD transmit filter 104 is configured to receive the FDD transmit signal outputted by the transmit port 101 , suppress signals outside the FDD transmit frequency band, and output the FDD transmit signal to the antenna port 103 .

[0133] The antenna port 103 is used to send the FDD transmission signal through the antenna 109 .

[0134] The antenna port 103 is further configured to receive FDD signals via the antenna 109 .

[0135] The FDD receiving filter 105 is configured to receive the FDD receiving signal input from the antenna port 103 , suppress signals outside the FDD receiving frequency band, and output the FDD receiving signal to the FDD receiving port 1022 .

[0136] The FDD receiving port 1022 is used to input the FDD receiving signal into the LNA-FDD for amplification for subsequent processing.

[0137] When the A and B terminals of the switch 108 are turned on:

[0138] The second TDD filter 107 is configured to receive the TDD transmit signal outputted by the transmit port 101 , suppress signals outside the TDD transmit frequency band, and output the TDD transmit signal to the first TDD filter 106 .

[0139] The first TDD filter 106 is configured to suppress signals outside the TDD transmit frequency band and output the TDD transmit signal to the antenna port 103 .

[0140] The antenna port 103 is used to send TDD transmission signals through the antenna 109 .

[0141] When the A terminal and the C terminal of the switch 108 are turned on:

[0142] The antenna port 103 is used to receive TDD signals through the antenna 109 .

[0143] The first TDD filter 106 is configured to receive a TDD receive signal input from the antenna port 103 , suppress signals outside the TDD receive frequency band, and output the TDD receive signal to the TDD receive port 1021 .

[0144] The TDD receiving port 1021 is used to input the TDD receiving signal into the LNA-TDD for amplification for subsequent processing.

[0145] Optionally, the functions of the various parts of the multiplexer 10 shown in FIG12 may be specifically referred to the description of the embodiment corresponding to FIG11 , and will not be described in detail here.

[0146] Alternatively, please refer to Figure 13, which is a schematic diagram of the structure of another multiplexer provided in an embodiment of the present application. As shown in Figure 13, the filter bank of the multiplexer 10 may further include a third TDD filter 110, wherein the input end of the third TDD filter 110 is connected to the C end of the switch 108, and the output end of the third TDD filter 110 is connected to the TDD receiving port 1021.

[0147] When the A terminal and the C terminal of the switch 108 are turned on:

[0148] The first TDD filter 106 is configured to receive a TDD receive signal input from the antenna port 103 , suppress signals outside the TDD receive frequency band, and output the TDD receive signal to the third TDD filter 110 .

[0149] The third TDD filter 110 is configured to TDD suppress signals outside the TDD reception band and output the TDD reception signal to the TDD reception port 1021 .

[0150] Optionally, the third TDD filter 110 can be used to suppress signals outside the fourth frequency band, and the first TDD filter 106 can be used to suppress signals outside the second frequency band and the third frequency band. The second frequency band, the third frequency band and the fourth frequency band are all outside the above-mentioned TDD transmit frequency band. For example, if the TDD transmit frequency band is 2-3 GHz, then the fourth frequency band can be 3.5-5 GHz, the second frequency band can be 1.5-2 GHz, and the third frequency band can be 3-3.5 GHz. In this way, the embodiment of the present application can suppress interference signals outside multiple TDD receive frequency bands respectively through multiple TDD filters, thereby ensuring the suppression effect of the interference signal, thereby ensuring the normal operation of TDD reception, and reducing the difficulty of implementing a single filter.

[0151] As shown in Figures 12 and 13, when FDD and TDD systems share a transmit port, they can share a single PA, enabling power sharing between the two systems. For example, if the PA has a maximum output power of 200W and both FDD and TDD transmit simultaneously, the PA can allocate 120W of power to FDD and 90W to TDD. Alternatively, the PA can allocate 100W of power to FDD and 100W to TDD, and so on. When TDD is in a receive timeslot, only FDD is transmitting. The PA can allocate the full 200W of power to the FDD system, or 180W of power to the FDD system. This enables flexible power sharing between the FDD and TDD systems and reduces the number of PAs and costs.

[0152] Embodiment 2: The multiplexer 10 includes a single transmitting port, a single receiving port, and a single antenna port.

[0153] Please refer to Figure 14, which is a schematic diagram of the structure of another multiplexer provided in an embodiment of the present application. As shown in Figure 14, multiplexer 10 includes a transmit port, a receive port, and an antenna port, specifically including transmit port 101, receive port 102, and antenna port 103. As shown in Figure 14, multiplexer 10 also includes a filter bank and a switch 108. For details, please refer to the description of the embodiment corresponding to Figure 12 above, and will not be repeated here.

[0154] As shown in Figure 12, terminal A of switch 108 is connected to first TDD filter 106, terminal B of switch 108 is connected to the output of second TDD filter 107, and terminal C of switch 108 is connected to receive port 102. Transmit port 101 is connected to the input of FDD transmit filter 104 and the input of second TDD filter 107. The output of FDD receive filter 105 is connected to receive port 102. The output of FDD transmit filter 104, the input of FDD receive filter 105, and first TDD filter 106 are respectively connected to antenna port 103.

[0155] Furthermore, as shown in FIG14 , the input end of the transmitting port 101 is connected to the output end of the PA, the output end of the receiving port 102 is connected to the input end of the LNA, and the antenna port 103 is connected to the antenna 109 .

[0156] The FDD transmit filter 104 is configured to receive the FDD transmit signal outputted by the transmit port 101 , suppress signals outside the FDD transmit frequency band, and output the FDD transmit signal to the antenna port 103 .

[0157] The antenna port 103 is used to send the FDD transmission signal through the antenna 109 .

[0158] The antenna port 103 is further configured to receive FDD signals via the antenna 109 .

[0159] The FDD receiving filter 105 is configured to receive the FDD receiving signal input from the antenna port 103 , suppress signals outside the FDD receiving frequency band, and output the FDD receiving signal to the receiving port 102 .

[0160] The receiving port 102 is used to input the FDD receiving signal into the LNA for amplification for subsequent processing.

[0161] When the A and B terminals of the switch 108 are turned on:

[0162] The second TDD filter 107 is configured to receive the TDD transmit signal outputted by the transmit port 101 , suppress signals outside the TDD transmit frequency band, and output the TDD transmit signal to the first TDD filter 106 .

[0163] The first TDD filter 106 is configured to suppress signals outside the TDD transmit frequency band and output the TDD transmit signal to the antenna port 103 .

[0164] The antenna port 103 is used to send TDD transmission signals through the antenna 109 .

[0165] When the A terminal and the C terminal of the switch 108 are turned on:

[0166] The antenna port 103 is used to receive TDD signals through the antenna 109 .

[0167] The first TDD filter 106 is configured to receive a TDD receive signal input from the antenna port 103 , suppress signals outside the TDD receive frequency band, and output the TDD receive signal to the receive port 102 .

[0168] The receiving port 102 is used to input the TDD receiving signal into the LNA for amplification for subsequent processing.

[0169] Optionally, the functions of the various parts of the multiplexer 10 shown in FIG14 may be specifically described in the corresponding embodiment of FIG12 , and will not be described in detail here.

[0170] Alternatively, refer to FIG15 , which is a schematic diagram of the structure of another multiplexer provided in an embodiment of the present application. As shown in FIG15 , the filter bank of the multiplexer 10 may further include a third TDD filter 110 , wherein the input end of the third TDD filter 110 is connected to the C end of the switch 108 , and the output end of the third TDD filter 110 is connected to the receiving port 102 .

[0171] When the A terminal and the C terminal of the switch 108 are turned on:

[0172] The first TDD filter 106 is configured to receive a TDD receive signal input from the antenna port 103 , suppress signals outside the TDD receive frequency band, and output the TDD receive signal to the third TDD filter 110 .

[0173] The third TDD filter 110 is configured to TDD suppress signals outside the TDD receiving frequency band and output the TDD receiving signal to the receiving port 102 .

[0174] Optionally, the functions of the various parts of the multiplexer 10 shown in FIG15 may be specifically described in the description of the embodiment corresponding to FIG13 above, and will not be repeated here.

[0175] As shown in Figures 14 and 15, when the FDD and TDD systems share a transmit port, the embodiments of the present application can further realize the sharing of TDD and FDD receive ports and the sharing of LNAs, thereby improving the multiplexing rate of the receive ports and further reducing circuit connections, circuit area and production costs.

[0176] Furthermore, as shown in Figures 14 and 15 , when FDD and TDD systems can share a single transmit port and a single receive port, the interface configuration of the multiplexer 10 is the same as that of a conventional FDD multiplexer (shown in Figure 4 ), with one transmit port and one receive port. This allows the multiplexer 10 to be fabricated as a single printed circuit board (PCB), enabling it to be used by both FDD and TDD systems, enhancing the multiplexer's flexible reusability.

[0177] Embodiment 3: The multiplexer 10 includes a single transmitting port, dual receiving ports and dual antenna ports.

[0178] (1) TDD and FDD RX share the same antenna

[0179] Please refer to Figure 16a, which is a schematic diagram of the structure of another multiplexer provided in an embodiment of the present application. As shown in Figure 16a, multiplexer 10 includes a transmit port, two receive ports, and two antenna ports, specifically including transmit port 101, TDD receive port 1021, FDD receive port 1022, antenna port 1031, and antenna port 1032. As shown in Figure 16a, multiplexer 10 also includes a filter bank and switch 108. For details, please refer to the description of the embodiment corresponding to Figure 12 above, and will not be repeated here.

[0180] As shown in Figure 16a, the output of FDD transmit filter 104 is connected to antenna port 1031, and the input of FDD receive filter 105 and first TDD filter 106 are respectively connected to antenna port 1032. Antenna port 1031 is connected to antenna 1091, and antenna port 1032 is connected to antenna 1092. The connection structure of multiplexer 10 shown in Figure 16a can be specifically described with reference to the description of the embodiment corresponding to Figure 12 above, and will not be repeated here.

[0181] The antenna port 1031 is used to receive the FDD transmit signal output by the FDD transmit filter 104 and send the FDD transmit signal through the antenna 1091 .

[0182] The antenna port 1032 is configured to receive an FDD receive signal through the antenna 1092 and input the FDD receive signal to the FDD receive filter 105 .

[0183] When the A and B terminals of the switch 108 are turned on:

[0184] The antenna port 1032 is used to receive the TDD transmit signal output by the first TDD filter 106 and send the TDD transmit signal through the antenna 1092 .

[0185] When the A terminal and the C terminal of the switch 108 are turned on:

[0186] The antenna port 1032 is configured to receive a TDD receive signal through the antenna 1092 and input the TDD receive signal to the first TDD filter 106 .

[0187] Optionally, the functions of the various parts of the multiplexer 10 shown in FIG16 a may be specifically described in the corresponding embodiment of FIG12 , and will not be repeated here.

[0188] Please refer to Figure 16b, which is a schematic diagram of the structure of another multiplexer provided in an embodiment of the present application. As shown in Figure 16b, the filter bank of multiplexer 10 may further include a third TDD filter 110. The input end of third TDD filter 110 is connected to the C end of switch 108, and the output end of third TDD filter 110 is connected to TDD receive port 1021. The specific function of third TDD filter 110 can be found in the description of the embodiment corresponding to Figure 13 above, and will not be repeated here.

[0189] (2) TDD and FDD TX share the same antenna

[0190] Please refer to Figure 17a, which is a schematic diagram of the structure of another multiplexer provided in an embodiment of the present application. As shown in Figure 17a, multiplexer 10 includes a transmit port, two receive ports, and two antenna ports, specifically including transmit port 101, TDD receive port 1021, FDD receive port 1022, antenna port 1031, and antenna port 1032. As shown in Figure 17a, multiplexer 10 also includes a filter bank and switch 108. For details, please refer to the description of the embodiment corresponding to Figure 12 above, and will not be repeated here.

[0191] As shown in Figure 17a, the output of FDD transmit filter 104 and first TDD filter 106 are respectively connected to antenna port 1031, and the input of FDD receive filter 105 is connected to antenna port 1032. Antenna port 1031 is connected to antenna 1091, and antenna port 1032 is connected to antenna 1092. The connection structure of multiplexer 10 shown in Figure 17a can be referred to the description of the embodiment corresponding to Figure 12 above, and will not be repeated here.

[0192] The antenna port 1031 is used to receive the FDD transmit signal output by the FDD transmit filter 104 and send the FDD transmit signal through the antenna 1091 .

[0193] The antenna port 1032 is configured to receive an FDD receive signal through the antenna 1092 and input the FDD receive signal to the FDD receive filter 105 .

[0194] When the A and B terminals of the switch 108 are turned on:

[0195] The antenna port 1031 is used to receive the TDD transmit signal output by the first TDD filter 106 and send the TDD transmit signal through the antenna 1091 .

[0196] When the A terminal and the C terminal of the switch 108 are turned on:

[0197] The antenna port 1031 is configured to receive a TDD receive signal through the antenna 1091 and input the TDD receive signal to the first TDD filter 106 .

[0198] Optionally, the functions of the various parts in the multiplexer 10 shown in FIG17 a may be specifically described in the description of the embodiment corresponding to FIG12 above, and will not be repeated here.

[0199] Please refer to Figure 17b, which is a schematic diagram of the structure of another multiplexer provided in an embodiment of the present application. As shown in Figure 17b, the filter bank of multiplexer 10 may further include a third TDD filter 110. The input end of third TDD filter 110 is connected to the C end of switch 108, and the output end of third TDD filter 110 is connected to TDD receive port 1021. The specific function of third TDD filter 110 can be found in the description of the embodiment corresponding to Figure 13 above, and will not be repeated here.

[0200] (3) FDD TX and FDD RX share the same antenna

[0201] Please refer to Figure 18a, which is a schematic diagram of the structure of another multiplexer provided in an embodiment of the present application. As shown in Figure 18a, multiplexer 10 includes a transmit port, two receive ports, and two antenna ports, specifically including transmit port 101, TDD receive port 1021, FDD receive port 1022, antenna port 1031, and antenna port 1032. As shown in Figure 18a, multiplexer 10 also includes a filter bank and switch 108. For details, please refer to the description of the embodiment corresponding to Figure 12 above, and will not be repeated here.

[0202] As shown in Figure 18a, the output of FDD transmit filter 104 and the input of FDD receive filter 105 are respectively connected to antenna port 1031, and first TDD filter 106 is connected to antenna port 1032. Antenna port 1031 is connected to antenna 1091, and antenna port 1032 is connected to antenna 1092. The connection structure of multiplexer 10 shown in Figure 18a can be referred to the description of the embodiment corresponding to Figure 12 above, and will not be repeated here.

[0203] The antenna port 1031 is used to receive the FDD transmit signal output by the FDD transmit filter 104 and send the FDD transmit signal through the antenna 1091 .

[0204] The antenna port 1031 is further configured to receive an FDD receive signal via the antenna 1091 and input the FDD receive signal to the FDD receive filter 105 .

[0205] When the A and B terminals of the switch 108 are turned on:

[0206] The antenna port 1032 is used to receive the TDD transmit signal output by the first TDD filter 106 and send the TDD transmit signal through the antenna 1092 .

[0207] When the A terminal and the C terminal of the switch 108 are turned on:

[0208] The antenna port 1032 is configured to receive a TDD receive signal through the antenna 1092 and input the TDD receive signal to the first TDD filter 106 .

[0209] Optionally, the functions of the various parts of the multiplexer 10 shown in FIG18 a may be specifically described in the description of the embodiment corresponding to FIG12 above, and will not be repeated here.

[0210] Please refer to Figure 18b, which is a schematic diagram of the structure of another multiplexer provided in an embodiment of the present application. As shown in Figure 18b, the filter bank of multiplexer 10 may further include a third TDD filter 110. The input end of third TDD filter 110 is connected to the C end of switch 108, and the output end of third TDD filter 110 is connected to TDD receive port 1021. The specific function of third TDD filter 110 can be found in the description of the embodiment corresponding to Figure 13 above, and will not be repeated here.

[0211] Embodiment 4: The multiplexer 10 includes a single transmitting port, a single receiving port and dual antenna ports.

[0212] (1) TDD and FDD RX share the same antenna

[0213] Please refer to Figure 19a, which is a schematic diagram of the structure of another multiplexer provided in an embodiment of the present application. As shown in Figure 19a, multiplexer 10 includes a transmit port, a receive port, and two antenna ports, specifically transmit port 101, receive port 102, antenna port 1031, and antenna port 1032. As shown in Figure 19a, multiplexer 10 also includes a filter bank and switch 108. For details, please refer to the description of the embodiment corresponding to Figure 14 above, and will not be repeated here.

[0214] As shown in Figure 19a, the output of FDD transmit filter 104 is connected to antenna port 1031, and the inputs of first TDD filter 106 and FDD receive filter 105 are respectively connected to antenna port 1032. Antenna port 1031 is connected to antenna 1091, and antenna port 1032 is connected to antenna 1092. The connection structure of multiplexer 10 shown in Figure 19a can be referred to the description of the embodiment corresponding to Figure 14 above, and will not be repeated here.

[0215] The antenna port 1031 is used to receive the FDD transmit signal output by the FDD transmit filter 104 and send the FDD transmit signal through the antenna 1091 .

[0216] The antenna port 1032 is configured to receive an FDD receive signal through the antenna 1092 and input the FDD receive signal to the FDD receive filter 105 .

[0217] When the A and B terminals of the switch 108 are turned on:

[0218] The antenna port 1032 is used to receive the TDD transmit signal output by the first TDD filter 106 and send the TDD transmit signal through the antenna 1092 .

[0219] When the A terminal and the C terminal of the switch 108 are turned on:

[0220] The antenna port 1032 is configured to receive a TDD receive signal through the antenna 1092 and input the TDD receive signal to the first TDD filter 106 .

[0221] Optionally, the functions of the various parts in the multiplexer 10 shown in FIG19 a may be specifically described in the corresponding embodiment of FIG14 above, and will not be repeated here.

[0222] Please refer to Figure 19b, which is a schematic diagram of the structure of another multiplexer provided in an embodiment of the present application. As shown in Figure 19b, the filter bank of multiplexer 10 may further include a third TDD filter 110. The input end of third TDD filter 110 is connected to the C end of switch 108, and the output end of third TDD filter 110 is connected to receive port 102. The specific function of third TDD filter 110 can be found in the description of the embodiment corresponding to Figure 15 above, and will not be repeated here.

[0223] (2) TDD and FDD TX share the same antenna

[0224] Please refer to Figure 20a, which is a schematic diagram of the structure of another multiplexer provided in an embodiment of the present application. As shown in Figure 20a, multiplexer 10 includes a transmit port, a receive port, and two antenna ports, specifically transmit port 101, receive port 102, antenna port 1031, and antenna port 1032. As shown in Figure 20a, multiplexer 10 also includes a filter bank and switch 108. For details, please refer to the description of the embodiment corresponding to Figure 14 above, and will not be repeated here.

[0225] The antenna port 1031 is used to receive the FDD transmit signal output by the FDD transmit filter 104 and send the FDD transmit signal through the antenna 1091 .

[0226] The antenna port 1032 is configured to receive an FDD receive signal through the antenna 1092 and input the FDD receive signal to the FDD receive filter 105 .

[0227] When the A and B terminals of the switch 108 are turned on:

[0228] The antenna port 1031 is used to receive the TDD transmit signal output by the first TDD filter 106 and send the TDD transmit signal through the antenna 1091 .

[0229] When the A terminal and the C terminal of the switch 108 are turned on:

[0230] The antenna port 1031 is configured to receive a TDD receive signal through the antenna 1091 and input the TDD receive signal to the first TDD filter 106 .

[0231] Optionally, the functions of the various parts of the multiplexer 10 shown in FIG20 a may be specifically described in the description of the embodiment corresponding to FIG14 above, and will not be repeated here.

[0232] Please refer to Figure 20b, which is a schematic diagram of the structure of another multiplexer provided in an embodiment of the present application. As shown in Figure 20b, the filter bank of multiplexer 10 may further include a third TDD filter 110. The input end of third TDD filter 110 is connected to the C end of switch 108, and the output end of third TDD filter 110 is connected to receive port 102. The specific function of third TDD filter 110 can be found in the description of the embodiment corresponding to Figure 15 above, and will not be repeated here.

[0233] (3) FDD TX and FDD RX share the same antenna

[0234] Please refer to Figure 21a, which is a schematic diagram of the structure of another multiplexer provided in an embodiment of the present application. As shown in Figure 21a, multiplexer 10 includes a transmit port, a receive port, and two antenna ports, specifically transmit port 101, receive port 102, antenna port 1031, and antenna port 1032. As shown in Figure 21a, multiplexer 10 also includes a filter bank and switch 108. For details, please refer to the description of the embodiment corresponding to Figure 14 above, and will not be repeated here.

[0235] As shown in Figure 21a, the output of FDD transmit filter 104 and the input of FDD receive filter 105 are respectively connected to antenna port 1031, and first TDD filter 106 is connected to antenna port 1032. Antenna port 1031 is connected to antenna 1091, and antenna port 1032 is connected to antenna 1092. The connection structure of multiplexer 10 shown in Figure 21a can be referred to the description of the embodiment corresponding to Figure 14 above, and will not be repeated here.

[0236] The antenna port 1031 is used to receive the FDD transmit signal output by the FDD transmit filter 104 and send the FDD transmit signal through the antenna 1091 .

[0237] The antenna port 1031 is further configured to receive an FDD receive signal via the antenna 1091 and input the FDD receive signal to the FDD receive filter 105 .

[0238] When the A and B terminals of the switch 108 are turned on:

[0239] The antenna port 1032 is used to receive the TDD transmit signal output by the first TDD filter 106 and send the TDD transmit signal through the antenna 1092 .

[0240] When the A terminal and the C terminal of the switch 108 are turned on:

[0241] The antenna port 1032 is configured to receive a TDD receive signal through the antenna 1092 and input the TDD receive signal to the first TDD filter 106 .

[0242] Optionally, the functions of the various parts of the multiplexer 10 shown in FIG21a may be specifically described in the corresponding embodiment of FIG14 above, and will not be repeated here.

[0243] Please refer to Figure 21b, which is a schematic diagram of the structure of another multiplexer provided in an embodiment of the present application. As shown in Figure 19b, the filter bank of multiplexer 10 may also include a third TDD filter 110. The input end of third TDD filter 110 is connected to the C end of switch 108, and the output end of third TDD filter 110 is connected to receive port 102. The specific function of third TDD filter 110 can be found in the description of the embodiment corresponding to Figure 15 above, and will not be repeated here.

[0244] As shown in FIG. 16 a to FIG. 21 b , the multiplexer 10 in the embodiment of the present application can be provided with two antenna ports to form air interface isolation of multiple frequency bands, thereby reducing the suppression degree of the filter and simplifying the difficulty of implementing the filter.

[0245] In summary, the embodiment of the present application has made structural innovations to the conventional multiplexer in the FDD+TDD scenario. By setting a switch and a TDD filter between the switch and the transmit port, the isolation between TDD reception and FDD transmission is improved, and the TDD receive time slot and the influence of FDD transmit spurious on the TDD receive signal are avoided, so that FDD and TDD can share a transmit port, reducing circuit wiring and circuit area. On the other hand, the embodiment of the present application separates the original TDD filter (for example, the filter 3 shown in Figure 8) into three filters (a first TDD filter, a second TDD filter, and a third TDD filter) by setting a switch. The first TDD filter mainly supports multiplexing with the FDD system and supports far-end spurious suppression, while the second TDD filter and the third TDD filter matched with the first TDD filter respectively support transmit spurious suppression and receive blocking suppression, with smaller overall loss and more conducive to realizing FDD and TDD sharing a receive port. Compared with the traditional solution that relies on only one filter to simultaneously support the suppression of transmitted spurious signals and received blocking signals, which results in the filter being difficult to implement, having many orders, and having large losses, the embodiments of the present application can reduce the difficulty of implementing a single filter and ensure the suppression effect.

[0246] Based on the multiplexer 10 described in the above embodiment, further, an embodiment of the present application also provides a communication device. Please refer to Figure 22, which is a structural diagram of a communication device provided in an embodiment of the present application. As shown in Figure 22, the communication device 30 includes a transmitting circuit 31, a receiving circuit 32, an antenna system 33, and a multiplexer 10. Among them, the transmitting circuit 31 can be connected to the transmitting port 101 of the multiplexer 10, the receiving circuit 32 can be connected to at least one receiving port in the multiplexer 10 (for example, N receiving ports 102), and the antenna system 33 can be connected to at least one antenna port in the multiplexer 10 (for example, M antenna ports 103). Optionally, the transmitting circuit 31 may include the above-mentioned PA, the receiving circuit 32 may include the above-mentioned LNA, and so on.

[0247] Optionally, the antenna system 33 includes an antenna, such as the antenna 109 shown in FIG. 12 , and the multiplexer 10 includes an antenna port, such as the antenna port 103 , and the antenna 109 is connected to the antenna port 103 .

[0248] Optionally, the antenna system 33 includes two antennas, a first antenna and a second antenna, such as antenna 1091 and antenna 1092 shown in Figure 16a, and the multiplexer 10 includes an antenna port, such as antenna port 1031 and antenna port 1032, the antenna 1091 is connected to antenna port 1031, and the antenna 1092 is connected to antenna port 1032.

[0249] Optionally, the communication device 30 further includes a control circuit, which is connected to the multiplexer 10 , specifically connected to the switch 108 in the multiplexer 10 , and is configured to output a control signal to control the switch 108 to be selectively turned on.

[0250] Optionally, the structure and functions of the communication device 30 may be specifically described in the description of the embodiments corresponding to Figures 10-21b above, and will not be further elaborated here. The communication device 30 may be a base station having the above-described structure and functions, or may be a terminal device, such as a smart wearable device, a smartphone, a tablet computer, a laptop computer, etc. Alternatively, the communication device may be a portion of a base station or a terminal device. For example, it may be a portion consisting of a transceiver and an antenna in a base station or a terminal device, etc., which is not specifically limited in the present embodiment of the application.

[0251] Based on the description of the above device embodiment, the present application also provides a communication method. Please refer to Figure 23, which is a schematic flow chart of a communication method provided in an embodiment of the present application. This communication method can be applied to the communication device 30 shown in Figure 22 above. The communication device 30 includes at least a multiplexer 10, which may include a transmit port, at least one receive port, at least one antenna port, a filter bank, and a switch, etc. For details, please refer to the description of the corresponding embodiments of Figures 11-21b above. The method may include the following steps S501-S505.

[0252] Step S501 : The first free end and the fixed end of the control switch are connected.

[0253] Step S502: receiving the TDD transmit signal outputted from the transmit port through the second TDD filter, suppressing signals outside the TDD transmit frequency band, and outputting the TDD transmit signal to the first TDD filter.

[0254] Step S503: Suppress signals outside the TDD transmit frequency band through the first TDD filter, and output the TDD transmit signal to the antenna port.

[0255] The frequency band of the TDD transmission signal is within the TDD transmission frequency band.

[0256] Step S504 , the second free end of the control switch is connected to the fixed end.

[0257] Step S505 : receiving the TDD receiving signal inputted from the antenna port through the first TDD filter, suppressing the signal outside the TDD receiving frequency band, and outputting the TDD receiving signal to the receiving port.

[0258] The frequency band of the TDD reception signal is within the TDD reception frequency band.

[0259] Thus, in the communication method provided in the embodiment of the present application, reliable switching between TDD transmission and TDD reception can be achieved by controlling the selective conduction of the fixed end of the switch between the two free ends. Moreover, based on the physical isolation between the two free ends of the switch, it is possible to effectively prevent the signals in the TDD transmission path and the TDD reception path from leaking into each other's paths. In particular, it is possible to effectively prevent the FDD transmission signal and the series of nonlinear spurious signals generated by it from leaking into the TDD reception path when FDD and TDD share a transmission port. Thus, compared with the solution in the prior art where TDD and FDD cannot share a transmission port, resulting in too many interfaces, complex circuits, and large circuit area, the embodiment of the present application can achieve the premise of ensuring that both FDD and TDD work reliably, so that the FDD and TDD systems share a transmission port, thereby improving the multiplexing rate of the transmission port, reducing circuit connections and circuit area, further reducing production costs, and meeting user needs.

[0260] Optionally, the communication method may be specifically described with reference to the description of the embodiments corresponding to Figures 11 to 21b above, and will not be repeated here. The communication method may be implemented in hardware, or in a combination of software and hardware. Among them, the hardware implementation may include logic circuits, algorithm circuits, or analog circuits. The software implementation may include program instructions, which can be regarded as a software product, stored in a memory, and can be executed by a processor to implement relevant functions.

[0261] The present application also provides a computer-readable storage medium, wherein the computer-readable storage medium may store a program, and when the program is executed by a processor, the processor may perform some or all of the steps of any one of the above method embodiments. The storage medium may include: a USB flash drive, a mobile hard drive, a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM), etc., which can store program code.

[0262] An embodiment of the present application also provides a computer program, which includes instructions. When the computer program is executed by a multi-core processor, the processor can execute some or all of the steps of any one of the above method embodiments.

[0263] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0264] It should be noted that, for the sake of simplicity, the aforementioned method embodiments are described as a series of action combinations. However, those skilled in the art should be aware that this application is not limited by the order of the actions described, because according to this application, certain steps may be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all preferred embodiments, and the actions and modules involved are not necessarily required by this application.

[0265] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A multiplexer, characterized in that: The multiplexer includes a transmitting port, at least one receiving port, at least one antenna port, a filter group and a switch; the filter group includes a frequency division duplex (FDD) transmitting filter, an FDD receiving filter, a first time division duplex (TDD) filter and a second TDD filter; wherein, The fixed end of the switch is connected to the first TDD filter, the first free end of the switch is connected to the output end of the second TDD filter, and the second free end of the switch is connected to one of the at least one receiving port; the transmit port is connected to the input end of the FDD transmit filter and the input end of the second TDD filter, and the output end of the FDD receive filter is connected to one of the at least one receiving port; the output end of the FDD transmit filter, the input end of the FDD receive filter, and the first TDD filter are respectively connected to one of the at least one antenna port.

2. The multiplexer according to claim 1, wherein: When the first free end of the switch is connected to the fixed end: The second TDD filter is configured to receive the TDD transmit signal output by the transmit port, suppress signals outside the TDD transmit frequency band, and output the TDD transmit signal to the first TDD filter; The first TDD filter is configured to suppress signals outside the TDD transmit frequency band and output the TDD transmit signal to the antenna interface; The frequency band of the TDD transmission signal is within the TDD transmission frequency band; When the second free end of the switch is connected to the fixed end: The first TDD filter is used to receive the TDD receive signal input by the antenna port, and to suppress signals outside the TDD receive frequency band, and output the TDD receive signal to the receive port; the frequency band of the TDD receive signal is within the TDD receive frequency band.

3. The multiplexer according to claim 2, wherein: The second TDD filter is specifically configured to suppress signals in the first frequency band and output the TDD transmit signal to the first TDD filter; The first TDD filter is specifically used to suppress signals in the second frequency band and the third frequency band, and output the TDD transmit signal to the antenna port; the first frequency band, the second frequency band and the third frequency band are all outside the TDD transmit frequency band.

4. The multiplexer according to claim 3, wherein: The filter group further includes a third TDD filter; an input end of the third TDD filter is connected to the second free end of the switch, and an output end of the third TDD filter is connected to one of the at least one receiving port.

5. The multiplexer according to claim 4, wherein: The first TDD filter is specifically configured to suppress signals in the second frequency band and the third frequency band, and output the TDD receive signal to the third TDD filter; The third TDD filter is used to suppress signals in a fourth frequency band and output the TDD receive signal to the receive port; the second frequency band, the third frequency band and the fourth frequency band are all outside the TDD receive frequency band.

6. The multiplexer according to any one of claims 1 to 3, wherein: The number of the at least one receiving port is one, and the receiving port is respectively connected to the output end of the FDD receiving filter and the second free end of the switch.

7. The multiplexer according to claim 6, wherein: The receiving port is used to receive the FDD receiving signal output by the FDD receiving filter; When the second free end of the switch is connected to the fixed end, the receiving port is further configured to receive the TDD receiving signal output by the first TDD filter.

8. The multiplexer according to any one of claims 4 to 5, wherein: The number of the at least one receiving port is one, and the receiving port is respectively connected to the output end of the FDD receiving filter and the output end of the third TDD filter.

9. The multiplexer according to claim 8, wherein: The receiving port is used to receive the FDD receiving signal output by the FDD receiving filter; When the second free end of the switch is connected to the fixed end, the receiving port is further configured to receive the TDD receiving signal output by the third TDD filter.

10. The multiplexer according to any one of claims 1 to 3, wherein: The at least one receiving port includes an FDD receiving port and a TDD receiving port, the FDD receiving port is connected to the output end of the FDD receiving filter, and the TDD receiving port is connected to the second free end of the switch.

11. The multiplexer according to claim 10, wherein: The FDD receiving port is used to receive the FDD receiving signal output by the FDD receiving filter; When the second free end of the switch is connected to the fixed end, the TDD receiving port is used to receive the TDD receiving signal output by the first TDD filter.

12. The multiplexer according to any one of claims 4 to 5, characterized in that: The at least one receiving port includes an FDD receiving port and a TDD receiving port. The FDD receiving port is connected to the output end of the FDD receiving filter, and the TDD receiving port is connected to the output end of the third TDD filter.

13. The multiplexer according to claim 12, wherein: The FDD receiving port is used to receive the FDD receiving signal output by the FDD receiving filter; When the second free end of the switch is connected to the fixed end, the TDD receiving port is used to receive the TDD receiving signal output by the third TDD filter.

14. The multiplexer according to any one of claims 1 to 13, wherein: The number of the at least one antenna port is one, and the antenna port is respectively connected to the output end of the FDD transmit filter, the input end of the FDD receive filter, and the first TDD filter.

15. The multiplexer according to any one of claims 1 to 13, characterized in that: The at least one antenna port includes a first antenna port and a second antenna port; the first antenna port is connected to the output end of the FDD transmit filter and the input end of the FDD receive filter, and the second antenna port is connected to the first TDD filter.

16. The multiplexer according to any one of claims 1 to 13, wherein: The at least one antenna port includes a first antenna port and a second antenna port; the first antenna port is connected to the output end of the FDD transmit filter and the first TDD filter, and the second antenna port is connected to the input end of the FDD receive filter.

17. The multiplexer according to any one of claims 1 to 13, wherein: The at least one antenna port includes a first antenna port and a second antenna port; the first antenna port is connected to the output end of the FDD transmit filter, and the second antenna port is connected to the input end of the FDD receive filter and the first TDD filter.

18. The multiplexer according to any one of claims 1 to 17, wherein: The FDD transmit filter is configured to receive the FDD transmit signal output by the transmit port, suppress signals outside the FDD transmit frequency band, and output the FDD transmit signal to the antenna port; the frequency band of the FDD transmit signal is within the FDD transmit frequency band; The FDD receiving filter is used to receive the FDD receiving signal input by the antenna port, and to suppress signals outside the FDD receiving frequency band, and output the FDD receiving signal to the receiving port; the frequency band of the FDD receiving signal is within the FDD receiving frequency band.

19. A communication device, characterized in that: The communication device includes a transmitting circuit, a receiving circuit, an antenna system, and a multiplexer described in any one of claims 1 to 14; the transmitting circuit is connected to a transmitting port in the multiplexer, the receiving circuit is connected to at least one receiving port in the multiplexer, and the antenna system is connected to at least one antenna port in the multiplexer.

20. The communication device according to claim 19, wherein The antenna system includes an antenna, and the number of the at least one antenna port is one; the antenna is connected to the antenna port.

21. The communication device according to claim 19, wherein: The antenna system includes a first antenna and a second antenna, and the at least one antenna port includes a first antenna port and a second antenna port; the first antenna is connected to the first antenna port, and the second antenna is connected to the second antenna port.

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