Semiconductor memory device and method for manufacturing semiconductor memory device

Abstract

According to one embodiment, a semiconductor memory device includes a substrate, a transistor, a stacked body, a columnar body, and a source line. The transistor is disposed on the substrate. The laminated body is formed by alternately laminating a plurality of gate electrode layers and a plurality of insulating layers layer by layer in a first direction. The columnar body includes an insulating core, a channel layer, and a memory film. The source line is disposed between the laminate and the substrate, and extends in at least a second direction intersecting the first direction. The columnar body has: a first end in contact with the source line; and a second end located on the opposite side of the first end in the first direction. The width of the first end in the second direction is larger than the width of the second end in the second direction.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing the semiconductor memory device. Background Art

[0002] There is known a semiconductor memory device including a stacked body in which word lines and insulating layers are alternately stacked, a memory column penetrating the stacked body, and a source line connected to the memory column.

[0003] Background Art Literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2018-142654 Summary of the invention

[0006] [Problems to be solved by the invention]

[0007] Embodiments of the present invention provide a semiconductor memory device and a method for manufacturing a semiconductor memory device that can improve manufacturability.

[0008] [Technical means to solve the problem]

[0009] A semiconductor memory device of an embodiment includes: a substrate, a transistor, a laminate, a columnar body, and a source line. The transistor is provided on the substrate. The laminate is arranged on the opposite side of the substrate relative to the transistor. The laminate is formed by stacking multiple gate electrode layers and multiple insulating layers alternately one by one in a first direction. The columnar body extends in the laminate along the first direction. The columnar body includes: an insulating core; a channel layer arranged between the multiple gate electrode layers and the insulating core; and a storage film arranged between the multiple gate electrode layers and the channel layer. The source line is arranged between the laminate and the substrate, and extends at least in a second direction intersecting the first direction. The columnar body includes: a first end connected to the source line; and a second end located on the opposite side of the first end in the first direction. The width of the first end in the second direction is larger than the width of the second end in the second direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a block diagram showing a part of the configuration of the semiconductor memory device according to the first embodiment.

[0011] Figure 2 This is a diagram showing an equivalent circuit of a part of the memory cell array according to the first embodiment.

[0012] Figure 3 It is a cross-sectional view showing a part of the semiconductor memory device according to the first embodiment.

[0013] Figure 4 Yes means Figure 3 FIG. 4 is a cross-sectional view of a region of the semiconductor memory device shown in FIG.

[0014] Figure 5 yes Figure 4 FIG. 1 is a cross-sectional view of the semiconductor memory device taken along line F5 - F5 .

[0015] Figure 6 Yes means Figure 4 FIG. 4 is a cross-sectional view of a region of the semiconductor memory device shown in FIG.

[0016] Figure 7 yes Figure 3 FIG. 1 is a cross-sectional view of the semiconductor memory device taken along line F7-F7.

[0017] Figure 8 Yes means Figure 7 FIG. 4 is a cross-sectional view of a region of the semiconductor memory device shown in FIG.

[0018] Fig. 9 It is a diagram showing the flow of the method for manufacturing the semiconductor memory device according to the first embodiment.

[0019] Fig. 10A It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment. Fig. 10B It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment. Fig. 10C It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment. Fig. 10D It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment. Fig. 10E It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment. Fig.10F It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment. Figure 10G It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment. Fig. 10H It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment. Fig.10I It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment. Fig.10J It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment. Figure 10K It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment. Fig.10L It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment. Figure 10MIt is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment. Fig.10N It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment. Fig.10O It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0020] Figure 10P It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0021] Fig.11 It is a cross-sectional view showing a part of the semiconductor memory device according to the second embodiment.

[0022] Fig.12 It is a cross-sectional view showing a part of the semiconductor memory device according to the third embodiment.

[0023] Fig.13 It is a cross-sectional view showing a part of the semiconductor memory device according to the fourth embodiment.

[0024] Fig.14 It is a diagram showing the flow of a method for manufacturing a semiconductor memory device according to a fourth embodiment.

[0025] Fig.15 It is a cross-sectional view showing a part of the semiconductor memory device according to the fifth embodiment.

[0026] Fig.16 It is a plan view schematically showing a part of the semiconductor storage device according to the sixth embodiment.

[0027] Fig.17 yes Fig.16 FIG. 1 is a cross-sectional view of the semiconductor memory device taken along line F17 - F17 . DETAILED DESCRIPTION

[0028] Hereinafter, a semiconductor memory device and a method for manufacturing a semiconductor memory device according to an embodiment will be described with reference to the drawings. In the following description, components having the same or similar functions are denoted by the same reference numerals. Moreover, repeated descriptions of these components are sometimes omitted. In the following description, reference symbols with numbers or letters at the end for distinguishing them may have the numbers or letters at the end omitted when they are not distinguishable from each other.

[0029] The so-called "parallel", "orthogonal", or "same" may include "approximately parallel", "approximately orthogonal", or "approximately the same", respectively. The so-called "connection" is not limited to mechanical connection, and may include electrical connection. In other words, the so-called "connection" is not limited to the situation where two elements as connection objects are directly connected, and may include the situation where the two elements are connected with other elements interposed in the middle. The so-called "annular" is not limited to a circular ring shape, and may include a rectangular ring shape or a triangular ring shape. The so-called "adjacent" is not limited to the situation where two elements are in contact, and may include the situation where two elements are separated from each other (for example, the situation where other elements are interposed between the two elements).

[0030] The X direction, Y direction, and Z direction are defined. The X direction is the word line WL described later (see Figure 3 ) extending in the direction. The Y direction is a direction intersecting (for example, orthogonal to) the X direction. The Y direction is a direction of the bit line BL (see Figure 7 ) extending in the direction. The Z direction is a direction intersecting (for example, orthogonal to) the X direction and the Y direction. The Z direction is a thickness direction of the semiconductor substrate 21 described later (see Figure 3 ). In the following description, the side where the laminate 51 is located when viewed from the semiconductor substrate 21 is sometimes referred to as "above", and the opposite side is referred to as "below". In addition, in the following description, the position in the Z direction is sometimes referred to as "height". However, these expressions are for the convenience of explanation and do not specify the direction of gravity. The Z direction is an example of the "first direction". The X direction is an example of the "second direction". The Y direction is an example of the "third direction". In addition, in some figures, the number of conductive layers 61 and the like are simplified for the convenience of explanation.

[0031] (First embodiment)

[0032] <1. Configuration of semiconductor memory device>

[0033] Figure 1 This is a block diagram showing a part of the structure of a semiconductor memory device 1. The semiconductor memory device 1 is, for example, a nonvolatile semiconductor memory device, and is a NAND flash memory. The semiconductor memory device 1 can be connected to an external host device, for example, and used as a storage space of the host device. The semiconductor memory device 1 includes, for example: a memory cell array 11, a command register 12, an address register 13, a control circuit (sequencer) 14, a driver module 15, a row decoder module 16, and a sense amplifier module 17.

[0034] The memory cell array 11 includes a plurality of blocks BLK0 to BLK(k-1) (k is an integer greater than 1). The block BLK is a collection of a plurality of memory cell transistors that store data non-volatilely. The block BLK is used as a unit of erasing data. A plurality of bit lines and a plurality of word lines are provided in the memory cell array 11. Each memory cell transistor is associated with one bit line and one word line.

[0035] The command register 12 holds the command CMD received from the host device by the semiconductor memory device 1. The address register 13 holds the address information ADD received from the host device by the semiconductor memory device 1. The control circuit 14 is a circuit for controlling various operations of the semiconductor memory device 1. For example, the control circuit 14 executes a data write operation, a data read operation, or an erase operation based on the command CMD held in the command register 12.

[0036] The driver module 15 includes a voltage generating circuit, and generates voltages used in various operations of the semiconductor memory device 1. The row decoder module 16 transmits the voltage applied to the signal line corresponding to the selected word line to the selected word line. The sense amplifier module 17 applies a desired voltage to each bit line in a write operation. In a read operation, the sense amplifier module 17 determines the data value stored in each memory cell transistor based on the voltage of each bit line, and transmits the determination result as read data DAT to the host device.

[0037] <2. Electrical structure of memory cell array>

[0038] Next, the electrical structure of the memory cell array 11 will be described.

[0039] Figure 2 1 is a diagram showing an equivalent circuit of a part of the memory cell array 11 . Figure 2 1 indicates one block BLK included in the memory cell array 11. The block BLK includes a plurality of (eg, four) character string units SU0 to SUQ (Q is an integer greater than or equal to 1).

[0040] Each string unit SU includes a plurality of NAND strings NS associated with bit lines BL0 to BLm (m is an integer greater than 1). Each NAND string NS includes, for example, a plurality of memory cell transistors MT0 to MTn (n is an integer greater than 1), one or more drain side selection transistors STD, and one or more source side selection transistors STS.

[0041] In each NAND string NS, memory cell transistors MT0 to MTn are connected in series. Each memory cell transistor MT includes a control gate and a charge storage unit. The control gate of the memory cell transistor MT is connected to any one of the word lines WL0 to WLn. Each memory cell transistor MT stores charge in the charge storage unit according to the voltage applied to the control gate through the word line WL, and maintains the data value in a non-volatile manner.

[0042] The drain of the drain-side selection transistor STD is connected to the bit line BL corresponding to the NAND string NS. The source of the drain-side selection transistor STD is connected to one end of the memory cell transistors MT0 to MTn connected in series. The control gate of the drain-side selection transistor STD is connected to any one of the drain-side selection gate lines SGD0 to SGDQ. The drain-side selection transistor STD is electrically connected to the row decoder module 16 via the drain-side selection gate line SGD. When a predetermined voltage is applied to the corresponding drain-side selection gate line SGD, the drain-side selection transistor STD connects the NAND string NS and the bit line BL.

[0043] The drain of the source side selection transistor STS is connected to the other end of the memory cell transistors MT0 to MTn connected in series. The source of the source side selection transistor STS is connected to the source line SL. The control gate of the source side selection transistor STS is connected to the source side selection gate line SGS. When a predetermined voltage is applied to the source side selection gate line SGS, the source side selection transistor STS connects the NAND string NS and the source line SL.

[0044] In the same block BLK, the control gates of the memory cell transistors MT0 to MTn are connected in common to the corresponding word lines WL0 to WLn. The control gates of the drain-side selection transistors STD in each string unit SU0 to SUQ are connected in common to the corresponding selection gate lines SGD0 to SGDQ. The control gates of the source-side selection transistors STS are connected in common to the selection gate line SGS. In the memory cell array 11, the bit line BL is shared by the NAND strings NS assigned the same column address in each string unit SU.

[0045] <3. Physical structure of semiconductor memory device>

[0046] Next, the physical structure of semiconductor memory device 1 will be described.

[0047] Figure 3 2 is a cross-sectional view showing a part of the semiconductor memory device 1. The semiconductor memory device 1 includes a first chip 2, a second chip 3, and an electrical connection portion 110, for example.

[0048] <3.1 First Chip>

[0049] First, the first chip 2 will be described. The first chip 2 is a circuit chip including a peripheral circuit 22. The first chip 2 includes a semiconductor substrate 21, a peripheral circuit 22, and a first insulating portion 23, for example.

[0050] The semiconductor substrate 21 is, for example, a substrate serving as a base of the first chip 2. At least a portion of the semiconductor substrate 21 is in a plate shape extending along the X direction and the Y direction. The semiconductor substrate 21 is, for example, formed of a semiconductor material such as silicon. The semiconductor substrate 21 is an example of a "substrate".

[0051] The peripheral circuit 22 is a circuit for making the memory cell array 11 function. The peripheral circuit 22 includes one or more of the command register 12, the address register 13, the control circuit 14, the driver module 15, the row decoder module 16, and the sense amplifier module 17. The peripheral circuit 22 includes, for example, a CMOS (Complementary Metal Oxide Semiconductor) circuit. The peripheral circuit 22 includes, for example, a plurality of transistors 31, a plurality of contacts 32, a multilayer wiring layer 33, and a plurality of through holes 34.

[0052] A plurality of transistors 31 are provided on the semiconductor substrate 21. The transistor 31 is, for example, a field effect transistor. In the present embodiment, the transistor 31 is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The transistor 31 includes, for example, a source region and a drain region formed on the upper surface of the semiconductor substrate 21.

[0053] The plurality of contacts 32 are conductive and extend in the Z direction. Each contact 32 is in contact with a source region, a drain region, or a gate electrode of the transistor 31. The multilayer wiring layer 33 is disposed above the plurality of transistors 31. The multilayer wiring layer 33 is disposed separately at a plurality of heights. Each wiring layer 33 includes a plurality of wirings 33a extending in the X direction or the Y direction. The plurality of wirings 33a include wirings 333a connected to the contacts 32. Each through hole 34 extends in the Z direction and connects two wirings 33a disposed at different heights.

[0054] The first insulating portion 23 is an insulating portion provided on the semiconductor substrate 21. The first insulating portion 23 covers a plurality of transistors 31, a plurality of contacts 32, a multilayer wiring layer 33, and a plurality of through holes 34. The first insulating portion 23 is formed, for example, of an insulating material such as silicon oxide. The first insulating portion 23 is formed, for example, of silicon oxide formed using TEOS (tetraethoxysilane (Si(OC2H5)4) gas. The first insulating portion 23 has a first surface (first bonding surface) S1 bonded to the second chip 3. In the present embodiment, there is no metal pad (e.g., copper pad) bonded to the second chip 3 on the first surface S1.

[0055] <3.2 Second chip>

[0056] Next, the second chip 3 will be described. The second chip 3 is an array chip including a memory cell array 11. The second chip 3 includes, for example, the memory cell array 11, an upper wiring portion 100, a second insulating portion 42, a third insulating portion 43, and a plurality of pads 44. Here, the second insulating portion 42, the third insulating portion 43, and the plurality of pads 44 will be described, and the memory cell array 11 and the upper wiring portion 100 will be described later.

[0057] The second insulating portion 42 is an insulating portion that forms a part of the outer profile of the second chip 3. The second insulating portion 42 covers the lower portion of the memory cell array 11. The second insulating portion 42 is formed of an insulating material such as silicon oxide, for example. The second insulating portion 42 is formed of silicon oxide formed by using TEOS gas, for example. The second insulating portion 42 has a second surface (second bonding surface) S2 bonded to the first chip 2. In the present embodiment, there is no metal pad (for example, a copper pad) bonded to the first chip 2 on the second surface S2.

[0058] In the present embodiment, the second surface S2 of the second insulating portion 42 is bonded to the first surface S1 of the first insulating portion 23 of the first chip 2. For example, the first surface S1 of the first insulating portion 23 is overlapped with the second surface S2 of the second insulating portion 42, and the first insulating portion 23 and the second insulating portion 42 are integrated by heating to a predetermined temperature and applying pressure. Thus, the first chip 2 and the second chip 3 are bonded. After the first chip 2 and the second chip 3 are bonded, the boundary between the first insulating portion 23 and the second insulating portion 42 disappears. As a result, the first insulating portion 23 and the second insulating portion 42 exist as one insulating portion IN.

[0059] The third insulating portion 43 is an insulating portion that forms another part of the outer profile of the second chip 3. The third insulating portion 43 covers the top of the memory cell array 11. The third insulating portion 43 is formed of an insulating material such as silicon oxide, for example. The third insulating portion 43 is formed of silicon oxide formed using TEOS gas, for example. The third insulating portion 43 has a third surface S3 located on the opposite side of the second surface S2.

[0060] The pads 44 are pads for external connection exposed outside the semiconductor memory device 1. The plurality of pads 44 are provided, for example, on the third surface S3 of the third insulating portion 43. The pads 44 are pads for signal input, signal output, signal input / output, or power supply, for example.

[0061] <4. Physical structure of memory cell array>

[0062] Next, the physical structure of the memory cell array 11 will be described.

[0063] like Figure 3 As shown, the memory cell array 11 includes a stacked body 51, an insulating layer 52, an insulating layer 53, a source line SL, a plurality of upper contacts 54, a plurality of memory pillars 55, a plurality of bit lines BL, a plurality of contacts 56, a plurality of contacts 81, and a plurality of dividing portions ST (see Figure 7 ), and a plurality of upper cutouts SHE (refer to Figure 7 ).

[0064] <4.1 Laminated body>

[0065] First, the laminated body 51 will be described. The laminated body 51 is arranged on the opposite side of the semiconductor substrate 21 with respect to the plurality of transistors 31 .

[0066] Figure 4 Yes means Figure 3 The cross-sectional view of the region surrounded by the line F4 of the memory cell array 11 is shown. The laminate 51 includes a plurality of conductive layers 61 and a plurality of insulating layers 62. The plurality of conductive layers 61 and the plurality of insulating layers 62 are alternately laminated one by one in the Z direction.

[0067] The conductive layer 61 is in a layer shape along the X direction and the Y direction. Each conductive layer 61 is formed of a conductive material such as tungsten, for example. The conductive layer 61 is an example of a "gate electrode layer".

[0068] One or more (e.g., multiple) conductive layers 61 disposed at the top of the multiple conductive layers 61 function as drain-side selection gate lines SGD. The drain-side selection gate lines SGD are provided in common for a plurality of storage pillars 55 arranged in the X direction or the Y direction. The intersection of the drain-side selection gate lines SGD and the channel layers 72 (described later) of the respective storage pillars 55 functions as the aforementioned drain-side selection transistors STD.

[0069] One or more (e.g., multiple) conductive layers 61 located at the bottom of the multiple conductive layers 61 function as source side selection gate lines SGS. The source side selection gate lines SGS are provided in common to a plurality of storage pillars 55 arranged in the X direction or the Y direction. The intersection of the source side selection gate lines SGS and the channel layer 72 of each storage pillar 55 functions as the source side selection transistor STS.

[0070] The remaining conductive layers 61 sandwiched between the conductive layers 61 functioning as the drain side selection gate line SGD or the source side selection gate line SGS in the multi-layer conductive layers 61 function as word lines WL. The word lines WL are provided in common with the plurality of storage columns 55 arranged in the X direction and the Y direction. In the present embodiment, the intersection of the word lines WL and the channel layer 72 of each storage column 55 functions as a storage cell transistor MT. The storage cell transistor MT will be described in detail later.

[0071] The insulating layer 62 is an interlayer insulating film provided between two conductive layers 61 adjacent to each other in the Z direction to insulate the two conductive layers 61. The insulating layer 62 is a layer extending along the X direction and the Y direction. The insulating layer 62 is formed of an insulating material such as silicon oxide.

[0072] <4.2 Insulation layer>

[0073] The insulating layer 52 is an insulating layer disposed between the laminate 51 and the source line SL. The insulating layer 52 is formed of an insulating material such as silicon oxide, for example. The insulating layer 52 is formed of silicon oxide formed using TEOS gas, for example. For example, the thickness of the insulating layer 52 in the Z direction is preferably greater than the thickness of the insulating layer 62 included in the laminate 51 in the Z direction.

[0074] <4.3 Insulation layer>

[0075] The insulating layer 53 is an insulating layer disposed above the laminate 51. The insulating layer 53 is formed of an insulating material such as silicon oxide, for example. The insulating layer 53 is formed of silicon oxide formed using TEOS gas, for example. For example, the thickness of the insulating layer 53 in the Z direction is greater than the thickness of the insulating layer 62 included in the laminate 51 in the Z direction.

[0076] <4.4 Source Line>

[0077] The source line SL is arranged between the laminate 51 and the semiconductor substrate 21. From another point of view, the source line SL is arranged between the storage column 55 described later and the semiconductor substrate 21. The source line SL extends at least in the second direction. The source line SL is formed of a conductive material. For example, the source line SL contains at least one of silicon and tungsten. In the present embodiment, as described in detail later, there is no copper pad and copper wiring in the step of forming the source line SL. Therefore, heat treatment and the like can be performed without worrying about the diffusion of the copper material. For example, in the case where the source line SL is formed of silicon, the source line SL can be heat treated at a desired temperature, thereby crystallizing the silicon of the source line SL to form polycrystalline silicon. As a result, the conductivity of the source line SL and the connectivity to the storage column 55 are improved.

[0078] In this embodiment, the source line SL is a plate-shaped conductive layer extending in the X direction and the Y direction (see Figure 3 and Figure 7 ). For example, the source line SL extends in a manner that covers a plurality of storage pillars 55 arranged along the X direction and below a plurality of storage pillars 55 arranged along the Y direction. In the present embodiment, the source line SL has an upper surface (joining surface) 65a to which the lower ends of the plurality of storage pillars 55 are connected. The upper surface 65a is along the X direction and the Y direction. The upper surface 65a includes: a first portion 65aa located below the storage pillar 55, and a second portion 65ab offset from below the storage pillar 55. The second portion 65ab is located below the multilayer conductive layer 61. The first portion 65aa and the second portion 65ab are located on the same surface.

[0079] <4.5 Upper contact>

[0080] The upper contact (upper connection portion) 54 is arranged on the opposite side of the source line SL with respect to the laminate 51. From another point of view, the upper contact 54 is arranged on the opposite side of the source line SL with respect to the memory column 55. The upper contact 54 is a conductive connection portion for connecting the memory column 55 and the bit line BL.

[0081] The upper contact 54 has a lower end 54a and an upper end 54b. The lower end 54a is connected to the storage column 55. The upper end 54b is located on the opposite side of the lower end 54a in the Z direction. In this embodiment, the upper contact 54 is in the shape of an inverted frustum. The outer diameter of the upper contact 54 (that is, the width in the X direction or the Y direction) decreases as it moves downward. The width W54a of the lower end 54a in the X direction is smaller than the width W54b of the upper end 54b in the X direction.

[0082] <4.6 Storage column>

[0083] Next, the storage column 55 is described. The storage column 55 extends in the Z direction and penetrates the laminate 51 and the insulating layers 52 and 53. The storage column 55 is, for example, cylindrical or truncated cone-shaped. In the present application, "cylindrical" or "truncated cone-shaped" may also include a case where the storage column 55 has a maximum outer diameter portion in the middle of the Z direction. The storage column 55 is an example of a "columnar body".

[0084] The storage column 55 has a lower end 55a and an upper end 55b. The lower end 55a is connected to the source line SL. The upper end 55b is located on the opposite side of the lower end 55a in the Z direction. The upper end 55b is connected to the upper contact 54. In this embodiment, the width W55a of the lower end 55a in the X direction is larger than the width W55b of the upper end 55b in the X direction. The lower end 55a is an example of the "first end". The upper end 55b is an example of the "second end". Here, the width W55a of the lower end 55a can be defined as the width of the portion 55s1 in the X direction that is opposite to the bottom conductive layer 61 in the multi-layer conductive layer 61 in the storage column 55, for example. In addition, the width W55b of the upper end 55b can be defined as the width of the portion 55s2 in the X direction that is opposite to the top conductive layer 61 in the multi-layer conductive layer 61 in the storage column 55, for example. Therefore, “the width W55a of the lower end 55a of the storage column 55 in the X direction is larger than the width W55b of the upper end 55b of the storage column 55 in the X direction”, for example, means that the width of part 55s1 of the storage column 55 in the X direction is larger than the width of part 55s2 of the storage column 55 in the X direction.

[0085] In this embodiment, the memory column 55 has a maximum outer diameter portion (maximum width portion) 55m, a first portion 55n1, and a second portion 55n2. The maximum outer diameter portion 55m is a portion having the largest outer diameter (that is, the width in the X direction or the Y direction) in the memory column 55. In this embodiment, the maximum outer diameter portion 55m is located below the center of the memory column 55 in the Z direction.

[0086] The first portion 55n1 is a constricted portion located between the lower end 55a and the maximum outer diameter portion 55m, where the outer diameter of the storage column 55 decreases as it moves downward. The second portion 55n2 is an expanded portion located between the upper end 55b and the maximum outer diameter portion 55m, where the outer diameter of the storage column 55 increases as it moves downward. In the present embodiment, the length L2 of the second portion 55n2 in the Z direction is greater than the length L1 of the first portion 55n1 in the Z direction.

[0087] Figure 5 yes Figure 4 The memory column 55 includes, for example, a memory film (multilayer film) 71, a channel layer 72, an insulating core 73, and a first cover portion 74 (see FIG. Figure 4 ), and the second cover portion 75 (refer to Figure 4 ).

[0088] The memory film 71 is provided on the outer peripheral side of the channel layer 72. The memory film 71 is located between the multi-layer conductive layer 61 and the channel layer 72. The memory film 71 includes, for example, a tunnel insulating film 71i, a charge trapping film 71j, and a blocking insulating film 71k.

[0089] The tunnel insulating film 71i is provided between the channel layer 72 and the charge trapping film 71j. The tunnel insulating film 71i is, for example, in a ring shape along the outer peripheral surface of the channel layer 72, and extends along the channel layer 72 in the Z direction. For example, the tunnel insulating film 71i covers the entire length of the storage column 55 in the Z direction. The tunnel insulating film 71i is a potential barrier between the channel layer 72 and the charge trapping film 71j. The tunnel insulating film 71i includes silicon oxide, or silicon oxide and silicon nitride.

[0090] The charge capture film 71j is disposed on the outer peripheral side of the tunnel insulating film 71i. The charge capture film 71j is located between the tunnel insulating film 71i and the blocking insulating film 71k. The charge capture film 71j extends along the Z direction, for example, throughout the entire length of the storage column 55 in the Z direction. The charge capture film 71j is a functional film having a plurality of crystal defects (capture energy levels) and capable of capturing charges in the crystal defects. The charge capture film 71j is formed of, for example, silicon nitride. The portion of the charge capture film 71j adjacent to each word line WL is an example of a "charge storage unit" that can store information by accumulating charges.

[0091] The blocking insulating film 71k is disposed on the outer peripheral side of the charge capture film 71j. The blocking insulating film 71k is located between the multilayer conductive layer 61 and the charge capture film 71j. The blocking insulating film 71k is an insulating film that suppresses reverse tunneling. Reverse tunneling is a phenomenon in which charges are injected from the word line WL into the charge capture film 71j. The blocking insulating film 71k extends along the Z direction and covers the entire length of the storage column 55 in the Z direction. The blocking insulating film 71k is, for example, a laminated structure film having a plurality of insulating films such as a silicon oxide film or a metal oxide film. An example of a metal oxide is aluminum oxide. The blocking insulating film 71k may include a high dielectric constant material (High-k material) such as silicon nitride or hafnium oxide.

[0092] The channel layer 72 is disposed on the inner side of the storage film 71. The channel layer 72 is formed in a ring shape. The channel layer 72 extends along the Z direction, for example, throughout the entire length of the storage column 55 in the Z direction). The channel layer 72 is formed of a semiconductor material such as polysilicon. The channel layer 72 may be doped with impurities. When a voltage is applied to the word line WL, the channel layer 72 forms a channel to electrically connect the bit line BL to the source line SL.

[0093] Thus, at the same height as each word line WL, a MANOS (Metal-Al-Nitride-Oxide-Silicon) type memory cell transistor MT is formed through the end of the word line WL adjacent to the memory pillar 55, the blocking insulating film 71k, the charge trapping film 71j, the tunnel insulating film 71i, and the channel layer 72. In addition, the memory film 71 may have a floating gate type charge storage part (floating gate electrode) as a charge storage part instead of the charge trapping film 71j. The floating gate electrode is formed of, for example, polysilicon containing impurities.

[0094] The insulating core 73 is provided inside the channel layer 72. The insulating core 73 fills a part of the inside of the channel layer 72. The insulating core 73 is formed of an insulating material such as silicon oxide. A part of the insulating core 73 may be formed in a ring shape along the inner circumference of the channel layer 72, and has a space portion (air gap) S inside.

[0095] like Figure 4 As shown in FIG. 1 , the insulating core 73 extends along the Z direction and covers most of the storage column 55 in the Z direction except the upper end and the lower end of the storage column 55. In the present embodiment, the lower end 73a of the insulating core 73 is away from the source line SL and is located above the source line SL. Similarly, the upper end 73b of the insulating core 73 is away from the upper contact 54 and is located below the upper contact 54.

[0096] The first cover portion 74 is disposed at the lower end portion of the storage column 55. The first cover portion 74 is disposed at least between the insulating core 73 and the source line SL. For example, the first cover portion 74 is disposed between the lower end 73a of the insulating core 73 and the source line SL. The first cover portion 74 is disposed on the inner peripheral side of the storage film 71 and is connected to the channel layer 72. In addition, the first cover portion 74 and the source line SL can be formed simultaneously by the same process. The first cover portion 74 contains polycrystalline silicon doped with impurities. The first cover portion 74 activates and diffuses the impurities by performing a heat treatment after doping the impurities. The first cover portion 74 is an example of a "first connecting portion". Impurities are, for example, phosphorus, arsenic, or antimony, but are not limited to these.

[0097] Figure 6 Yes means Figure 4 1 is a cross-sectional view of the region surrounded by line F6 of the memory cell array 11 shown in FIG. 1. In the present embodiment, the one or more source side selection gate lines SGS include: one or more (e.g., multiple) first source side selection gate lines SGS-1, and one or more (e.g., multiple) second source side selection gate lines SGS-2. The second source side selection gate line SGS-2 is arranged between the first source side selection gate line SGS-1 and the source line SL.

[0098] The first source side selection gate line SGS-1 is a conductive layer to which a predetermined voltage (first voltage) is applied when the NAND string NS and the source line SL are electrically connected. The second source side selection gate line SGS-2 is a conductive layer to which a predetermined voltage (first voltage) is applied when the NAND string NS and the source line SL are electrically connected. In addition, the second source side selection gate line SGS-2 is a conductive layer to which a predetermined high voltage (second voltage higher than the first voltage) is applied when erasing the data value of the memory cell transistor MT contained in the written NAND string NS. For example, by applying a predetermined high voltage to the second source side selection gate line SGS-2, holes are generated in the channel layer 72 through the gate-induced drain leakage current (GIDL), and the charges accumulated in the memory cell transistor MT are extracted through the generated holes. As a result, the memory cell transistor MT is in an erased state.

[0099] In this embodiment, the impurities doped in the first cover portion 74 are diffused by heat treatment. For example, Figure 6 The region R surrounded by the double-dashed line in shows the region where the impurities are diffused by the heat treatment of the first cover portion 74. In the present embodiment, part of the impurities are diffused by the heat treatment, and thus are also included in the portion 72s adjacent to the second source side selection gate line SGS-2 in the channel layer 72. According to such a configuration, holes formed by GIDL are easily generated in the channel layer 72 during the data erasing operation.

[0100] (Connection Structure between Storage Pillar and Source Line)

[0101] Next, the connection structure between the memory column 55 and the source line SL will be described.

[0102] In the present embodiment, the storage film 71 (for example, each of the tunnel insulating film 71i, the charge trapping film 71j, and the blocking insulating film 71k) extends in the Z direction inside the storage column 55 and reaches the upper surface 65a of the source line SL. The lower end 71a of the storage film 71 (for example, the lower end of the tunnel insulating film 71i, the lower end of the charge trapping film 71j, and the lower end of the blocking insulating film 71k) is in contact with the upper surface 65a of the source line SL. On the other hand, the storage film 71 does not protrude into the interior of the source line SL. That is, the storage film 71 does not protrude below the upper surface 65a of the source line SL (that is, toward the semiconductor substrate 21 side).

[0103] In this embodiment, the lower end 74a of the first cover portion 74 is located on the same surface as the lower end 71a of the memory film 71. The lower end 74a of the first cover portion 74 is in contact with the upper surface 65a of the source line SL. Thus, the first cover portion 74 is electrically connected to the source line SL. The first cover portion 74 does not protrude into the inside of the source line SL. In addition, the first cover portion 74 and the source line SL can be formed simultaneously by the same process. In this case, the first cover portion 74 is formed integrally with the source line SL.

[0104] In addition, the connection structure between the storage column 55 and the source line SL is not limited to the above example. For example, when the source line SL is made of metal, the connection structure between the storage column 55 and the source line SL may be a Schottky junction. For example, by pre-implanting impurities into the upper surface of the first cover portion 74 and supplying a metal material forming the source line SL onto the first cover portion 74, a connection structure formed by a Schottky junction is realized.

[0105] Next, return Figure 4 , the second cover portion 75 will be described.

[0106] The second cover 75 is provided at the upper end of the storage column 55. The second cover 75 is arranged at least between the insulating core 73 and the upper contact 54. For example, the second cover 75 is arranged between the upper end 73b of the insulating core 73 and the upper contact 54. The second cover 75 is provided on the inner peripheral side of the storage film 71 and is formed integrally with the channel layer 72. The second cover 75 contains polysilicon doped with impurities. The second cover 75 is heat-treated after being doped with impurities, and the impurities are diffused. The second cover 75 is an example of a "second connecting portion".

[0107] (Connection structure between storage column and upper contact)

[0108] Next, the connection structure between the memory column 55 and the upper contact 54 will be described.

[0109] In the present embodiment, the storage film 71 (for example, each of the tunnel insulating film 71i, the charge trapping film 71j, and the blocking insulating film 71k) extends in the Z direction inside the storage pillar 55 and reaches the upper contact 54. The upper end 71b of the storage film 71 (for example, the upper end of the tunnel insulating film 71i, the upper end of the charge trapping film 71j, and the upper end of the blocking insulating film 71k) is in contact with the lower surface 54a of the upper contact 54. On the other hand, the storage film 71 does not protrude into the interior of the upper contact 54.

[0110] In this embodiment, the upper end 75b of the second cover 75 is located on the same plane as the upper end 71b of the memory film 71. The upper end 75b of the second cover 75 is in contact with the lower surface 54a of the upper contact 54. Thus, the second cover 75 is electrically connected to the upper contact 54. The second cover 75 does not protrude into the interior of the upper contact 54.

[0111] <4.7 bit lines>

[0112] Next, the bit line BL is described. The bit line BL is a wiring for controlling the voltage in order to select the storage column 55. A plurality of bit lines BL are arranged along the X direction. Each bit line BL extends along the Y direction. Each bit line BL is arranged on the opposite side of the source line SL relative to the storage column 55. The bit line BL is arranged above the upper contact 54. The bit line BL is, for example, a wiring containing copper, that is, a copper wiring.

[0113] A contact 56 extending in the Z direction is provided between the bit line BL and the upper contact 54. The bit line BL is electrically connected to the upper end 55b of the memory column 55 through the contact 56 and the upper contact 54. For example, the bit line BL is electrically connected to the second cover portion 75 of the memory column 55 through the contact 56 and the upper contact 54. Thus, by combining the word line WL and the bit line BL, any memory cell transistor MT can be selected from a plurality of memory cell transistors MT arranged in a three-dimensional shape.

[0114] <4.8 Steps>

[0115] Next, return Figure 3 , the step portion 80 provided in the memory cell array 11 will be described.

[0116] The step portion 80 is a structure for ensuring electrical connection for the multi-layer conductive layer 61. In the step portion 80, the length of the multi-layer conductive layer 61 in the X direction is longer, for example, as the conductive layer 61 is located at the lower position. Thus, the end of each conductive layer 61 in the X direction has a terrace portion that does not overlap with another conductive layer 61 located above the conductive layer 61. The step portion 80 is covered by the third insulating portion 43.

[0117] In the present embodiment, the multilayer conductive layer 61 includes a first conductive layer 61A, a second conductive layer 61B, and a third conductive layer 61C. The first conductive layer 61A is located at the top of the three conductive layers 61A, 61B, and 61C. The second conductive layer 61B is located in the middle of the three conductive layers 61A, 61B, and 61C. In other words, the second conductive layer 61B is arranged between the first conductive layer 61A and the semiconductor substrate 21. The third conductive layer 61C is located at the bottom of the three conductive layers 61A, 61B, and 61C. In other words, the third conductive layer 61C is arranged between the second conductive layer 61B and the semiconductor substrate 21. The first conductive layer 61A is an example of a "first gate electrode layer". The second conductive layer 61B is an example of a "second gate electrode layer". The third conductive layer 61C is an example of a "third gate electrode layer". In this embodiment, the length of the second conductive layer 61B in the X direction is longer than the length of the first conductive layer 61A in the X direction. The length of the third conductive layer 61C in the X direction is longer than the length of the second conductive layer 61B in the X direction.

[0118] A plurality of contacts 81 are arranged above the step portion 80. The plurality of contacts 81 are conductive and extend in the Z direction. Each contact 81 is an electrical connection portion that connects the conductive layer 61 and the wiring 101 included in the upper wiring portion 100. The plurality of contacts 81 are arranged at positions corresponding to the terrace portions of the multi-layer conductive layer 61 when viewed from above. The lengths of the plurality of contacts 81 in the Z direction are different from each other. The lower end of each contact 81 is in contact with the terrace portion of the corresponding conductive layer 61.

[0119] For example, the plurality of contacts 81 include a first contact 81A, a second contact 81B, and a third contact 81C. The first contact 81A is provided corresponding to the platform portion of the first conductive layer 61A and is in contact with the platform portion of the first conductive layer 61A. The second contact 81B extends downward longer than the first contact 81A. The second contact 81B is provided corresponding to the platform portion of the second conductive layer 61B and is in contact with the platform portion of the second conductive layer 61B. The third contact 81C extends downward longer than the second contact 81B. The third contact 81C is provided corresponding to the platform portion of the third conductive layer 61C and is in contact with the platform portion of the third conductive layer 61C.

[0120] <4.9 Breaking part>

[0121] Next, the separating portion ST will be described.

[0122] Figure 7 yes Figure 3 The memory cell array 11 is shown in a cross-sectional view taken along the line F7-F7. The partitioning portion ST extends in the Z direction and penetrates the laminate 51 and the insulating layer 52. The partitioning portion ST is a wall portion that partitions the laminate 51 in the Y direction.

[0123] Figure 8 Yes means Figure 7 FIG. 1 is a cross-sectional view of a region surrounded by line F8 of the memory cell array 11. The partition portion ST includes, for example, an insulating portion 91 and a conductive portion 92.

[0124] The insulating portion 91 forms the outer contour of the partition portion ST. The insulating portion 91 extends in the Z direction and penetrates the laminate 51 and the insulating layer 52. The insulating portion 91 partitions each of the plurality of conductive layers 61 included in the laminate 51 in the Y direction. The insulating portion 91 is formed of an insulating material such as silicon oxide.

[0125] The conductive portion 92 is provided inside the insulating portion 91. The conductive portion 92 extends in the Z direction and penetrates the laminate 51 and the insulating layer 52. The lower end 92a of the conductive portion 92 is located inside the source line SL. The conductive portion 92 is formed of a conductive material such as tungsten or polysilicon. The conductive portion 92 is a wiring that connects the source line SL to the wiring in the memory cell array 11.

[0126] The dividing portion ST has a lower end 90a and an upper end 90b. The lower end 90a is connected to the source line SL. The upper end 90b is located on the opposite side of the lower end 90a in the Z direction. In the present embodiment, the width W90a of the lower end 90a in the Y direction is smaller than the width W90b of the upper end 90b in the Y direction. The lower end 90a is an example of the "third end". The upper end 90b is an example of the "fourth end". Here, the width W90a of the lower end 90a can be defined as the width in the Y direction of a portion 90s1 that is opposite to the bottom conductive layer 61 of the multi-layer conductive layer 61 in the dividing portion ST. In addition, the width W90b of the upper end 90b can be defined as the width in the X direction of a portion 90s2 that is opposite to the top conductive layer 61 of the multi-layer conductive layer 61 in the dividing portion ST, for example. Therefore, "the width W90a of the lower end 90a of the breaking portion ST in the Y direction is larger than the width W90b of the upper end 90b of the breaking portion ST in the X direction", for example, means that the width of part 90s1 of the breaking portion ST in the Y direction is larger than the width of part 90s2 of the breaking portion ST in the X direction.

[0127] In the present embodiment, the segmented portion ST includes a maximum width portion 90m, a first portion 90n1, and a second portion 90n2. The maximum width portion 90m is a portion of the segmented portion ST having the largest width in the Y direction. In the present embodiment, the maximum width portion 90m is located above the center of the segmented portion ST in the Z direction.

[0128] The first portion 90n1 is a reduced portion located between the lower end 90a and the maximum width portion 90m, and the width of the segment ST in the Y direction decreases as it moves downward. The second portion 90n2 is an expanded portion located between the upper end 90b and the maximum width portion 90m, and the width of the segment ST in the Y direction increases as it moves downward. In the present embodiment, the length L4 of the second portion 90n2 in the Z direction is smaller than the length L3 of the first portion 90n1 in the Z direction.

[0129] <4.10 Upper section>

[0130] Next, return Figure 7, the upper disconnection portion SHE is described. The upper disconnection portion SHE is a disconnection portion that is shallower than the dividing portion ST. The upper disconnection portion SHE is provided at the upper end portion of the laminate 51 and extends to the middle of the laminate 51 along the Z direction. The upper disconnection portion SHE extends along the X direction. The upper disconnection portion SHE penetrates the conductive layer 61 that functions as the drain side selection gate line SGD. On the other hand, the upper disconnection portion SHE does not reach the conductive layer 61 that functions as the word line WL. The upper disconnection portion SHE is a wall portion that divides the conductive layer 61 that functions as the drain side selection gate line SGD along the Y direction. The upper disconnection portion SHE is formed of an insulating material such as silicon oxide. In the present embodiment, the area divided by the upper disconnection portion SHE corresponds to one string unit SU. The conductive layer 61 corresponding to the drain side selection gate line SGD is divided along the Y direction by the dividing portion ST and the upper disconnection portion SHE. Thus, a drain side selection gate line SGD extending along the X direction is formed.

[0131] <5. Upper wiring section>

[0132] Next, the upper wiring portion 100 will be described. The upper wiring portion 100 is provided above the laminate 51. The upper wiring portion 100 includes a plurality of wirings 101. The plurality of wirings 101 include, for example, a first wiring 101A electrically connected to the contact 81 for the step portion 80 (see Figure 3 ), the second wiring 101B electrically connected to the bit line BL (refer to Figure 7 ), and the third wiring 101C electrically connected to the pad 44 (see Figure 7 ). Each of the plurality of wirings 101 is, for example, a wiring containing copper, that is, a copper wiring. In the present embodiment, the plurality of copper wirings (for example, the plurality of wirings 101) are arranged above the second cover portion 75 of the storage column 55 in the semiconductor storage device 1. In the present embodiment, there is no copper wiring below the second cover portion 75. The upper wiring portion 100 is an example of a "connection wiring portion".

[0133] <6. Electrical connection including through-contact>

[0134] Next, the electrical connection portion 110 will be described. The electrical connection portion 110 is an electrical connection portion that electrically connects the first chip 2 and the second chip 3. For example, the electrical connection portion 110 is an electrical connection portion that electrically connects the peripheral circuit 22 of the first chip 2 and the plurality of wirings 101 included in the upper wiring portion 100 of the second chip 3. The electrical connection portion 110 includes, for example, a first electrical connection portion 111, a second electrical connection portion 112, and a third electrical connection portion 113.

[0135] The first electrical connection portion 111 is a connection portion that electrically connects the transistor 31 included in the peripheral circuit 22 and the first wiring 101A included in the upper wiring portion 100. In other words, the first electrical connection portion 111 electrically connects the transistor 31 included in the peripheral circuit 22 and the conductive layer 61. The first electrical connection portion 111 includes a first through contact 121. The first through contact 121 has conductivity and extends in the Z direction.

[0136] The first through contact 121 penetrates the second insulating portion 42 of the second chip 3 and at least a portion of the first insulating portion 23 of the first chip 2. The first through contact 121 extends along the Z direction from below the source line SL to above the upper end 55b of the storage column 55, and electrically connects the transistor 31 of the peripheral circuit 22 and the conductive layer 61. For example, the first through contact 121 is connected to the wiring 33a included in the wiring layer 33 inside the first chip 2. The first through contact 121 is connected to the wiring 101A included in the upper wiring portion 100 inside the second chip 3 (for example, above the upper end 55b of the storage column 55).

[0137] The second electrical connection portion 112 is a connection portion that electrically connects another transistor 31 included in the peripheral circuit 22 and the second wiring 101B included in the upper wiring portion 100. That is, the second electrical connection portion 112 electrically connects the transistor 31 included in the peripheral circuit 22 and the bit line BL. The second electrical connection portion 112 includes a second through contact 122. The second through contact 122 has conductivity and extends in the Z direction.

[0138] The second through contact 122 penetrates the second insulating portion 42 of the second chip 3 and at least a portion of the first insulating portion 23 of the first chip 2. The second through contact 122 extends from below the source line SL along the Z direction to above the upper end 55b of the storage column 55, and electrically connects the transistor 31 and the bit line BL of the peripheral circuit 22. The second through contact 122 is connected to the wiring 33a included in the wiring layer 33 inside the first chip 2. The second through contact 122 is connected to the wiring 101B included in the upper wiring portion 100 inside the second chip 3 (for example, above the upper end 55b of the storage column 55).

[0139] The third electrical connection portion 113 is a connection portion that electrically connects another transistor 31 included in the peripheral circuit 22 and the third wiring 101C included in the upper wiring portion 100. That is, the third electrical connection portion 113 connects the transistor 31 included in the peripheral circuit 22 and the pad 44. The third electrical connection portion 113 includes a third through-contact 123. The third through-contact 123 has conductivity and extends in the Z direction.

[0140] The third through-contact 123 penetrates the second insulating portion 42 of the second chip 3 and at least a portion of the first insulating portion 23 of the first chip 2 along the Z direction. The third through-contact 123 is connected to the wiring 33a included in the wiring layer 33 inside the first chip 2. The third through-contact 123 is connected to the wiring 101C included in the upper wiring portion 100 inside the second chip 3 (for example, at a position above the upper end 55b of the storage pillar 55).

[0141] <7. Other components>

[0142] like Figure 3 and Figure 7 As shown, in this embodiment, there is no copper pad for bonding the first chip 2 and the second chip 3. In other words, there is no copper pad between the source line SL and the semiconductor substrate 21.

[0143] <8. Manufacturing method>

[0144] Next, a method for manufacturing semiconductor memory device 1 will be described.

[0145] Fig. 9 It is a diagram showing the flow of a method for manufacturing the semiconductor memory device 1 . Figure 10A to Figure 10P It is a diagram for explaining a method of manufacturing semiconductor memory device 1 .

[0146] First, an insulating layer 202 is formed on a semiconductor substrate 201. Next, sacrificial layers 203 and insulating layers 62 are alternately stacked on the insulating layer 202 to form a stacked body 210 (see FIG. 2 ). Fig. 9 S101 in Fig. 10A ). The sacrificial layer 203 is formed of, for example, silicon nitride. The sacrificial layer 203 is an example of a "first layer". The insulating layer 62 is an example of a "second layer".

[0147] Next, a hole for forming the memory column 55, that is, a memory hole 211 (see Fig. 9 S102 in Fig. 10B Then, a memory film 71, a channel layer 72, and an insulating core 73 are sequentially formed inside the memory hole 211 (see Fig. 9 S103 in Fig. 10C ).

[0148] Next, the first cover portion 74 is formed (see Fig. 9 S104 in Fig. 10D). For example, the end of the insulating core 73 located at the first end 221 of the storage column 55 is removed by etching. Then, a silicon material is supplied to the inside of the depression generated by removing the end of the insulating core 73 to fill the depression. Then, impurities (such as phosphorus) are doped into the silicon material supplied to the depression, and the impurities are diffused by heat treatment, and the silicon material is crystallized. Thus, the first cover portion 74 is formed at the first end 221 of the storage column 55.

[0149] Next, a source line SL (see Fig. 9 S105 in Fig. 10E ). For example, the source line SL is formed by supplying tungsten or silicon material onto the stacked body 210 and the first cover portion 74 and performing a desired process. Next, an insulating material is supplied so as to cover the source line SL, and a second insulating portion 42 covering the source line SL is formed (see Fig. 9 S106 in Fig.10F ). Thus, the second chip 3 is formed.

[0150] Next, the first chip 2 prepared separately is bonded to the second chip 3 formed in the above step (see Fig. 9 S107 in Figure 10G ). For example, the second chip 3 is turned upside down, the first surface S1 of the first insulating portion 23 of the first chip 2 is overlapped with the second surface S2 of the second insulating portion 42 of the second chip 3, and heated to a predetermined temperature and pressed. Thus, the first chip 2 and the second chip 3 are bonded together.

[0151] Next, the back surface of the second chip 3 is polished by CMP (Chemical Mechanical Polishing) or the like to remove the semiconductor substrate 201 (see Fig. 9 S108 in Fig. 10H Next, the second cover portion 75 is formed (see Fig. 9 S109 in Fig.10I ). For example, the end of the insulating core 73 located at the second end 222 of the storage column 55 is removed by etching. Then, the depression is filled by supplying silicon material to the inside of the depression generated by removing the end of the insulating core 73. Then, impurities (such as phosphorus) are doped into the silicon material supplied to the depression, and the impurities are diffused by heat treatment, and the silicon material is crystallized. Thus, the second cover portion 75 is formed. Next, the upper disconnecting portion SHE is formed for the laminate 210.

[0152] Next, a step portion 80 ( Fig. 9 S110, Fig.10JNext, an insulating portion covering the step portion 80 is provided, and a plurality of contacts 81 are formed on the step portion 80 (see Fig. 9 S111 in Figure 10K ).

[0153] Next, the slit 220 for forming the partition portion ST is formed in the laminate 210 (see Fig. 9 S112 in Fig.10L Next, a replacement step is performed to replace the multi-layer sacrificial layer 203 with the multi-layer conductive layer 61 (see Fig. 9 S113 in Figure 10M ). For example, by supplying hot phosphoric acid or the like through the slot 220, the sacrificial film 203 of the laminate 210 is removed, and a conductive material is supplied to the space formed by the removal. Thus, a laminate 51 including a plurality of conductive layers 61 is formed. Then, a separation portion ST is provided inside the slot 220, and an insulating portion is provided on the laminate 51 (see Fig. 9 S114 in Fig.10N ).

[0154] Next, an electrical connection portion 120 including through contacts 121, 122, and 123 is provided (see Fig. 9 S115 in Fig.10O Then, the bit line BL, the wiring 101 included in the upper wiring portion 100, and the pad 44 are formed (see Fig. 9 S116 in Figure 10P ). Thus, the semiconductor memory device 1 is manufactured.

[0155] <9. Advantages>

[0156] As a comparative example 1, consider an example in which a laminate 51 including a conductive layer 61 (word line WL) and an insulating layer 62 is formed above a peripheral circuit 22 provided on a semiconductor substrate 21. In this comparative example, a source line SL is formed between the laminate 51 and the semiconductor substrate 21. In this case, the structure of the connection portion between the source line SL and the storage column 55 is sometimes complicated. For example, in a highly laminated semiconductor memory device in recent years, the steps for forming the connection portion between the lower end portion of the storage column 55 located at the lower end portion of the laminate 51 and the source line SL are complicated. As a result, the manufacturability of the semiconductor memory device is sometimes reduced.

[0157] As a comparative example 2, consider an example in which, in addition to the first chip 2 including the peripheral circuit 22, a second chip 3 including the memory cell array 11 is formed, and the first chip 2 and the second chip 3 are bonded together using a copper pad for bonding to form a semiconductor memory device. In this case, after bonding the first chip 2 and the second chip 3, it is necessary to consider the copper diffusion of the copper pad, and it is difficult to perform heat treatment at a high temperature. Therefore, in the step of forming the source line SL at the upper end of the second chip 3 after bonding to the first chip 2, it is difficult to perform heat treatment for crystallization of polysilicon and diffusion of impurities, and the step of forming the connection portion between the memory column 55 and the source line SL is complicated. As a result, the manufacturability of the semiconductor memory device is sometimes reduced.

[0158] On the other hand, the semiconductor memory device 1 of the present embodiment includes: a semiconductor substrate 21, a transistor 31, a laminate 51, a memory column 55, and a source line SL. The transistor 31 is provided on the semiconductor substrate 21. The laminate 51 is arranged on the opposite side of the semiconductor substrate 21 to the transistor 31. The memory column 55 extends in the Z direction in the laminate 51. The source line SL is arranged between the laminate 51 and the semiconductor substrate 21. The memory column 55 has a lower end 55a connected to the source line SL, and an upper end 55b located on the opposite side of the lower end 55a. The width W55a of the lower end 55a in the X direction is larger than the width W55b of the upper end 55b in the X direction.

[0159] According to such a configuration, the source line SL can be formed in a state where the source line SL is located on the upper side of the laminated body 210. Therefore, even when the laminated body 210 is highly laminated, the connection portion between the storage pillar 55 and the source line SL can be easily formed compared with, for example, Comparative Example 1 or Comparative Example 2. Thus, the manufacturability of the semiconductor memory device 1 can be improved.

[0160] In this embodiment, the memory column 55 has a first cover portion 74 that is disposed at least between the insulating core 73 and the source line SL and contains polysilicon. According to such a configuration, the connectivity and conductivity between the first cover portion 74 and the source line SL can be further improved. Thus, the electrical characteristics of the semiconductor memory device 1 can be improved.

[0161] In this embodiment, there is no copper pad between the source line SL and the semiconductor substrate 21. According to such a configuration, the need to consider copper diffusion is reduced, and compared with the case where there is a copper pad between the source line SL and the semiconductor substrate 21 as in the comparative example 2, a heat treatment can be performed at a high temperature when the source line SL is formed or when the first cover portion 74 is formed. As a result, the electrical characteristics of the semiconductor memory device 1 can be improved.

[0162] In the present embodiment, the storage column 55 has a second cover portion 75 that is at least arranged between the insulating core 73 and the bit line BL and contains polysilicon. The upper wiring portion 100 includes a plurality of copper wirings (e.g., a plurality of wirings 101). The plurality of copper wirings are arranged above the second cover portion 75 in the semiconductor storage device 1, and there are no copper wirings below the second cover portion 75. According to such a configuration, compared with the case where there are copper wirings below the second cover portion 75, the necessity of considering copper diffusion becomes less, and heat treatment can be performed at a high temperature when the second cover portion 75 is formed. As a result, the electrical characteristics of the semiconductor storage device 1 can be improved.

[0163] In the present embodiment, the semiconductor storage device 1 further includes a disconnecting portion ST, which penetrates the laminate 51 in the Z direction and disconnects each of the multiple conductive layers 61 in the Y direction. The disconnecting portion ST has a lower end 90a connected to the source line SL, and an upper end 90b located on the opposite side of the lower end 90a. The width W90a of the lower end 90a in the Y direction is smaller than the width W90b of the upper end 90b in the Y direction. In other words, the disconnecting portion ST is larger on the upper side and smaller on the lower side when macroscopically observed. On the other hand, the storage column 55 is smaller on the upper side and larger on the lower side when macroscopically observed. According to such a structure, it is possible to avoid the maximum diameter portion 55m of the storage column 55 and the maximum width portion 90m of the disconnecting portion ST being adjacent to each other in the X direction or the Y direction. Therefore, the distance between the storage column 55 and the disconnecting portion ST can be reduced, and the miniaturization of the semiconductor storage device 1 can be sought.

[0164] (Second embodiment)

[0165] Next, the second embodiment will be described. The second embodiment is different from the first embodiment in that the lower end of the memory column 55 does not have the first cover portion 74. The configuration other than that described below is the same as that of the first embodiment.

[0166] Fig.11 1 is a cross-sectional view showing a portion of the semiconductor memory device 1A according to the second embodiment. In the present embodiment, the lower end portion of the memory column 55 does not have the first cover portion 74. In the lower end portion of the memory column 55, each of the memory film 71, the channel layer 72, and the insulating core 73 extends in the Z direction, and each of the memory film 71, the channel layer 72, and the insulating core 73 is in contact with the upper surface 65a of the source line SL. In the present embodiment, the lower end 71a of the memory film 71 and the lower end 73a of the insulating core 73 are located on the same plane. However, the memory film 71, the channel layer 72, and the insulating core 73 do not protrude below the upper surface 65a of the source line SL (that is, on the semiconductor substrate 21 side).

[0167] According to such a configuration, similarly to the first embodiment, the source line SL can be formed in a state where the source line SL is located on the upper side of the stacked body 210. This can improve the manufacturability of the semiconductor memory device 1A.

[0168] (Third embodiment)

[0169] Next, the third embodiment will be described. The third embodiment is different from the first embodiment in that the storage column 55 is a column composed of two sections including a lower column 231 and an upper column 232. In addition, the structure other than that described below is the same as that of the first embodiment. In addition, although a column composed of two sections is described in this embodiment, a structure of three or more sections may be adopted.

[0170] Fig.12 1 is a cross-sectional view showing a part of the semiconductor memory device 1B according to the third embodiment. In the present embodiment, the stacked body 51 includes: a lower stacked body (first stacked body) 51a, an upper stacked body (second stacked body) 51b, and an insulating layer 62A. In the lower stacked body 51a, a plurality of conductive layers 61 and a plurality of insulating layers 62 are alternately stacked one by one in the Z direction. The upper stacked body 51b is arranged above the lower stacked body 51a. In the upper stacked body 51b, a plurality of conductive layers 61 and a plurality of insulating layers 62 are alternately stacked one by one in the Z direction. The insulating layer 62A is arranged between the lower stacked body 51a and the upper stacked body 51b. The thickness of the insulating layer 62A in the Z direction is greater than the thickness of the insulating layer 62 in the lower stacked body 51a, and is greater than the thickness of the insulating layer 62 in the Z direction in the upper stacked body 51b.

[0171] The storage column 55 includes a lower column 231 , an upper column 232 , and a connecting portion 233 .

[0172] The lower column 231 extends along the Z direction in the lower laminate 51a. The lower column 231 has a lower end 231a and an upper end 231b. The lower end 231a is the lower end 55a of the storage column 55. The lower end 231a is connected to the source line SL. The upper end 231b is located on the opposite side of the lower end 231a in the Z direction. The upper end 231b is connected to the connection portion 233 described later. In this embodiment, the width W231a of the lower end 231a in the X direction is larger than the width W231b of the upper end 231b in the X direction. Here, the width W231a of the lower end 231a can be defined as the width of the portion 231s1 in the X direction opposite to the bottommost conductive layer 61 of the multilayer conductive layer 61 of the lower laminate 51a, for example, in the lower column 231. In addition, the width W231b of the upper end 231b can be defined as, for example, the width in the X direction of the portion 231s2 that is opposite to the uppermost conductive layer 61 of the multilayer conductive layer 61 of the lower laminate 51a in the lower column 231. Therefore, "the width W231a in the X direction of the lower end 231a of the lower column 231 is larger than the width W231b in the X direction of the upper end 231b of the lower column 231", for example, means that the width in the X direction of the portion 231s1 of the lower column 231 is larger than the width in the X direction of the portion 231s2 of the lower column 231.

[0173] The lower column 231 has a maximum outer diameter portion (maximum width portion) 231m, a first portion 231n1, and a second portion 231n2. The maximum outer diameter portion 231m is a portion having the largest outer diameter (that is, the width in the X direction or the Y direction) in the lower column 231. In the present embodiment, the maximum outer diameter portion 231m is located below the center of the lower column 231 in the Z direction.

[0174] The first portion 231n1 is a constricted portion located between the lower end 231a and the maximum outer diameter portion 231m, and the outer diameter of the storage column 55 decreases as it moves downward. The second portion 231n2 is an expanded portion located between the upper end 231b and the maximum outer diameter portion 231m, and the outer diameter of the storage column 55 increases as it moves downward. The length L6 of the second portion 231n2 in the Z direction is greater than the length L5 of the first portion 231n1 in the Z direction.

[0175] The upper column 232 extends along the Z direction in the upper laminate body 51b. The upper column 232 has a lower end 232a and an upper end 232b. The lower end 232a is connected to the connecting portion 233. The upper end 232b is located on the opposite side of the lower end 232a in the Z direction. The upper end 232b is the upper end 55b of the storage column 55. The upper end 232b is electrically connected to the bit line BL. In this embodiment, the width W232a of the lower end 232a in the X direction is larger than the width W232b of the upper end 232b in the X direction. Here, the width W232a of the lower end 232a can be defined as the width of the portion 232s1 in the X direction opposite to the bottommost conductive layer 61 of the multilayer conductive layer 61 of the upper laminate body 51b in the upper column 232, for example. In addition, the width W232b of the upper end 232b can be defined as, for example, the width in the X direction of the portion 232s2 that is opposite to the uppermost conductive layer 61 of the multi-layer conductive layer 61 of the upper laminate 51b in the upper column 232. Therefore, "the width W232a in the X direction of the lower end 232a of the upper column 232 is larger than the width W232b in the X direction of the upper end 232b of the upper column 232", for example, means that the width in the X direction of the portion 232s1 of the upper column 232 is larger than the width in the X direction of the portion 232s2 of the upper column 232.

[0176] The upper column 232 has a maximum outer diameter portion (maximum width portion) 232m, a first portion 232n1, and a second portion 232n2. The maximum outer diameter portion 232m is a portion having the largest outer diameter (that is, the width in the X direction or the Y direction) in the upper column 232. In the present embodiment, the maximum outer diameter portion 232m is located below the center of the upper column 232 in the Z direction.

[0177] The first portion 232n1 is a constricted portion located between the lower end 232a and the maximum outer diameter portion 232m, and the outer diameter of the storage column 55 decreases as it moves downward. The second portion 232n2 is an expanded portion located between the upper end 232b and the maximum outer diameter portion 232m, and the outer diameter of the storage column 55 increases as it moves downward. In the upper column 232, the length L8 of the second portion 232n2 in the Z direction is greater than the length L7 of the first portion 232n1 in the Z direction.

[0178] Moreover, in the present embodiment, the width W231a of the lower end 231a of the lower column 231 in the X direction is larger than the width W232b of the upper end 232b of the upper column 232 in the X direction. Here, "the width W231a of the lower end 231a of the lower column 231 in the X direction is larger than the width W232b of the upper end 232b of the upper column 232 in the X direction" means, for example, that the width of the portion 231s1 of the lower column 231 in the X direction is larger than the width of the portion 232s2 of the upper column 232 in the X direction.

[0179] The connection portion 233 is disposed in the insulating layer 62A. The connection portion 233 is disposed between the lower pillar 231 and the upper pillar 232. In the connection portion 233, the outer diameter (e.g., the width in the X direction or the Y direction) of the storage pillar 55 is enlarged compared with the lower pillar 231 and the upper pillar 232. In addition, the connection portion 233 can be omitted, and the lower pillar 231 and the upper pillar 232 can be directly connected.

[0180] According to such a structure, the dividing portion ST is larger on the upper side and smaller on the lower side when macroscopically observed. On the other hand, the storage column 55 is smaller on the upper side and larger on the lower side when macroscopically observed. Therefore, the maximum width portion 55m of the storage column 55 and the maximum width portion 90m of the dividing portion ST are easily located at different heights in the Z direction. Therefore, the distance between the storage column 55 and the dividing portion ST can be reduced. Thus, the miniaturization of the semiconductor storage device 1B can be sought.

[0181] (Fourth embodiment)

[0182] Next, the fourth embodiment is described. The fourth embodiment is different from the first embodiment in that the width W90a of the lower end 90a of the partition portion ST in the Y direction is larger than the width W90b of the upper end 90b in the Y direction. The configuration other than that described below is the same as that of the first embodiment.

[0183] Fig.13 1 is a cross-sectional view showing a portion of a semiconductor storage device 1C according to a fourth embodiment. In this embodiment, the dividing portion ST has a lower end 90a and an upper end 90b. The width W90a of the lower end 90a in the Y direction is larger than the width W90b of the upper end 90b in the Y direction. In this embodiment, the maximum width portion 90m of the dividing portion ST is located below the center of the dividing portion ST in the Z direction. In addition, the length L4 of the second portion 90n2 in the Z direction is larger than the length L3 of the first portion 90n1 in the Z direction.

[0184] Fig.14 1 is a diagram showing a process flow of a method for manufacturing a semiconductor memory device 1C according to a fourth embodiment. In this embodiment, before bonding the first chip 2 and the second chip 3, a step of forming a slot 220 for providing a dividing portion ST is performed in the second chip 3 ( Fig.14 S112 in the above), replacing the sacrificial layer 203 with the conductive layer 61 ( Fig.14 S113 in the embodiment), and the step of forming the dividing portion ST inside the narrow groove 220 (refer to Fig.14 Therefore, when the finished product of the semiconductor memory device 1C is observed, the dividing portion ST is formed into an inverted tapered shape. In addition, the step (S105) of forming the source line SL may be performed before the step (S112) of forming the narrow groove 220 for the dividing portion ST, instead of after the step (S114) of forming the dividing portion ST.

[0185] According to such a configuration, similarly to the first embodiment, the source line SL can be formed in a state where the source line SL is located on the upper side of the stacked body 210. This can improve the manufacturability of the semiconductor memory device 1C.

[0186] (Fifth embodiment)

[0187] Next, the fifth embodiment will be described. The fifth embodiment is different from the first embodiment in that the layered body 51 does not have the step portion 80. The configuration other than that described below is the same as that of the first embodiment.

[0188] Fig.15 1 is a cross-sectional view showing a portion of a semiconductor storage device 1D according to a fifth embodiment. In this embodiment, the lengths of the multiple conductive layers 61 in the X direction are the same. In this embodiment, the multiple contacts 81 extend in the Z direction while maintaining insulation between the conductive layer 61 that is not the connection object and through the holes that penetrate the conductive layer 61 in the Z direction. The multiple contacts 81 extend in the Z direction, and the lengths in the Z direction are different from each other. The lower end of each contact 81 is in contact with the conductive layer 61 of the connection object.

[0189] According to such a configuration, similarly to the first embodiment, the source line SL can be formed in a state where the source line SL is located on the upper side of the stacked body 210. This can improve the manufacturability of the semiconductor memory device 1D.

[0190] (Sixth Implementation Method)

[0191] Next, the sixth embodiment will be described. The sixth embodiment is different from the first embodiment in that a step portion 80 is provided in the center of the stacked body 51 instead of at the end of the stacked body 51. The configuration other than that described below is the same as that of the first embodiment.

[0192] Fig.16 This is a schematic top view of a portion of the semiconductor memory device 1 according to the sixth embodiment. In this embodiment, the laminate 51 has a first memory plane PL1 (first region) and a second memory plane PL2 (second region). Each of the first memory plane PL1 and the second memory plane PL2 has a plurality of conductive layers 61 and a plurality of insulating layers 62 stacked in the Z direction.

[0193] In this embodiment, the step portion 80 is provided at the center portion in the X direction of the laminate 51. In other words, the step portion 80 is provided at the end portion of the first memory surface PL1 adjacent to the second memory surface PL2, and at the end portion of the second memory surface PL2 adjacent to the first memory surface PL1. In each of the first memory surface PL1 and the second memory surface PL2, the step portion 80 is provided only in a part of the laminate 51. The first memory surface PL1 and the second memory surface PL2 may be electrically disconnected, or may be electrically connected to each other in a region excluding the step portion 80.

[0194] Fig.17 yes Fig.16 1 is a cross-sectional view of the semiconductor memory device 1 along the line F17-F17. In the present embodiment, as described above, a step portion 80 is provided at the center of the stacked body 51 in the X direction. A plurality of contacts 81 are provided at the center of the stacked body 51 in the X direction in a manner corresponding to the upper portion of the step portion 80. The lengths of the plurality of contacts 81 in the Z direction are different from each other. The lower end of each contact 81 is in contact with the terrace portion of the corresponding conductive layer 61.

[0195] For example, the plurality of contacts 81 include a first contact 81A, a second contact 81B, and a third contact 81C. The first contact 81A is provided corresponding to the platform portion of the first conductive layer 61A and is in contact with the platform portion of the first conductive layer 61A. The second contact 81B extends downward longer than the first contact 81A. The second contact 81B is provided corresponding to the platform portion of the second conductive layer 61B and is in contact with the platform portion of the second conductive layer 61B. The third contact 81C extends downward longer than the second contact 81B. The third contact 81C is provided corresponding to the platform portion of the third conductive layer 61C and is in contact with the platform portion of the third conductive layer 61C.

[0196] According to such a configuration, similarly to the first embodiment, the source line SL can be formed in a state where the source line SL is located on the upper side of the stacked body 210. This can improve the manufacturability of the semiconductor memory device 1D.

[0197] According to at least one embodiment described above, a semiconductor memory device comprises: a substrate, a transistor, a laminate, a columnar body, and a source line. The transistor is disposed on the substrate. The laminate is formed by alternately laminating a plurality of gate electrode layers and a plurality of insulating layers in a first direction. The columnar body comprises an insulating core, a channel layer, and a storage film. The source line is arranged between the laminate and the substrate, and extends at least in a second direction intersecting the first direction. The columnar body comprises: a first end connected to the source line; and a second end located on the opposite side of the first end in the first direction. The width of the first end in the second direction is greater than the width of the second end in the second direction. According to such a configuration, it is possible to seek to improve manufacturability.

[0198] Several semiconductor memory devices and methods for manufacturing the semiconductor memory devices are described below. [1]

[0200] A semiconductor storage device comprising:

[0201] substrate;

[0202] A transistor, disposed on the substrate;

[0203] A laminated body, arranged on the opposite side of the substrate relative to the transistor, formed by alternately laminating a plurality of gate electrode layers and a plurality of insulating layers in a first direction;

[0204] a columnar body extending in the first direction in the laminated body and comprising: an insulating core; a channel layer disposed between the multi-layer gate electrode layer and the insulating core; and a storage film disposed between the multi-layer gate electrode layer and the channel layer; and

[0205] a source line disposed between the laminate and the substrate and extending at least along a second direction intersecting the first direction; and

[0206] The columnar body has a first end connected to the source line SL and a second end located on the opposite side of the first end in the first direction. The width of the first end in the second direction is greater than the width of the second end in the second direction.

[0207] [2] The semiconductor memory device according to [1], wherein

[0208] The source line has a surface facing the laminate; and

[0209] The memory film extends in the first direction within the columnar body and contacts the surface of the source line, and does not protrude beyond the surface of the source line to the substrate side.

[0210] [3] The semiconductor memory device according to [1] or [2], wherein

[0211] The columnar body has a first connection portion that is disposed at least between the insulating core and the source line and contains polysilicon.

[0212] [4] The semiconductor memory device according to [1] or [2], wherein

[0213] The source line has a surface facing the laminate; and

[0214] The insulating core extends in the first direction within the columnar body and contacts the surface of the source line, and does not protrude beyond the surface of the source line to the substrate side.

[0215] [5] A semiconductor memory device according to any one of [1] to [4], wherein

[0216] There is no copper pad between the source line and the substrate.

[0217] [6] A semiconductor memory device according to any one of [1] to [5], wherein

[0218] The source line contains at least one of silicon and tungsten.

[0219] [7] The semiconductor memory device according to any one of [1] to [6], further comprising:

[0220] a bit line located on the opposite side of the source line relative to the column and extending in a third direction intersecting the first direction and the second direction; and

[0221] The second end of the pillar is electrically connected to the bit line.

[0222] [8] The semiconductor memory device according to [7] further comprises:

[0223] a peripheral circuit including the transistor; and

[0224] The contact extends from below the source line along the first direction to above the second end of the columnar body when the laminated body is viewed from the substrate as an upper side, and electrically connects the peripheral circuit and the bit line.

[0225] [9] The semiconductor memory device according to [7] or [8], further comprising a connection wiring portion; and

[0226] The columnar body has a second connection portion, the second connection portion is arranged at least between the insulating core and the bit line and contains polysilicon;

[0227] The connection wiring section includes a plurality of copper wirings;

[0228] The plurality of copper wirings are arranged above the second connection portion in the semiconductor memory device, and no copper wiring exists below the second connection portion.

[0229]

[10] The semiconductor memory device according to any one of [1] to [9], further comprising a plurality of contacts; and

[0230] The multi-layer gate electrode layer includes: a first gate electrode layer; a second gate electrode layer disposed between the first gate electrode layer and the substrate; and a third gate electrode layer disposed between the second gate electrode layer and the substrate; and

[0231] The multiple contacts include: a first contact, which is connected to the first gate electrode layer; a second contact, which extends longer toward the substrate side than the first contact and is connected to the second gate electrode layer; and a third contact, which extends longer toward the substrate side than the second contact and is connected to the third gate electrode layer.

[0232]

[11] The semiconductor memory device according to any one of [1] to

[10] , further comprising:

[0233] a dividing portion that penetrates the laminate along the first direction, extends along the second direction, and divides each of the plurality of gate electrode layers in a third direction that intersects the first direction and the second direction; and

[0234] The dividing portion has: a third end connected to the source line; and a fourth end located on the opposite side of the third end in the first direction; and a width of the third end in the third direction is smaller than a width of the fourth end in the third direction.

[0235]

[12] The semiconductor memory device according to any one of [1] to

[10] , further comprising:

[0236] a dividing portion that penetrates the laminate along the first direction, extends along the second direction, and divides each of the plurality of gate electrode layers in a third direction that intersects the first direction and the second direction; and

[0237] The dividing portion has: a third end connected to the source line; and a fourth end located on the opposite side of the third end in the first direction; and a width of the third end in the third direction is greater than a width of the fourth end in the third direction.

[13]

[0239] A semiconductor storage device comprising:

[0240] substrate;

[0241] A transistor, disposed on the substrate;

[0242] A laminated body, arranged on the opposite side of the substrate relative to the transistor, formed by alternately laminating a plurality of gate electrode layers and a plurality of insulating layers in a first direction;

[0243] a columnar body extending in the first direction in the laminated body and comprising: an insulating core; a channel layer disposed between the multi-layer gate electrode layer and the insulating core; and a storage film disposed between the multi-layer gate electrode layer and the channel layer; and

[0244] a source line disposed between the laminate and the substrate and extending at least along a second direction intersecting the first direction; and

[0245] The source line has a surface facing the laminate;

[0246] The memory film extends in the first direction within the columnar body and contacts the surface of the source line, and does not protrude beyond the surface of the source line to the substrate side.

[14]

[0248] A semiconductor storage device comprising:

[0249] substrate;

[0250] A transistor, disposed on the substrate;

[0251] A laminated body, arranged on the opposite side of the substrate relative to the transistor, formed by alternately laminating a plurality of gate electrode layers and a plurality of insulating layers in a first direction;

[0252] a columnar body extending in the first direction in the laminated body and comprising: an insulating core; a channel layer disposed between the multi-layer gate electrode layer and the insulating core; and a storage film disposed between the multi-layer gate electrode layer and the channel layer; and

[0253] a source line disposed between the laminate and the substrate and extending at least along a second direction intersecting the first direction; and

[0254] The columnar body has a first connection portion that is disposed at least between the insulating core and the source line and contains polysilicon.

[15]

[0256] A semiconductor storage device comprising:

[0257] substrate;

[0258] A transistor, disposed on the substrate;

[0259] A laminated body, arranged on the opposite side of the substrate relative to the transistor, formed by alternately laminating a plurality of gate electrode layers and a plurality of insulating layers in a first direction;

[0260] a columnar body extending in the first direction in the laminated body and comprising: an insulating core; a channel layer disposed between the multi-layer gate electrode layer and the insulating core; and a storage film disposed between the multi-layer gate electrode layer and the channel layer; and

[0261] The source line extends at least along a second direction intersecting the first direction; and

[0262] The columnar body has: a first end connected to the source line; and a second end located on the opposite side of the first end in the first direction; and the width of the first end in the second direction is greater than the width of the second end in the second direction;

[0263] There is no copper pad between the source line and the substrate.

[16]

[0265] A semiconductor storage device comprising:

[0266] substrate;

[0267] A transistor, disposed on the substrate;

[0268] A laminated body, arranged on the opposite side of the substrate relative to the transistor, formed by alternately laminating a plurality of gate electrode layers and a plurality of insulating layers in a first direction;

[0269] A columnar body extending in the first direction in the laminated body and comprising: an insulating core; a channel layer disposed between the multi-layer gate electrode layer and the insulating core; and a storage film disposed between the multi-layer gate electrode layer and the channel layer;

[0270] a source line extending at least along a second direction intersecting the first direction; and

[0271] Multiple touch points; and

[0272] The columnar body has: a first end connected to the source line; and a second end located on the opposite side of the first end in the first direction; and the width of the first end in the second direction is greater than the width of the second end in the second direction;

[0273] The multi-layer gate electrode layer includes: a first gate electrode layer; a second gate electrode layer disposed between the first gate electrode layer and the substrate; and a third gate electrode layer disposed between the second gate electrode layer and the substrate; and

[0274] The multiple contacts include: a first contact, which is connected to the first gate electrode layer; a second contact, which extends longer toward the substrate side than the first contact and is connected to the second gate electrode layer; and a third contact, which extends longer toward the substrate side than the second contact and is connected to the third gate electrode layer.

[17]

[0276] A semiconductor storage device comprising:

[0277] substrate;

[0278] A transistor, disposed on the substrate;

[0279] A laminated body, arranged on the opposite side of the substrate relative to the transistor, formed by alternately laminating a plurality of gate electrode layers and a plurality of insulating layers in a first direction;

[0280] A columnar body extending in the first direction in the laminated body and comprising: an insulating core; a channel layer disposed between the multi-layer gate electrode layer and the insulating core; and a storage film disposed between the multi-layer gate electrode layer and the channel layer;

[0281] a dividing portion that penetrates the laminate along the first direction, extends along the second direction intersecting the first direction, and divides each of the plurality of gate electrode layers in a third direction intersecting the first direction and the second direction; and

[0282] The source line extends at least along a second direction intersecting the first direction; and

[0283] The columnar body has: a first end connected to the source line; and a second end located on the opposite side of the first end in the first direction; and the width of the first end in the second direction is greater than the width of the second end in the second direction;

[0284] The dividing portion has: a third end connected to the source line; and a fourth end located on the opposite side of the third end in the first direction; and a width of the third end in the third direction is smaller than a width of the fourth end in the third direction.

[18]

[0286] A method for manufacturing a semiconductor memory device, comprising: preparing a first chip and a second chip; and

[0287] The first chip comprises:

[0288] substrate;

[0289] A transistor is disposed on the substrate; and

[0290] a first insulating portion covering the transistor; and

[0291] The second chip comprises:

[0292] A laminated body, formed by alternately laminating a plurality of first layers and a plurality of second layers in a first direction;

[0293] A columnar body extending in the laminate body along the first direction and comprising: an insulating core; a channel layer disposed between the first layer and the insulating core; and a storage film disposed between the first layer and the channel layer;

[0294] a source line extending at least along a second direction intersecting the first direction; and

[0295] a second insulating portion covering the source line; and

[0296] The first insulating portion and the second insulating portion are bonded together so that the source line is located between the laminate and the first chip.

[0297]

[19] The method for manufacturing a semiconductor memory device according to

[18] , wherein

[0298] The first layer is a sacrificial layer that is replaced with a conductive layer after the first insulating portion and the second insulating portion are bonded together.

[0299]

[20] . The method for manufacturing a semiconductor memory device according to

[18] , wherein the first layer is a conductive layer.

[0300] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the present invention. These embodiments and their variations are included in the scope and gist of the invention, and are also included in the invention described in the claims and their equivalents.

[0301] [Explanation of symbols]

[0302] 1, 1A, 1B, 1C, 1D…semiconductor storage device, 21…semiconductor substrate (substrate), 31…transistor, 51…laminate, 55…storage column (columnar body), 55a…lower end (first end), 55b…upper end (second end), 61…conductive layer (gate electrode layer), 62…insulating layer, 71…storage film (multilayer film), 72…channel layer, 73…insulating core, 74…first cover portion (first connecting portion), 75…second cover portion (second connecting portion), 81…contact, ST…dividing portion, 90a…lower end (first end), 90b…upper end (second end), 111, 112…electrical connecting portion, 121, 122, 123…through contact (contact).

Claims

1. A semiconductor storage device, comprising: substrate; A transistor, disposed on the substrate; A laminated body, arranged on the opposite side of the substrate relative to the transistor, formed by alternately laminating a plurality of gate electrode layers and a plurality of insulating layers in a first direction; a columnar body extending in the first direction in the laminated body and comprising: an insulating core; a channel layer disposed between the multi-layer gate electrode layer and the insulating core; and a storage film disposed between the multi-layer gate electrode layer and the channel layer; and a source line disposed between the laminate and the substrate and extending at least along a second direction intersecting the first direction; and The columnar body has a first end connected to the source line SL and a second end located on the opposite side of the first end in the first direction. The width of the first end in the second direction is greater than the width of the second end in the second direction.

2. The semiconductor memory device according to claim 1, wherein the source line has a surface facing the laminate; and The memory film extends in the first direction within the columnar body and contacts the surface of the source line, and does not protrude beyond the surface of the source line to the substrate side. 3 . The semiconductor memory device according to claim 1 , wherein the columnar body has a first connection portion, the first connection portion being disposed at least between the insulating core and the source line and containing polysilicon.

4. The semiconductor memory device according to claim 1, wherein the source line has a surface facing the laminated body; and The insulating core extends in the first direction within the columnar body and contacts the surface of the source line, and does not protrude beyond the surface of the source line to the substrate side. 5 . The semiconductor memory device according to claim 1 , wherein there is no copper pad between the source line and the substrate.

6. The semiconductor memory device according to claim 1, wherein the source line contains at least one of silicon and tungsten.

7. The semiconductor memory device according to claim 1, further comprising a bit line located on the opposite side of the source line relative to the pillar and extending in a third direction intersecting the first direction and the second direction; and The second end of the pillar is electrically connected to the bit line.

8. The semiconductor memory device according to claim 7, further comprising: a peripheral circuit including the transistor; and The contact extends from below the source line along the first direction to above the second end of the columnar body when the laminated body is viewed from the substrate as an upper side, and electrically connects the peripheral circuit and the bit line.

9. The semiconductor memory device according to claim 7, further comprising a connection wiring portion; and The columnar body has a second connection portion, the second connection portion is arranged at least between the insulating core and the bit line and contains polysilicon; The connection wiring section includes a plurality of copper wirings; The plurality of copper wirings are arranged above the second connection portion in the semiconductor memory device, and no copper wiring exists below the second connection portion.

10. The semiconductor memory device according to claim 1, further comprising a plurality of contacts; and The multi-layer gate electrode layer includes: a first gate electrode layer; a second gate electrode layer disposed between the first gate electrode layer and the substrate; and a third gate electrode layer disposed between the second gate electrode layer and the substrate; and The multiple contacts include: a first contact, which is connected to the first gate electrode layer; a second contact, which extends longer toward the substrate side than the first contact and is connected to the second gate electrode layer; and a third contact, which extends longer toward the substrate side than the second contact and is connected to the third gate electrode layer.

11. The semiconductor memory device according to claim 1, further comprising: a dividing portion that penetrates the laminate along the first direction, extends along the second direction, and divides each of the plurality of gate electrode layers in a third direction that intersects the first direction and the second direction; and The dividing portion has: a third end connected to the source line; and a fourth end located on the opposite side of the third end in the first direction; and a width of the third end in the third direction is smaller than a width of the fourth end in the third direction.

12. The semiconductor memory device according to claim 1, further comprising: a dividing portion that penetrates the laminate along the first direction, extends along the second direction, and divides each of the plurality of gate electrode layers in a third direction that intersects the first direction and the second direction; and The dividing portion has: a third end connected to the source line; and a fourth end located on the opposite side of the third end in the first direction; and a width of the third end in the third direction is greater than a width of the fourth end in the third direction.

13. A semiconductor memory device, comprising: substrate; A transistor, disposed on the substrate; A laminated body, arranged on the opposite side of the substrate relative to the transistor, formed by alternately laminating a plurality of gate electrode layers and a plurality of insulating layers in a first direction; a columnar body extending in the first direction in the laminated body and comprising: an insulating core; a channel layer disposed between the multi-layer gate electrode layer and the insulating core; and a storage film disposed between the multi-layer gate electrode layer and the channel layer; and a source line disposed between the laminate and the substrate and extending at least along a second direction intersecting the first direction; and The source line has a surface facing the laminate; The memory film extends in the first direction within the columnar body and contacts the surface of the source line, and does not protrude beyond the surface of the source line to the substrate side.

14. A semiconductor memory device, comprising: substrate; A transistor, disposed on the substrate; A laminated body, arranged on the opposite side of the substrate relative to the transistor, formed by alternately laminating a plurality of gate electrode layers and a plurality of insulating layers in a first direction; a columnar body extending in the first direction in the laminated body and comprising: an insulating core; a channel layer disposed between the multi-layer gate electrode layer and the insulating core; and a storage film disposed between the multi-layer gate electrode layer and the channel layer; and a source line disposed between the laminate and the substrate and extending at least along a second direction intersecting the first direction; and The columnar body has a first connection portion that is disposed at least between the insulating core and the source line and contains polysilicon.

15. A semiconductor memory device comprising: substrate; A transistor, disposed on the substrate; A laminated body, arranged on the opposite side of the substrate relative to the transistor, formed by alternately laminating a plurality of gate electrode layers and a plurality of insulating layers in a first direction; a columnar body extending in the first direction in the laminated body and comprising: an insulating core; a channel layer disposed between the multi-layer gate electrode layer and the insulating core; and a storage film disposed between the multi-layer gate electrode layer and the channel layer; and The source line extends at least along a second direction intersecting the first direction; and The columnar body has: a first end connected to the source line; and a second end located on the opposite side of the first end in the first direction; and the width of the first end in the second direction is greater than the width of the second end in the second direction; There is no copper pad between the source line and the substrate.

16. A semiconductor memory device, comprising: substrate; A transistor, disposed on the substrate; A laminated body, arranged on the opposite side of the substrate relative to the transistor, formed by alternately laminating a plurality of gate electrode layers and a plurality of insulating layers in a first direction; A columnar body extending in the first direction in the laminated body and comprising: an insulating core; a channel layer disposed between the multi-layer gate electrode layer and the insulating core; and a storage film disposed between the multi-layer gate electrode layer and the channel layer; A source line extending at least along a second direction intersecting the first direction; as well as Multiple touch points; and The columnar body has: a first end connected to the source line; and a second end located on the opposite side of the first end in the first direction; and the width of the first end in the second direction is greater than the width of the second end in the second direction; The multi-layer gate electrode layer includes: a first gate electrode layer; a second gate electrode layer disposed between the first gate electrode layer and the substrate; and a third gate electrode layer disposed between the second gate electrode layer and the substrate; The plurality of contacts include: a first contact in contact with the first gate electrode layer; a second contact extending longer than the first contact toward the substrate and in contact with the second gate electrode layer; and a third contact extending longer toward the substrate than the second contact and in contact with the third gate electrode layer.

17. A semiconductor memory device, comprising: substrate; A transistor, disposed on the substrate; A laminated body, arranged on the opposite side of the substrate relative to the transistor, formed by alternately laminating a plurality of gate electrode layers and a plurality of insulating layers in a first direction; A columnar body extending in the first direction in the laminated body and comprising: an insulating core; a channel layer disposed between the multi-layer gate electrode layer and the insulating core; and a storage film disposed between the multi-layer gate electrode layer and the channel layer; a dividing portion penetrating the laminate along the first direction, extending along the second direction intersecting the first direction, and dividing each of the plurality of gate electrode layers in a third direction intersecting the first direction and the second direction; as well as The source line extends at least along a second direction intersecting the first direction; and The columnar body has: a first end connected to the source line; and a second end located on the opposite side of the first end in the first direction; and the width of the first end in the second direction is greater than the width of the second end in the second direction; The dividing portion has: a third end connected to the source line; and a fourth end located on the opposite side of the third end in the first direction; and a width of the third end in the third direction is smaller than a width of the fourth end in the third direction.

18. A method for manufacturing a semiconductor memory device, comprising: preparing a first chip and a second chip; and The first chip comprises: substrate; A transistor is disposed on the substrate; and a first insulating portion covering the transistor; and The second chip comprises: A laminated body, formed by alternately laminating a plurality of first layers and a plurality of second layers in a first direction; A columnar body extending in the laminated body along the first direction and comprising: an insulating core; a channel layer disposed between the first layer and the insulating core; and a storage film, disposed between the first layer and the channel layer; A source line extending at least along a second direction intersecting the first direction; as well as a second insulating portion covering the source line; and The first insulating portion and the second insulating portion are bonded together so that the source line is located between the laminate and the first chip. 19 . The method for manufacturing a semiconductor memory device according to claim 18 , wherein the first layer is a sacrificial layer that is replaced with a conductive layer after the first insulating portion and the second insulating portion are bonded together.

20. The method for manufacturing a semiconductor memory device according to claim 18, wherein the first layer is a conductive layer.

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