Array substrate and display panel

Abstract

The invention provides an array substrate and a display panel, and relates to the technical field of display, and the array substrate comprises a substrate; the active layer, the gate driving layer and the source and drain electrode layer are arranged on the substrate; the insulating layer is formed on the source and drain electrode layer, and a touch signal line is arranged in the insulating layer; the common electrode layer, the passivation layer and the pixel electrode layer are arranged on the insulating layer; wherein the common electrode layer is electrically connected with a touch signal line through a first via hole, the pixel electrode layer is electrically connected with a drain electrode of the source and drain electrode layer through a second via hole, the pixel electrode layer located in the second via hole is formed by a composite material layer, and the composite material layer comprises an organic conductive polymer material layer and a transparent metal oxide material layer which are arranged in a stacked mode. According to the technical scheme provided by the invention, the line breaking rate in the array substrate can be reduced, and the reliability of the array substrate is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] With the rapid development of liquid crystal display technology, touch display devices have been widely used in various fields due to their advantages such as ease of use, fast response speed and space saving.

[0003] According to the setting mode of the touch sensing layer, it can be divided into add-on mode, in-cell and on-cell structures. Among them, the in-cell structure integrates the touch sensor into the embedded liquid crystal display layer, so it can effectively reduce the thickness of the entire display panel, making the product thinner and lighter. In the related art, the electrode layer is usually made of indium tin oxide (ITO), but ITO has high hardness and brittleness, which makes ITO easy to break when subjected to external force. In addition, in the production process of the array substrate, especially in the vias where the touch electrode is formed, ITO may cause defects inside the touch electrode due to process problems, resulting in broken wires, resulting in reduced reliability of the array substrate. Summary of the invention

[0004] In view of this, the present application provides an array substrate and a display panel, which are used to improve the reliability of the array substrate.

[0005] In order to achieve the above-mentioned object, in a first aspect, an embodiment of the present application provides an array substrate, the array substrate comprising:

[0006] substrate substrate;

[0007] An active layer, a gate driving layer, and a source-drain layer are arranged on the substrate;

[0008] An insulating layer formed on the source and drain electrode layer, wherein a touch signal line is disposed in the insulating layer;

[0009] Disposing a common electrode layer, a passivation layer and a pixel electrode layer on the insulating layer;

[0010] Among them, the common electrode layer is electrically connected to the touch signal line through a first via hole, the pixel electrode layer is electrically connected to the drain electrode of the source and drain electrode layer through a second via hole, and the pixel electrode layer located in the second via hole is formed by a composite material layer, and the composite material layer includes a stacked organic conductive polymer material layer and a transparent metal oxide material layer.

[0011] In a possible implementation manner of the first aspect, the insulating layer includes an organic insulating layer and an inorganic insulating layer stacked together, the touch signal line is located between the organic insulating layer and the inorganic insulating layer, and the touch signal line includes a first signal line and a second signal line connected to each other;

[0012] The first via hole penetrates the inorganic insulating layer to expose the first signal line, and the second via hole penetrates the passivation layer, the inorganic insulating layer and the organic insulating layer to expose the drain electrode;

[0013] The common electrode layer includes a first common electrode and a second common electrode arranged at intervals, and the first common electrode is electrically connected to the first signal line through the first via hole; part of the pixel electrode layer, part of the second common electrode and part of the second signal line are located in the second via hole, and in the second via hole, the pixel electrode layer is electrically connected to the drain through the second common electrode and the second signal line in turn.

[0014] In a possible implementation of the first aspect, the organic conductive polymer material layer includes: a first organic conductive polymer material layer and a second organic conductive polymer material layer, and the first organic conductive polymer material layer, the transparent metal oxide material layer and the second organic conductive polymer material layer are stacked.

[0015] In a possible implementation of the first aspect,

[0016] The pixel electrode layer includes a first pixel electrode and a second pixel electrode;

[0017] The insulating layer is an organic insulating layer, the source-drain electrode layer covers a portion of the gate driving layer, the organic insulating layer covers the source-drain electrode layer and another portion of the gate driving layer, and the touch signal line is formed on the other portion of the gate driving layer;

[0018] The first via hole includes a first sub-via hole and a second sub-via hole, the first pixel electrode is electrically connected to the common electrode layer through the first sub-via hole, and the first pixel electrode is electrically connected to the touch signal line through the second sub-via hole;

[0019] The second pixel electrode is electrically connected to the drain electrode through a second via hole.

[0020] In a possible implementation of the first aspect, the common electrode layer includes a first common electrode and a second common electrode that are spaced apart from each other, the first pixel electrode layer is electrically connected to the first common electrode through the first sub-via hole, and the second via hole is located between the first common electrode and the second common electrode.

[0021] In a possible implementation manner of the first aspect, the first pixel electrode located in the first via hole and the second pixel electrode located in the second via hole are both formed by using the composite material layer.

[0022] In a possible implementation manner of the first aspect, the second via hole is formed by using a one-time photomask process after forming the organic insulating layer and the passivation layer.

[0023] In a possible implementation of the first aspect, the gate drive layer includes a stacked gate insulating layer, a gate layer, and an interlayer dielectric layer, the gate layer includes a gate line, and at least a portion of the gate line is formed by a stacked metal layer and an organic conductive polymer material layer.

[0024] In a possible implementation of the first aspect, the organic conductive polymer is PEDOT, and the transparent metal oxide is ITO.

[0025] In a second aspect, an embodiment of the present application provides a display panel, comprising: an array substrate as described in the first aspect or any one of the first aspects, an opposing substrate arranged opposite to the array substrate, and a display medium layer located between the array substrate and the opposing substrate.

[0026] The array substrate provided in the embodiment of the present application includes a base substrate; an active layer, a gate driving layer, and a source-drain electrode layer arranged on the base substrate; an insulating layer formed on the source-drain electrode layer, in which a touch signal line is arranged; a common electrode layer, a passivation layer, and a pixel electrode layer arranged on the insulating layer; wherein the common electrode layer is electrically connected to the touch signal line through a first via hole, the pixel electrode layer is electrically connected to the drain electrode of the source-drain electrode layer through a second via hole, and the pixel electrode layer located in the second via hole is formed by a composite material layer, and the composite material layer includes a stacked organic conductive polymer material layer and a transparent metal oxide material layer. The technical solution provided in the present application can reduce the occurrence of disconnection in the array substrate and improve the reliability of the array substrate.

[0027] It can be understood that the beneficial effects of the second aspect mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic diagram of the structure of a first array substrate provided in an embodiment of the present application;

[0029] Figure 2 An oblique view of the routing of the gate lines of the non-curved display panel provided in an embodiment of the present application;

[0030] Figure 3 An oblique view of the routing of the gate lines of the curved display panel provided in an embodiment of the present application;

[0031] Figure 4 A schematic diagram of a non-touch array substrate provided in an embodiment of the present application;

[0032] Figure 5 A schematic diagram of the film structure of an organic conductive polymer material layer and a transparent metal oxide material layer provided in an embodiment of the present application;

[0033] Figure 6A-6C A schematic flow chart of a method for preparing a pixel electrode layer provided in an embodiment of the present application;

[0034] Figure 7 A schematic diagram of a second array substrate provided in an embodiment of the present application;

[0035] Figure 8 A schematic diagram of the structure of a display panel provided in an embodiment of the present application.

[0036] Description of reference numerals:

[0037] 10-substrate substrate; 11-active layer; 12-gate driving layer; 120-gate insulating layer; 121-gate layer; 122-interlayer dielectric layer; 13-source-drain electrode layer; 130-source electrode; 131-drain electrode;

[0038] 14-insulating layer; 140-organic insulating layer; 141-inorganic insulating layer; 15-common electrode layer; 150-first common electrode; 151-second common electrode; 16-passivation layer;

[0039] 17-pixel electrode layer; 170-organic conductive polymer material layer; 171-transparent metal oxide material layer; 17a-first pixel electrode; 17b-second pixel electrode; 18-touch signal line; 180-first signal line; 181-second signal line;

[0040] 19 - first contact hole; 20 - second contact hole; 21 - second via hole; 22 - first via hole; 220 - first sub-via hole; 221 - second sub-via hole; 23 - third contact hole;

[0041] 100 - array substrate; 200 - opposite substrate; 300 - display medium layer. DETAILED DESCRIPTION

[0042] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application. The terms used in the implementation method section of the embodiments of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0043] In an embedded touch display panel, a touch signal line is provided in the array substrate, which can respond to a touch operation after receiving a user's touch operation. In existing display panels, when preparing the electrode layer, a deposition process is usually used to deposit ITO material. However, when the tapper angle of the process hole (or via) in the array substrate is too large or the ITO is subjected to stress, poor hole overlap or even wire breakage may occur, resulting in abnormal touch, which will reduce the reliability of the array substrate and cause customer complaints.

[0044] In view of this, the present application provides an array substrate, which may include: a base substrate, an active layer, a gate drive layer, a source-drain layer arranged on the base substrate, an insulating layer formed on the source-drain layer, and a touch signal line may be arranged in the insulating layer. A common electrode layer, a passivation layer, and a pixel electrode layer are arranged on the insulating layer. Among them, the common electrode layer can be electrically connected to the touch signal line through a first via hole, the pixel electrode layer can be electrically connected to the drain of the source-drain layer through a second via hole, and the pixel electrode layer located in the second via hole can be formed by a composite material layer, and the composite material layer may include an organic conductive polymer material layer and a transparent metal oxide material layer stacked.

[0045] The array substrate described in the embodiments of the present application is described below by way of example using two specific embodiments in combination with the accompanying drawings and implementation modes.

[0046] Embodiment 1

[0047] Figure 1 This is a schematic diagram of the structure of the array substrate provided in the embodiment of the present application. Figure 1 As shown, the array substrate may include a stacked base substrate 10, an active layer 11 and a gate driving layer 12, a source and drain layer 13, an insulating layer 14, a common electrode layer 15, a passivation layer 16 and a pixel electrode layer 17, and a touch signal line 18 is also arranged in the insulating layer 14.

[0048] The material of the base substrate 10 may be quartz, glass, organic polymer, silicon, metal or other semiconductor materials. In some embodiments, the base substrate 10 may also be a flexible substrate, and the material may be polyimide.

[0049] It should be noted that when the base substrate 10 is a transparent substrate, a light shielding layer (not shown) may be formed between the base substrate 10 and the active layer 11 to shield the backlight and prevent the active layer 11 from being irradiated by the backlight to generate photogenerated carriers, thereby increasing the leakage current of the device. The material of the light shielding layer may be a light-absorbing and shielding material such as amorphous silicon or metal, and the present application does not impose any particular limitation on this.

[0050] The active layer 11 can be prepared in a partial area on the substrate 10. During the preparation, a chemical vapor deposition process can be used to deposit semiconductor materials, and the semiconductor materials are subjected to a mask process to form the active layer. The mask process can mainly include: coating photoresist, patterning and developing the photoresist, etching (dry etching or wet etching), and removing the photoresist.

[0051] The gate drive layer 12 may include a gate insulating layer 120, a gate layer 121, and an interlayer dielectric layer 122 that are stacked. The gate insulating layer 120 may cover the active layer 11 and the base substrate 10 to increase the gate electrode capacitance, thereby enhancing the gate's control over the channel. The material of the gate insulating layer 120 may be any one or more of oxides, nitrides, or oxynitrides, such as silicon nitride. The material of the interlayer dielectric layer 122 may be one or more of silicon oxide, silicon nitride, silicon oxide, and silicon nitride.

[0052] The gate layer 121 may include a plurality of gate lines, and is usually made of one or more inorganic metals such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper. Figure 2 This is an oblique view of the routing of the gate lines of the non-curved display panel provided in an embodiment of the present application. Figure 3 This is an oblique view of the routing of the gate lines of the curved display panel provided in the embodiment of the present application, see Figure 1-Figure 3 The gate line 1210 is horizontally arranged in the gate layer 121 of the display panel to provide a scanning signal to the gate of the thin film transistor. For a curved display panel, the gate line 1210 is in a curved state at the edge area of ​​the display panel. During the edge curved surface manufacturing process and product use, it is easy to be brittle or even broken under the action of bending stress, resulting in abnormal touch control and abnormal visual effects of partial display screen breakage.

[0053] In one possible implementation, an organic conductive polymer material may be used in the edge region to prepare the gate line 1210. The organic conductive polymer material may be poly(3,4-ethylenedioxythiophene) (PEDOT). PEDOT has good flexibility and ductility as well as excellent electrical conductivity, and thus can effectively resist bending stress and reduce the occurrence of line breakage. In addition, since the PEDOT layer is a light-transmitting layer, the amount of shading can also be reduced, thereby improving the utilization rate of light. Of course, PEDOT can also be used in the flat region to prepare the gate line 1210, so that the preparation materials of the same routing are the same to reduce the difficulty of preparation.

[0054] Taking into account that the material of PEDOT is relatively soft, in order to reduce scratches on the PEDOT layer during the process, in some embodiments, a transparent metal oxide material layer or a metal layer can also be prepared on one side of the PEDOT layer. This can not only improve the brittleness and breakage of the gate line 1210, but also reduce scratches on the PEDOT layer, extend the service life of the gate line 1210, and thus improve the reliability of the array substrate.

[0055] It is understandable that, taking the metal layer as an example, since the PEDOT layer is only arranged on one side of the metal layer, when the curvature of the edge area is large, cracks may occur on the side of the metal layer away from the PEDOT layer, resulting in abnormal resistance and electrical properties. In other embodiments, the PEDOT layer can also be arranged on the upper and lower sides of the metal layer.

[0056] It is understandable that the above description is based on the gate line 1210 as an example. In some embodiments, other metal traces of the array substrate, such as data lines, can also be prepared using organic conductive polymer materials or a composite film layer of organic conductive polymer materials and metal layers.

[0057] The interlayer dielectric layer 122 can prevent interlayer short circuits and signal interference, and improve the overall performance and energy efficiency of the array substrate. The material of the interlayer dielectric layer 122 can be one or more of silicon oxide, silicon nitride, silicon oxide and silicon nitride. When preparing the interlayer dielectric layer 122, a chemical vapor deposition process can be used on the gate layer 121 to prepare it.

[0058] After forming the interlayer dielectric layer 122, the interlayer dielectric layer 122 and the gate insulating layer 120 may be dry-etched by a photomask process to form a first contact hole 19 and a second contact hole 20, both of which penetrate the interlayer dielectric layer 122 and expose the active layer 11. Afterwards, a source-drain metal layer may be formed on the interlayer dielectric layer 122 by a physical vapor deposition process or a sputtering process, and a source-drain electrode layer 13 may be formed by a photomask process, wherein the source-drain electrode layer 13 may include a source electrode 130 and a drain electrode 131, the source electrode 130 may be electrically connected to the active layer 11 through the first contact hole 19, and the drain electrode 131 may be electrically connected to the active layer 11 through the second contact hole 20. In some embodiments, the material of the source-drain electrode layer 13 may be the same as that of the gate layer 121.

[0059] After the source-drain electrode layer 13 is formed, an insulating layer 14 may be formed over the source-drain electrode layer 13. In this embodiment, the insulating layer 14 may include an organic insulating layer 140 and an inorganic insulating layer 141 stacked in layers. Figure 1The touch signal line 18 may be located between the organic insulating layer 140 and the inorganic insulating layer 141. For example, the organic insulating layer 140 may be formed on the source and drain electrode layer 13, and the material of the organic insulating layer 140 may be indium gallium zinc oxide. Then, a photomask process may be used to form the second via hole 21 to expose the drain electrode 131.

[0060] Exemplarily, a metal material may be deposited on the organic insulating layer 140 by a physical vapor deposition process to form a touch metal layer, and the touch metal layer may be subjected to a mask process to form a first signal line 180 and a second signal line 181 that are interconnected. The material of the touch signal line 18 may be the same as that of the gate layer 121 to reduce the difficulty of preparation. The first signal line 180 may be located above the source 130 to reduce the amount of light shielding. Of course, the first signal line 180 may also be located at other locations, such as on the side of the drain 131 away from the source 130. Part of the second signal line 181 may be located in the second via 21 and connected to the drain 131 through the second via 21.

[0061] An inorganic insulating material may be deposited on the touch signal line 18 and the organic insulating layer 140 by a chemical vapor deposition process to form an inorganic insulating layer 141. The inorganic insulating layer 141 may be made of an inorganic insulating material such as silicon nitride, silicon oxide, or silicon hydroxide. A first via 22 is formed on the inorganic insulating layer 141 by a photomask process to expose the first signal line 180, and the inorganic insulating material in the second via 21 is removed to expose the drain 142.

[0062] Afterwards, a common electrode layer 15 may be formed on the inorganic insulating layer 141. Exemplarily, a physical vapor deposition process may be used to deposit the common electrode material, and a mask process may be used to form a first common electrode 150 and a second common electrode 151 that are spaced apart. By dividing the common electrode layer 15, the embodiment of the present application can more accurately control the electric field distribution, thereby optimizing the display effect, enhancing the reliability of the array substrate, and reducing the risk of failure of the entire display panel due to a single electrode failure. Among them, the first common electrode 150 may be electrically connected to the first signal line 180 through the first via hole 22. Part of the second common electrode 162 may be located in the second via hole 21 and electrically connected to the drain 131 through the second signal line 181.

[0063] By electrically connecting the first common electrode 150 to the first signal line 180, and the second common electrode 151 to the second signal line 181, the first common electrode 150 and the second common electrode 151 can be reused as touch electrodes. On the one hand, there is no need to set different film layer structures for the touch electrode and the common electrode, respectively, thereby simplifying the film layer structure of the display panel and reducing the thickness of the display panel; on the second hand, this can reduce the process flow and preparation cost caused by the additional preparation of touch electrodes, and help reduce the complexity of material and process preparation; on the third hand, the touch electrode is usually made of metal material. By reusing the common electrode layer 15, the weight of the display panel can be reduced, so as to achieve lightweight display panel; on the fourth hand, by reusing the common electrode layer, the sensitivity and accuracy of touch sensing can also be improved.

[0064] It is understandable that, in some embodiments, the common electrode layer 15 may further include a third common electrode. The number of the third common electrodes may be plural and connected to the second common electrode 151 by a bridge, thereby increasing the driving area of ​​the liquid crystal.

[0065] A passivation layer 16 may be further prepared on the common electrode layer 15. Exemplarily, a chemical vapor deposition process may be used to deposit a passivation layer material on the inorganic insulating layer 141 and the common electrode layer 15, and a photomask process may be used on the passivation layer material to remove at least a portion of the passivation layer material in the second via hole 21 to form the passivation layer 16. A pixel electrode material may be deposited on the passivation layer 16, and a photomask process may be used on the pixel electrode material to form a pixel electrode layer 17 after patterning, and a portion of the pixel electrode layer 17 is located in the second via hole 21 and is electrically connected to the second common electrode 162.

[0066] Figure 4 This is a schematic diagram of a non-touch array substrate provided in an embodiment of the present application, see Figure 1 and Figure 4 Compared with the non-touch array substrate, since the present solution adds the inorganic insulating layer 151 and the touch signal line 190, taking the thickness of the inorganic insulating layer 141 as 0.25-1.5 um as an example, the hole depth is also increased accordingly. When preparing the second via hole 21, since the materials of the organic insulating layer 140 and the inorganic insulating layer 141 are different, the etching rates of the organic insulating layer 140 and the inorganic insulating layer 141 are also different, and the tapper angle of the inorganic insulating layer 140 is larger. The pixel electrode layer 17 is more likely to crack or even break when climbing, thereby causing display abnormality of the display panel.

[0067] In an optional implementation, the pixel electrode layer 17 located in the second via hole 21 can be formed by a composite material layer, and the composite material layer includes a stacked organic conductive polymer material layer and a transparent metal oxide material layer. The organic conductive polymer can be PEDOT, and the transparent metal oxide can be ITO. PEDOT has the characteristics of good ductility, excellent electrical conductivity, high visible light transmittance and low cost, which can effectively reduce the occurrence of cracks and disconnection in the pixel electrode layer 17. Of course, the pixel electrode layer 17 can also be prepared by a composite material layer on the entire surface. In some embodiments, the composite material layer can also be prepared by forming a mixed solution of an organic conductive polymer material and a transparent metal oxide material.

[0068] In some embodiments, polystyrene sulfonic acid (PSS) may be doped into PEDOT to further improve flexibility and stretchability, thereby improving the ability of the organic conductive polymer material layer to resist stress.

[0069] See also Figure 1 , the organic conductive polymer material layer 170 may be disposed below the transparent metal oxide material layer 171 . It is understood that the transparent metal oxide material layer 171 may also be disposed below the organic conductive polymer material layer 170 .

[0070] In some embodiments, see Figure 5 The organic conductive polymer material layer 170 may also include: a first organic conductive polymer material layer 1700 and a second organic conductive polymer material layer 1701. The first organic conductive polymer material layer 1700, the transparent metal oxide material layer 171 and the second organic conductive polymer material layer 1701 may be stacked from bottom to top, which may further reduce the disconnection of the pixel electrode layer 17.

[0071] The following examples all take the transparent metal oxide material layer 171 disposed on the organic conductive polymer material layer 170 as an example. Figure 6A-6C Schematic diagram of the method for preparing the pixel electrode layer provided in the embodiment of the present application. When preparing the pixel electrode layer 17, a solution of an organic conductive polymer material can be first applied to the target area (e.g., the area selected by the dotted line in the figure) where the organic conductive polymer material layer 170 is to be formed on the passivation layer 16 by means of a stamp coating method, and then the solution is heated to solidify the solution into a film to form the organic conductive polymer material layer 170, see Fig. 6A Afterwards, a sputtering process may be used to deposit a whole layer of transparent metal oxide on the organic conductive polymer material layer 170 to form a transparent metal oxide material layer 171. A photoresist layer A is coated on the transparent metal oxide material layer 171. Figure 6BThe photoresist layer A is exposed and developed using a mask (not shown) to expose the transparent metal oxide material layer 171 to be etched, and then the transparent metal oxide material layer 171 above the passivation layer 16 is removed by wet etching, leaving only the transparent metal oxide material layer 171 above the organic conductive polymer material layer 170, and finally the remaining photoresist layer A is removed to form a pixel electrode layer 17, as shown in FIG. Figure 6C shown.

[0072] In some embodiments, the organic conductive polymer material layer 170 is disposed above the transparent metal oxide material layer 171. During preparation, the transparent metal oxide material layer 171 can be first sputtered on the passivation layer 16, and then the transparent metal oxide material layer 171 is wet-etched to retain only the transparent metal oxide material layer 171 in the target area. Thereafter, the organic conductive polymer material layer 170 is formed on the transparent metal oxide material layer 171. This can also reduce the damage to the underlying organic conductive polymer material layer 170 when etching the transparent metal oxide material layer 171.

[0073] The thickness ratio of the organic conductive polymer material layer 170 and the transparent metal oxide material layer 171 may be 2:1, so as to ensure conductivity while reducing the possibility of line breakage. Of course, the specific thickness ratio may be determined according to actual needs.

[0074] Through the above-mentioned implementation, in the display stage, after the gate line 1210 applies a scanning signal to the thin film transistor, the thin film transistor is turned on, and the drain 131 can apply a driving voltage to the pixel electrode layer 17 through the second signal line 181 and the second common electrode 151, and sequentially apply a driving voltage to the first common electrode 150 through the second signal line 181 and the first signal line 180, wherein the driving voltage applied to the first common electrode 150 has a voltage difference with the driving voltage applied to the pixel electrode layer 17 due to impedance and other reasons, thereby driving the liquid crystal to deflect, so that the display panel can display the picture.

[0075] During the touch stage, if the user touches the area above the first common electrode 150 or the second common electrode 151, taking the user touching the first common electrode 150 as an example, the touch operation can cause a change in the capacitance value of the first common electrode 150, and the change in the capacitance value can be transmitted to the touch chip through the first signal line 180 to achieve touch sensing.

[0076] Second embodiment

[0077] Compared with the first embodiment, the main difference of this embodiment lies in the film layer structure above the interlayer dielectric layer.

[0078] Specifically, Figure 7This is a schematic diagram of a second array substrate provided in an embodiment of the present application. Figure 7 Above the interlayer dielectric layer 122 , a source-drain electrode layer 13 , an insulating layer, a common electrode layer 15 , a passivation layer 16 and a pixel electrode layer 17 may be stacked.

[0079] The source-drain electrode layer 13 may partially cover the interlayer dielectric layer 122. The insulating layer may be an organic insulating layer 140, thereby reducing the stress difference between different materials and providing a flat surface for the preparation of subsequent film layers. The organic insulating layer 140 may cover the source-drain electrode layer 13 and another portion of the interlayer dielectric layer 122, and the touch signal line 18 may be formed on another portion of the interlayer dielectric layer 122.

[0080] After forming the interlayer dielectric layer 122, when using a photomask process, in addition to forming the first contact hole 19 and the second contact hole 20, a third contact hole 23 may be formed to expose the gate layer 121. Then, a source-drain metal layer may be formed above the interlayer dielectric layer 122, and the source-drain metal layer may be subjected to a photomask process so that the source electrode 130, the drain electrode 131 and the touch signal line 18 may be formed simultaneously, and the touch signal line 18 is electrically connected to the gate layer 121, and the source electrode 130 and the drain electrode 131 are electrically connected to the active layer 11. By covering the touch signal line 18 and the source-drain electrode layer 13 with an organic insulating layer 140, it is unnecessary to prepare an inorganic insulating layer, thereby reducing the film structure and further reducing the thickness of the display panel.

[0081] The organic insulating layer 140 can be prepared by a chemical vapor deposition process. The first via 22 may include a first sub-via 220 and a second sub-via 221. Exemplarily, a photomask process can be used for the organic insulating layer 140 to form a first sub-via 220 exposing the touch signal line 18 and a second via 21 exposing the drain 131. A common electrode material can be deposited on the organic insulating layer 140 by a sputtering process or a physical vapor deposition process to form a common electrode layer 15. A passivation layer 16 can be formed on the common electrode layer 15 by a chemical vapor deposition process. A photomask process is used for the passivation layer 16 to remove the passivation layer material in the first sub-via 220 and the second via 21, and a second sub-via 221 is formed on the common electrode layer 15.

[0082] Considering that both the second via 21 and the first sub-via 220 have steps at the interlayer junction of the organic insulating layer 140 and the passivation layer 16, and the tapper angle difference is relatively obvious, it is easy to produce burrs, fractures or missing at the step turning points, resulting in changes in the resistance, electrical properties and surface roughness of the pixel electrode layer 17.

[0083] In some embodiments, an organic insulating layer 140, a common electrode layer 15 and a passivation layer 16 may be formed in sequence first, and then the passivation layer 16 and the organic insulating layer 140 may be etched in sequence using a single photomask process to form a first sub-via 220 exposing the touch signal line 18 and a second via 21 exposing the drain 131, and the passivation layer 16 may be etched to form a second sub-via 221 exposing the common electrode layer 15.

[0084] Since the second sub-via hole 221 exposes the common electrode layer 15, the etching gas of the dry etching will not etch the common electrode layer 15. Through the above embodiment, on the one hand, the first sub-via hole 220, the second sub-via hole 221 and the second via hole 21 can be formed by only one mask, thereby reducing the use of masks and reducing the preparation cost; on the other hand, this can also reduce the step, so that the tapper angle at the interface between layers is close or even the same, so as to reduce the situation of broken wires and improve the reliability of the array substrate.

[0085] A pixel electrode material may be deposited on top of the passivation layer 16 and the pixel electrode material may be subjected to a photomask process and patterned to form a first pixel electrode 17a and a second pixel electrode 17b. The first pixel electrode 17a may be electrically connected to the common electrode layer 15 through the first sub-via 220, and the first pixel electrode 17a may also be electrically connected to the touch signal line 18 through the second sub-via 221, and the second pixel electrode 17b may be electrically connected to the drain 131 through the second via 21.

[0086] The first pixel electrode 17a located in the first via hole 22 can be formed by a composite material layer. Of course, the pixel electrode layer 17 can also be made of a composite material layer to reduce the difficulty of preparation. Figure 7 Only the first pixel electrode 17a is used for exemplary description. Compared with the first embodiment, since the array substrate described in this embodiment does not include an inorganic insulating layer, the hole depth is shallower, and the thickness ratio of the organic conductive polymer material layer 170 and the transparent metal oxide material layer 171 can be 1:1, thereby reducing the material cost. The preparation method and stacking method of the composite material layer can refer to the first embodiment, and will not be repeated here.

[0087] In some embodiments, the common electrode layer 15 may include a first common electrode 150 and a second common electrode 151 that are spaced apart. The first common electrode 150 may be electrically connected to the touch signal line 18 through the first pixel electrode 17a. The second via hole 21 may be located between the first common electrode 150 and the second common electrode 151. Specifically, the spacing distance between the first common electrode 150 and the second common electrode 151 may be greater than the aperture of the second via hole 21 to improve the connection reliability between the second pixel electrode 17b and the drain electrode 131.

[0088] In the display stage, the thin film transistor is turned on, the drain 131 applies a driving voltage to the second pixel electrode 17b, and the gate layer 121 can apply a driving voltage to the common electrode layer 15 through the touch signal line 18. Since there is a voltage difference between the driving voltage applied to the second pixel electrode 17b and the driving voltage applied to the first common electrode 150, the liquid crystal can be driven to deflect, so that the display panel can display the picture.

[0089] During the touch stage, the first common electrode 150 can be reused as a touch electrode. If the user touches the area above the first common electrode 150, the touch operation can cause the capacitance value of the first common electrode 150 to change, and it is transmitted to the touch chip through the touch signal line 18 to achieve touch sensing.

[0090] It should be noted that in the embodiments of the present application, when performing the mask process, the masks used can be the same or different, and the thickness of each film layer structure can also be determined according to actual needs. The embodiments of the present application do not impose any special restrictions on this. Moreover, the embodiments of the present application can be used not only for liquid crystal display devices, but also for organic light emitting diode display devices, etc. Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these modifications and variations.

[0091] The array substrate provided in the embodiment of the present application includes a base substrate; an active layer, a gate driving layer, and a source-drain electrode layer arranged on the base substrate; an insulating layer formed on the source-drain electrode layer, in which a touch signal line is arranged; a common electrode layer, a passivation layer, and a pixel electrode layer arranged on the insulating layer; wherein the common electrode layer is electrically connected to the touch signal line through a first via hole, the pixel electrode layer is electrically connected to the drain electrode of the source-drain electrode layer through a second via hole, and the pixel electrode layer located in the second via hole is formed by a composite material layer, and the composite material layer includes a stacked organic conductive polymer material layer and a transparent metal oxide material layer. The technical solution provided in the present application can reduce the occurrence of disconnection in the array substrate and improve the reliability of the array substrate.

[0092] Based on the same inventive concept, an embodiment of the present application also provides a display panel. Figure 8 A schematic diagram of the structure of a display panel provided in an embodiment of the present application is shown in FIG. Figure 8 As shown, the display panel may include the array substrate 100 described in any of the above embodiments, an opposite substrate 200 disposed opposite to the array substrate, and a display medium layer 300 located between the array substrate 100 and the opposite substrate 200 .

[0093] The liquid crystal in the display medium layer 300 can be deflected under the drive of the array substrate 100 to transmit light, and the light is emitted from the display panel after being filtered by the opposite substrate 200, so that the picture is displayed on the display panel.

[0094] Since the display panel in this embodiment includes the array substrate in the above embodiment, that is, the display panel in this embodiment has all the technical features and technical effects of the above array substrate embodiments, specific reference is made to the above embodiment and no further details are given here.

[0095] It should be understood that in the description of the present application specification and the appended claims, the terms "include", "comprises", "has" and any variations thereof are intended to cover non-exclusive inclusions and mean "including but not limited to", unless otherwise specifically emphasized.

[0096] In the description of this application, unless otherwise specified, " / " indicates that the objects associated with each other are in an "or" relationship. For example, A / B can represent A or B. "And / or" in this application is used to describe the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural.

[0097] Furthermore, in the description of the present application, unless otherwise specified, "plurality" refers to two or more than two. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items.

[0098] In addition, in the description of the present application, it should be understood that the terms "longitudinal", "horizontal", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "vertical", "top", "bottom", "inside", "outside", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0099] In the present application, unless otherwise clearly specified and limited, the terms "connection", "connected", etc. should be understood in a broad sense. For example, it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium. It can be the internal connection of two elements or the interaction relationship between two elements. Unless otherwise clearly defined, ordinary technicians in this field can understand the specific meanings of the above terms in this application according to the specific circumstances.

[0100] In addition, in the description of the present specification and the appended claims, the terms "first", "second", etc. are used to distinguish similar objects, but not necessarily to describe a specific order or sequence, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein; the features defined as "first" or "second" may explicitly or implicitly include at least one of the features.

[0101] In the embodiments of the present application, the words "exemplarily" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplarily" or "for example" is intended to present related concepts in a specific way.

[0102] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. appearing in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, characterized in that: include: substrate substrate; An active layer, a gate driving layer, and a source-drain layer are arranged on the substrate; An insulating layer formed on the source and drain electrode layer, wherein a touch signal line is disposed in the insulating layer; A common electrode layer, a passivation layer and a pixel electrode layer are arranged on the insulating layer; Among them, the common electrode layer is electrically connected to the touch signal line through a first via hole, the pixel electrode layer is electrically connected to the drain electrode of the source and drain electrode layer through a second via hole, and the pixel electrode layer located in the second via hole is formed by a composite material layer, and the composite material layer includes a stacked organic conductive polymer material layer and a transparent metal oxide material layer.

2. The array substrate according to claim 1, characterized in that: The insulating layer includes an organic insulating layer and an inorganic insulating layer stacked together, the touch signal line is located between the organic insulating layer and the inorganic insulating layer, and the touch signal line includes a first signal line and a second signal line connected to each other; The first via hole penetrates the inorganic insulating layer to expose the first signal line, and the second via hole penetrates the passivation layer, the inorganic insulating layer and the organic insulating layer to expose the drain electrode; The common electrode layer includes a first common electrode and a second common electrode arranged at intervals, and the first common electrode is electrically connected to the first signal line through the first via hole; part of the pixel electrode layer, part of the second common electrode and part of the second signal line are located in the second via hole, and in the second via hole, the pixel electrode layer is electrically connected to the drain through the second common electrode and the second signal line in turn.

3. The array substrate according to claim 1, characterized in that: The organic conductive polymer material layer includes: a first organic conductive polymer material layer and a second organic conductive polymer material layer, wherein the first organic conductive polymer material layer, the transparent metal oxide material layer and the second organic conductive polymer material layer are stacked.

4. The array substrate according to claim 1, characterized in that: The pixel electrode layer includes a first pixel electrode and a second pixel electrode; The insulating layer is an organic insulating layer, the source-drain electrode layer covers a portion of the gate driving layer, the organic insulating layer covers the source-drain electrode layer and another portion of the gate driving layer, and the touch signal line is formed on the other portion of the gate driving layer; The first via hole includes a first sub-via hole and a second sub-via hole, the first pixel electrode is electrically connected to the common electrode layer through the first sub-via hole, and the first pixel electrode is electrically connected to the touch signal line through the second sub-via hole; The second pixel electrode is electrically connected to the drain electrode through a second via hole.

5. The array substrate according to claim 4, characterized in that: The common electrode layer includes a first common electrode and a second common electrode that are spaced apart from each other. The first pixel electrode layer is electrically connected to the first common electrode through the first sub-via hole. The second via hole is located between the first common electrode and the second common electrode.

6. The array substrate according to claim 4, characterized in that: The first pixel electrode located in the first via hole and the second pixel electrode located in the second via hole are both formed by using the composite material layer.

7. The array substrate according to claim 4, characterized in that: The second via hole is formed by a one-time photomask process after forming the organic insulating layer and the passivation layer.

8. The array substrate according to claim 1, characterized in that: The gate driving layer includes a gate insulating layer, a gate layer and an interlayer dielectric layer which are stacked, the gate layer includes a gate line, and at least a part of the gate line is formed by a stacked metal layer and an organic conductive polymer material layer.

9. The array substrate according to any one of claims 1 to 8, characterized in that: The organic conductive polymer is PEDOT, and the transparent metal oxide is ITO.

10. A display panel, characterized in that: include: An array substrate as claimed in any one of claims 1 to 9, an opposing substrate arranged opposite to the array substrate, and a display medium layer located between the array substrate and the opposing substrate.

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