Array substrate, display panel and display device

Abstract

The embodiment of the invention provides an array substrate, a display panel and a display device. The array substrate comprises a substrate body, and the substrate body comprises a plurality of sub-pixel areas arranged in an array; the pixel electrode is located in the sub-pixel area; the first common voltage lines extend in the first direction between the sub-pixel areas, the first common voltage lines and the pixel electrodes are arranged on the same layer, and the first direction is the row direction or the column direction; a gate line extending in a first direction between the sub-pixel regions; the grid line comprises two edge parts extending in the first direction and a middle part located between the edge parts, the orthographic projection of at least part of the area of the edge parts on the substrate is located in the orthographic projection of the first common voltage line on the substrate, and the orthographic projection of at least part of the area of the edge parts is located in the orthographic projection of the second common voltage line on the substrate. And the orthographic projection of the middle part on the substrate is not overlapped with the orthographic projection of the first common voltage line on the substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD) has the characteristics of small size, low power consumption, high image quality, no radiation and easy to carry. It has been rapidly developed in recent years and has gradually replaced the traditional cathode ray tube display (CRT) and has occupied a dominant position in the current flat panel display market. At present, TFT-LCD has been widely used in various large, medium and small sized products, covering almost all major electronic products in today's information society, such as LCD TV, high-definition digital TV, computer (desktop and notebook), mobile phone, tablet computer, navigation system, car display, projection display, video camera, digital camera, electronic watch, calculator, electronic instrument, meter, public display and virtual display, etc. Summary of the invention

[0003] The present disclosure provides an array substrate, a display panel and a display device, and the specific scheme is as follows:

[0004] In one aspect, an embodiment of the present disclosure provides an array substrate, comprising:

[0005] A base substrate, the base substrate comprising a plurality of sub-pixel regions arranged in an array;

[0006] A pixel electrode, located in the sub-pixel area;

[0007] A first common voltage line extending between the sub-pixel areas along a first direction, the first common voltage line and the pixel electrode being arranged in the same layer, the first direction being a row direction or a column direction;

[0008] A gate line extends along the first direction between the sub-pixel areas; the gate line includes two edge portions extending along the first direction, and a middle portion located between the edge portions, wherein the orthographic projection of at least a portion of the edge portions on the substrate is located within the orthographic projection of the first common voltage line on the substrate, and the orthographic projection of the middle portion on the substrate does not overlap with the orthographic projection of the first common voltage line on the substrate.

[0009] In some embodiments, in the above array substrate provided by the embodiments of the present disclosure, a transistor coupled to the pixel electrode is further included;

[0010] The orthographic projection of the edge portion on the substrate has an overlapping area with the orthographic projections of the first electrode and the second electrode of the transistor on the substrate, and at least a portion of the overlapping area does not overlap with the orthographic projection of the first common voltage line on the substrate.

[0011] In some embodiments, in the above array substrate provided by the embodiments of the present disclosure, it further includes data lines extending along a second direction between the sub-pixel areas, and the second direction intersects with the first direction;

[0012] The pixel electrode includes a first pixel electrode, the transistor includes a first transistor, a first electrode of the first transistor is coupled to the data line, and a second electrode of the first transistor is coupled to the first pixel electrode;

[0013] The orthographic projection of the edge portion on the substrate has a first overlapping region with the orthographic projection of the first electrode of the first transistor on the substrate, and the orthographic projection of the edge portion on the substrate has a second overlapping region with the orthographic projection of the second electrode of the first transistor on the substrate;

[0014] The orthographic projection of the first common voltage line on the base substrate is disconnected in the first overlapping area and does not overlap with a part of the second overlapping area.

[0015] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the pixel electrode includes a second pixel electrode, the transistor includes a second transistor, a first electrode of the second transistor is multiplexed with a first electrode of the first transistor, and a second electrode of the second transistor is coupled to the second pixel electrode;

[0016] The orthographic projection of the edge portion on the substrate and the orthographic projection of the second electrode of the second transistor on the substrate have a third overlapping area;

[0017] The orthographic projection of the first common voltage line on the base substrate is disconnected in the third overlapping area.

[0018] In some embodiments, in the above array substrate provided by the embodiments of the present disclosure, it further includes a discharge line penetrating the sub-pixel area in a second direction, and the second direction is arranged to intersect with the first direction;

[0019] The pixel electrode includes a second pixel electrode, the transistor includes a third transistor, a first electrode of the third transistor is coupled to the second pixel electrode, and a second electrode of the third transistor is coupled to the discharge line;

[0020] The orthographic projection of the edge portion on the substrate and the orthographic projection of the first electrode of the third transistor on the substrate have a fourth overlapping area, and the orthographic projection of the edge portion on the substrate and the orthographic projection of the second electrode of the third transistor on the substrate have a fifth overlapping area;

[0021] An orthographic projection of the first common voltage line on the base substrate is located between the fourth overlapping region and the sub-pixel region, and between the fifth overlapping region and the sub-pixel region.

[0022] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a connection line disposed on the same layer as the pixel electrode, and the two first common voltage lines at the same gap between the sub-pixel areas are integrally disposed with the connection line.

[0023] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the sub-pixel area includes a blue sub-pixel area, and the orthographic projection of the connecting line on the base substrate is located between the blue sub-pixel areas.

[0024] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a second common voltage line disposed in the same layer as the gate line, and the connecting line is coupled to the second common voltage line.

[0025] In some embodiments, in the above array substrate provided by the embodiments of the present disclosure, the pixel electrode includes a protrusion close to one side of the gate line;

[0026] The second common voltage line includes a first branch extending along the first direction, the orthographic projection of the first branch on the base substrate overlaps with the orthographic projection of the edge of the pixel electrode on the side where the protrusion is located on the base substrate, and the first branch is widened at the location of the protrusion.

[0027] In some embodiments, in the above array substrate provided by the embodiments of the present disclosure, the first branch portion includes a fracture;

[0028] The array substrate further includes a discharge line running through the sub-pixel area in a second direction, the second direction intersecting the first direction, and the discharge line includes a first line segment, a second line segment, and a third line segment connected in sequence;

[0029] Wherein, the orthographic projection of the second line segment on the substrate intersects with the orthographic projection of the gate line on the substrate;

[0030] The first line segment and the second line segment extend along the first direction, and the orthographic projection of the first line segment on the substrate and the orthographic projection of the third line segment on the substrate are respectively located within the orthographic projections of the breaks on both sides of the gate line on the substrate.

[0031] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the second common voltage line further includes a main body extending along the first direction, and a second branch extending in the second direction and connecting the main body and the first branch;

[0032] The orthographic projection of the main body on the base substrate overlaps with the orthographic projection of the edge of the pixel electrode in the same row in the first direction on the base substrate opposite to the protruding portion;

[0033] An orthographic projection of the second branch on the base substrate overlaps with an orthographic projection of an edge of the pixel electrode extending along the second direction on the base substrate.

[0034] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a third common voltage line extending along a second direction between the sub-pixel areas, the third common voltage line is integrally arranged with the first common voltage line, and the second direction intersects with the first direction.

[0035] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a data line extending along the second direction between the sub-pixel areas, and the orthographic projection of the data line on the base substrate is located within the orthographic projection of the third common voltage line on the base substrate.

[0036] On the other hand, an embodiment of the present disclosure provides a display panel, including an array substrate and an opposite substrate arranged opposite to each other, wherein the array substrate is the above-mentioned array substrate provided in the embodiment of the present disclosure, and the opposite substrate includes a common electrode.

[0037] On the other hand, an embodiment of the present disclosure provides a display device, including the above-mentioned display panel provided by an embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A schematic diagram showing bending of the display device;

[0039] Figure 2 is a schematic structural diagram of a first pixel electrode, a second pixel electrode and a gate line in the related art;

[0040] Figure 3 It is a light leakage principle diagram in the related art;

[0041] Figure 4 is a schematic diagram of actual light leakage in the related art;

[0042] Figure 5 A schematic diagram of the structure of an array substrate provided in an embodiment of the present disclosure;

[0043] Figure 6 for Figure 5 Schematic diagram of the enlarged structure of the middle M region;

[0044] Figure 7 for Figure 6 A schematic diagram of the overlap of the first electrode and the second electrode, the first common electrode line and the gate line of the transistor;

[0045] Figure 8 For along Figure 5 A-A' cross-sectional view;

[0046] Fig. 9 For along Figure 5 The cross-sectional view along line B-B';

[0047] Fig.10 A schematic diagram of improving light leakage in the present disclosure;

[0048] Fig.11 A practical schematic diagram of improving light leakage in the present disclosure;

[0049] Fig.12 for Figure 5 A schematic diagram of the structure of the layer where the middle grid line is located;

[0050] Fig.13 for Figure 5 Schematic diagram of the structure of the active layer;

[0051] Fig.14 for Figure 5 The structural diagram of the layer where the data line is located;

[0052] Fig.15 for Figure 5 Schematic diagram of the structure of the passivation layer and the gate insulation layer;

[0053] Fig.16 for Figure 5 A schematic diagram of the structure of the layer where the pixel electrode is located;

[0054] Fig.17 A schematic diagram of the structure of a display panel provided in an embodiment of the present disclosure;

[0055] Fig.18 A schematic diagram of another structure of a display panel provided in an embodiment of the present disclosure;

[0056] Fig.19 An equivalent circuit diagram corresponding to a bright pixel area and a dark pixel area provided in an embodiment of the present disclosure;

[0057] Fig. 20 A schematic diagram of another structure of a display panel provided in an embodiment of the present disclosure;

[0058] Fig.21 A schematic diagram of a structure of a display device provided in an embodiment of the present disclosure;

[0059] Fig. 22 A schematic diagram of another structure of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0060] In order to make the purpose, technical solution and advantages of the embodiment of the present disclosure clearer, the technical solution of the embodiment of the present disclosure will be clearly and completely described in conjunction with the drawings of the embodiment of the present disclosure. It should be noted that in the drawings, the thickness of the layer, film, panel, area, etc. is magnified for clarity. In the present disclosure, exemplary embodiments are described with reference to cross-sectional views of schematic diagrams of idealized embodiments. In this way, deviations from the shape of the figure as a result of, for example, manufacturing technology and / or tolerances will be expected. Therefore, the embodiments described in the present disclosure should not be interpreted as being limited to the specific shape of the area shown in the present disclosure, but include deviations in shape caused by, for example, manufacturing. For example, an area illustrated or described as flat may typically have rough and / or nonlinear features; the illustrated sharp corners may be rounded, etc. Therefore, the areas shown in the figures are schematic in nature, and their sizes and shapes are not intended to illustrate the exact shape of the area, do not reflect the true proportion, and the purpose is only to illustrate the content of the present disclosure. And the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of well-known functions and well-known components.

[0061] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" and the like mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower", etc. are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0062] In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, the element or layer may be directly on, directly connected to, or there may be an intermediate element or intermediate layer. When an element or layer is referred to as being "disposed on one side of" another element or layer, the element or layer may be directly on one side of, directly connected to, or there may be an intermediate element or intermediate layer. However, when an element or layer is referred to as being "directly on" or "directly connected to" another element or layer, there are no intermediate elements or intermediate layers. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0063] With the upgrading of electronic products, the display screens of various display devices (such as display TVs) are becoming larger and larger. This is because a larger display screen can provide users with rich information, improve the efficiency of human-computer communication, and bring a better user experience.

[0064] However, if Figure 1 As shown, a display device 100 with a larger size is heavier and is prone to bending during transportation. After the display device is bent, the gate line (GL) extending direction (i.e. Figure 1 The light-shielding black matrix (BM) in the X direction (shown in FIG. 1 ) will also shift and cannot shield light in the direction in which the gate lines extend. Figure 2 In the pixel design shown, the first pixel electrode P1 and the second pixel electrode P2 can cooperate with the common electrode (COM) to present two brightness levels: bright and dark. Figure 2 In the pixel design shown in FIG. 1 , the voltage of the gate line GL is usually 20V to 30V, and the voltage of the first pixel electrode P1 and the second pixel electrode P2 is 0 to 14V, resulting in a large voltage difference of 16V to 30V between the gate line GL and the first pixel electrode P1 and the second pixel electrode P2, forming an electric field, causing the liquid crystal LC to rotate and light up abnormally, such as Figure 3 As shown in FIG. 1 , after the display device is bent, the black matrix (BM) cannot shield the gate line from light in the extending direction. Therefore, obvious light leakage may occur due to the large voltage difference between the gate line GL and the first pixel electrode P1 and the second pixel electrode P2. Figure 4 shown.

[0065] In order to at least improve the above technical problems existing in the related art, the present disclosure provides an array substrate, such as Figures 5 to 9 As shown, including:

[0066] The base substrate 101 includes a plurality of sub-pixel regions (eg, a red sub-pixel region R, a green sub-pixel region G, and a blue sub-pixel region B) arranged in an array; optionally, the base substrate 101 is a substrate that allows visible light to pass through, such as glass, quartz, plastic, or the like.

[0067] The pixel electrode 102 is located in a sub-pixel region (eg, red sub-pixel region R, green sub-pixel region G, blue sub-pixel region B); the material of the pixel electrode 102 may include transparent conductive materials such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0068] The first common voltage line 103 extends along the first direction X between the sub-pixel areas (e.g., the red sub-pixel area R, the green sub-pixel area G, and the blue sub-pixel area B). The first common voltage line 103 is arranged in the same layer and the same material as the pixel electrode 102. The first direction X is the row direction or the column direction. The disclosure takes the first direction X as the row direction as an example for explanation. In the disclosure, "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for making a specific pattern, and then using the same mask template through a single patterning process. That is, a single patterning process corresponds to a mask template (mask, also called a photomask). Depending on the specific pattern, a single patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may be at the same height or have the same thickness, or at different heights or have different thicknesses.

[0069] The gate line 104 extends along the first direction X between the sub-pixel regions (e.g., the red sub-pixel region R, the green sub-pixel region G, and the blue sub-pixel region B); the gate line 104 includes two edge portions 401 extending along the first direction X, and a middle portion 402 located between the edge portions 401, wherein the orthographic projection of at least a portion of the edge portion 401 on the substrate 101 is located within the orthographic projection of the first common voltage line 103 on the substrate 101, and the orthographic projection of the middle portion 402 on the substrate 101 does not overlap with the orthographic projection of the first common voltage line 103 on the substrate 101. In some embodiments, the material of the gate line 104 may include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni), and the gate line 104 may be a single-layer structure or a stacked-layer structure, for example, the gate line 104 is a single-layer structure composed of a molybdenum metal layer.

[0070] like Fig.10As shown, the present disclosure sets a first common voltage line 103 of the same layer and the same material as the pixel electrode 102, and makes the orthographic projection of the first common voltage line 103 on the base substrate 101 overlap with the orthographic projection of the edge portion 401 of the gate line 104 on the base substrate 101, so that the first common voltage line 103 can be used to effectively shield the signal of the gate line 104, so that the pixel electrode 102 will no longer be disturbed by the gate line 104, but will form a coupling capacitor with the first common voltage line 103. The voltage of the first common voltage line 103 is about 7V (for example, 8V), and the voltage difference between the first common voltage line 103 and the pixel electrode 102 is about 0 to 7V, which is smaller than the voltage difference of 16V to 30V between the gate line 104 and the pixel electrode 102 in the related art, thereby effectively improving the phenomenon that the liquid crystal LC rotates abnormally and lights up due to the electric field formed by the large voltage difference, and by Fig.11 It can be seen from the actual light leakage schematic diagram provided by the present disclosure that there is no obvious light leakage phenomenon in the present disclosure.

[0071] In some embodiments, taking into account the alignment deviation (CD) and process fluctuations, to ensure that the first common voltage line 103 can completely cover the edge portion 401 of the gate line 104, the orthographic projection of the first common voltage line 103 on the base substrate 101 can be set to exceed 2 μm on one side relative to the orthographic projection of the edge portion 401 on the base substrate 101, and the width of the edge portion 401 is 2 μm.

[0072] In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, if Figure 6 and Figure 7 As shown, it may also include a transistor (for example, T1, T2, T3) coupled to the pixel electrode 102; the orthographic projection of the edge portion 401 of the gate line 104 on the substrate 101 and the orthographic projection of the first pole (for example, s1, s2, s3) and the second pole (for example, d1, d2, d3) of the transistor (for example, T1, T2, T3) on the substrate 101 have an overlapping area (for example, ol1, ol2, ol3, ol4, ol5), and at least a portion of the overlapping area (for example, ol1, ol2, ol3, ol4, ol5) does not overlap with the orthographic projection of the first common voltage line 103 on the substrate 101.

[0073] Optionally, the first electrode (e.g., s1, s2, s3) is a source electrode, and the second electrode (e.g., d1, d2, d3) is a drain electrode; or, the first electrode (e.g., s1, s2, s3) is a drain electrode, and the second electrode (e.g., d1, d2, d3) is a source electrode, which is not limited here. In some embodiments, the first electrode (e.g., s1, s2, s3) and the second electrode (e.g., d1, d2, d3) are both arranged in the same layer and the same material as the data line 105. The transistor (e.g., T1, T2, T3) can be a bottom-gate transistor, a top-gate transistor, or a double-gate transistor. The present disclosure takes the transistor (e.g., T1, T2, T3) as a bottom-gate transistor as an example for explanation. In addition, the transistor (e.g., T1, T2, T3) can be a P-type transistor or an N-type transistor, which is not limited here.

[0074] In the process of the array substrate, the first electrode (e.g., s1, s2, s3) and the second electrode (e.g., d1, d2, d3) of the transistor (e.g., T1, T2, T3) may be short-circuited with the gate line 104 through the conductive particles (particles) remaining in the process. In this case, the present disclosure can cut off the first electrode (e.g., s1, s2, s3) and the second electrode (e.g., d1, d2, d3) at the short-circuit position to solve the problem of the first electrode (e.g., s1, s2, s3) and the second electrode (e.g., d1, d2, d3) being short-circuited with the gate line 104; and the present disclosure can use the material of the layer where the first common voltage line 103 is located to perform cross-layer overlap at the position where the overlapping area (e.g., ol1, ol2, ol3, ol4, ol5) and the first common voltage line 103 do not overlap each other, and connect the cut first electrode (e.g., s1, s2, s3) and the second electrode (e.g., d1, d2, d3) to ensure the normal operation of the transistor (e.g., T1, T2, T3).

[0075] In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, if Figures 5 to 7As shown, it also includes a data line 105 extending along the second direction Y between sub-pixel areas (such as red sub-pixel area R, green sub-pixel area G, and blue sub-pixel area B), and the second direction Y intersects with the first direction X. The disclosure takes the second direction Y as the column direction as an example for explanation; optionally, the material of the data line 105 may include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni), and the data line 105 may be a single-layer structure or a stacked structure, for example, the data line 105 is a stacked structure composed of a titanium metal layer / aluminum metal layer / titanium metal layer. The pixel electrode 102 includes a first pixel electrode P1, and the transistor includes a first transistor T1, wherein a first electrode s1 of the first transistor T1 is coupled to the data line 105, and a second electrode s2 of the first transistor T1 is coupled to the first pixel electrode P1; the "coupling" in the disclosure may be a direct electrical connection or an indirect electrical connection, for example, an electrical connection is achieved through other circuits or components. The orthographic projection of the edge portion 401 of the gate line 104 on the substrate substrate 101 and the orthographic projection of the first electrode s1 of the first transistor T1 on the substrate substrate 101 have a first overlapping area ol1, and the orthographic projection of the edge portion 401 on the substrate substrate 101 and the orthographic projection of the second electrode d1 of the first transistor T1 on the substrate substrate 101 have a second overlapping area ol2; the orthographic projection of the first common voltage line 103 on the substrate substrate 101 is disconnected in the first overlapping area ol1 (equivalent to the first common voltage line 103 having no pattern in the first overlapping area ol1), and does not overlap with a part of the second overlapping area ol2 (equivalent to the first common voltage line 103 having no pattern in a local area of ​​the second overlapping area ol2, and the first common voltage line 103 has a pattern in the remaining area of ​​the second overlapping area ol2).

[0076] In some embodiments, if the first electrode s1 and the second electrode d1 of the first transistor T1 are short-circuited with the gate line 104 by conductive particles remaining in the manufacturing process, the present disclosure can cut off the first electrode s1 and the second electrode d1 of the first transistor T1 at the short-circuited position to solve the problem of the first electrode s1 and the second electrode d1 of the first transistor T1 being short-circuited with the gate line 104; and, the present disclosure can use the material of the layer where the first common voltage line 103 is located to perform cross-layer overlap in the first overlapping area ol1 to connect the first electrode s1 cut off in the first transistor T1, and use the material of the layer where the first common voltage line 103 is located to perform cross-layer overlap in a local area of ​​the second overlapping area ol2 to connect the second electrode d1 cut off in the first transistor T1, thereby ensuring the normal operation of the first transistor T1.

[0077] In addition, the first common voltage line 103 has a pattern in the remaining area of ​​the second overlapping area ol2, which can ensure that the first common voltage line 103 is continuously set, so as to realize the transmission of the common voltage signal on the first common voltage line 103. The first common voltage line 103 that is disconnected in the first overlapping area ol1 can be coupled with the first common voltage line 103 that has a pattern in the remaining area of ​​the second overlapping area ol2, so as to ensure that the first common voltage line 103 that is disconnected in the first overlapping area ol1 also has a common voltage signal.

[0078] Continue to see Figures 5 to 7 It can be known that in the array substrate provided by the embodiment of the present disclosure, the pixel electrode 102 may further include a second pixel electrode P2, and optionally, the first pixel electrode P1 and the second pixel electrode P2 are alternately arranged in the second direction Y, and the first pixel electrode P1 is a bright pixel area, and the second pixel electrode P2 is a dark pixel area. The transistor may further include a second transistor T2, the first electrode s2 of the second transistor T2 is reused with the first electrode s1 of the first transistor T1, and the second electrode d2 of the second transistor T2 is coupled to the second pixel electrode P2; the positive projection of the edge portion 401 of the gate line 104 on the substrate substrate 101 and the positive projection of the second electrode d2 of the second transistor T2 on the substrate substrate 101 have a third overlapping area ol3; the positive projection of the first common voltage line 103 on the substrate substrate 101 is disconnected in the third overlapping area ol3, that is, the first common voltage line 103 has no pattern in the third overlapping area ol3.

[0079] In some embodiments, if the second electrode d2 of the second transistor T2 is short-circuited with the gate line 104 by conductive particles remaining in the manufacturing process, the present disclosure can cut off the second electrode d2 of the second transistor T2 at the short-circuited position to solve the problem of the second electrode d2 of the second transistor T2 being short-circuited with the gate line 104; and, the present disclosure can use the material of the layer where the first common voltage line 103 is located to perform cross-layer overlap in the third overlapping area ol3 to connect the cut-off second electrode d2 in the second transistor T2 to ensure the normal operation of the second transistor T2.

[0080] In addition, since the first electrode s2 of the second transistor T2 is reused with the first electrode s1 of the first transistor T1, the orthographic projection of the edge portion 401 of the gate line 104 on the substrate 101 and the orthographic projection of the first electrode s1 of the first transistor T1 on the substrate 101 have a first overlapping area ol1, and the orthographic projection of the first common voltage line 103 on the substrate 101 is disconnected in the third overlapping area ol3; therefore, when the first electrode s2 of the second transistor T2 is short-circuited with the gate line 104 by the conductive particles (particles) remaining in the process, the present disclosure can cut off the first electrode s2 of the second transistor T2 at the short-circuited position to solve the problem of the short-circuit between the first electrode s2 of the second transistor T2 and the gate line 104; and, the present disclosure can use the material of the layer where the first common voltage line 103 is located to perform cross-layer overlap in the first overlapping area ol1 to connect the cut-off first electrode s2 of the second transistor T2 to ensure the normal operation of the second transistor T2.

[0081] In some embodiments, Figure 7 and Fig.13 As shown, the first part of the gate line 104 can be used as the gate g1 of the first transistor T1, the second part of the gate line 104 can be used as the gate g2 of the second transistor T2, and the gate g1 of the first transistor T1 and the gate g2 of the second transistor T2 can be integrally arranged, and the third part of the gate line 104 can be used as the gate g3 of the third transistor T3; in addition, the active layer a1 of the first transistor T1 can be integrally arranged with the active layer a2 of the second transistor T2, and the active layer a3 of the third transistor T3 is the same layer and the same material as the active layer a1 of the first transistor T1 and the active layer a2 of the second transistor T2. In some embodiments, the materials of the active layer a1 of the first transistor T1, the active layer a2 of the second transistor T2, and the active layer a3 of the third transistor T3 can be amorphous silicon a-Si, polycrystalline silicon P-Si, oxide (such as indium gallium zinc oxide), etc.

[0082] In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, if Figures 5 to 7As shown, a discharge line 106 may also be included that runs through the sub-pixel area (e.g., the red sub-pixel area R, the green sub-pixel area G, and the blue sub-pixel area B) in the second direction Y. Optionally, the discharge line 106 is provided in the same layer and the same material as the data line 105. The transistor may also include a third transistor T3, a first electrode s3 of the third transistor T3 (which may be provided integrally with the second electrode d2 of the second transistor T2) coupled to the second pixel electrode P2, and a second electrode d3 of the third transistor T3 coupled to the discharge line 106; an orthographic projection of an edge portion 401 of the gate line 104 on the substrate 101 and an orthographic projection of the first electrode s3 of the third transistor T3 on the substrate 101 have a fourth overlapping area ol4, and an orthographic projection of the edge portion 401 of the gate line 104 on the substrate 101 and a first electrode s3 of the third transistor T3 on the substrate 101 have a fourth overlapping area ol5. The orthographic projection of the diode d3 on the substrate 101 has a fifth overlapping area ol5; the orthographic projection of the first common voltage line 103 on the substrate 101 is located between the fourth overlapping area ol4 and the sub-pixel area (for example, the red sub-pixel area R, the green sub-pixel area G, and the blue sub-pixel area B), and between the fifth overlapping area ol5 and the sub-pixel area (for example, the red sub-pixel area R, the green sub-pixel area G, and the blue sub-pixel area B). Based on this, it can be known that the first common voltage line 103 has no pattern in the fourth overlapping area ol4 and the fifth overlapping area ol5.

[0083] In some embodiments, if the first electrode s3 and the second electrode d3 of the third transistor T3 are short-circuited with the gate line 104 by conductive particles remaining in the manufacturing process, the present disclosure can cut off the first electrode s3 and the second electrode d3 of the third transistor T3 at the short-circuited position to solve the problem of the first electrode s3 and the second electrode d3 of the third transistor T3 being short-circuited with the gate line 104; and, the present disclosure can use the material of the layer where the first common voltage line 103 is located to perform cross-layer overlap in the fourth overlapping area ol4 to connect the first electrode s3 cut off in the third transistor T3, and use the material of the layer where the first common voltage line 103 is located to perform cross-layer overlap in the fifth overlapping area ol5 to connect the second electrode d3 cut off in the third transistor T3 to ensure the normal operation of the third transistor T3.

[0084] In addition, the orthographic projection of the first common voltage line 103 on the base substrate 101 is located between the fourth overlapping area ol4 and the sub-pixel area (for example, the red sub-pixel area R, the green sub-pixel area G, and the blue sub-pixel area B), and between the fifth overlapping area ol5 and the sub-pixel area (for example, the red sub-pixel area R, the green sub-pixel area G, and the blue sub-pixel area B), thereby ensuring that the first common voltage line 103 is continuously set and realizing the transmission of the common voltage signal on the first common voltage line 103.

[0085] In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, if Figure 5 and Fig.16As shown, two first common voltage lines 103 respectively overlapping with two edge portions 401 of the same gate line 104 are provided at the same gap between the sub-pixel areas (e.g., the red sub-pixel area R, the green sub-pixel area G, and the blue sub-pixel area B). Optionally, the array substrate is further provided with a connecting line 107 provided in the same layer and with the same material as the pixel electrode 102, so that the two first common voltage lines 103 at the same gap between the sub-pixel areas (e.g., the red sub-pixel area R, the green sub-pixel area G, and the blue sub-pixel area B) are coupled through the connecting line 107. In some embodiments, the two first common voltage lines 103 at the same gap between the sub-pixel areas (e.g., the red sub-pixel area R, the green sub-pixel area G, and the blue sub-pixel area B) are integrally provided with the connecting line 107.

[0086] In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, if Figure 5 and Fig.16 As shown, the sub-pixel region may include a red sub-pixel region R, a green sub-pixel region G and a blue sub-pixel region B, and the orthographic projection of the connecting line 107 on the base substrate 101 is located between the blue sub-pixel regions B. Figure 5 and Fig.16 It can be seen that the connection line 107 has a design structure with a wide end and a narrow middle, and in order to avoid short circuit with the pixel electrode 102 arranged in the same layer, the pixel electrode 102 in the blue sub-pixel region B, which is in the same layer and made of the same material as the connection line 107, is provided with a corner cut at the end of the connection line 107. This has a certain impact on the aperture ratio of the blue sub-pixel region B, but considering that the pixel brightness of the blue sub-pixel region B is the lowest among the red sub-pixel region R, the green sub-pixel region G and the blue sub-pixel region B, even if part of the aperture ratio of the blue sub-pixel region B is sacrificed, it will not have a significant impact on the overall transmittance of the product.

[0087] In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, if Figure 5 , Fig.12 , Fig.15 and Fig.16 As shown, a second common voltage line 108 provided in the same layer and the same material as the gate line 104 may also be included, and the connection line 107 is coupled to the second common voltage line 108. Optionally, the connection line 107 is coupled to the second common voltage line 108 through a first via hole h1 penetrating the passivation layer 109 and the gate insulating layer 110; and to ensure the coupling effect, the second common voltage line 108 is widened at the coupling position, and the connection line 107 is coupled to the second common voltage line 108 at the wider end. Optionally, the materials of the passivation layer 109 and the gate insulating layer 110 can be at least one of inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0088] In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, if Figure 5, Figure 6 , Fig.12 , Figures 14 to 16 As shown, the pixel electrode 102 includes a protrusion 201 close to the side of the gate line 104, and the first pixel electrode P1 is coupled to the second electrode d1 of the first transistor T1 at the protrusion 201 through the second via hole h2 penetrating the passivation layer 109, and the second pixel electrode P2 is coupled to the second electrode d2 of the second transistor T2 (equivalent to the first electrode s3 of the third transistor T3) at the protrusion 201 through the third via hole h3 penetrating the passivation layer 109; the second common voltage line 108 includes a first branch 801 extending along the first direction X, the orthographic projection of the first branch 801 on the base substrate 101 overlaps with the orthographic projection of the edge of the pixel electrode 102 on the side where the protrusion 201 is located on the base substrate 101, and the first branch 801 is widened at the protrusion 201, so that the resistance of the first branch 801 is small, thereby improving the voltage drop (IR drop) of the common voltage on the first branch 801. In addition, by Fig.12 It can be seen that in order to avoid short circuit between the first branch 801 and the gate line 104 , the line width of the gate line 104 is smaller at the position where the first branch 801 is widened.

[0089] In some embodiments, Figure 5 , Figure 6 , Fig.12 and Fig.14 As shown, the first branch 801 includes a break O, and the discharge line 106 includes a first line segment 601, a second line segment 602, and a third line segment 603 that are sequentially connected, wherein the orthographic projection of the second line segment 602 on the substrate 101 and the orthographic projection of the gate line 104 on the substrate 101 intersect each other, the first line segment 601 and the second line segment 602 extend along the first direction X, and the orthographic projection of the first line segment 601 on the substrate 101 and the orthographic projection of the third line segment 603 on the substrate 101 are respectively located within the orthographic projection of the break O on both sides of the gate line 104 on the substrate 101. Since the discharge line 106 is wider at the first line segment 601 and the third line segment 603, by setting the break O at the first branch 801 where the first line segment 601 and the third line segment 603 are located, a large coupling capacitance can be avoided between the first branch 801 and the discharge line 601. In some embodiments, as Fig.14 As shown, a portion of the third line segment 603 can be used as the second electrode d3 of the third transistor T3, and the first line segment 601, the second line segment 602 and the third line segment 603 together form an escape space to avoid short circuit between the first electrode s3 and the second electrode d3 of the third transistor T3.

[0090] In some embodiments, Figure 6 , Fig.12 and Fig.14As shown, in order to reduce the coupling capacitance between the data line 105 and the gate line 104, the widths of the gate line 104 and the data line 105 are narrowed at the overlapping position of the data line 105 and the gate line 104; in addition, in order to reduce the parasitic capacitance between the gate line 104 and the discharge line 106, the line width of the gate line 104 at the overlapping position with the discharge line 106 (specifically, the second line segment 602) is also narrowed, but because the second line segment 602 itself is relatively narrow, in order to avoid the second line segment 602 from being broken, the present disclosure does not reduce the width of the second line segment 602 at the overlapping position with the gate line 104.

[0091] In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, if Figure 5 , Fig.12 and Fig.16 As shown, the second common voltage line 108 may also include a main body 802 extending along the first direction X, and a second branch 803 extending in the second direction Y and connecting the main body 802 and the first branch 801; wherein the orthographic projection of the main body 802 on the base substrate 101 overlaps with the orthographic projection of the edge of the pixel electrode 102 in the same row on the opposite side of the protrusion 201 on the base substrate 101; the orthographic projection of the second branch 803 on the base substrate 101 overlaps with the orthographic projection of the edge of the pixel electrode 102 extending along the second direction Y on the base substrate 101. In this way, the main body 802, the second branch 803, and the first branch 801 can form a storage capacitor with the pixel electrode 102. Specifically, among the two second common voltage lines 108 on both sides of the gate line 104, the main body 802, the second branch 803, and the first branch 801 of one of the second common voltage lines 108 can form a first storage capacitor Cst1 with the first pixel electrode P1, and the main body 802, the second branch 803, and the first branch 801 of the other second common voltage line 108 can form a second storage capacitor Cst2 with the second pixel electrode P2.

[0092] In some embodiments, the first body portion 802 of each second common voltage line 108 can be coupled to a ring-shaped common voltage line disposed around the display area (AA) in the non-display area, so that each second common voltage line 108 has the same common voltage signal. In addition, in order to reduce the coupling capacitance between the second common voltage line 108 and the data line 105, as Figure 5 , Fig.12 and Fig.14 As shown, the second common voltage line 108 (specifically the first main body 802) can be narrowed at the position where it overlaps with the data line 105. And because the line width of the second common voltage line 108 (specifically the first main body 802) and the discharge line 106 at the overlap position is relatively narrow, in order to avoid line breakage, the present disclosure does not reduce the line width at the overlap position.

[0093] In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, if Figure 5 , Figure 6 and Fig.16 As shown, a third common voltage line 111 extending along the second direction Y between sub-pixel areas (e.g., red sub-pixel area R, green sub-pixel area G, and blue sub-pixel area B) may also be included. The third common voltage line 111 is integrally arranged with the first common voltage line 103, so that the first common voltage line 103 and the third common voltage line 111 form a mesh structure to improve the uniformity of the common voltage signal. Optionally, the orthographic projection of the data line 105 on the substrate 101 is located within the orthographic projection of the third common voltage line 111 on the substrate 101, so as to shield the signal of the data line 103 by the third common voltage line 111, and avoid mutual interference between the adjacent and uncoupled data line 105 and the pixel electrode 102. In some embodiments, considering the alignment deviation (CD) and process fluctuations, in order to ensure that the third common voltage line 111 can completely block the data line 105, the orthographic projection of the third common voltage line 111 on the substrate 101 can be set to exceed 2μm on one side relative to the orthographic projection of the data line 105 on the substrate 101.

[0094] Based on the same inventive concept, the embodiment of the present disclosure provides a display panel, such as Figures 17 to 19 As shown, it includes an array substrate 001 and an opposing substrate 002 arranged opposite to each other, wherein the array substrate 001 is the above-mentioned array substrate 001 provided in the embodiment of the present disclosure, and the opposing substrate 002 includes a common electrode 201, and the common electrode 201 is arranged on the entire surface of the display area AA, and the common electrode 201 and the first pixel electrode P1 form a first liquid crystal capacitor Cpx1, and the common electrode 201 and the second pixel electrode P2 form a second liquid crystal capacitor Cpx2. In some embodiments, the common electrode 201 can also be arranged on the array substrate, which is not limited here. The present disclosure is described by taking the common electrode 201 being located on the opposing substrate 002 as an example.

[0095] The equivalent circuit diagram of the bright pixel area and the dark pixel area in the display panel provided by the embodiment of the present disclosure is as follows: Fig.19 As shown. Combined Figure 6 and Fig.19It can be seen that the second common voltage line 108 on one side of the gate line 104 and the first pixel electrode P1 constitute the first storage capacitor Cst1 of the bright pixel area, and the second common voltage line 108 on the other side of the gate line 104 and the second pixel electrode P2 constitute the second storage capacitor Cst2 of the dark pixel area. The second common voltage line 108 can provide a fixed voltage (for example, 8V), so that the first storage capacitor Cst1 is used to charge the first pixel electrode P1 and maintain the voltage on the first pixel electrode P1 during the period when a row of scan lines is closed, and the second storage capacitor Cst2 is used to charge the second pixel electrode P2 and maintain the voltage on the second pixel electrode P2 during the period when a row of scan lines is closed.

[0096] And, in Figure 6 and Fig.19 In the embodiment, the common electrode 201 and the first pixel electrode P1 form a first liquid crystal capacitor Cpx1 in the bright pixel area, and the common electrode 201 and the second pixel electrode P2 form a second liquid crystal capacitor Cpx2 in the dark pixel area. When the gate line 104 provides a scanning voltage, the data voltage from the data line 105 can be applied to the first pixel electrode P1 and the second pixel electrode P2 respectively through the first transistor T1 and the second transistor T2, so that the electric field between the first pixel electrode P1 and the common electrode 201 can drive the corresponding liquid crystal molecules in the bright pixel area to rotate, and the electric field between the second pixel electrode P2 and the common electrode 201 can drive the corresponding liquid crystal molecules in the dark pixel area to rotate. The corresponding liquid crystal molecules in the moving dark pixel area rotate; at the same time, the third transistor T3 is turned on, and shares the data voltage from the data line 105 with the second transistor T2, so as to discharge the second pixel electrode P2; finally, the voltage difference between the first pixel electrode P1 and the common electrode 201 is greater than the voltage difference between the second pixel electrode P2 and the common electrode 201, so that the brightness of the area where the first pixel electrode P1 is located is greater than the brightness of the area where the second pixel electrode P2 is located, thereby adopting a method of combining a less domain (for example, 4 domains) orientation with a voltage difference drive to achieve a liquid crystal display effect with more domains (for example, 8 domains).

[0097] In some embodiments, Fig.17 and Fig.18 As shown, the counter substrate 002 may further include a black matrix 202, which is a grid-like structure. Optionally, the orthographic projection of the gate line 104 on the base substrate 101 is located within the orthographic projection of the black matrix 202 on the base substrate 101, and the orthographic projection of the data line 105 on the base substrate 101 is located within the orthographic projection of the black matrix 202 on the base substrate 101. Fig.17 and Fig.18It can be seen that the opposing substrate 002 can also include a color resist 203 and a substrate 204. Optionally, the color resist 203 includes a red color resist corresponding to the red sub-pixel area R, a blue color resist corresponding to the blue sub-pixel area B, and a green color resist corresponding to the green sub-pixel area G; the substrate 204 is a substrate that allows visible light to pass through, such as glass, quartz, plastic and other materials.

[0098] In some embodiments, Fig. 20 As shown, the display panel provided by the embodiment of the present disclosure may further include a liquid crystal layer 003 between the array substrate 001 and the counter substrate 002, a first polarizer 004 on the side of the array substrate 001 away from the counter substrate 002, and a second polarizer 005 on the side of the counter substrate 002 away from the array substrate 001, and the polarization direction of the first polarizer 004 is perpendicular to the polarization direction of the second polarizer 005. Other essential components of the display panel should be understood by those skilled in the art, and will not be described in detail here, nor should they be used as limitations to the present disclosure.

[0099] Based on the same inventive concept, the present disclosure provides a display device, such as Fig.21 and Fig. 22 As shown, it includes the above-mentioned display panel PN provided by the embodiment of the present disclosure, and a backlight module BL located on the light incident side of the display panel PN. The backlight module BL can be a direct-type backlight module or an edge-type backlight module. Optionally, the edge-type backlight module may include a light bar, a reflective sheet, a light guide plate, a diffuser, a prism group, etc., which are stacked, and the light bar is located on one side of the thickness direction of the light guide plate. The direct-type backlight module may include a matrix light source, a reflective sheet, a diffuser, and a brightness enhancement film, etc., which are stacked on the light emitting side of the matrix light source, and the reflective sheet includes an opening that is arranged opposite to the position of each lamp bead in the matrix light source. The lamp beads in the light bar and the lamp beads in the matrix light source may be light-emitting diodes (LEDs), such as micro light-emitting diodes (Mini LED, Micro LED, etc.).

[0100] Submillimeter or even micron-scale micro-LEDs are self-luminous devices like organic light-emitting diodes (OLEDs). Like organic light-emitting diodes, they have a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angles. And because the light emission of inorganic light-emitting diodes is based on metal semiconductors with more stable properties and lower resistance, compared with organic light-emitting diodes that emit light based on organic matter, they have the advantages of lower power consumption, greater resistance to high and low temperatures, and longer service life. And when micro-LEDs are used as backlight sources, more precise dynamic backlight effects can be achieved. While effectively improving the brightness and contrast of the screen, it can also solve the glare caused by traditional dynamic backlighting between the bright and dark areas of the screen, optimizing the visual experience.

[0101] In some embodiments, the above-mentioned display device provided in the embodiments of the present disclosure may be: a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, and any other product or component with a display function. Optionally, the display device provided by the present disclosure includes, but is not limited to, components such as a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, and a control chip. Optionally, the control chip is a central processing unit, a digital signal processor, a system chip (SoC), and the like. For example, the control chip may also include a memory, and may also include a power module, and the like, and realize power supply and signal input and output functions through additionally provided wires, signal lines, and the like. For example, the control chip may also include a hardware circuit and a computer executable code, and the like. The hardware circuit may include a conventional very large scale integration (VLSI) circuit or gate array and existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include a field programmable gate array, a programmable array logic, a programmable logic device, and the like. In addition, those skilled in the art will appreciate that the above structure does not constitute a limitation on the above display device provided in the embodiment of the present disclosure. In other words, the above display device provided in the embodiment of the present disclosure may include more or fewer of the above components, or a combination of certain components, or different component arrangements.

[0102] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0103] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. An array substrate, wherein: include: A base substrate, the base substrate comprising a plurality of sub-pixel regions arranged in an array; A pixel electrode, located in the sub-pixel area; A first common voltage line extending between the sub-pixel areas along a first direction, the first common voltage line and the pixel electrode being arranged in the same layer, the first direction being a row direction or a column direction; A gate line extends along the first direction between the sub-pixel areas; the gate line includes two edge portions extending along the first direction, and a middle portion located between the edge portions, wherein the orthographic projection of at least a portion of the edge portions on the substrate is located within the orthographic projection of the first common voltage line on the substrate, and the orthographic projection of the middle portion on the substrate does not overlap with the orthographic projection of the first common voltage line on the substrate.

2. The array substrate according to claim 1, wherein: Also included is a transistor coupled to the pixel electrode; The orthographic projection of the edge portion on the substrate has an overlapping area with the orthographic projections of the first electrode and the second electrode of the transistor on the substrate, and at least a portion of the overlapping area does not overlap with the orthographic projection of the first common voltage line on the substrate.

3. The array substrate according to claim 2, wherein: Also included are data lines extending along a second direction between the sub-pixel areas, wherein the second direction intersects the first direction; The pixel electrode includes a first pixel electrode, the transistor includes a first transistor, a first electrode of the first transistor is coupled to the data line, and a second electrode of the first transistor is coupled to the first pixel electrode; The orthographic projection of the edge portion on the substrate has a first overlapping region with the orthographic projection of the first electrode of the first transistor on the substrate, and the orthographic projection of the edge portion on the substrate has a second overlapping region with the orthographic projection of the second electrode of the first transistor on the substrate; The orthographic projection of the first common voltage line on the base substrate is disconnected in the first overlapping area and does not overlap with a part of the second overlapping area.

4. The array substrate according to claim 3, wherein: The pixel electrode includes a second pixel electrode, the transistor includes a second transistor, a first electrode of the second transistor is multiplexed with a first electrode of the first transistor, and a second electrode of the second transistor is coupled to the second pixel electrode; The orthographic projection of the edge portion on the substrate and the orthographic projection of the second electrode of the second transistor on the substrate have a third overlapping area; The orthographic projection of the first common voltage line on the base substrate is disconnected in the third overlapping area.

5. The array substrate according to any one of claims 1 to 4, wherein: It also includes a discharge line that runs through the sub-pixel area in a second direction, wherein the second direction intersects with the first direction; The pixel electrode includes a second pixel electrode, the transistor includes a third transistor, a first electrode of the third transistor is coupled to the second pixel electrode, and a second electrode of the third transistor is coupled to the discharge line; The orthographic projection of the edge portion on the substrate and the orthographic projection of the first electrode of the third transistor on the substrate have a fourth overlapping area, and the orthographic projection of the edge portion on the substrate and the orthographic projection of the second electrode of the third transistor on the substrate have a fifth overlapping area; An orthographic projection of the first common voltage line on the base substrate is located between the fourth overlapping region and the sub-pixel region, and between the fifth overlapping region and the sub-pixel region.

6. The array substrate according to any one of claims 1 to 5, wherein: It also includes a connecting line arranged in the same layer as the pixel electrode, and the two first common voltage lines at the same gap between the sub-pixel areas are integrally arranged with the connecting line.

7. The array substrate according to claim 6, wherein: The sub-pixel region includes a blue sub-pixel region, and the orthographic projection of the connecting line on the base substrate is located between the blue sub-pixel regions.

8. The array substrate according to claim 6 or 7, wherein: It also includes a second common voltage line disposed in the same layer as the gate line, and the connecting line is coupled to the second common voltage line.

9. The array substrate according to claim 8, wherein: The pixel electrode comprises a protrusion close to one side of the gate line; The second common voltage line includes a first branch extending along the first direction, the orthographic projection of the first branch on the base substrate overlaps with the orthographic projection of the edge of the pixel electrode on the side where the protrusion is located on the base substrate, and the first branch is widened at the location of the protrusion.

10. The array substrate according to claim 9, wherein: The first branch includes a fracture; The array substrate further includes a discharge line running through the sub-pixel area in a second direction, the second direction intersecting the first direction, and the discharge line includes a first line segment, a second line segment, and a third line segment connected in sequence; Wherein, the orthographic projection of the second line segment on the substrate intersects with the orthographic projection of the gate line on the substrate; The first line segment and the second line segment extend along the first direction, and the orthographic projection of the first line segment on the substrate and the orthographic projection of the third line segment on the substrate are respectively located within the orthographic projections of the breaks on both sides of the gate line on the substrate.

11. The array substrate according to claim 9, wherein: The second common voltage line further includes a main body extending along the first direction, and a second branch extending in the second direction and connecting the main body and the first branch; The orthographic projection of the main body on the base substrate overlaps with the orthographic projection of the edge of the pixel electrode in the same row in the first direction on the base substrate opposite to the protruding portion; An orthographic projection of the second branch on the base substrate overlaps with an orthographic projection of an edge of the pixel electrode extending along the second direction on the base substrate.

12. The array substrate according to any one of claims 1 to 11, wherein: It also includes a third common voltage line extending along a second direction between the sub-pixel areas, the third common voltage line is integrally arranged with the first common voltage line, and the second direction intersects with the first direction.

13. The array substrate according to claim 12, wherein: It also includes a data line extending along the second direction between the sub-pixel areas, wherein the orthographic projection of the data line on the base substrate is located within the orthographic projection of the third common voltage line on the base substrate.

14. A display panel, wherein: The invention comprises an array substrate and an opposite substrate which are opposite to each other, wherein the array substrate is the array substrate according to any one of claims 1 to 13, and the opposite substrate comprises a common electrode.

15. A display device, wherein: Comprising the display panel as claimed in claim 14.

Images