Display substrate, display device and preparation method of display substrate

Abstract

The embodiment of the invention provides a display substrate, a display device and a preparation method of the display substrate. The display substrate is provided with a display area, and the display area comprises a pixel opening area; the display substrate comprises a substrate body and a driving circuit layer arranged on one side of the substrate body. The driving circuit layer is provided with a gate layer, a gate insulating layer and a source-drain layer in the pixel opening area; in the pixel opening area, the display substrate further comprises a first passivation layer on the side, away from the substrate, of the driving circuit layer, a first electrode layer on the side, away from the substrate, of the first passivation layer, a second passivation layer on the side, away from the substrate, of the first electrode layer, and a second electrode layer on the side, away from the substrate, of the second passivation layer. The gate layer and the source-drain layer form a first storage capacitor, the source-drain layer and the first electrode layer form a second storage capacitor, and the first electrode layer and the second electrode layer form a third storage capacitor. By applying the embodiment of the invention, the pixel size of the display substrate can be further reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display substrate, a display device, and a method for preparing the display substrate. Background Art

[0002] In recent years, electronic paper products have been widely used in electronic tags, electronic reading and other fields due to their advantages such as low energy consumption, healthy eye protection, and readability in sunlight.

[0003] Electronic paper products usually use a TFT (Thin Film Transistor) array substrate as the backplane. The TFT array substrate has a display area, which contains multiple pixels, and a storage capacitor structure is required in each pixel. In the current TFT array substrate structure, the storage capacitor structure in the pixel generally includes two parts: one is the capacitor formed between the gate metal layer and the source and drain metal layer, and the other is the capacitor formed between the source and drain metal layer and the pixel electrode layer.

[0004] In order to ensure the quality of the actual product, the capacitance of the storage capacitor structure in the pixel needs to meet certain requirements. Since the capacitance of the storage capacitor structure is positively correlated with the size of the storage capacitor structure, the minimum size of the storage capacitor structure in each pixel is limited to ensure product quality. Since the size of each pixel in the TFT array substrate is restricted by the size of the storage capacitor structure set therein, it is currently difficult to further reduce the pixel size in the TFT array substrate while ensuring product quality, and it is also difficult to develop products with higher PPI (Pixels Per Inch). Summary of the invention

[0005] The purpose of the present application is to provide a display substrate, a display device and a method for manufacturing a display substrate, so as to further reduce the pixel size of the display substrate and improve the display quality.

[0006] In a first aspect, the present application provides a display substrate, the display substrate having a display area, wherein the display area includes a pixel opening area; the display substrate comprises: a substrate and a driving circuit layer arranged on one side of the substrate;

[0007] The driving circuit layer comprises, in the pixel opening region: a gate layer, a gate insulating layer arranged on a side of the gate layer away from the substrate, and a source-drain electrode layer arranged on a side of the gate insulating layer away from the substrate;

[0008] In the pixel opening region, the display substrate further comprises: a first passivation layer disposed on a side of the driving circuit layer away from the substrate, a first electrode layer disposed on a side of the first passivation layer away from the substrate, a second passivation layer disposed on a side of the first electrode layer away from the substrate, and a second electrode layer disposed on a side of the second passivation layer away from the substrate;

[0009] The gate layer and the source-drain layer form a first storage capacitor, the source-drain layer and the first electrode layer form a second storage capacitor, and the first electrode layer and the second electrode layer form a third storage capacitor.

[0010] In a second aspect, the present application provides a method for preparing a display substrate, wherein the display substrate has a display area, and the display area includes a pixel opening area; the method comprises:

[0011] A driving circuit layer is formed on the substrate; the driving circuit layer comprises, in the pixel opening region, a gate layer, a gate insulating layer arranged on a side of the gate layer away from the substrate, and a source-drain layer arranged on a side of the gate insulating layer away from the substrate;

[0012] forming a first passivation layer on a side of the driving circuit layer away from the substrate;

[0013] forming a first electrode layer on a side of the first passivation layer away from the substrate;

[0014] forming a second passivation layer on a side of the first electrode layer away from the substrate;

[0015] forming a second electrode layer on a side of the second passivation layer away from the substrate;

[0016] In the pixel opening region, the gate layer and the source-drain layer form a first storage capacitor, the source-drain layer and the first electrode layer form a second storage capacitor, and the first electrode layer and the second electrode layer form a third storage capacitor.

[0017] In a third aspect, the present application provides a display device, comprising the display substrate of any one of the aforementioned first aspects.

[0018] Beneficial effects of this application:

[0019] The display substrate, display device and method for preparing the display substrate provided by the present application, the driving circuit layer of the display substrate has a gate layer in the pixel opening area, a gate insulating layer arranged on the side of the gate layer away from the substrate, and a source-drain layer arranged on the side of the gate insulating layer away from the substrate. In the pixel opening area, the display substrate also includes: a first passivation layer arranged on the side of the driving circuit layer away from the substrate, a first electrode layer arranged on the side of the first passivation layer away from the substrate, a second passivation layer arranged on the side of the first electrode layer away from the substrate, and a second electrode layer arranged on the side of the second passivation layer away from the substrate. The gate layer and the source-drain layer form a first storage capacitor, the source-drain layer and the first electrode layer form a second storage capacitor, and the first electrode layer and the second electrode layer form a third storage capacitor.

[0020] It can be seen that compared with the double-layer storage capacitor structure in conventional display substrate products, in the display substrate provided by the present application, the number of capacitors contained in the storage capacitor structure in the thickness direction has been increased, so that the capacitance of the storage capacitor structure per unit area has been improved. Therefore, in practical applications, under the premise of ensuring that the capacitance of the storage capacitor structure does not decrease, the area occupied by the storage capacitor structure in the pixel can be further reduced, thereby further reducing the pixel size, which is helpful to improve the display quality of the display substrate and also helps to achieve products with higher PPI.

[0021] Of course, implementing any product or method of the present application does not necessarily require achieving all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0023] Figure 1 A preparation flow chart of a TFT array substrate in the related art;

[0024] Figure 2 Based on Figure 1 A top view of the structure of a TFT array substrate obtained by the process in a pixel of the display area;

[0025] Figure 3 for Figure 2 A cross-sectional structural diagram of the middle array substrate along AB;

[0026] Figure 4 Based on Figure 1 A cross-sectional structural diagram of a TFT array substrate obtained by the process in a binding area;

[0027] Figure 5 for Figure 4 A schematic diagram of the preparation process of the array substrate;

[0028] Figure 6 A cross-sectional structural diagram of a display substrate in a display area provided in an embodiment of the present application;

[0029] Figure 7 A cross-sectional structural diagram of a display substrate in a binding according to an embodiment of the present application;

[0030] Figure 8 Another cross-sectional structural diagram of the display substrate in the display area provided by the embodiment of the present application;

[0031] Fig. 9 Another cross-sectional structural diagram of a display substrate in a binding according to an embodiment of the present application;

[0032] Figure 10 to Figure 51 A schematic diagram of the preparation process of a display substrate provided in an embodiment of the present application.

[0033] Reference numerals:

[0034] Substrate-01, gate layer-02, gate insulating layer-03, active layer-04, source-drain electrode layer-05, first passivation layer-06, organic film layer-07, second passivation layer-08, light-shielding metal layer-09, pixel electrode layer-10, protective electrode layer-11; first gate electrode-021, first binding electrode-022; first via-031, third via-032, first insulating layer via-033; first source-drain electrode-051, second source-drain electrode-052, third source-drain electrode-053, first sub-electrode-053a, second sub-electrode-053b, fourth source-drain electrode-054, second binding electrode-055; first passivation structure-061, second passivation structure-062; second via-081, fourth via- 082, first passivation layer via-083, second passivation layer via-084, third passivation layer via-085, fourth passivation layer via-086, fifth passivation layer via-087, sixth passivation layer via-088, seventh passivation layer via-089, eighth passivation layer via-080; first shading structure-091, second shading structure-092, third shading structure-093, fourth shading structure-094; first pixel electrode-101, third sub-electrode-101a, fourth sub-electrode-101b, second pixel electrode-102, third pixel electrode-103, fourth pixel electrode-104, first connection electrode-105, second connection electrode-106; first protective electrode-111, second protective electrode-112. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field based on the present application belong to the scope of protection of the present application.

[0036] Compared with the existing TFT array substrate structure, the display substrate provided by one or more embodiments of the present application can increase the number of capacitors contained in the storage capacitor structure in the pixel, so as to improve the capacitance that can be achieved per unit area of ​​the storage capacitor structure, thereby helping to further reduce the pixel size of the product. Figure 1-Figure 3 The basic structure of a TFT array substrate in the related art is described. Figure 1 is a preparation flow chart of the TFT array substrate, Figure 2 is a top view of a pixel in the array substrate. Figure 3 for Figure 1 Cross-sectional structural diagram of the middle structure along AB.

[0037] Combination Figure 1-Figure 3 It can be seen that according to the existing TFT array substrate preparation process, the gate layer 02, the gate insulating layer 03, the active layer 04, the source and drain electrode layer 05, the first passivation layer 06, the organic film layer 07, the second passivation layer 08, the light shielding metal layer 09 and the pixel electrode layer 10 are prepared in sequence on the substrate 01. Among them, in the preparation process of the gate layer 02, the active layer 04, the source and drain electrode layer 05, the organic film layer 07, the second passivation layer 08, and the light shielding metal layer 09, in addition to the coating process, it also includes a mask process and an etching process, and the mask process and the etching process are used to form the pattern of the current film layer. The preparation process of the gate insulating layer 03 only includes a coating process, and after the preparation of the active layer 04 is completed, the first via hole 031 on the gate insulating layer 03 is prepared by a single-step process of perforating the insulating layer, so that the source and drain electrode layer 05 is connected to the bottom gate layer 02 through the first via hole 031. In addition, in the preparation process of the organic film layer 07, a large hole needs to be dug in the organic film layer 07 in each pixel to form a pixel opening area I (i.e. Figure 2), and after the preparation of the organic film layer 07 is completed, the first passivation layer 06 in the pixel opening area is etched away through the organic film etching process, so as to subsequently establish an electrical connection between the pixel electrode layer 10 and the source and drain electrode layer 05. Specifically, in order to establish an electrical connection between the pixel electrode layer 10 and the source and drain electrode layer 05, a second via 081 is formed on the second passivation layer 08 during the preparation process of the second passivation layer 08, so that the light-shielding metal layer 09 and the pixel electrode layer 10 are connected to the source and drain electrode layer 05 through the second via 081. Since the source and drain electrode layer 05 is connected to the gate layer 02 through the first via 031, the pixel electrode layer 10 also achieves an electrical connection with the gate layer 02. Thus, Figure 3 In the illustrated structure, a double-layer storage capacitor structure within the pixel is formed between the gate layer 02 , the source-drain layer 05 and the pixel electrode layer 10 .

[0038] In order to increase the achievable capacitance of the storage capacitor structure, this application is directed to Figure 3 The structure shown in the figure is improved to provide a display substrate. The display substrate has a display area, and the display area includes a pixel opening area; the display substrate includes: a substrate and a driving circuit layer arranged on one side of the substrate.

[0039] Specifically, the display area is the area in the display substrate used for displaying images, and the display area includes a pixel array composed of pixels. The pixel opening area can be understood as the organic film layer hole area in the pixel, which can be used to set the storage capacitor structure. Figure 3 The driving circuit layer refers to the TFT layer, which generally includes a gate layer, a gate insulating layer, an active layer, and a source-drain electrode layer, and the driving circuit layer is specifically formed in the pixel opening area with: a gate layer, a source-drain electrode layer arranged on the side of the gate layer away from the substrate, and a source-drain electrode layer arranged on the side of the gate insulating layer away from the substrate, and can also refer to Figure 3 's hint.

[0040] And within the pixel opening area, the display substrate provided by the present application also includes: a first passivation layer arranged on a side of the driving circuit layer away from the substrate, a first electrode layer arranged on a side of the first passivation layer away from the substrate, a second passivation layer arranged on a side of the first electrode layer away from the substrate, and a second electrode layer arranged on a side of the second passivation layer away from the substrate.

[0041] The gate layer and the source-drain layer form a first storage capacitor, the source-drain layer and the first electrode layer form a second storage capacitor, and the first electrode layer and the second electrode layer form a third storage capacitor.

[0042] It can be seen that in the above display substrate provided in the present application, the storage capacitor structure in the pixel includes three parts: the first storage capacitor, the second storage capacitor and the third storage capacitor. Figure 3Compared with the double-layer storage capacitor structure in the structure, the number of capacitors contained in the storage capacitor structure in the thickness direction is increased, so that the capacitance of the storage capacitor structure per unit area is improved. Therefore, in practical applications, under the premise of ensuring that the capacitance of the storage capacitor structure does not decrease, the area occupied by the storage capacitor structure in the pixel can be further reduced, thereby further reducing the pixel size, which helps to improve the display quality of the display substrate and also helps to achieve products with higher PPI.

[0043] Apart from Figure 2-Figure 3 In addition to the display area shown in FIG. 1 , the current TFT array substrate generally has a binding area, which is used to connect the TFT array substrate to an external driver integrated circuit, and the binding area is generally arranged on one or more sides of the periphery of the display area. Figure 1 ,as well as Figure 4-Figure 5 The structure of the binding area is described. Figure 1 Preparation process, the cross-sectional structure of the prepared TFT array substrate in the binding area Figure 1 Prajna Figure 4 shown.

[0044] See also Figure 4 , the binding area includes a binding electrode area III and an adjacent area around the binding electrode area. The driving circuit layer has in the binding area: a binding electrode structure located in the binding electrode area, the binding electrode structure includes a first binding electrode 022 of the gate layer 02 in the binding electrode area, and a second binding electrode 055 of the source-drain layer 05 in the binding electrode area, and the first binding electrode 022 is connected to the second binding electrode 055 through a third via 032 on the gate insulating layer 03. In a common structure, the organic film layer 07 also includes a pattern arranged in the binding area, which is used as an isolation pad structure to prevent the crack from spreading between the display area and the binding area. In addition, the light-shielding metal layer 09 and the pixel electrode layer 10 also have an electrode pattern arranged in the binding electrode area, and the electrode pattern is connected to the second binding electrode 055 through a fourth via 082 on the second passivation layer 08, which is used to bind the TFT array substrate to an external driving integrated circuit.

[0045] Combination Figure 5 For further explanation, follow Figure 1 The process, such as Figure 5 As shown in (a) of FIG. 1 , after the preparation of the driving circuit layer is completed, a first passivation layer 06 is formed on the side of the driving circuit layer away from the substrate 01 . Figure 5 As shown in (b) of FIG. 1 , the first passivation layer 06 covering the gate insulating layer 03 will be etched away during the organic film etching process. Figure 3The structure is easy to understand. Since the storage capacitor structure occupies a large area, a large hole needs to be dug in the organic film layer 07 to accommodate the storage capacitor structure. Therefore, the area of ​​the first passivation layer 06 that needs to be etched in the hole-digging area of ​​the organic film layer 07 is also large, and the etching time and cost increase, resulting in a large amount of etching byproducts attached to the surface of the gate insulating layer 03. After the preparation of the second passivation layer 08 is completed, Figure 5 As shown in (c), due to the presence of etching byproducts, the adhesion between the gate insulating layer 03 and the second passivation layer 08 will deteriorate. Therefore, in the subsequent bonding process, under the influence of high temperature and pressure, the second passivation layer 08 in the bonding area is prone to bulging and peeling, resulting in a loss of product yield and poor reliability.

[0046] In order to avoid the above-mentioned bulging and falling off of the film layer in the binding area, and improve the yield and reliability of the product. In the display substrate provided in the present application, the first passivation layer is also arranged in the binding area, and is at least located on the side of the driving circuit layer away from the substrate in the adjacent area; the second passivation layer is also arranged in the binding area, and is located on the side of the first passivation layer away from the substrate.

[0047] It can be seen that in the above-mentioned display substrate provided in the present application, the gate insulation layer in the adjacent area will be protected by the first passivation layer and the second passivation layer at the same time, thereby effectively preventing the second passivation layer from bulging and falling off during the binding process, and improving the product yield and reliability performance.

[0048] Figure 6 FIG. 1 shows a cross-sectional structural diagram of a display substrate provided in an embodiment of the present application in a display area. Figure 3 The structure in Figure 6 In the schematic diagram, the first passivation layer 06 in the pixel opening region is retained, and a protective electrode layer 11 is additionally provided on the side of the first passivation layer 06 in the pixel opening region away from the substrate 01, and the protective electrode layer 11 is used as the first electrode layer. The light shielding metal layer 09 and the pixel electrode layer 10 provided on the side of the light shielding metal layer 09 away from the substrate 01 are used as the second electrode layer.

[0049] exist Figure 6 In the illustrated display substrate, the first passivation layer 06 includes a first passivation structure 061 located in the pixel opening region, and the protective electrode layer 11 includes a first protective electrode 111 disposed on a side of the first passivation structure 061 away from the substrate 01 .

[0050] exist Figure 6In the schematic diagram, the display substrate also includes an organic film layer 07, which is located in the TFT switching area II and is arranged on the side of the driving circuit layer away from the substrate 01; the second passivation layer 08 and the second electrode layer are also arranged in the TFT switching area, and are located on the side of the organic film layer 07 away from the substrate 01.

[0051] exist Figure 6 In the actual preparation process of the substrate shown in Figure 1 On the basis of the above process, after the preparation of the first passivation layer 06 and before the preparation of the second passivation layer 08, a protective electrode layer 11 is first prepared on the side of the first passivation layer 06 away from the substrate 01, and the protective electrode layer 11 is patterned to form a first protective electrode 111. The first protective electrode 111 can act as an anti-etching layer, and can provide protection for the underlying first passivation layer 06 in the organic film etching process for the first passivation layer 06, so that the first passivation structure 061 is retained in the finished product. In one example, ITO (IndiumTinOxide) can be selected as the material for preparing the protective electrode layer 11.

[0052] Thus in Figure 6 In the pixel opening region I of the provided display substrate, the gate layer 02 and the source-drain layer 05 are isolated from each other by the gate insulating layer 03, forming a first storage capacitor C1; the source-drain layer 05 and the first protective electrode 111 are isolated from each other by the first passivation layer 06, forming a second storage capacitor C2; the first protective electrode 111 and the pixel electrode layer 10 are isolated from each other by the second passivation layer 08, forming a third storage capacitor C3. The above three storage capacitors are connected in parallel, so that the capacitance of the storage capacitor structure is C1+C2+C3.

[0053] In addition, as explained above, Figure 6 The provided display substrate can reduce the size of the storage capacitor structure within the pixel. On this basis, the area of ​​the hole on the organic film layer 07 will also be reduced, so that the area of ​​the first passivation layer 06 that needs to be etched in the organic film etching process will also be reduced. The overall time consumption of the organic film etching process will be reduced, and the etching by-products will also be reduced. Therefore, the problem of poor adhesion between the gate insulation layer 03 and the second passivation layer 08 mentioned in the previous article can be improved to a certain extent.

[0054] Combine the following Figure 6 , the overlapping method between the gate layer 02, the source and drain layer 05, the protective electrode layer 11, the light shielding metal layer 09 and the pixel electrode layer 10 is described in detail:

[0055] The gate insulating layer 03 is provided with a first insulating layer via hole 033 located in the pixel opening area;

[0056] The source-drain layer 05 includes a first source-drain electrode 051 and a second source-drain electrode 052 arranged in the pixel opening area. The first source-drain electrode 051 drives the switch structure of the circuit layer in the TFT switch area. The projection of the second source-drain electrode 052 on the substrate 01 covers the projection of the first insulating layer via 033 on the substrate 01, and is connected to the gate layer 02 through the first insulating layer via 033.

[0057] The first passivation structure 061 and the first protection electrode 111 are arranged on a side of the first source-drain electrode 051 away from the substrate 01;

[0058] The second passivation layer 08 is provided with a first passivation layer via hole 083, a second passivation layer via hole 084 and a third passivation layer via hole 085 located in the pixel opening area: the projection of the first passivation layer via hole 083 on the substrate 01 is located within the projection range of the first protection electrode 111 on the substrate 01; the projection of the second passivation layer via hole 084 on the substrate 01 is located within the projection range of the first source-drain electrode 051 on the substrate 01, and is located outside the projection range of the first protection electrode 111 on the substrate 01; the projection of the third passivation layer via hole 085 on the substrate 01 is located within the projection range of the second source-drain electrode 052 on the substrate 01;

[0059] The light-shielding metal layer 09 includes a first light-shielding structure 091 located in the TFT switch area and the pixel opening area, and a second light-shielding structure 092 located in the pixel opening area; the projection of the first light-shielding structure 091 on the substrate 01 at least partially overlaps with the projection of the first protection electrode 111 on the substrate 01, and the projection of the first light-shielding structure 091 on the substrate 01 covers the projection of the second passivation layer via 084 on the substrate 01; the projection of the second light-shielding structure 092 on the substrate 01 covers the projection of the first passivation layer via 083 and the third passivation layer via 085 on the substrate 01;

[0060] The first shading structure 091 is connected to the first source-drain electrode 051 through the second passivation layer via 084; the second shading structure 092 is connected to the first protection electrode 111 through the first passivation layer via 083, and is connected to the gate layer 02 through the third passivation layer via 085 and the second source-drain electrode 052, so that the first protection electrode 111 is connected to the gate layer 02.

[0061] The pattern of the pixel electrode layer 10 is similar to that of the shading metal layer 09 , including a third pixel electrode 103 and a fourth pixel electrode 104 . The third pixel electrode 103 is located on a side of the first shading structure 091 away from the substrate 01 , and the fourth pixel electrode 104 is located on a side of the second shading structure 092 away from the substrate 01 .

[0062] In actual use of the display substrate, the first gate electrode 021 in the gate layer 02 and the first source-drain electrode 051 can both receive external power supply, thereby Figure 6 The overlapping manner enables the first protection electrode 111 and the third pixel electrode 103 to receive power smoothly.

[0063] It can be seen that in Figure 6 In the schematic structure, the first gate electrode 021, the first source-drain electrode 051, the first protection electrode 111 and the third pixel electrode 103 together form a three-layer storage capacitor structure. Figure 3 Compared with the structure shown in FIG. 1 , the capacitance that can be achieved per unit area of ​​the storage capacitor structure is improved.

[0064] Continue to use Figure 6 The idea of ​​using the protective electrode layer 11 as an anti-etching layer to protect the first passivation layer 06 from being etched can also achieve improvements on the binding area in the display substrate. Figure 7 This is explained.

[0065] See also Figure 7 The first passivation layer 06 includes: a second passivation structure 062 located in an adjacent region and arranged on a side of the driving circuit layer away from the substrate 01;

[0066] The protection electrode layer 11 further includes: a second protection electrode 112 disposed on a side of the second passivation structure 062 away from the substrate 01;

[0067] The second passivation layer 08 is disposed on a side of the second protection electrode 112 and the binding electrode structure away from the substrate 01 , and a seventh passivation layer via 089 is disposed on the second passivation layer 08 and located on a side of the binding electrode structure away from the substrate 01 ;

[0068] The light shielding metal layer 09 further includes a third light shielding structure 093 disposed in the binding region, the projection of the third light shielding structure 093 on the substrate 01 covers the projection of the seventh passivation layer via 089 on the substrate 01, and is connected to the binding electrode structure through the seventh passivation layer via 089;

[0069] The pixel electrode layer 10 further includes a first connection electrode 105 disposed on a side of the third light shielding structure 093 away from the substrate 01 .

[0070] In the actual preparation process of the display substrate, Figure 1On the basis of the above process, after the preparation of the first passivation layer 06 and before the preparation of the second passivation layer 08, a protective electrode layer 11 is first prepared on the side of the first passivation layer 06 away from the substrate 01, and the protective electrode layer 11 is patterned to form a second protective electrode 112. The second protective electrode 112 can act as an anti-etching layer, and can provide protection for the underlying first passivation layer 06 in the organic film etching process for the first passivation layer 06, so that the second passivation structure 062 is retained in the finished product.

[0071] for Figure 7 For the structure shown in FIG. 1 , in the organic film etching process for the second passivation layer 08, due to the protection of the second protection electrode 112, the gate insulating layer 03 will not be Figure 5 In addition, the adjacent areas in the display substrate binding area are protected by the first protective electrode 111, the first passivation layer 06 and the second passivation layer 08, thereby effectively preventing the second passivation layer 08 from bulging and falling off during the binding process, thereby improving the yield and reliability of the product.

[0072] Figure 8 Another cross-sectional structural diagram of the display substrate provided in the embodiment of the present application in the display area is shown. Figure 3 The structure in Figure 8 In the illustration, the first passivation layer 06 in the pixel opening area is not etched away, and the film positions of the second passivation layer 08 and the light-shielding metal layer 09 are swapped, the light-shielding metal layer 09 is used as the first electrode layer, and the pixel electrode layer 10 is used as the second electrode layer.

[0073] exist Figure 8 In the schematic diagram, the first passivation layer 06 is also arranged in the TFT switch area II, and is located on the side of the driving circuit layer away from the substrate 01. The display substrate also includes an organic film layer 07, which is located in the TFT switch area and is arranged on the side of the first passivation layer 06 away from the substrate 01; the light shielding metal layer 09, the second passivation layer 08 and the pixel electrode layer 10 are also arranged in the TFT switch area, and are located on the side of the organic film layer 07 away from the substrate 01.

[0074] exist Figure 8 In the actual preparation process of the substrate shown in Figure 1 On the basis of the above process, the organic film etching process is not performed, and the preparation order of the light-shielding metal layer 09 and the pixel electrode layer 10 is exchanged.

[0075] exist Figure 8In the pixel opening area I of the provided display substrate, the gate layer 02 and the source-drain electrode layer 05 are isolated from each other by the gate insulating layer 03, forming a first storage capacitor C1; the source-drain electrode layer 05 and the light-shielding metal layer 09 are isolated from each other by the first passivation layer 06, forming a second storage capacitor C2; the light-shielding metal layer 09 and the pixel electrode layer 10 are isolated from each other by the second passivation layer 08, forming a third storage capacitor C3. The above three storage capacitors are connected in parallel, so that the capacitance of the storage capacitor structure is C1+C2+C3.

[0076] It can be seen that Figure 8 As for the structure shown in FIG, it is only necessary to skip the organic film etching process on the basis of the conventional TFT array substrate structure and exchange the film layer positions of the light-shielding metal layer 09 and the pixel electrode layer 10, so that the source-drain electrode layer 05 and the light-shielding metal layer 09 are separated by the first passivation layer 06 to form a second storage capacitor, and the light-shielding metal layer 09 and the pixel electrode layer 10 are separated by the second passivation layer 08 to form a third storage capacitor. The number of storage capacitors included in the storage capacitor structure in the pixel can be increased without adding an additional film layer structure, and the implementation cost of the solution is lower and easy to implement.

[0077] In addition, based on Figure 8 It can be seen that the third storage capacitor formed by the light-shielding metal layer 09 and the pixel electrode layer 10 exists not only in the pixel opening area I, but also in the TFT switch area II and the step area IV at the junction of the pixel opening area and the TFT switch area. The third storage capacitor is expanded from a planar structure in the pixel opening area to a three-dimensional structure, which can greatly increase the size of the third storage capacitor, thereby increasing the capacitance of the storage capacitor structure in the pixel, which helps to further reduce the pixel size.

[0078] Combine the following Figure 8 , the overlapping method between the gate layer 02, the source and drain layer 05, the light shielding metal layer 09 and the pixel electrode layer 10 is described in detail:

[0079] The gate insulating layer 03 is provided with a first insulating layer via hole 033 located in the pixel opening area;

[0080] The source-drain layer 05 includes: a third source-drain electrode 053 and a fourth source-drain electrode 054 arranged in the pixel opening area; the third source-drain electrode 053 is led out from the switch structure of the driving circuit layer in the TFT switch area; the projection of the fourth source-drain electrode 054 on the substrate 01 covers the projection of the first insulating layer via 033 on the substrate 01, and is connected to the gate layer 02 through the first insulating layer via 033.

[0081] exist Figure 8In the illustration, the third source-drain electrode 053 includes two parts, a first sub-electrode 053a and a second sub-electrode 053b, and the first sub-electrode 053a and the second sub-electrode 053b are electrically connected.

[0082] The projection of the light shielding metal layer 09 in the pixel opening region on the substrate 01 is located within the projection range of the third source-drain electrode 053 on the substrate 01;

[0083] The second passivation layer 08 is provided with a fourth passivation layer via hole 086, a fifth passivation layer via hole 087 and a sixth passivation layer via hole 088 located in the pixel opening area; the projection of the fourth passivation layer via hole 086 on the substrate 01 is located within the projection range of the light shielding metal layer 09 on the substrate 01; the projection of the fifth passivation layer via hole 087 on the substrate 01 is located within the projection range of the third source-drain electrode 053 on the substrate 01, and is located outside the projection range of the light shielding metal layer 09 on the substrate 01, and the fifth passivation layer via hole 087 also penetrates the first passivation layer 06; the projection of the sixth passivation layer via hole 088 on the substrate 01 is located within the projection range of the fourth source-drain electrode 054 on the substrate 01, and the sixth passivation layer via hole 088 also penetrates the first passivation layer 06;

[0084] The pixel electrode layer 10 includes a first pixel electrode 101 located in the TFT switch area and the pixel opening area, and a second pixel electrode 102 located in the pixel opening area; the projection of the first pixel electrode 101 on the substrate 01 at least partially overlaps with the projection of the shading metal layer 09 on the substrate 01, and the projection of the first pixel electrode 101 on the substrate 01 covers the projection of the fifth passivation layer via 087 on the substrate 01, and the projection of the second pixel electrode 102 on the substrate 01 covers the projection of the fourth passivation layer via 086 and the sixth passivation layer via 088 on the substrate 01.

[0085] exist Figure 8 In the illustration, the first pixel electrode 101 includes two parts, a third sub-electrode 101a and a fourth sub-electrode 101b, and the third sub-electrode 101a and the fourth sub-electrode 101b are electrically connected.

[0086] The first pixel electrode 101 is connected to the third source-drain electrode 053 through the fifth passivation layer via 087; the second pixel electrode 102 is connected to the shading metal layer 09 through the fourth passivation layer via 086, and is connected to the gate layer 02 through the sixth passivation layer via 088 and the fourth source-drain electrode 054, so that the shading metal layer 09 is connected to the gate layer 02.

[0087] In actual use of the display substrate, the first gate electrode 021 in the gate layer 02 and the third source-drain electrode 053 can both receive external power supply, thereby Figure 8 The overlapping manner enables the light-shielding metal layer 09 and the first pixel electrode 101 to receive power smoothly.

[0088] It can be seen that in Figure 8 In the schematic structure, the first gate electrode 021, the first sub-electrode 053a of the third source-drain electrode 053, the light-shielding metal layer 09 and the third sub-electrode 101a of the third pixel electrode 103 together form a three-layer storage capacitor structure. Figure 3 Compared with the structure shown in FIG. 1 , the capacitance that can be achieved per unit area of ​​the storage capacitor structure is improved.

[0089] Continue to use Figure 8 The idea of ​​not etching the first passivation layer 06 and exchanging the positions of the light shielding metal layer 09 and the pixel electrode layer 10 can also achieve improvements on the binding area in the display substrate. Fig. 9 This is explained.

[0090] See also Fig. 9 , the first passivation layer 06 is disposed on the entire surface of the side of the driving circuit layer away from the substrate 01;

[0091] An eighth passivation layer via hole 080 is provided on the second passivation layer 08 and is located on a side of the binding electrode structure away from the substrate 01 . The eighth passivation layer via hole 080 also penetrates the first passivation layer 06 .

[0092] The pixel electrode layer 10 further includes a second connection electrode 106 disposed in the binding region. The projection of the second connection electrode 106 on the substrate 01 covers the projection of the eighth passivation layer via 080 on the substrate 01 , and is connected to the binding electrode structure through the eighth passivation layer via 080 .

[0093] Fig. 9 Schematic structure and Figure 4 In comparison, since the first passivation layer 06 is not etched, but the second connection electrode 106 and the binding electrode structure are interconnected by drilling holes in the first passivation layer 06, the problem of poor adhesion between the film layers mentioned above will not occur. In addition, the adjacent areas in the display substrate binding area are protected by the first passivation layer 06 and the second passivation layer 08, thereby effectively preventing the second passivation layer 08 from bulging and falling off during the binding process, which can improve the product yield and reliability performance.

[0094] Based on the same inventive concept, the present application also provides a method for preparing a display substrate, wherein the display substrate to be prepared has a display area, and the display area includes a pixel opening area. The preparation method comprises:

[0095] Step 1: forming a driving circuit layer on a substrate; the driving circuit layer comprises in a pixel opening region: a gate layer, a gate insulating layer arranged on a side of the gate layer away from the substrate, and a source-drain layer arranged on a side of the gate insulating layer away from the substrate.

[0096] Step 2: forming a first passivation layer on a side of the driving circuit layer away from the substrate.

[0097] Step 3: forming a first electrode layer on a side of the first passivation layer away from the substrate.

[0098] Step 4: forming a second passivation layer on a side of the first electrode layer away from the substrate.

[0099] Step 5: forming a second electrode layer on a side of the second passivation layer away from the substrate.

[0100] In the pixel opening area of ​​the display substrate obtained based on the above steps 1 to 5, the gate layer and the source-drain layer form a first storage capacitor, the source-drain layer and the first electrode layer form a second storage capacitor, and the first electrode layer and the second electrode layer form a third storage capacitor. The capacitance of the storage capacitor structure in the display substrate has been improved. Therefore, in practical applications, under the premise of ensuring that the capacitance of the storage capacitor structure does not decrease, the area occupied by the storage capacitor structure in the pixel can be further reduced, thereby further reducing the pixel size, which helps to improve the display quality of the display substrate and also helps to achieve products with higher PPI.

[0101] Similar to the display substrate embodiment described above, the present application is directed to Figure 1 The basic process in is improved, and two different implementation schemes are provided to implement the process of steps 1 to 5 above, and detailed steps under the two implementation schemes are provided respectively. The first implementation scheme is: after completing the preparation of the first passivation layer and before preparing the second passivation layer, a protective electrode layer is first prepared on the side of the first passivation layer away from the substrate, and the protective electrode layer is patterned to use the pattern of the protective electrode layer as an anti-etching layer to protect the first passivation layer from being etched. The second implementation scheme is: the first passivation layer is not etched, and the preparation order of the light-shielding metal layer and the pixel electrode layer is swapped. The detailed steps of steps 1 to 5 are described below for the above two implementation schemes respectively:

[0102] See also Figure 10-Figure 19 , step 1 includes the following refinement steps:

[0103] Step 11: Select a substrate 01 and prepare a patterned gate layer 02 through processes such as coating, photolithography, and etching.

[0104] After completing step 11, the structures of the display substrate in the display area and the binding area are as follows: Fig.10 , Fig.11 As shown, it can be seen that the pattern of the gate layer 02 includes not only the gate electrode in the display area, but also the first binding electrode 022 in the binding area.

[0105] Step 12: Deposit a gate insulating layer 03.

[0106] In practical applications, the gate insulating layer 03 is generally deposited by PECVD (plasma enhanced chemical vapor deposition) and the like, and the deposited material is generally SiNx and the like.

[0107] After completing step 12, the structures of the display substrate in the display area and the binding area are as follows: Fig.12 , Fig.13 shown.

[0108] Step 13: Prepare the active layer 04 through film formation, exposure, etching and other processes.

[0109] The active layer 04 pattern only exists in the display area. After completing step 13, the structure of the display substrate in the display area is as follows: Fig.14 shown.

[0110] Step 14: Prepare via holes on the gate insulating layer 03 through exposure, etching and other processes.

[0111] After completing step 14, the structures of the display substrate in the display area and the binding area are as follows: Fig.15 , Fig.16 As shown, it can be seen that the via holes on the gate insulating layer 03 include: a first insulating layer via hole 033 in the pixel opening area, and a third via hole 032 in the binding area.

[0112] Step 15: Prepare a patterned source and drain layer 05 by film formation, exposure, wet etching, etc.

[0113] After completing step 15, the structure of the display substrate in the display area obtained based on the first embodiment is as follows: Fig.17 As shown, the structure of the display substrate in the display area obtained based on the second embodiment is as follows Fig.18 As shown, the structures of the display substrates obtained based on the first embodiment and the second embodiment in the binding area are as follows Fig.19 shown.

[0114] It can be seen that in the first embodiment, the pattern of the source-drain electrode layer 05 in the pixel opening region includes the first source-drain electrode 051 and the second source-drain electrode 052. In the second embodiment, the pattern of the source-drain electrode layer 05 in the pixel opening region includes the third source-drain electrode 053 and the fourth source-drain electrode 054. The third source-drain electrode 053 includes the first sub-electrode 053a and the second sub-electrode 053b. The first sub-electrode 053a and the second sub-electrode 053b are electrically connected. In both the first and second embodiments, the pattern of the source-drain electrode layer 05 in the binding region includes the second binding electrode 055.

[0115] See also Fig. 20 After completing the above steps 11 to 15, the deposition of the first passivation layer 06 can be performed according to step 2.

[0116] After completing step 2, the structure of the display substrate in the display area obtained based on the first embodiment is as follows: Fig. 20 As shown, the structure of the display substrate in the display area obtained based on the second embodiment is as follows Fig.21 As shown, the structures of the display substrates obtained based on the first embodiment and the second embodiment in the binding area are as follows Fig. 22 shown.

[0117] For example, the first passivation layer 06 can be deposited by PECVD, the film material of the first passivation layer 06 can be SiNx, and the film forming temperature is 280° C. to 290° C. Under this process, the first passivation layer 06 is formed more densely and has a better passivation protection effect.

[0118] The subsequent processes in Implementation Plan 1 and Implementation Plan 2 are described below respectively.

[0119] Implementation plan 1:

[0120] In the first embodiment, after completing the above step 2, the subsequent step 3 can be performed. The first electrode layer is a protective electrode layer 11, and the above step 3 specifically includes:

[0121] Step 3 - 1 : depositing a protective electrode layer 11 on a side of the first passivation layer 06 away from the substrate 01 .

[0122] The protective electrode layer 11 can be a transparent ITO film layer. After completing step 3-1, the display substrate obtained has the following structures in the display area and the binding area: Fig.23 , Fig.24 shown.

[0123] In the first embodiment, after the deposition of the protective electrode layer 11 is completed based on step 3-1, before the preparation of the second passivation layer 08 based on step 4, it is necessary to perform patterning of the protective electrode layer 11 and the first passivation layer 06. The present application provides two different processes, process one and process two, to achieve the patterning of the two film layers, which are described below respectively:

[0124] See also Figure 25-Figure 30 In process 1, after completing step 3-1 and before proceeding to step 4, the following detailed steps are also included:

[0125] Step 3.5-A1: Prepare a first pattern of the protective electrode layer 11 by photolithography exposure and wet etching.

[0126] In the display area, the first pattern of the protective electrode layer 11 includes: a first protective electrode 111 located in the pixel opening area. After completing step 3.5-A1, the structure of the display substrate in the display area is as follows: Fig.25 shown.

[0127] In the binding area, the first pattern of the protective electrode layer 11 includes: a second protective electrode 112 located in an adjacent area. After completing step 3.5-A1, the structure of the display substrate in the binding area is as follows Fig.26 shown.

[0128] Step 3.5-A2: forming an organic film layer 07 on a side of the first passivation layer 06 away from the substrate 01 .

[0129] Specifically, the pattern of the organic film layer 07 can be prepared by coating, exposing, and developing.

[0130] In the display area, the organic film layer 07 in the area for accommodating the storage capacitor structure needs to be completely removed, and the pattern of the organic film layer 07 is formed in the TFT switch area. After completing step 3.5-A2, the structure of the display substrate in the display area is as follows: Fig. 27 shown.

[0131] In the binding area, the organic film layer 07 above the binding electrode structure needs to be completely removed. After completing step 3.5-A2, the structure of the display substrate in the binding area is as follows: Fig.28 shown.

[0132] Step 3.5-A3: Using the organic film layer 07 and the first pattern as masks, the first passivation layer 06 is etched by dry etching.

[0133] Specifically, the pattern of the organic film layer 07 and the first pattern of the protective electrode layer 11 have a blocking effect, that is, etching methods such as plasma dry etching cannot etch the organic film layer 07 and the protective electrode layer 11. Therefore, in this step, the pattern of the organic film layer 07 and the first passivation layer 06 under the first pattern will be retained, and the first passivation layer 06 at other locations will be completely etched away.

[0134] After completing step 3.5-A3, the structures of the display substrate in the display area and the binding area are as follows: Fig.29 , Fig.30 shown.

[0135] See also Figure 25-26 ,as well as Figure 30-Figure 33 In process 2, after completing step 3-1 and before proceeding to step 4, the following detailed steps are also included:

[0136] Step 3.5-B1: Prepare the first pattern of the protective electrode layer 11 by photolithography exposure and wet etching.

[0137] This is consistent with step 3.5-A1 above. Please refer to the previous step 3.5-A1 and Figure 25-26 Description.

[0138] Step 3.5-B2: Using the photoresist mask of the first pattern as an anti-etching layer, the first passivation layer 06 is etched by dry etching.

[0139] Specifically, the photoresist mask left on the first pattern of the protective electrode layer 11 in step 3.5-B1 has an anti-etching effect, so when etching is performed by dry etching, the first passivation layer 06 under the first pattern will be retained.

[0140] After completing step 3.5-B2, the structures of the display substrate in the display area and the binding area are as follows: Fig.31 , Fig.32 shown.

[0141] Step 3.5-B3: Form an organic film layer 07 on a side of the first passivation layer 06 away from the substrate 01 .

[0142] Consistent with the description of step 3.5-A2 above, it is necessary to form an organic film layer 07 pattern in both the display area and the binding area. After completing step 3.5-B3, the structure of the display substrate in the display area is as follows: Fig.33 As shown, the structure of the substrate in the binding area is similar to Fig.30 Consistent.

[0143] In the second process, the pattern of the protective electrode layer 11 and the pattern of the first passivation layer 06 are etched and prepared in the same mask process, without the need for a separate organic film etching process. In addition, since the area to be etched is small, it is possible to prevent a large amount of etching byproducts from adhering to the surface of the gate insulating layer 03 due to long-term etching, thereby avoiding the problem caused by poor adhesion between the gate insulating layer 03 and the second passivation layer 08.

[0144] Based on the steps 3.5-A1 to 3.5-A3 of the above process 1, or based on the steps 3.5-B1 to 3.5-B3 of the above process 2, the patterning of the first passivation layer 06 and the protective electrode layer 11 can be achieved. The difference between the display substrates prepared based on the two processes is that in the pattern of the first passivation layer 06 obtained based on process 1, a part of the first passivation layer 06 is also retained in the TFT switch area; in the pattern of the first passivation layer 06 obtained based on process 2, the first passivation layer 06 is not retained in the TFT switch area.

[0145] After completing the above process 1 or process 2, you can proceed to the subsequent step 4. Figure 34-Figure 39 In implementation scheme 1, step 4 specifically includes:

[0146] Step 41 - 1 : depositing a second passivation layer 08 on a side of the protective electrode layer 11 away from the substrate 01 .

[0147] In process one, Fig.29 Based on the structure shown in FIG. 4 , after completing step 41-1, the structure of the display substrate in the display area is shown in FIG. Fig.34 . The result obtained in process 2 Fig.33 Based on the structure shown in FIG. 4 , after completing step 41-1, the structure of the display substrate in the display area is shown in FIG. Fig.35 .

[0148] For the structures obtained in process 1 and process 2, after completing step 41-1, the structure of the substrate in the binding area is shown as Fig.36 shown.

[0149] For example, the second passivation layer 08 can be deposited by the PECVD method, the preparation material can be SiNx, and the film forming temperature can be set to 250°C to 260°C. By setting the film forming temperature to 250°C to 260°C, it is possible to prevent the second passivation layer 08 from falling off due to the release of Outgas (degassing) by the organic film layer 07 due to excessive temperature. The second passivation layer 08 formed by low-temperature film formation is generally not as dense as the first passivation layer 06.

[0150] Step 42 - 1 : Prepare via holes on the second passivation layer 08 by photolithography and etching.

[0151] After step 42-1 is completed, in the case where the patterning of the first passivation layer 06 and the protective electrode layer 11 is completed by applying process 1, the structure of the display substrate in the display area is as follows: Fig.37 As shown; in the case where the patterning of the first passivation layer 06 and the protective electrode layer 11 is completed by applying the second process, the structure of the display substrate in the display area is as shown Fig.38 As shown; the structure of the substrate in the binding area is shown as Fig.39 shown.

[0152] It can be seen that in the display area, the vias to be prepared on the second passivation layer 08 include: the first passivation layer via 083, the second passivation layer via 084 and the third passivation layer via 085 located in the pixel opening area: the projection of the first passivation layer via 083 on the substrate 01 is located within the projection range of the first protection electrode 111 on the substrate 01; the projection of the second passivation layer via 084 on the substrate 01 is located within the projection range of the first source-drain electrode 051 on the substrate 01, and is located outside the projection range of the first protection electrode 111 on the substrate 01; the projection of the third passivation layer via 085 on the substrate 01 is located within the projection range of the second source-drain electrode 052 on the substrate 01. In the binding area, the vias to be prepared on the second passivation layer 08 include: the seventh passivation layer via 089 located on the side of the binding electrode structure away from the substrate 01.

[0153] In the first implementation, after completing the above steps 41-1 to 42-1, the subsequent step 5 can be performed. Figure 40-Figure 42 , step 5 includes:

[0154] Step 51 - 1 : forming a light shielding metal layer 09 on a side of the second passivation layer 08 away from the substrate 01 .

[0155] Step 52 - 2 : forming a pixel electrode layer 10 on a side of the light shielding metal layer 09 away from the substrate 01 .

[0156] Specifically, the second pattern of the light-shielding metal layer 09 can be prepared by film formation, photolithography, etching and the like; and the third pattern of the pixel electrode layer 10 can be prepared by film formation, photolithography, etching and the like.

[0157] After completing step 51-1 to step 52-1, in the case where the patterning of the first passivation layer 06 and the protective electrode layer 11 is completed by applying process 1, the structure of the display substrate in the display area is as follows: Fig.40 As shown; in the case where the patterning of the first passivation layer 06 and the protective electrode layer 11 is completed by applying the second process, the structure of the display substrate in the display area is as shown Fig.41 As shown; the structure of the substrate in the binding area is as shown Fig.42 shown.

[0158] It can be seen that in the display area, the second pattern of the light shielding metal layer 09 includes: a first light shielding structure 091 located in the TFT switch area and the pixel opening area, and a second light shielding structure 092 located in the pixel opening area; the projection of the first light shielding structure 091 on the substrate 01 at least partially overlaps with the projection of the first protection electrode 111 on the substrate 01, and the projection of the first light shielding structure 091 on the substrate 01 covers the projection of the second passivation layer via 084 on the substrate 01; the projection of the second light shielding structure 092 on the substrate 01 covers the projection of the first passivation layer via 083 and the third passivation layer via 085 on the substrate 01. The third pattern of the pixel electrode layer 10 includes: a third pixel electrode 103 located on the side of the first light shielding structure 091 away from the substrate 01, and a fourth pixel electrode 104 located on the side of the second light shielding structure 092 away from the substrate 01.

[0159] In the binding area, the second pattern of the light shielding metal layer 09 includes: a third light shielding structure 093, the projection of the third light shielding structure 093 on the substrate 01 covers the projection of the seventh passivation layer via 089 on the substrate 01, and is connected to the binding electrode structure through the seventh passivation layer via 089. The third pattern of the pixel electrode layer 10 includes: a first connection electrode 105, and the first connection electrode 105 is located on the side of the third light shielding structure 093 away from the substrate 01.

[0160] The first light shielding structure 091 of the light shielding metal layer 09 located in the TFT switch area can shield the TFT channel. The third pixel electrode 103, the fourth pixel electrode 104 and the first connection electrode 105 of the pixel electrode layer 10 can protect the via hole and prevent corrosion.

[0161] At this point, the preparation of the display substrate in the first embodiment is completed.

[0162] Implementation Plan 2:

[0163] See also Figure 43-Figure 44 In the second implementation scheme, after completing the above step 2 and before executing the subsequent step 3, the following step 2.5 needs to be executed:

[0164] Step 2.5: An organic film layer 07 located in the TFT switching area is formed on the side of the first passivation layer 06 away from the substrate 01 .

[0165] Specifically, the pattern of the organic film layer 07 can be prepared by coating, exposing, and developing.

[0166] In the display area, the organic film layer 07 in the area for accommodating the storage capacitor structure needs to be completely removed, and the pattern of the organic film layer 07 is formed in the TFT switch area. After completing step 2.5, the structure of the display substrate in the display area is as follows: Fig.43 shown.

[0167] In the binding area, the organic film layer 07 above the binding electrode structure needs to be completely removed. After completing step 2.5, the structure of the display substrate in the binding area is as follows: Fig.44 shown.

[0168] In the second implementation scheme, after completing the above step 2.5, the subsequent step 3 can be performed. Fig.45 , the first electrode layer is a light shielding metal layer 09, and step 3 specifically includes:

[0169] Step 3-2: forming a light shielding metal layer 09 on a side of the first passivation layer 06 away from the substrate 01 .

[0170] Specifically, the pattern of the light-shielding metal layer 09 can be formed by film formation, photolithography, and etching. The pattern of the light-shielding metal layer 09 is formed only in the display area, including: a fourth light-shielding structure 094 located in the TFT switch area and the pixel opening area, and the projection of the fourth light-shielding structure 094 on the substrate 01 is located within the projection range of the third source-drain electrode 053 on the substrate 01. In addition to shielding the TFT channel, the portion of the fourth light-shielding structure 094 in the TFT switch area can also form a storage capacitor with the subsequent pixel electrode layer 10.

[0171] After completing step 3-2, the structure of the display substrate in the display area is as follows Fig.45 shown.

[0172] After completing the above steps 3-2, you can proceed to the subsequent step 4. Figure 46-Figure 49 In the second implementation scheme, step 4 specifically includes:

[0173] Step 41 - 2 : depositing a second passivation layer 08 on the side of the light-shielding metal layer 09 away from the substrate 01 .

[0174] Please refer to the above description of step 41 - 1.

[0175] After completing step 41-2, the structures of the display substrate in the display area and the binding area are respectively as follows: Fig.46 , Fig.47 shown.

[0176] Step 42 - 2 : Prepare via holes on the second passivation layer 08 by photolithography and etching.

[0177] After completing step 42-2, the structures of the display substrate in the display area and the binding area are respectively as follows: Fig.48 , Fig.49 shown.

[0178] It can be seen that in the display area, the via holes to be prepared on the second passivation layer 08 include: the fourth passivation layer via hole 086, the fifth passivation layer via hole 087 and the sixth passivation layer via hole 088 located in the pixel opening area; the projection of the fourth passivation layer via hole 086 on the substrate 01 is located within the projection range of the light shielding metal layer 09 on the substrate 01; the projection of the fifth passivation layer via hole 087 on the substrate 01 is located within the projection range of the third source-drain electrode 053 on the substrate 01, and is located outside the projection range of the light shielding metal layer 09 on the substrate 01, and the fifth passivation layer via hole 087 also penetrates the first passivation layer 06; the projection of the sixth passivation layer via hole 088 on the substrate 01 is located within the projection range of the fourth source-drain electrode 054 on the substrate 01, and the sixth passivation layer via hole 088 also penetrates the first passivation layer 06. In the binding area, the eighth passivation layer via hole 080 is located in the binding electrode area, and the eighth passivation layer via hole 080 also penetrates the first passivation layer 06.

[0179] In the second implementation scheme, after completing the above steps 41-2 to 42-2, the subsequent step 5 can be executed. Figure 50-Figure 51 , step 5 includes:

[0180] Step 5-2: forming a pixel electrode layer 10 on a side of the second passivation layer 08 away from the substrate 01 .

[0181] Specifically, the fourth pattern of the pixel electrode layer 10 can be prepared by film formation, photolithography, etching and the like.

[0182] After completing step 5-2, the structures of the display substrate in the display area and the binding area are respectively as follows: Fig.50 , Fig.51 shown.

[0183] It can be seen that in the display area, the fourth pattern of the pixel electrode layer 10 includes: a first pixel electrode 101 located in the TFT switch area and the pixel opening area, and a second pixel electrode 102 located in the pixel opening area; the projection of the first pixel electrode 101 on the substrate 01 at least partially overlaps with the projection of the light shielding metal layer 09 on the substrate 01, and the projection of the first pixel electrode 101 on the substrate 01 covers the projection of the fifth passivation layer via 087 on the substrate 01, and the projection of the second pixel electrode 102 on the substrate 01 covers the projection of the fourth passivation layer via 086 and the sixth passivation layer via 088 on the substrate 01. In the binding area, the fourth pattern of the pixel electrode layer 10 includes: a second connection electrode 106, the projection of the second connection electrode 106 on the substrate 01 covers the projection of the eighth passivation layer via 080 on the substrate 01, and is connected to the binding electrode structure through the eighth passivation layer via 080.

[0184] At this point, the preparation of the display substrate in the second embodiment is completed.

[0185] Based on the same inventive concept, an embodiment of the present application further provides a display device, comprising the display substrate in any of the aforementioned embodiments.

[0186] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0187] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0188] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A display substrate, characterized in that: The display substrate has a display area, and the display area includes a pixel opening area; the display substrate includes: a substrate and a driving circuit layer arranged on one side of the substrate; The driving circuit layer comprises, in the pixel opening region: a gate layer, a gate insulating layer arranged on a side of the gate layer away from the substrate, and a source-drain electrode layer arranged on a side of the gate insulating layer away from the substrate; In the pixel opening region, the display substrate further comprises: a first passivation layer disposed on a side of the driving circuit layer away from the substrate, a first electrode layer disposed on a side of the first passivation layer away from the substrate, a second passivation layer disposed on a side of the first electrode layer away from the substrate, and a second electrode layer disposed on a side of the second passivation layer away from the substrate; The gate layer and the source-drain layer form a first storage capacitor, the source-drain layer and the first electrode layer form a second storage capacitor, and the first electrode layer and the second electrode layer form a third storage capacitor.

2. The display substrate according to claim 1, characterized in that: The display substrate further has a binding area, wherein the binding area includes a binding electrode area and an adjacent area located around the binding electrode area; The first passivation layer is also disposed in the binding region and is at least located on a side of the driving circuit layer in the adjacent region away from the substrate; The second passivation layer is also disposed in the binding region and is located on a side of the first passivation layer away from the substrate.

3. The display substrate according to claim 1, characterized in that: The display area also includes a TFT switch area; the first electrode layer is a protective electrode layer, and the second electrode layer includes a light-shielding metal layer and a pixel electrode layer arranged on a side of the light-shielding metal layer away from the substrate; The first passivation layer includes a first passivation structure located in the pixel opening area; the protection electrode layer includes a first protection electrode disposed on a side of the first passivation structure away from the substrate; The display substrate further includes an organic film layer, which is located in the TFT switch area and is arranged on a side of the drive circuit layer away from the substrate; The second passivation layer and the second electrode layer are also arranged in the TFT switch area, and are located on a side of the organic film layer away from the substrate.

4. The display substrate according to claim 3, characterized in that: The gate insulating layer is provided with a first insulating layer via hole located in the pixel opening area; The source-drain electrode layer comprises: a first source-drain electrode and a second source-drain electrode arranged in the pixel opening area; the first source-drain electrode is led out from the switch structure of the driving circuit layer in the TFT switch area; the projection of the second source-drain electrode on the substrate covers the projection of the first insulating layer via hole on the substrate, and is connected to the gate layer through the first insulating layer via hole; The first passivation structure and the first protection electrode are arranged on a side of the first source-drain electrode away from the substrate; The second passivation layer is provided with a first passivation layer via hole, a second passivation layer via hole and a third passivation layer via hole located in the pixel opening area: the projection of the first passivation layer via hole on the substrate is located within the projection range of the first protection electrode on the substrate; the projection of the second passivation layer via hole on the substrate is located within the projection range of the first source-drain electrode on the substrate and outside the projection range of the first protection electrode on the substrate; the projection of the third passivation layer via hole on the substrate is located within the projection range of the second source-drain electrode on the substrate; The light-shielding metal layer includes a first light-shielding structure located in the TFT switch area and the pixel opening area, and a second light-shielding structure located in the pixel opening area; a projection of the first light-shielding structure on the substrate at least partially overlaps with a projection of the first protection electrode on the substrate, and the projection of the first light-shielding structure on the substrate covers a projection of the second passivation layer via on the substrate; a projection of the second light-shielding structure on the substrate covers a projection of the first passivation layer via and a projection of the third passivation layer via on the substrate; The first shading structure is connected to the first source-drain electrode through the second passivation layer via; the second shading structure is connected to the first protection electrode through the first passivation layer via, and is connected to the gate layer through the third passivation layer via and the second source-drain electrode, so that the first protection electrode is connected to the gate layer.

5. The display substrate according to claim 1, characterized in that: The display area also includes a TFT switch area; the first electrode layer is a light-shielding metal layer, and the second electrode layer is a pixel electrode layer; The first passivation layer is also arranged in the TFT switch area, and is located on a side of the driving circuit layer away from the substrate; The display substrate further includes an organic film layer, which is located in the TFT switch area and is arranged on a side of the first passivation layer away from the substrate; The light-shielding metal layer, the second passivation layer and the pixel electrode layer are also arranged in the TFT switch area, and are located on a side of the organic film layer away from the substrate.

6. The display substrate according to claim 5, characterized in that: The gate insulating layer is provided with a first insulating layer via hole located in the pixel opening area; The source-drain electrode layer comprises: a third source-drain electrode and a fourth source-drain electrode arranged in the pixel opening area; the third source-drain electrode is led out from the switch structure of the driving circuit layer in the TFT switch area; the projection of the fourth source-drain electrode on the substrate covers the projection of the first insulating layer via hole on the substrate, and is connected to the gate layer through the first insulating layer via hole; The projection of the light shielding metal layer in the pixel opening area on the substrate is within the projection range of the third source-drain electrode on the substrate; The second passivation layer is provided with a fourth passivation layer via hole, a fifth passivation layer via hole and a sixth passivation layer via hole located in the pixel opening area; the projection of the fourth passivation layer via hole on the substrate is located within the projection range of the light-shielding metal layer on the substrate; the projection of the fifth passivation layer via hole on the substrate is located within the projection range of the third source-drain electrode on the substrate and is located outside the projection range of the light-shielding metal layer on the substrate, and the fifth passivation layer via hole also penetrates the first passivation layer; the projection of the sixth passivation layer via hole on the substrate is located within the projection range of the fourth source-drain electrode on the substrate, and the sixth passivation layer via hole also penetrates the first passivation layer; The pixel electrode layer includes a first pixel electrode located in the TFT switch area and the pixel opening area, and a second pixel electrode located in the pixel opening area; a projection of the first pixel electrode on the substrate at least partially overlaps with a projection of the light-shielding metal layer on the substrate, and the projection of the first pixel electrode on the substrate covers a projection of the fifth passivation layer via hole on the substrate, and a projection of the second pixel electrode on the substrate covers a projection of the fourth passivation layer via hole and a projection of the sixth passivation layer via hole on the substrate; The first pixel electrode is connected to the third source-drain electrode through the fifth passivation layer via hole; the second pixel electrode is connected to the shading metal layer through the fourth passivation layer via hole, and is connected to the gate layer through the sixth passivation layer via hole and the fourth source-drain electrode, so that the shading metal layer is connected to the gate layer.

7. The display substrate according to claim 2, characterized in that: The first electrode layer is a protective electrode layer, and the second electrode layer includes a light-shielding metal layer and a pixel electrode layer arranged on a side of the light-shielding metal layer away from the substrate; The driving circuit layer has in the binding area: a binding electrode structure located in a binding electrode area; The first passivation layer comprises: a second passivation structure located in the adjacent region and arranged on a side of the driving circuit layer away from the substrate; The protection electrode layer further includes: a second protection electrode disposed on a side of the second passivation structure away from the substrate; The second passivation layer is arranged on a side of the second protection electrode and the binding electrode structure away from the substrate, and a seventh passivation layer via hole is arranged on the second passivation layer and located on a side of the binding electrode structure away from the substrate; The light-shielding metal layer further includes a third light-shielding structure disposed in the binding region, the projection of the third light-shielding structure on the substrate covers the projection of the seventh passivation layer via hole on the substrate, and is connected to the binding electrode structure through the seventh passivation layer via hole; The pixel electrode layer further includes a first connecting electrode disposed on a side of the third light shielding structure away from the substrate.

8. The display substrate according to claim 2, characterized in that: The first electrode layer is a light-shielding metal layer, and the second electrode layer is a pixel electrode layer; The driving circuit layer has in the binding area: a binding electrode structure located in a binding electrode area; The first passivation layer is disposed on the entire surface of a side of the driving circuit layer away from the substrate; An eighth passivation layer via hole is provided on the second passivation layer and is located on a side of the binding electrode structure away from the substrate, and the eighth passivation layer via hole also penetrates the first passivation layer; The pixel electrode layer also includes a second connecting electrode arranged in the binding area, the projection of the second connecting electrode on the substrate covers the projection of the eighth passivation layer via on the substrate, and is connected to the binding electrode structure through the eighth passivation layer via.

9. A method for preparing a display substrate, characterized in that: The display substrate has a display area, and the display area includes a pixel opening area; the method includes: A driving circuit layer is formed on the substrate; the driving circuit layer comprises, in the pixel opening region, a gate layer, a gate insulating layer arranged on a side of the gate layer away from the substrate, and a source-drain layer arranged on a side of the gate insulating layer away from the substrate; forming a first passivation layer on a side of the driving circuit layer away from the substrate; forming a first electrode layer on a side of the first passivation layer away from the substrate; forming a second passivation layer on a side of the first electrode layer away from the substrate; forming a second electrode layer on a side of the second passivation layer away from the substrate; In the pixel opening region, the gate layer and the source-drain layer form a first storage capacitor, the source-drain layer and the first electrode layer form a second storage capacitor, and the first electrode layer and the second electrode layer form a third storage capacitor.

10. The method according to claim 9, characterized in that The display area further includes a TFT switch area, the first electrode layer is a protective electrode layer, and after forming the protective electrode layer, the method further includes: A first pattern of the protective electrode layer is prepared by photolithography exposure and wet etching; the first pattern includes: a first protective electrode located in the pixel opening area; forming an organic film layer located in the TFT switch area on a side of the first passivation layer away from the substrate; Using the organic film layer and the first pattern as masks, etching the first passivation layer by dry etching; The forming of a second electrode layer on a side of the second passivation layer away from the substrate comprises: forming a light-shielding metal layer on a side of the second passivation layer away from the substrate; A pixel electrode layer is formed on a side of the light-shielding metal layer away from the substrate.

11. The method according to claim 9, characterized in that The display area further includes a TFT switch area, the first electrode layer is a protective electrode layer, and after forming the protective electrode layer, the method further includes: A first pattern of the protective electrode layer is prepared by photolithography exposure and wet etching; the first pattern includes: a first protective electrode located in the pixel opening area; Using the photoresist mask of the first pattern as an anti-etching layer, etching the first passivation layer by dry etching; forming an organic film layer located in the TFT switch area on a side of the driving circuit layer away from the substrate; The forming of a second electrode layer on a side of the second passivation layer away from the substrate comprises: forming a light-shielding metal layer on a side of the second passivation layer away from the substrate; A pixel electrode layer is formed on a side of the light-shielding metal layer away from the substrate.

12. The method according to claim 10 or 11, characterized in that: The gate insulating layer is provided with a first insulating layer via hole located in the pixel opening area; the source-drain electrode layer includes: a first source-drain electrode and a second source-drain electrode arranged in the pixel opening area; the first source-drain electrode is led out from the switch structure of the driving circuit layer in the TFT switch area; the projection of the second source-drain electrode on the substrate covers the projection of the first insulating layer via hole on the substrate, and is connected to the gate layer through the first insulating layer via hole; After forming the second passivation layer, the method further includes: A first passivation layer via hole, a second passivation layer via hole and a third passivation layer via hole are prepared on the second passivation layer and are located in the pixel opening area: the projection of the first passivation layer via hole on the substrate is located within the projection range of the first protection electrode on the substrate; the projection of the second passivation layer via hole on the substrate is located within the projection range of the first source-drain electrode on the substrate and is located outside the projection range of the first protection electrode on the substrate; the projection of the third passivation layer via hole on the substrate is located within the projection range of the second source-drain electrode on the substrate; After forming the light-shielding metal layer, the method comprises: Prepare a second pattern of the light-shielding metal layer: the second pattern includes: a first light-shielding structure located in the TFT switch area and the pixel opening area, and a second light-shielding structure located in the pixel opening area; the projection of the first light-shielding structure on the substrate at least partially overlaps with the projection of the first protection electrode on the substrate, and the projection of the first light-shielding structure on the substrate covers the projection of the second passivation layer via on the substrate; the projection of the second light-shielding structure on the substrate covers the projection of the first passivation layer via and the third passivation layer via on the substrate; After forming the pixel electrode layer, the method further includes: A third pattern of the pixel electrode layer is prepared; the third pattern comprises: a third pixel electrode located on a side of the first light-shielding structure away from the substrate, and a fourth pixel electrode located on a side of the second light-shielding structure away from the substrate.

13. The method according to claim 10 or 11, characterized in that: The display substrate further has a binding area, which includes a binding electrode area and an adjacent area around the binding electrode area; the driving circuit layer has in the binding area: a binding electrode structure located in the binding electrode area; The first pattern further includes: a second protection electrode located in the adjacent region; After forming the second passivation layer, the method further includes: Preparing a seventh passivation layer via hole on the second passivation layer, which is located on a side of the binding electrode structure away from the substrate; After forming the light-shielding metal layer, the method further comprises: Prepare a third light-shielding structure of the light-shielding metal layer, wherein the projection of the third light-shielding structure on the substrate covers the projection of the seventh passivation layer via hole on the substrate, and is connected to the binding electrode structure through the seventh passivation layer via hole; After forming the pixel electrode layer, the method further includes: A first connecting electrode of the pixel electrode layer is prepared, wherein the first connecting electrode is located at a side of the third light-shielding structure away from the substrate.

14. The method according to claim 9, characterized in that The display area further includes a TFT switch area, the first electrode layer is a light-shielding metal layer, and the second electrode layer is a pixel electrode layer; after forming the first passivation layer and before forming the light-shielding metal layer, the method further includes: An organic film layer located in the TFT switch region is formed on a side of the first passivation layer away from the substrate.

15. The method according to claim 14, characterized in that The gate insulating layer is provided with a first insulating layer via hole located in the pixel opening area; the source-drain electrode layer includes: a third source-drain electrode and a fourth source-drain electrode arranged in the pixel opening area; the third source-drain electrode is led out from the switch structure of the driving circuit layer in the TFT switch area; the projection of the fourth source-drain electrode on the substrate covers the projection of the first insulating layer via hole on the substrate, and is connected to the gate layer through the first insulating layer via hole; After forming the light-shielding metal layer, the method further comprises: A fourth pattern of the light-shielding metal layer is prepared; the fourth pattern includes a fourth light-shielding structure located in the TFT switch area and the pixel opening area, and the projection of the fourth light-shielding structure on the substrate is located within the projection range of the third source-drain electrode on the substrate; After forming the second passivation layer, the method further includes: A fourth passivation layer via hole, a fifth passivation layer via hole and a sixth passivation layer via hole are prepared on the second passivation layer and are located in the pixel opening area; the projection of the fourth passivation layer via hole on the substrate is located within the projection range of the light-shielding metal layer on the substrate; the projection of the fifth passivation layer via hole on the substrate is located within the projection range of the third source-drain electrode on the substrate and is located outside the projection range of the light-shielding metal layer on the substrate, and the fifth passivation layer via hole also penetrates the first passivation layer; the projection of the sixth passivation layer via hole on the substrate is located within the projection range of the fourth source-drain electrode on the substrate, and the sixth passivation layer via hole also penetrates the first passivation layer; After forming the pixel electrode layer, the method further includes: A fourth pattern of the pixel electrode layer is prepared; the fourth pattern includes: a first pixel electrode located in the TFT switch area and the pixel opening area, and a second pixel electrode located in the pixel opening area; the projection of the first pixel electrode on the substrate at least partially overlaps with the projection of the light-shielding metal layer on the substrate, and the projection of the first pixel electrode on the substrate covers the projection of the fifth passivation layer via on the substrate, and the projection of the second pixel electrode on the substrate covers the projection of the fourth passivation layer via and the sixth passivation layer via on the substrate.

16. The method according to claim 14, characterized in that The display substrate further has a binding area, which includes a binding electrode area and an adjacent area around the binding electrode area; the driving circuit layer has in the binding area: a binding electrode structure located in the binding electrode area; After forming the second passivation layer, the method further includes: Preparing an eighth passivation layer via hole located in the binding electrode region on the second passivation layer, wherein the eighth passivation layer via hole also penetrates the first passivation layer; After forming the pixel electrode layer, the method further includes: A second connecting electrode of the pixel electrode layer is prepared, wherein the projection of the second connecting electrode on the substrate covers the projection of the eighth passivation layer via hole on the substrate, and the second connecting electrode is connected to the binding electrode structure through the eighth passivation layer via hole.

17. A display device, characterized in that: The display substrate comprises the display substrate as claimed in any one of claims 1 to 8.

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