Method and device for optimizing power consumption of multi-core heterogeneous ASIC (Application Specific Integrated Circuit) computing mainboard

Abstract

The invention relates to a power consumption optimization method and device for a multi-core heterogeneous ASIC (Application Specific Integrated Circuit) computing mainboard. The method comprises the following steps: in combination with task attribute information of each calculation task in a multi-core heterogeneous ASIC calculation mainboard and heterogeneous attribute information of each heterogeneous processing unit, performing calculation resource allocation processing on each calculation task in a chemical reaction optimization algorithm to obtain a calculation resource allocation result of each calculation task; obtaining the task path length and task relaxation time of each calculation task by combining the calculation resource allocation result of each calculation task and the running state of each heterogeneous processing unit; and in combination with the task path length and the task relaxation time of each calculation task, obtaining each adjusted heterogeneous processing unit under the condition of meeting the deadline constraint of the calculation task, so as to execute each calculation task according to the optimal energy consumption ratio. By adopting the method, high-efficiency and low-power-consumption computing resource scheduling can be realized.

Description

Technical Field

[0001] The present application relates to the technical field of power consumption optimization, and in particular to a method and device for optimizing power consumption of a multi-core heterogeneous ASIC computing motherboard. Background Art

[0002] In the field of power consumption optimization technology, it involves optimizing the power consumption of multi-core heterogeneous ASIC computing motherboards to achieve high-performance computing and low-energy operation.

[0003] Related power consumption optimization methods use fixed power consumption management strategies or static task allocation to achieve power consumption optimization of multi-core heterogeneous ASIC computing motherboards and heterogeneous processing units. However, this method has the disadvantages of insufficient adaptability to heterogeneous processing units and low task scheduling flexibility, making it difficult to achieve efficient and low-power computing resource scheduling. Summary of the invention

[0004] Based on this, it is necessary to provide a power consumption optimization method, device, computer equipment and computer-readable storage medium for a multi-core heterogeneous ASIC computing motherboard to address the above technical problems, so as to be used for efficient and low-power computing resource scheduling and improve the overall performance and energy efficiency of the multi-core heterogeneous ASIC computing motherboard.

[0005] In a first aspect, the present application provides a method for optimizing power consumption of a multi-core heterogeneous ASIC computing motherboard, comprising: Determine each computing task corresponding to the preset multi-core heterogeneous ASIC computing motherboard, combine the task attribute information of each computing task and the heterogeneous attribute information of each heterogeneous processing unit in the multi-core heterogeneous ASIC computing motherboard, perform computing resource allocation processing on each computing task in a preset chemical reaction optimization algorithm, and obtain the computing resource allocation result corresponding to each computing task; Combined with the computing resource allocation results corresponding to each computing task and the operating status of each heterogeneous processing unit, the task path length and task relaxation time of each computing task are calculated; In combination with the task path length and task slack time of each computing task, and under the condition of satisfying the preset computing task deadline constraint, the electrical parameters of each heterogeneous processing unit are adjusted to obtain each adjusted heterogeneous processing unit, and the each adjusted heterogeneous processing unit is used to execute each computing task of the multi-core heterogeneous ASIC computing motherboard according to the optimal energy consumption ratio.

[0006] In a second aspect, the present application also provides a power consumption optimization device for a multi-core heterogeneous ASIC computing motherboard, comprising: An allocation module is used to determine each computing task corresponding to a preset multi-core heterogeneous ASIC computing mainboard, and perform computing resource allocation processing on each computing task in a preset chemical reaction optimization algorithm in combination with task attribute information of each computing task and heterogeneous attribute information of each heterogeneous processing unit in the multi-core heterogeneous ASIC computing mainboard, to obtain computing resource allocation results corresponding to each computing task; The time analysis module is used to calculate the task path length and task slack time of each computing task by combining the computing resource allocation results corresponding to each computing task and the operating status of each heterogeneous processing unit; The adjustment module is used to adjust the electrical parameters of each heterogeneous processing unit in combination with the task path length and task slack time of each computing task, under the condition of satisfying the preset computing task deadline constraint, to obtain each adjusted heterogeneous processing unit, and the each adjusted heterogeneous processing unit is used to execute each computing task of the multi-core heterogeneous ASIC computing motherboard according to the optimal energy consumption ratio.

[0007] In a third aspect, the present application further provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the above steps when executing the computer program.

[0008] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the above steps when executed by a processor.

[0009] The above-mentioned power consumption optimization method, device, computer equipment and computer-readable storage medium of the multi-core heterogeneous ASIC computing motherboard, first, in the multi-core heterogeneous ASIC computing motherboard, combined with the task attribute information of each computing task and the heterogeneous attribute information of each heterogeneous processing unit, the computing resource allocation processing is performed through the chemical reaction optimization algorithm to obtain the computing resource allocation result corresponding to each computing task, thereby ensuring that the computing resources are preliminarily reasonably matched for each computing task; secondly, combined with the computing resource allocation result and the running state of the heterogeneous processing unit, the task path length and the task relaxation time are calculated, so as to further adjust the electrical parameters of each heterogeneous processing unit on the basis of preliminarily reasonably matching the computing resources for each computing task under the condition of satisfying the deadline constraint of the computing task, thereby combining the computing task level and the heterogeneous processing unit level to achieve efficient and low-power computing resource scheduling, and improve the overall performance and energy efficiency of the multi-core heterogeneous ASIC computing motherboard. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0011] Figure 1 A schematic diagram of a flow chart of a method for optimizing power consumption of a multi-core heterogeneous ASIC computing motherboard in one embodiment; Figure 2 It is a structural block diagram of a power consumption optimization device for a multi-core heterogeneous ASIC computing motherboard in one embodiment. DETAILED DESCRIPTION

[0012] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0013] In one embodiment, Figure 1 As shown, a method for optimizing power consumption of a multi-core heterogeneous ASIC computing motherboard is provided. This embodiment uses the method applied to a server as an example. It can be understood that the method can also be applied to a terminal, and can also be applied to a system including a terminal and a server, and is implemented through the interaction between the terminal and the server. In this embodiment, the method includes the following steps S101 to S103.

[0014] Step S101, determine each computing task corresponding to the preset multi-core heterogeneous ASIC computing motherboard, combine the task attribute information of each computing task and the heterogeneous attribute information of each heterogeneous processing unit in the multi-core heterogeneous ASIC computing motherboard, perform computing resource allocation processing on each computing task in the preset chemical reaction optimization algorithm, and obtain the computing resource allocation result corresponding to each computing task.

[0015] Among them, the multi-core heterogeneous ASIC computing motherboard represents an application-specific integrated circuit (ASIC) computing hardware containing multiple heterogeneous processing units, which is used to collaboratively process computing tasks through multiple heterogeneous processing units; the heterogeneous processing unit represents the computing cores with different computing architectures, computing capabilities and power consumption characteristics in the multi-core heterogeneous ASIC computing motherboard; the computing task represents the data processing or computing operation performed on the multi-core heterogeneous ASIC computing motherboard.

[0016] Among them, the task attribute information of the computing task represents a set of parameters that describe the characteristics of the computing task, such as the computational complexity, execution latency, power consumption requirements, and parallelism requirements of the task; the heterogeneous attribute information of the heterogeneous processing unit represents a set of parameters that describe the characteristics of the heterogeneous processing unit, such as computing performance, power consumption level, storage bandwidth, computing latency, and programming flexibility.

[0017] Among them, the chemical reaction optimization algorithm represents a global optimization algorithm based on chemical reaction process simulation, which is used to determine the computing resource allocation result of the computing task by simulating the reaction state changes between chemical molecules; the computing resource allocation result represents the mapping relationship between the computing task and the computing resource obtained after calculation by the chemical reaction optimization algorithm, which is used to guide the computing resource utilization of the computing task on the multi-core heterogeneous ASIC computing motherboard.

[0018] Exemplarily, in combination with the task attribute information of each computing task and the heterogeneous attribute information of each heterogeneous processing unit, computing resources are matched and scheduled for each computing task through a chemical reaction optimization algorithm, that is, each computing task can be regarded as a reactant in a chemical reaction, and different heterogeneous processing units can be regarded as different catalysts. The computing resource allocation process is the optimization evolution process of the chemical reaction, and the optimal solution is sought by simulating the state changes of chemical molecules during the reaction process; finally, the state change process of each computing task is mapped to the execution efficiency change on different heterogeneous processing units, indicating which processing units each computing task should be assigned to and how it should be executed, so as to achieve the optimal utilization of computing resources, that is, to obtain the computing resource allocation result of each computing task on a multi-core heterogeneous ASIC computing motherboard.

[0019] Step S102, combining the computing resource allocation results corresponding to each computing task and the operating status of each heterogeneous processing unit, calculates the task path length and task slack time of each computing task.

[0020] The operating status of the heterogeneous processing unit represents the working status of the heterogeneous computing unit in a specific time period, such as current load, execution efficiency, power consumption level and other information.

[0021] Among them, the task path length represents the total execution time experienced by the computing task from the start to the completion, including factors such as computing time, data transmission time and scheduling delay; the task slack time represents the maximum adjustable range allowed for the execution time of the computing task.

[0022] Exemplarily, the computing resources allocated to each computing task and the computing performance of each heterogeneous processing unit can be determined by combining the computing resource allocation results corresponding to each computing task and the operating status of each heterogeneous processing unit. Thus, the computing time, data transmission time and scheduling delay of the computing task can be further calculated, and the task path length of each computing task can be obtained by combining the above time factors. Furthermore, based on the task path length of each computing task, the earliest start time and the latest completion time corresponding to each computing task can be determined, wherein the earliest start time indicates the earliest time when a computing task can be started after the completion of the preceding task, and the latest completion time indicates the latest time when a computing task can be completed without affecting the entire computing task process. Then, the earliest start time and the latest completion time are respectively relative to the additional time range corresponding to the original task execution time as the task slack time of the computing task.

[0023] Step S103, combining the task path length and task relaxation time of each computing task, and under the condition of satisfying the preset computing task deadline constraint, adjusting the electrical parameters of each heterogeneous processing unit to obtain each adjusted heterogeneous processing unit, and the adjusted heterogeneous processing unit is used to execute each computing task of the multi-core heterogeneous ASIC computing motherboard according to the optimal energy consumption ratio.

[0024] The deadline constraint of a computing task indicates a hard time requirement that the computing task must be completed within a specific time.

[0025] The electrical parameters of the heterogeneous processing unit represent electrical characteristic parameters that affect the power consumption and computing performance of the heterogeneous processing unit, such as operating voltage, clock frequency, power management mode and other information.

[0026] Exemplarily, in combination with the task path length and task relaxation time of each computing task, the electrical parameters of each heterogeneous processing unit are adjusted without violating the deadline constraint of the computing task, that is, by means of voltage regulation, clock frequency control, etc., based on the total execution time of each computing task and the maximum adjustable range allowed by the execution time, the electrical parameters such as the working voltage and working frequency of each heterogeneous processing unit are reasonably adjusted. For example, if the task relaxation time of a computing task is long, the voltage and clock frequency of the heterogeneous processing unit used by the computing task can be adaptively reduced based on the task path length of the computing task to reduce the overall power consumption without affecting the final completion time of the computing task; and for computing tasks with high time sensitivity and short task relaxation time, the voltage and clock frequency of the corresponding heterogeneous processing unit can be adaptively maintained or only slightly reduced based on the task path length of the computing task to ensure the timely completion of the computing task. Finally, after the above optimization adjustment, each heterogeneous processing unit can complete the computing task under the condition of the optimal energy consumption ratio and achieve the goal of power consumption optimization.

[0027] In the above-mentioned power consumption optimization method of the multi-core heterogeneous ASIC computing motherboard, firstly, in the multi-core heterogeneous ASIC computing motherboard, the task attribute information of each computing task and the heterogeneous attribute information of each heterogeneous processing unit are combined, and the computing resource allocation processing corresponding to each computing task is obtained through the chemical reaction optimization algorithm, so as to ensure that the computing resources are preliminarily reasonably matched for each computing task; secondly, the task path length and the task relaxation time are calculated in combination with the computing resource allocation result and the running state of the heterogeneous processing unit, so as to further adjust the electrical parameters of each heterogeneous processing unit on the basis of preliminarily reasonably matching the computing resources for each computing task under the condition of satisfying the deadline constraint of the computing task, so as to combine the computing task level and the heterogeneous processing unit level, realize efficient and low-power computing resource scheduling, and improve the overall performance and energy efficiency of the multi-core heterogeneous ASIC computing motherboard.

[0028] In an exemplary embodiment, based on the task attribute information of each computing task and the heterogeneous attribute information of each heterogeneous processing unit in a multi-core heterogeneous ASIC computing motherboard, computing resource allocation processing is performed on each computing task in a preset chemical reaction optimization algorithm to obtain computing resource allocation results corresponding to each computing task, including steps S201 to S203.

[0029] Step S201 , performing feature extraction processing on the task attribute information of each computing task to generate a task attribute matrix, and performing feature extraction processing on the heterogeneous attribute information of each heterogeneous processing unit to generate a processing unit attribute matrix.

[0030] Among them, the task attribute matrix represents a matrix data structure constructed based on the characteristic data of the task attribute information of each computing task. In this matrix, the rows represent different computing tasks, the columns represent the characteristic data such as the computational complexity, data dependency, and execution priority of the computing tasks, and each element is a numerical representation of the corresponding characteristic data.

[0031] Among them, the processing unit attribute matrix represents a matrix data structure constructed based on the characteristic data of the heterogeneous attribute information of each heterogeneous processing unit. In this matrix, the rows represent different heterogeneous processing units, and the columns represent the characteristic data such as computing performance, power consumption level, parallel capability, etc. of the heterogeneous processing units. Each element is a numerical representation of the corresponding characteristic data.

[0032] Step S202, combining the task attribute matrix and the processing unit attribute matrix, constructing and processing the energy consumption of the multi-core heterogeneous ASIC computing motherboard during the task scheduling process, and obtaining a resource allocation optimization objective function.

[0033] Among them, the resource allocation optimization objective function represents a mathematical function that measures the energy consumption of a multi-core heterogeneous ASIC computing motherboard during task scheduling, and is used to optimize and solve the optimal solution for allocating computing resources to computing tasks.

[0034] Exemplarily, the energy consumption of a multi-core heterogeneous ASIC computing motherboard during task scheduling can be analyzed based on the degree of fit between the task attribute matrix and the processing unit attribute matrix, that is, the degree of fit between each computing task and each heterogeneous processing unit is quantified by determining the degree of fit between each feature data in the task attribute matrix and each feature data in the processing unit attribute matrix, thereby constructing a corresponding resource allocation optimization objective function for providing an optimal allocation plan of computing resources for each computing task according to the above-mentioned degree of fit.

[0035] Step S203, in the chemical reaction optimization algorithm, combining the operation behavior of the molecular dynamics simulation and the resource allocation optimization objective function, by performing computing resource allocation processing on each computing task, the computing resource allocation result corresponding to each computing task is obtained.

[0036] Among them, the operational behavior of molecular dynamics simulation refers to the movement, collision, energy change and other behaviors of the simulated molecules in the chemical reaction process in the chemical reaction optimization algorithm.

[0037] For example, in the chemical reaction optimization algorithm, each computing task is regarded as a reactant of the chemical reaction, and each heterogeneous processing unit is regarded as a different catalyst. Based on the simulation of the movement, collision, energy change and other behaviors of molecules in the chemical reaction process, the migration and allocation of computing tasks in computing resources are simulated accordingly. Thus, the resource allocation optimization objective function is calculated according to the simulation results, so as to dynamically adjust the resource allocation scheme of the computing tasks, so that the multi-core heterogeneous ASIC computing motherboard tends to the optimal energy consumption state. Finally, after iterative optimization, the optimal resource allocation scheme for each computing task is determined, that is, the computing resource allocation result corresponding to each computing task.

[0038] In this embodiment, first, feature extraction is performed on the task attribute information of the computing task and the heterogeneous attribute information of the heterogeneous processing units, and a task attribute matrix and a processing unit attribute matrix are constructed respectively, so as to structure the features of the computing task and the features of the computing resources, and provide a quantitative basis for subsequent resource allocation; secondly, the task attribute matrix and the processing unit attribute matrix are combined to analyze the energy consumption of the multi-core heterogeneous ASIC computing motherboard during the task scheduling process, so as to construct a resource allocation optimization objective function, so as to describe the impact of task scheduling on energy consumption based on a mathematical model, and improve the computability and optimizability of resource allocation and energy consumption management; thirdly, in combination with the operation behavior of molecular dynamics simulation and the resource allocation optimization objective function, computing resource allocation processing is performed on each computing task, so as to dynamically adjust the computing resource allocation scheme of the computing task, and realize efficient and low-power computing resource management.

[0039] In an exemplary embodiment, the energy consumption of a multi-core heterogeneous ASIC computing motherboard during task scheduling is constructed and processed by combining the task attribute matrix and the processing unit attribute matrix to obtain a resource allocation optimization objective function, including steps S301 to S303.

[0040] Step S301, calculate the fitness between the task attribute matrix and the processing unit attribute matrix to generate a task resource fitness matrix, which represents the fitness between the computing load of each computing task and the computing performance of each heterogeneous processing unit in matrix form.

[0041] Among them, the task resource adaptation matrix represents a matrix data structure constructed based on the adaptation between the task attribute matrix and the processing unit attribute matrix. In this matrix, the rows represent different computing tasks, the columns represent different heterogeneous processing units, and the numerical value of each element represents the adaptation between the computing load of the corresponding computing task and the computing performance of the corresponding heterogeneous processing unit.

[0042] Exemplarily, the fitness of the characteristic data in the task attribute matrix and the characteristic data in the processing unit attribute matrix is ​​calculated to obtain the fitness between the computing load of each computing task and the computing performance of each heterogeneous processing unit. Then, a task resource fitness matrix is ​​constructed by using a matrix expression method in which different rows represent different computing tasks and different columns represent different heterogeneous processing units. The fitness between the computing load of different computing tasks and the computing performance of different heterogeneous processing units is expressed by the numerical values ​​of the elements in the matrix.

[0043] Step S302, based on the task resource adaptation matrix, the energy consumption of each computing task executed on each heterogeneous processing unit is calculated and processed to obtain the energy consumption constraint condition of each computing task executed on each heterogeneous processing unit.

[0044] Among them, the energy consumption constraints represent the energy consumption range of each computing task when it is executed on different heterogeneous processing units and the energy consumption limit during optimized scheduling. For example, the energy consumption constraints may include the maximum power consumption threshold when the computing task is executed on a specific heterogeneous processing unit, the energy consumption limit when the computing task is executed on multiple heterogeneous processing units, the energy consumption loss limit caused by the migration of computing tasks, etc.

[0045] Exemplarily, the computing characteristics of each computing task executed on different heterogeneous processing units are determined based on the task resource adaptation matrix, that is, in the task resource adaptation matrix, the adaptation corresponding to each element value reflects the adaptation between the computing requirements of the corresponding computing task and the computing capabilities of the heterogeneous processing unit. The higher the adaptation, the higher the computing efficiency of the computing task when it is executed on the heterogeneous processing unit, and it may also mean lower energy consumption or shorter computing delay. Furthermore, based on the computing characteristics of each computing task executed on different heterogeneous processing units, the energy consumption constraint conditions of each computing task executed on each heterogeneous processing unit are further calculated, that is, the higher the adaptation, the better the computing characteristics of the corresponding computing task executed on the corresponding heterogeneous processing unit, and the maximum power consumption threshold of the computing task when it is executed on the heterogeneous processing unit can be adaptively adjusted to serve as the energy consumption constraint condition of the computing task executed on the heterogeneous processing unit, thereby providing a larger adjustable range for the power consumption of the computing task executed on the heterogeneous processing unit.

[0046] Step S303, combining the energy consumption constraints of each computing task executed on each heterogeneous processing unit and minimizing the comprehensive energy consumption of all computing tasks, to obtain a resource allocation optimization objective function.

[0047] Exemplarily, the energy consumption constraints of each computing task executed on each heterogeneous processing unit are taken as boundary conditions, and minimizing the comprehensive energy consumption of all computing tasks is taken as the optimization goal, so as to construct a resource allocation optimization objective function based on the above boundary conditions and optimization goals. The resource allocation optimization objective function is used to quantify the power consumption of each computing task executed on different heterogeneous processing units, so as to ensure that the heterogeneous processing units are reasonably allocated to each computing task under the corresponding energy consumption constraints and the computing resources corresponding to the heterogeneous processing units are allocated, while minimizing the comprehensive energy consumption of all computing tasks.

[0048] In this embodiment, firstly, in the task attribute matrix and the processing unit attribute matrix, a task resource adaptation matrix is ​​generated according to the adaptability between the computing load of the computing task and the computing performance of the heterogeneous processing unit, so as to achieve quantitative matching between the computing task requirements and the computing resource capabilities, and provide an accurate data basis for subsequent energy consumption analysis; secondly, the energy consumption of each computing task on different heterogeneous processing units is calculated according to the task resource adaptation matrix, and energy consumption constraints are formed, so as to accurately evaluate the constraint range corresponding to the energy consumption of different computing resource allocation schemes; thirdly, the energy consumption constraints of each computing task executed on each heterogeneous processing unit and the minimization of the comprehensive energy consumption of all computing tasks are combined to obtain the resource allocation optimization objective function, so as to achieve the adaptive and accurate scheduling of computing resources through mathematical optimization according to the resource allocation optimization objective function. In an exemplary embodiment, in a chemical reaction optimization algorithm, the operational behavior of molecular dynamics simulation and the resource allocation optimization objective function are combined, and computing resource allocation processing is performed on each computing task to obtain the computing resource allocation results corresponding to each computing task, including steps S401 to S402.

[0049] Step S401, in the chemical reaction optimization algorithm, based on the decomposition operation, exchange operation and synthesis operation of the molecular dynamics simulation, the allocation relationship between each computing task and each heterogeneous processing unit is iteratively adjusted, and the iteratively adjusted allocation relationship is used as the input variable of the resource allocation optimization objective function in different outer iteration rounds.

[0050] The allocation relationship between each computing task and each heterogeneous processing unit represents the mapping relationship between the computing tasks on the multi-core heterogeneous ASIC computing motherboard and the corresponding heterogeneous processing units, which is used to indicate that the computing tasks are executed on the corresponding heterogeneous processing units.

[0051] The decomposition operation represents the simulation of the decomposition behavior of molecules during a chemical reaction, which corresponds to splitting the allocation relationship between computing tasks and heterogeneous processing units, so that the computing tasks originally allocated to a single heterogeneous processing unit can be reallocated to multiple different heterogeneous processing units for evaluation.

[0052] The interactive operation represents the replacement behavior of the simulated molecules in the chemical reaction process, which corresponds to the interchange of the allocation relationship between the computing tasks and the heterogeneous processing units, so that the computing tasks can be migrated or exchanged between different heterogeneous processing units.

[0053] Among them, the synthesis operation represents the simulation of the synthesis behavior of molecules in the process of chemical reaction, which corresponds to the merging of the allocation relationship between computing tasks and heterogeneous processing units, so that multiple computing tasks that were originally executed independently can be reallocated to the same heterogeneous processing unit or multiple heterogeneous processing units for collaborative evaluation.

[0054] The outer iteration refers to the iterative optimization process performed on the input variables of the resource allocation optimization objective function before the input variables are input into the resource allocation optimization objective function.

[0055] Exemplarily, in a chemical reaction optimization algorithm, the allocation relationship between each computing task and each heterogeneous processing unit is iteratively adjusted through the decomposition operation, exchange operation and synthesis operation of molecular dynamics simulation, so as to obtain the input variables of the resource allocation optimization objective function in different outer iteration rounds, so as to seek the optimal allocation scheme between computing tasks and heterogeneous processing units. For example: through the decomposition operation, the allocation relationship between a certain computing task and a certain heterogeneous processing unit is split, and the allocation relationship between the computing task and different heterogeneous processing units is obtained again; further, through the exchange operation, the allocation relationship between the computing tasks and the heterogeneous processing units in the two pairs is replaced, and the allocation relationship between the computing tasks in one pair and the heterogeneous processing units in the other pair is obtained again; further, through the synthesis operation, the allocation relationship between the computing tasks and the heterogeneous processing units in multiple pairs is merged, and the overall allocation relationship between all computing tasks in the multiple pairs and all heterogeneous processing units is obtained again.

[0056] Step S402, calculate the resource allocation optimization objective function based on the function values ​​of the inner layer iteration outputs corresponding to the input variables of different outer layer iteration rounds, until multiple objective function values ​​corresponding to the optimization goal that meets the resource allocation optimization objective function are obtained, and use the multiple objective function values ​​as the computing resource allocation results corresponding to each computing task.

[0057] The inner iteration refers to the iterative optimization process of the internal variables of the resource allocation optimization objective function after the input variables are input into the resource allocation optimization objective function.

[0058] Among them, the optimization goal of the resource allocation optimization objective function can be expressed as minimizing the comprehensive consumption of all computing tasks.

[0059] Exemplarily, the input variables of different outer iteration rounds are respectively input into the resource allocation optimization objective function, and the resource allocation optimization objective function implements inner iterative calculation based on the input variables, that is, the input variables are the allocation schemes between computing tasks and heterogeneous processing units, and the input variables can be inner iteratively calculated based on the optimization objective of the resource allocation optimization objective function to further determine the impact of each allocation scheme on the comprehensive energy consumption, and based on minimizing the comprehensive consumption of all computing tasks, on the basis of the allocation schemes between computing tasks and heterogeneous processing units, further accurately determine the allocation schemes between each computing task and the computing resources of the corresponding heterogeneous processing units, for example, adjust the specific computing resources such as CPU occupancy, memory usefulness, data throughput, etc. allocated by the heterogeneous processing units to the corresponding computing tasks, until multiple objective function values ​​corresponding to the optimization objectives of the resource allocation optimization objective function are obtained, and used as the computing resource allocation results corresponding to each computing task, that is, the optimal allocation scheme between each computing task and the computing resources of the corresponding heterogeneous processing unit.

[0060] In this embodiment, first, based on the decomposition operation, exchange operation and synthesis operation of the molecular dynamics simulation, the allocation relationship between the computing tasks and the heterogeneous processing units is iteratively adjusted so that the allocation scheme of the computing tasks and the heterogeneous processing units gradually approaches the optimal one; secondly, the allocation scheme of the computing tasks and the heterogeneous processing units generated by the outer iteration is used as the input variable, and the computing resource allocation optimization objective function performs inner iterative calculation based on the input variable and the optimization objective, so that the allocation scheme between the computing tasks and the computing resources of the corresponding heterogeneous processing units gradually approaches the optimal one, so as to achieve the lowest comprehensive energy consumption.

[0061] In an exemplary embodiment, the task path length and task slack time of each computing task are calculated based on the computing resource allocation results corresponding to each computing task and the operating status of each heterogeneous processing unit, including steps S501 to S503.

[0062] Step S501, based on the scheduling order of each computing task in the corresponding computing resource allocation result, generate a task execution sequence corresponding to all computing tasks, and determine the resource dependency of each computing task in the task execution sequence based on the operating status of each heterogeneous processing unit.

[0063] Among them, the scheduling order represents the execution order of computing tasks on a multi-core heterogeneous ASIC computing motherboard; the task execution sequence represents the execution list of all computing tasks arranged in the scheduling order, which is used to provide a complete task execution timeline to fully reflect the execution order, parallel relationship and execution duration of each computing task in the entire computing process; the resource dependency relationship represents the dependency of a computing task on other computing tasks during the execution process, for example, the start of execution of one computing task depends on the completion of another computing task.

[0064] Exemplarily, based on the scheduling order of each computing task in the corresponding computing resource allocation result, a task execution sequence corresponding to all computing tasks is generated on the dimension of the time axis. Furthermore, in the task execution sequence, the data flow between each computing task is analyzed to determine the resource dependency of each computing task in the task execution sequence. That is, in the continuously arranged computing tasks in the task execution sequence, the correlation relationship between the input and output of a computing task and the input and output of the continuously arranged computing tasks is analyzed according to the operating state of the data transmission direction of each heterogeneous processing unit, thereby obtaining the resource dependency of the continuously arranged computing tasks in the task execution sequence.

[0065] Step S502 , based on the accumulated execution time of each computing task having a resource dependency relationship in the task execution sequence, obtain the task path length of each computing task.

[0066] The cumulative execution time refers to the total execution time accumulated by the computing task in the task execution sequence due to resource dependencies, including computing time, data transmission time, and scheduling delay.

[0067] Exemplarily, when calculating the task path length of each computing task, it is necessary to traverse the resource dependencies of each computing task in the task execution sequence to obtain the cumulative time of each computing task during the execution process, that is, the task path length, where: for independently executed computing tasks, their task path length is mainly determined by the computing time of the computing tasks, and for computing tasks with resource dependencies, their task path length includes not only their own computing time, but also the corresponding data transmission time and scheduling delay after the completion of the preceding task.

[0068] Step S503 , combining the task path lengths of the various computing tasks and the differences between the computing times of the corresponding heterogeneous processing units, to obtain the task slack time of the various computing tasks.

[0069] Among them, the computing time of the computing task in the corresponding heterogeneous processing unit refers to the time dedicated to computing the computing task on the corresponding heterogeneous processing unit, and does not include time parameters that do not involve computing processing, such as data transmission time and scheduling delay.

[0070] Exemplarily, based on the difference between the task path length of a computing task and the computing time of the computing task in the corresponding heterogeneous processing unit, the task slack time corresponding to the computing task is obtained, that is, in a computing task, the difference between its task path length and the computing time is calculated, and the difference is used as the task slack time corresponding to the computing task, which is equivalent to, the difference represents the waiting time of the computing task in the task execution sequence, involving the occupation of the computing resources of the corresponding heterogeneous processing unit, but not involving the specific computing processing process.

[0071] In this embodiment, firstly, in the constructed task execution sequence, by determining the resource dependencies of each computing task in the task execution sequence, the task path length of the computing task with resource dependencies in the task execution sequence can be efficiently obtained, thereby accurately evaluating the execution time of the computing task, and providing precise time parameters for optimizing task scheduling; secondly, combining the difference between the task path length of each computing task and the computing time in the corresponding heterogeneous processing unit, the task slack time of each computing task can be efficiently obtained, thereby improving the flexibility of task scheduling.

[0072] In an exemplary embodiment, in combination with the task path length and task slack time of each computing task, the electrical parameters of each heterogeneous processing unit are adjusted under the condition of satisfying the preset computing task deadline constraint to obtain adjusted heterogeneous processing units, including steps S601 to S604.

[0073] Step S601, based on the task path length and task slack time of each computing task and in combination with the deadline constraints of the computing tasks, multiple groups of time adjustment parameters corresponding to all computing tasks are determined.

[0074] Among them, multiple groups of time adjustment parameters represent multiple time adjustment schemes formulated based on the task path length, task slack time and deadline constraints of the computing tasks. Each time adjustment scheme is used to describe the computing time of all computing tasks after pre-adjustment within the allowable adjustment range of their computing time.

[0075] Exemplarily, based on the task path length and task slack time of each computing task, combined with the computing task deadline constraints corresponding to each computing task, the computing time of each computing task is adjusted, so that the computing times of all computing tasks obtained after pre-adjustment within the allowable adjustment range of their computing times are combined into a set of time adjustment parameters. As a result, the same computing task can correspond to different pre-adjusted computing times, so that the pre-adjusted computing times corresponding to different computing tasks are freely combined to obtain multiple sets of time adjustment parameters.

[0076] Step S602: Based on the multiple groups of time adjustment parameters and in combination with the computing load distribution characteristics of each heterogeneous processing unit, an electrical parameter adjustment strategy corresponding to each group of time adjustment parameters is obtained.

[0077] Among them, the computing load distribution characteristics of the heterogeneous processing units represent the computing load conditions when different computing tasks are executed on different heterogeneous processing units on a multi-core heterogeneous ASIC computing motherboard, such as the occupancy rate of the computing core, data throughput, and storage access conditions.

[0078] The electrical parameter adjustment strategy represents an electrical parameter adjustment scheme for the heterogeneous processing unit formulated based on a set of time adjustment parameters corresponding to all computing tasks and in combination with the computing load distribution characteristics and power consumption characteristics of the heterogeneous processing unit.

[0079] Exemplarily, in each group of time adjustment parameters, based on the pre-adjusted computing duration corresponding to each computing task, the computing load distribution characteristics such as the computing core occupancy rate, data throughput, and storage access of each computing task when executed on the corresponding heterogeneous processing unit based on the corresponding computing duration are further determined, thereby obtaining the electrical parameter adjustment strategy of the heterogeneous processing unit corresponding to various time adjustment parameters, that is, under the conditions corresponding to a certain group of time adjustment parameters, the electrical parameters of the heterogeneous processing unit are adaptively adjusted to make the computing performance of the heterogeneous processing unit compatible with the computing requirements of the computing task in the dimensions of computing duration and computing load. For example, for heterogeneous processing units with high computing load but long computing duration, it is possible to choose to appropriately reduce the operating voltage and operating frequency to reduce power consumption, while for heterogeneous processing units with low computing load but short computing duration, it is necessary to maintain a higher operating frequency to ensure computing performance.

[0080] Step S603 , performing energy consumption ratio simulation processing on each heterogeneous processing unit based on each electrical parameter adjustment strategy, and obtaining energy consumption ratio simulation results corresponding to each electrical parameter adjustment strategy.

[0081] Among them, the energy consumption ratio simulation results represent the ratio of the computing amount to the power consumption when each heterogeneous processing unit performs the corresponding computing task under different electrical parameter adjustment strategies, as well as the ratio of the comprehensive computing amount to the comprehensive power consumption when all heterogeneous processing units perform the corresponding computing tasks.

[0082] Exemplarily, in an electrical parameter adjustment strategy, the electrical parameters of each heterogeneous processing unit are pre-adjusted, and then the corresponding computing tasks are performed by the heterogeneous processing units after the pre-adjustment of the electrical parameters, and the computing amount and power consumption of each heterogeneous processing unit when performing the corresponding computing tasks are predicted, as well as the comprehensive computing amount and comprehensive power consumption of all heterogeneous processing units when performing the corresponding computing tasks, thereby combining the energy consumption ratio simulation results corresponding to the electrical parameter adjustment strategy.

[0083] Step S604, based on the energy consumption ratio simulation results corresponding to each electrical parameter adjustment strategy, a target electrical parameter adjustment strategy is screened out from each electrical parameter adjustment strategy, and the electrical parameters of each heterogeneous processing unit are adjusted based on the target electrical parameter adjustment strategy to obtain adjusted heterogeneous processing units.

[0084] Exemplarily, based on the optimal energy consumption ratio, the energy consumption ratio simulation results corresponding to each electrical parameter adjustment strategy are screened, so that the electrical parameter adjustment strategy corresponding to the optimal energy consumption ratio is used as the target electrical parameter adjustment strategy to ensure that the final electrical parameter adjustment scheme of the heterogeneous processing unit can achieve the optimal computing energy efficiency.

[0085] In the present embodiment, firstly, according to the task path length, task slack time and deadline constraints of the computing task, multiple groups of time adjustment parameters are determined, so as to provide more optimization adjustment space for the computing time of the computing task; secondly, according to the multiple groups of time adjustment parameters and in combination with the computing load distribution characteristics of the heterogeneous processing units, different electrical parameter adjustment strategies are formulated, so as to ensure that the electrical parameter adjustment scheme of the heterogeneous processing units is effectively determined at the level of computing time and computing load; thirdly, according to different electrical parameter adjustment strategies, energy consumption ratio simulation processing is performed on the heterogeneous processing units to obtain energy consumption ratio simulation results corresponding to each electrical parameter adjustment strategy, so as to effectively quantify the actual energy efficiency of different electrical parameter adjustment strategies; thirdly, based on the energy consumption ratio simulation results corresponding to each electrical parameter adjustment strategy, the optimal electrical parameter adjustment strategy is screened and applied to each heterogeneous processing unit, so as to effectively realize the parameter configuration optimization of the heterogeneous processing units.

[0086] In an exemplary embodiment, energy consumption ratio simulation processing is performed on each heterogeneous processing unit based on each electrical parameter adjustment strategy to obtain energy consumption ratio simulation results corresponding to each electrical parameter adjustment strategy, including steps S701 to S704.

[0087] Step S701 : based on the corresponding electrical parameters in each electrical parameter adjustment strategy and in combination with the computing resource allocation results corresponding to each computing task, the dynamic power consumption simulation results corresponding to each electrical parameter adjustment strategy are calculated.

[0088] The dynamic power consumption simulation result refers to the simulation result obtained by dynamic power consumption calculation based on the electrical parameter adjustment strategy, which reflects the power consumption change caused by electrical parameters such as voltage and frequency when the heterogeneous processing unit performs computing tasks.

[0089] Exemplarily, in the computing resource allocation results corresponding to each computing task, the allocation relationship between the computing task and the heterogeneous processing unit is determined, as is the allocation relationship between the computing task and the computing resources of the corresponding heterogeneous computing unit. Furthermore, in an electrical parameter adjustment strategy, based on the heterogeneous processing unit after electrical parameter pre-adjustment and the computing resources of the heterogeneous processing unit allocated for the computing task, the dynamic power consumption of the heterogeneous processing unit when executing the corresponding computing task is simulated and calculated, and correspondingly, the comprehensive dynamic power consumption of all heterogeneous processing units when executing the corresponding computing task is simulated and calculated. Thus, based on the dynamic power consumption of each heterogeneous processing unit and the comprehensive dynamic power consumption of all heterogeneous processing units, the dynamic power consumption simulation result corresponding to the electrical parameter adjustment strategy is obtained.

[0090] Step S702 , combining the corresponding electrical parameters in each electrical parameter adjustment strategy and the physical characteristics of each heterogeneous processing unit, calculate and obtain the static power consumption simulation result corresponding to each electrical parameter adjustment strategy.

[0091] The physical characteristics of the heterogeneous processing unit refer to the hardware characteristics of the heterogeneous processing unit, such as process technology, storage architecture, low power management mechanism and other parameters.

[0092] The static power consumption simulation result refers to the simulation result obtained by calculating the static power consumption based on the electrical parameter adjustment strategy, which reflects the leakage power consumption and standby power consumption of the heterogeneous processing unit in a low-load state or an idle state.

[0093] Exemplarily, in an electrical parameter adjustment strategy, based on a heterogeneous processing unit after pre-adjustment of electrical parameters, the static power consumption generated by the heterogeneous processing unit based on the corresponding physical characteristics is simulated and calculated, and correspondingly, the comprehensive static power consumption generated by all heterogeneous processing units based on the corresponding physical characteristics is simulated and calculated. Thus, based on the static power consumption of each heterogeneous processing unit and the comprehensive static power consumption of all heterogeneous processing units, the static power consumption simulation result corresponding to the electrical parameter adjustment strategy is obtained in combination.

[0094] Step S703 , based on the dynamic power consumption simulation results and the static power consumption simulation results of each electrical parameter adjustment strategy, the total power consumption simulation results of each electrical parameter adjustment strategy are calculated.

[0095] The total power consumption simulation result indicates a total power consumption evaluation value calculated by combining the dynamic power consumption simulation result and the static power consumption simulation result under a certain electrical parameter adjustment strategy.

[0096] For example, in an electrical parameter adjustment strategy, the total power consumption simulation result may represent the independent total power consumption of dynamic power consumption and static power consumption corresponding to a single heterogeneous processing unit, or the comprehensive total power consumption of comprehensive dynamic power consumption and comprehensive static power consumption corresponding to all heterogeneous processing units.

[0097] Step S704 , combining the total power consumption simulation results and the calculation amount of each electrical parameter adjustment strategy to obtain the energy consumption ratio simulation results of each electrical parameter adjustment strategy.

[0098] Exemplarily, in an electrical parameter adjustment strategy, for a single heterogeneous processing unit, an independent energy consumption ratio simulation result of the heterogeneous processing unit is obtained based on the ratio of the computing amount of the heterogeneous processing unit to the independent total power consumption; for all heterogeneous processing units, a comprehensive energy consumption ratio simulation result of all heterogeneous processing units is obtained based on the ratio of the computing amount of all heterogeneous processing units to the comprehensive total power consumption; the independent energy consumption ratio simulation results of each heterogeneous processing unit and the comprehensive energy consumption ratio simulation results of all heterogeneous processing units are used as the energy consumption ratio simulation results of the electrical parameter adjustment strategy.

[0099] In this embodiment, first, the dynamic power consumption simulation results of each electrical parameter adjustment strategy are calculated in combination with the electrical parameters of each electrical parameter adjustment strategy and the resource allocation results of the computing task, so as to quantify the impact of different electrical parameter adjustments on the dynamic power consumption during the execution of the computing task; secondly, the static power consumption simulation results corresponding to each electrical parameter adjustment strategy are calculated in combination with the electrical parameters of each electrical parameter adjustment strategy and the physical characteristics of the heterogeneous processing unit, so as to accurately evaluate the energy consumption characteristics of the heterogeneous processing unit under low load or idle state; thirdly, the total power consumption simulation results of each electrical parameter adjustment strategy are calculated based on the dynamic power consumption simulation results and the static power consumption simulation results, and then the total power consumption simulation results of each electrical parameter adjustment strategy are combined with the calculation amount to obtain the energy consumption ratio simulation results of each electrical parameter adjustment strategy, so as to effectively quantify the relationship between the calculation amount and power consumption of different electrical parameter adjustment strategies, and screen out the electrical parameter adjustment scheme with the highest energy efficiency.

[0100] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0101] Based on the same inventive concept, the embodiment of the present application also provides a power consumption optimization device for a multi-core heterogeneous ASIC computing motherboard for implementing the power consumption optimization method for a multi-core heterogeneous ASIC computing motherboard involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in the embodiments of the power consumption optimization device for one or more multi-core heterogeneous ASIC computing motherboards provided below can refer to the limitations of the power consumption optimization method for a multi-core heterogeneous ASIC computing motherboard above, and will not be repeated here.

[0102] In an exemplary embodiment, Figure 2 As shown, a power consumption optimization device for a multi-core heterogeneous ASIC computing motherboard is provided, including: an allocation module 201, a time analysis module 202 and an adjustment module 203, wherein: The allocation module 201 is used to determine each computing task corresponding to the preset multi-core heterogeneous ASIC computing motherboard, and perform computing resource allocation processing on each computing task in a preset chemical reaction optimization algorithm in combination with task attribute information of each computing task and heterogeneous attribute information of each heterogeneous processing unit in the multi-core heterogeneous ASIC computing motherboard, to obtain computing resource allocation results corresponding to each computing task; The time analysis module 202 is used to calculate the task path length and task slack time of each computing task by combining the computing resource allocation results corresponding to each computing task and the operation status of each heterogeneous processing unit; The adjustment module 203 is used to adjust the electrical parameters of each heterogeneous processing unit in combination with the task path length and task relaxation time of each computing task, under the condition of satisfying the preset computing task deadline constraint, to obtain each adjusted heterogeneous processing unit, and the adjusted heterogeneous processing unit is used to execute each computing task of the multi-core heterogeneous ASIC computing motherboard according to the optimal energy consumption ratio.

[0103] In an exemplary embodiment, the allocation module 201 is also used to: perform feature extraction processing on the task attribute information of each computing task to generate a task attribute matrix, perform feature extraction processing on the heterogeneous attribute information of each heterogeneous processing unit to generate a processing unit attribute matrix; combine the task attribute matrix with the processing unit attribute matrix to construct and process the energy consumption of the multi-core heterogeneous ASIC computing motherboard during the task scheduling process to obtain a resource allocation optimization objective function; in the chemical reaction optimization algorithm, combine the operational behavior of the molecular dynamics simulation and the resource allocation optimization objective function, and obtain the computing resource allocation results corresponding to each computing task by performing computing resource allocation processing on each computing task.

[0104] In an exemplary embodiment, the allocation module 201 is also used to: calculate the fitness between the task attribute matrix and the processing unit attribute matrix to generate a task resource fitness matrix, which represents the fitness between the computing load of each computing task and the computing performance of each heterogeneous processing unit in matrix form; based on the task resource fitness matrix, calculate the energy consumption of each computing task executed on each heterogeneous processing unit to obtain the energy consumption constraint conditions of each computing task executed on each heterogeneous processing unit; combine the energy consumption constraint conditions of each computing task executed on each heterogeneous processing unit and minimize the comprehensive energy consumption of all computing tasks to obtain the resource allocation optimization objective function.

[0105] In an exemplary embodiment, the allocation module 201 is also used for: in a chemical reaction optimization algorithm, iteratively adjusting the allocation relationship between each computing task and each heterogeneous processing unit based on the decomposition operation, exchange operation and synthesis operation of the molecular dynamics simulation, and using the iteratively adjusted allocation relationship as the input variable of the resource allocation optimization objective function in different outer iteration rounds; calculating the function value of the inner iteration output corresponding to the input variables of different outer iteration rounds of the resource allocation optimization objective function, until obtaining multiple objective function values ​​corresponding to the optimization goal that meets the resource allocation optimization objective function, and using the multiple objective function values ​​as the computing resource allocation results corresponding to each computing task.

[0106] In an exemplary embodiment, the time analysis module 202 is also used to: generate a task execution sequence corresponding to all computing tasks based on the scheduling order of each computing task in the corresponding computing resource allocation result, and determine the resource dependency of each computing task in the task execution sequence based on the operating status of each heterogeneous processing unit; obtain the task path length of each computing task based on the cumulative execution time of each computing task with resource dependencies in the task execution sequence; and obtain the task slack time of each computing task by combining the task path length of each computing task and the difference between the computing time in the corresponding heterogeneous processing unit.

[0107] In an exemplary embodiment, the adjustment module 203 is also used to: determine multiple groups of time adjustment parameters corresponding to all computing tasks based on the task path length and task slack time of each computing task, combined with the deadline constraints of the computing tasks; based on the multiple groups of time adjustment parameters, combined with the computing load distribution characteristics of each heterogeneous processing unit, obtain the electrical parameter adjustment strategies corresponding to each group of time adjustment parameters; based on each electrical parameter adjustment strategy, perform energy consumption ratio simulation processing on each heterogeneous processing unit to obtain the energy consumption ratio simulation results corresponding to each electrical parameter adjustment strategy; based on the energy consumption ratio simulation results corresponding to each electrical parameter adjustment strategy, screen out the target electrical parameter adjustment strategy from each electrical parameter adjustment strategy, and adjust the electrical parameters of each heterogeneous processing unit based on the target electrical parameter adjustment strategy to obtain each adjusted heterogeneous processing unit.

[0108] In an exemplary embodiment, the adjustment module 203 is also used to: calculate the dynamic power consumption simulation results corresponding to each electrical parameter adjustment strategy based on the corresponding electrical parameters in each electrical parameter adjustment strategy and the computing resource allocation results corresponding to each computing task; calculate the static power consumption simulation results corresponding to each electrical parameter adjustment strategy in combination with the corresponding electrical parameters in each electrical parameter adjustment strategy and the physical characteristics of each heterogeneous processing unit; calculate the total power consumption simulation results of each electrical parameter adjustment strategy based on the dynamic power consumption simulation results and the static power consumption simulation results of each electrical parameter adjustment strategy; and obtain the energy consumption ratio simulation results of each electrical parameter adjustment strategy in combination with the total power consumption simulation results and the calculation amount of each electrical parameter adjustment strategy.

[0109] Each module in the power consumption optimization device of the multi-core heterogeneous ASIC computing motherboard can be implemented in whole or in part by software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module.

[0110] In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in any of the above embodiments when executing the computer program.

[0111] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in any of the above embodiments are implemented.

[0112] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0113] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0114] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A method for optimizing power consumption of a multi-core heterogeneous ASIC computing motherboard, characterized in that: The method comprises: Determine each computing task corresponding to the preset multi-core heterogeneous ASIC computing motherboard, combine the task attribute information of each computing task and the heterogeneous attribute information of each heterogeneous processing unit in the multi-core heterogeneous ASIC computing motherboard, perform computing resource allocation processing on each computing task in a preset chemical reaction optimization algorithm, and obtain the computing resource allocation result corresponding to each computing task; Combined with the computing resource allocation results corresponding to each computing task and the operating status of each heterogeneous processing unit, the task path length and task relaxation time of each computing task are calculated; In combination with the task path length and task slack time of each computing task, and under the condition of satisfying the preset computing task deadline constraint, the electrical parameters of each heterogeneous processing unit are adjusted to obtain each adjusted heterogeneous processing unit, and the each adjusted heterogeneous processing unit is used to execute each computing task of the multi-core heterogeneous ASIC computing motherboard according to the optimal energy consumption ratio.

2. The method according to claim 1, characterized in that: The task attribute information of each computing task and the heterogeneous attribute information of each heterogeneous processing unit in the multi-core heterogeneous ASIC computing mainboard are combined to perform computing resource allocation processing on each computing task in a preset chemical reaction optimization algorithm to obtain computing resource allocation results corresponding to each computing task, including: Perform feature extraction processing on the task attribute information of each computing task to generate a task attribute matrix, perform feature extraction processing on the heterogeneous attribute information of each heterogeneous processing unit to generate a processing unit attribute matrix; Combining the task attribute matrix with the processing unit attribute matrix, constructing and processing the energy consumption of the multi-core heterogeneous ASIC computing motherboard during the task scheduling process to obtain a resource allocation optimization objective function; In the chemical reaction optimization algorithm, the operation behavior of the molecular dynamics simulation and the resource allocation optimization objective function are combined, and the computing resource allocation processing is performed on each computing task to obtain the computing resource allocation result corresponding to each computing task.

3. The method according to claim 2, characterized in that The combining of the task attribute matrix and the processing unit attribute matrix to construct and process the energy consumption of the multi-core heterogeneous ASIC computing motherboard during the task scheduling process to obtain a resource allocation optimization objective function includes: Calculating the degree of fit between the task attribute matrix and the processing unit attribute matrix to generate a task resource fit matrix, wherein the task resource fit matrix represents the degree of fit between the computing load of each computing task and the computing performance of each heterogeneous processing unit in a matrix form; Based on the task resource adaptation matrix, the energy consumption of each computing task executed on each heterogeneous processing unit is calculated and processed to obtain the energy consumption constraint condition of each computing task executed on each heterogeneous processing unit; The resource allocation optimization objective function is obtained by combining the energy consumption constraints of each computing task executed on each heterogeneous processing unit and minimizing the comprehensive energy consumption of all computing tasks.

4. The method according to claim 2, characterized in that: In the chemical reaction optimization algorithm, the operation behavior of the molecular dynamics simulation and the resource allocation optimization objective function are combined to obtain the computing resource allocation results corresponding to each computing task by performing computing resource allocation processing on each computing task, including: In the chemical reaction optimization algorithm, based on the decomposition operation, exchange operation and synthesis operation of the molecular dynamics simulation, the allocation relationship between each computing task and each heterogeneous processing unit is iteratively adjusted, and the iteratively adjusted allocation relationship is used as the input variable of the resource allocation optimization objective function in different outer iteration rounds; Calculate the function values ​​of the inner iterative outputs corresponding to the input variables of different outer iterative rounds of the resource allocation optimization objective function, until multiple objective function values ​​corresponding to the optimization objectives that satisfy the resource allocation optimization objective function are obtained, and use the multiple objective function values ​​as the computing resource allocation results corresponding to each computing task.

5. The method according to claim 1, characterized in that The step of calculating the task path length and task relaxation time of each computing task by combining the computing resource allocation results corresponding to each computing task and the operating status of each heterogeneous processing unit includes: Generate a task execution sequence corresponding to all computing tasks based on the scheduling order of each computing task in the corresponding computing resource allocation result, and determine the resource dependency relationship of each computing task in the task execution sequence based on the running status of each heterogeneous processing unit; Obtaining the task path length of each computing task based on the accumulated execution time of each computing task having a resource dependency relationship in the task execution sequence; The task slack time of each computing task is obtained by combining the task path length of each computing task and the difference between the computing times of the corresponding heterogeneous processing units.

6. The method according to claim 1, characterized in that The step of adjusting the electrical parameters of each heterogeneous processing unit based on the task path length and task slack time of each computing task and satisfying the preset computing task deadline constraint to obtain each adjusted heterogeneous processing unit includes: Based on the task path length and task slack time of each computing task and in combination with the deadline constraints of the computing tasks, determine multiple groups of time adjustment parameters corresponding to all computing tasks; Based on the multiple groups of time adjustment parameters and in combination with the computing load distribution characteristics of each heterogeneous processing unit, an electrical parameter adjustment strategy corresponding to each group of time adjustment parameters is obtained; Based on each electrical parameter adjustment strategy, energy consumption ratio simulation processing is performed on each heterogeneous processing unit to obtain energy consumption ratio simulation results corresponding to each electrical parameter adjustment strategy; Based on the energy consumption ratio simulation results corresponding to each electrical parameter adjustment strategy, a target electrical parameter adjustment strategy is screened out from each electrical parameter adjustment strategy, and the electrical parameters of each heterogeneous processing unit are adjusted based on the target electrical parameter adjustment strategy to obtain adjusted heterogeneous processing units.

7. The method according to claim 6, characterized in that The energy consumption ratio simulation processing is performed on each heterogeneous processing unit based on each electrical parameter adjustment strategy to obtain the energy consumption ratio simulation results corresponding to each electrical parameter adjustment strategy, including: Based on the corresponding electrical parameters in each electrical parameter adjustment strategy and in combination with the computing resource allocation results corresponding to each computing task, the dynamic power consumption simulation results corresponding to each electrical parameter adjustment strategy are calculated; Combining the corresponding electrical parameters in each electrical parameter adjustment strategy and the physical characteristics of each heterogeneous processing unit, the static power consumption simulation result corresponding to each electrical parameter adjustment strategy is calculated; Based on the dynamic power consumption simulation results and the static power consumption simulation results of each electrical parameter adjustment strategy, the total power consumption simulation results of each electrical parameter adjustment strategy are calculated; The total power consumption simulation results and the calculation amount of each electrical parameter adjustment strategy are combined to obtain the energy consumption ratio simulation results of each electrical parameter adjustment strategy.

8. A power consumption optimization device for a multi-core heterogeneous ASIC computing motherboard, characterized in that: The device comprises: An allocation module is used to determine each computing task corresponding to a preset multi-core heterogeneous ASIC computing mainboard, and perform computing resource allocation processing on each computing task in a preset chemical reaction optimization algorithm in combination with task attribute information of each computing task and heterogeneous attribute information of each heterogeneous processing unit in the multi-core heterogeneous ASIC computing mainboard, to obtain computing resource allocation results corresponding to each computing task; The time analysis module is used to calculate the task path length and task slack time of each computing task by combining the computing resource allocation results corresponding to each computing task and the operating status of each heterogeneous processing unit; The adjustment module is used to adjust the electrical parameters of each heterogeneous processing unit in combination with the task path length and task slack time of each computing task, under the condition of satisfying the preset computing task deadline constraint, to obtain each adjusted heterogeneous processing unit, and the each adjusted heterogeneous processing unit is used to execute each computing task of the multi-core heterogeneous ASIC computing motherboard according to the optimal energy consumption ratio.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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