A digital in-memory computing chip based on dynamic logic calculation

Abstract

This application discloses a digital in-memory computing chip based on dynamic logic computation, comprising a multiplier circuit and / or a half-adder circuit and / or a first full adder circuit and / or a second full adder circuit, including: a primary circuit and a secondary circuit, including pull-up networks and / or pull-down networks, for implementing basic logic computation; the primary circuit is started by a primary clock signal; the secondary circuit is started by a secondary clock signal; charging transistors and discharging transistors; the pull-up network and pull-down network are switched on and off according to the primary or secondary clock signal to control the computation and output the computation result of the primary circuit to the secondary circuit for logic computation. The multiply-add unit designed in this application uses a significantly reduced number of transistors, improving key performance indicators such as latency and power consumption, and solving the problems of excessive power consumption and area occupation in the process of deploying digital in-memory computing chips for large AI models.

Description

Technical Field

[0001] This application belongs to the field of integrated circuit technology, specifically relating to a digital in-memory computing chip based on dynamic logic calculation. Background Technology

[0002] Currently, in-memory computing chips significantly reduce data movement in traditional von Neumann architectures by integrating digital logic computing units within the storage array, solving problems such as high latency and high power consumption. However, the computing unit, as the core of data processing, still suffers from excessive area overhead and high computational latency, which is detrimental to the miniaturization and low-power design of edge AI chips. The computing unit of an in-memory computing chip mainly refers to the addition tree structure composed of multipliers, half-adders, and full adders (hereinafter collectively referred to as multiply-add units).

[0003] Currently, the widely used multiply-accumulate units are circuits based on static complementary CMOS design, mainly composed of two parts: a pull-up network (PUN) and a pull-down network (PDN). The pull-up network consists of p-type MOSFETs and is the path between the output and the high level, while the pull-down network consists of n-type MOSFETs and is the path between the output and the power supply and ground. Both can perform logic judgment functions, and the circuit structure can be complementary or mirrored. Multiply-accumulate units designed with static complementary CMOS have high noise margins, stable structures, and good output signal quality. The drawback is that it has high requirements for the number of transistors and high area overhead. Because the circuit structure under static complementary CMOS design consists of two parts, it means that any circuit unit with n inputs will consume 2n transistors. In a full adder, a standard static complementary full adder unit will consist of 28 transistors, which will greatly increase the area overhead. Especially in AI chips such as digital in-memory computing chips, the addition tree of traditional static complementary CMOS design will occupy more than 70% of the entire chip area, which is too costly.

[0004] A multiply-accumulate unit design scheme based on transfer transistor logic exists in academia, which can significantly reduce the number of transistors and area overhead in the multiply-accumulate unit. The special feature of transfer transistor logic lies in the fact that its inputs differ from traditional static logic, which only uses them to drive the gate. In fact, in transfer transistor logic, the inputs can drive any two of the transistor's gate, source, and drain terminals, and the output is obtained from the remaining third terminal. Although this introduces some transmission losses, it greatly reduces the number of transistors used. For example, a full adder based on the transfer transistor design uses only 16 transistors.

[0005] However, its multi-layer cascading performance and signal transmission quality are relatively poor. This is because in transmission transistor logic, when a signal is input from the source and output from the drain, there is a threshold voltage drop. Therefore, when using transmission transistor logic for multi-layer cascading, level restorers need to be inserted between each layer. This means that in practical applications, the transmission transistor logic design scheme cannot fully utilize its area advantage. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this application proposes a digital in-memory computing chip based on dynamic logic computation, comprising a multiplier circuit and / or a half-adder circuit and / or a first full adder circuit and / or a second full adder circuit, including:

[0007] The primary and secondary circuits, including pull-up and / or pull-down networks, are used to implement basic logic calculations; the primary circuit is started by the primary clock signal; the secondary circuit is started by the secondary clock signal.

[0008] Charging transistors and discharging transistors; switched on and off according to a primary clock signal or a secondary clock signal, used to implement the calculation control of pull-up or pull-down networks and output the calculation results of the primary circuit to the secondary circuit for logic calculation.

[0009] Optionally, the pull-down network includes: a first logical AND pull-down network, a second logical AND pull-down network, a first logical OR pull-down network, a second logical OR pull-down network, and a third logical OR pull-down network;

[0010] The first logic AND pull-down network, the first logic OR pull-down network, and the third logic OR pull-down network each include two NMOS transistors, with the gates of the two NMOS transistors connected to signals A and B, respectively. The second logic AND pull-down network and the second logic OR pull-down network each include three NMOS transistors, with the gates of the three NMOS transistors connected to signals A, B, and C, respectively. i Signal.

[0011] Optionally, the charging transistor is a PMOS transistor, including a first charging PMOS transistor, a second charging PMOS transistor, a third charging PMOS transistor, and a fourth charging PMOS transistor; the discharging transistor is an NMOS transistor, including a first discharging NMOS transistor, a second discharging NMOS transistor, and a third discharging NMOS transistor.

[0012] Optionally, the first stage circuit of the first full adder circuit includes: a first NMOS transistor, a first logic AND pull-down network, a first logic OR pull-down network, a first charging PMOS transistor, a second charging PMOS transistor, and a first discharging NMOS transistor; the second stage circuit includes: a second NMOS transistor, a second logic AND pull-down network, a second logic OR pull-down network, a third charging PMOS transistor, a fourth charging PMOS transistor, and a second discharging NMOS transistor.

[0013] The source of the first charging PMOS transistor is connected to the power supply voltage, the gate is connected to a primary clock signal, and the drain is connected to the drain of the first NOMS transistor. The gate of the first NOMS transistor is connected to C. i The signal is as follows: the source of the first NMOS transistor is connected to the drain of the first discharge NMOS transistor, the gate of the first discharge NMOS transistor is connected to a clock signal, and the source of the first discharge NMOS transistor is grounded.

[0014] The source of the second charging PMOS transistor is connected to the power supply voltage, the gate is connected to a first-level clock signal, and the drain is connected to the input of the first logic OR pull-down network, the input of the first logic AND pull-down network, and the gate of the second NMOS transistor. The output of the first logic OR pull-down network is connected to the drain of the first charging PMOS transistor and the drain of the first NMOS transistor. The output of the first logic AND pull-down network is connected to the drain of the first discharging NMOS transistor and the source of the second discharging NMOS transistor.

[0015] The source of the third charging PMOS transistor is connected to the power supply voltage, the gate is connected to the secondary clock signal, and the drain is connected to the input of the second logic OR pull-down network and the input of the second logic AND pull-down network, respectively. The output of the second logic OR pull-down network is connected to the drain of the second NMOS transistor and the drain of the fourth charging PMOS transistor, respectively. The gate of the fourth charging PMOS transistor is connected to the secondary clock signal, and the source is connected to the power supply voltage.

[0016] The output of the second logic and pull-down network and the source of the second NMOS transistor are respectively connected to the drain of the second discharge NMOS transistor, and the gate of the second discharge NMOS transistor is connected to the second-level clock signal.

[0017] Optionally, the delay time between the secondary clock signal and the primary clock signal is greater than the startup and operation time of the primary circuit.

[0018] Optionally, the first-stage circuit of the multiplier circuit includes: a first logic AND pull-down network, a first logic OR pull-down network, a first charging PMOS transistor, a second charging PMOS transistor, a first discharging NMOS transistor, and a second discharging NMOS transistor; the second-stage circuit includes: a second charging PMOS transistor, a third logic OR pull-down network, and a third discharging NMOS transistor.

[0019] The source of the first charging PMOS transistor is connected to the power supply voltage, the gate is connected to the first-level clock signal, and the drain is connected to the input of the first logic and pull-down network. At the same time, it is inverted by an inverter and connected to the gate of an NMOS transistor in the third logic or pull-down network. The output of the first logic and pull-down network is connected to the drain of the first discharging NMOS transistor. The gate of the first discharging NMOS transistor is connected to the first-level clock signal, and the source of the first discharging NMOS transistor is grounded.

[0020] The source of the second charging PMOS transistor is connected to the power supply voltage, the gate is connected to the first-level clock signal, and the drain is connected to the input of the first logic or pull-down network, and is also connected to the gate of another NMOS transistor in the third logic or pull-down network; the output of the first logic or pull-down network is connected to the drain of the second discharging NMOS transistor, the gate of the second discharging NMOS transistor is connected to the first-level clock signal, and the source of the second discharging NMOS transistor is grounded.

[0021] The source of the third charging PMOS transistor is connected to the power supply voltage, the gate is connected to the secondary clock signal, the drain is connected to the input of the third logic OR pull-down network, the output of the third logic OR pull-down network is connected to the drain of the third discharging NMOS transistor, the gate of the third discharging NMOS transistor is connected to the secondary clock signal, and the source of the third discharging NMOS transistor is grounded.

[0022] Optionally, the first-stage circuit of the half-adder circuit includes: a first logic AND pull-down network, a first charging PMOS transistor, a second charging PMOS transistor, a fourth charging PMOS transistor, and a first discharging NMOS transistor; the second-stage circuit includes: a first NMOS transistor, a first logic OR pull-down network, a third charging PMOS transistor, and a second discharging NMOS transistor.

[0023] The sources of the first, second, third, and fourth charging PMOS transistors are connected to the power supply voltage. The gates of the first, second, and fourth charging PMOS transistors are connected to a first-level clock signal, and the gate of the third charging PMOS transistor is connected to a second-level clock signal. The drain of the first charging PMOS transistor is connected to the midpoint of the two series-connected NMOS transistors in the first logic and pull-down network. The drain of the second charging PMOS transistor is connected to the input of the first logic and pull-down network and the gate of the first NMOS transistor. The output of the first logic and pull-down network is connected to the drain of the first discharging NMOS transistor and the source of the second discharging NMOS transistor. The gate of the first discharging NMOS transistor is connected to the first-level clock signal, and its source is grounded. The gate of the second discharging NMOS transistor is connected to the second-level clock signal, and its drain is connected to the source of the first NMOS transistor. The drain of the first NMOS transistor is connected to the output of the first logic or pull-down network and the drain of the fourth charging PMOS transistor. The input of the first logic or pull-down network is connected to the drain of the third charging PMOS transistor.

[0024] Optionally, the first-stage circuit of the second full adder circuit includes: a first logic AND pull-down network, a first logic OR pull-down network, a first NMOS transistor, a first charging PMOS transistor, and a first discharging NMOS transistor; the second-stage circuit includes: a second logic AND pull-down network, a second logic OR pull-down network, a second NMOS transistor, a second charging PMOS transistor, and a second discharging NMOS transistor;

[0025] The outputs of the first logic AND pull-down network, the second logic AND pull-down network, the first logic OR pull-down network, and the second logic OR pull-down network are respectively connected to the drains of the first discharge NMOS transistor and the second NMOS transistor. The sources of the first discharge NMOS transistor and the second NMOS transistor are respectively grounded. The gates of the first discharge NMOS transistor and the second NMOS transistor are respectively connected to the clock signal. The input of the first logic NOT pull-down network is connected to the source of the first NMOS transistor, and the gate of the first NMOS transistor is connected to C. i The signal is generated as follows: the drain of the first NMOS transistor is connected to the drain of the first charging PMOS transistor, the input of the first logic AND pull-down network, and the gate of the second NMOS transistor. The gates of the first and second charging PMOS transistors are connected to the clock signal, and the sources of the first and second charging PMOS transistors are connected to the power supply voltage. The drain of the second NMOS transistor is connected to the drain of the second charging PMOS transistor, and the input of the second logic AND pull-down network is connected to the drain of the second charging PMOS transistor. The source of the second NMOS transistor is connected to the input of the second logic OR pull-down network, and the output of the second logic OR pull-down network is connected to the drain of the second discharging NMOS transistor. The gate of the second discharging NMOS transistor is connected to the clock signal, and the source of the second discharging NMOS transistor is grounded. The input of the second logic OR pull-down network outputs the calculation result signal.

[0026] Optionally, the first-stage circuit of the pull-up logic half-adder circuit includes: a first logic NAND pull-up network, a first charging PMOS transistor, a first discharging NMOS transistor, and a second discharging NMOS transistor; the second-stage circuit includes: a first logic OR pull-up network, a second charging PMOS transistor, a third discharging NMOS transistor, and a fourth discharging NMOS transistor.

[0027] The drains of the first, second, third, and fourth discharge NMOS transistors are grounded; the gates of the first, first, second, and fourth discharge NMOS transistors are connected to a first-level clock signal, and the gates of the second-level charging PMOS transistor and the third discharge NMOS transistor are connected to a second-level clock signal; the source of the first discharge NMOS transistor is connected to the midpoint of the two series-connected PMOS transistors in the first logic and non-pull-up network, and the source of the second discharge NMOS transistor is connected to both the first logic and non-pull-up network. The input terminal of the network is connected to the gate of the first PMOS transistor. The output terminal of the first logic AND non-pull-up network is connected to the drain of the first charging PMOS transistor and the source of the second charging PMOS transistor, respectively. The gate of the first charging PMOS transistor is connected to a first-level clock signal, and the source is grounded. The gate of the second charging PMOS transistor is connected to a second-level clock signal, and the drain is connected to the source of the first PMOS transistor. The drain of the first NMOS transistor is connected to the output terminal of the first logic OR non-pull-up network and the source of the fourth discharging NMOS transistor, respectively. The input terminal of the first logic OR non-pull-up network is connected to the source of the third discharging NMOS transistor.

[0028] Optionally, the first-stage circuit of the pull-up logic multiplier circuit includes: a first logic NOR pull-up network, a first logic AND pull-up network, a first charging PMOS transistor, a second charging PMOS transistor, a first discharging NMOS transistor, and a second discharging NMOS transistor; the second-stage circuit includes: a third charging PMOS transistor, a third logic AND pull-up network, and a third discharging NMOS transistor.

[0029] The source of the first charging PMOS transistor is connected to the power supply voltage, the gate is connected to a first-level clock signal, and the drain is connected to the input of the first logic or non-pull-up network. At the same time, it is inverted by an inverter and connected to the gate of a PMOS transistor in the third logic or non-pull-up network. The output of the first logic or non-pull-up network is connected to the drain of the first discharging NMOS transistor. The gate of the first discharging NMOS transistor is connected to a first-level clock signal, and the source of the first discharging NMOS transistor is grounded.

[0030] The source of the second charging PMOS transistor is connected to the power supply voltage, the gate is connected to the first-level clock signal, and the drain is connected to the input of the first logic AND non-pull-up network, and is also connected to the gate of another PMOS transistor in the third logic AND non-pull-up network; the output of the first logic AND non-pull-up network is connected to the drain of the second discharging NMOS transistor, the gate of the second discharging NMOS transistor is connected to the first-level clock signal, and the source of the second discharging NMOS transistor is grounded.

[0031] The source of the third charging PMOS transistor is connected to the power supply voltage, the gate is connected to the secondary clock signal, and the drain is connected to the input of the third logic AND pull-up network. The output of the third logic AND pull-up network is connected to the drain of the third discharging NMOS transistor. The gate of the third discharging NMOS transistor is connected to the secondary clock signal, and the source of the third discharging NMOS transistor is grounded.

[0032] Optionally, the first-stage circuit of the pull-up logic full adder circuit includes: a first logic NOR pull-up network, a first logic AND pull-up network, a first PMOS transistor, a first charging PMOS transistor, a first discharging NMOS transistor, and a second discharging NMOS transistor; the second-stage circuit includes: a second logic NOR pull-up network, a second logic AND pull-up network, a second PMOS transistor, a second charging PMOS transistor, a third discharging NMOS transistor, and a fourth discharging NMOS transistor.

[0033] The gates of the first logic NOR pull-up network, the first logic AND pull-up network, and the second PMOS transistor are connected to the drain of the second discharge NMOS transistor; the outputs of the second logic NOR pull-up network and the second logic AND pull-up network are connected to the drain of the third discharge NMOS transistor; the sources of the second and third discharge NMOS transistors are grounded, and the gates of the second and third discharge NMOS transistors are connected to the first and second stage clock signals, respectively; the input of the first logic NOR pull-up network is connected to the drain of the first PMOS transistor, and the gate of the first PMOS transistor is connected to C. i The signal is generated as follows: the source of the first PMOS transistor is connected to the drain of the first charging PMOS transistor, the input of the first logic AND-NOT pull-up network, and the source of the second charging PMOS transistor. The gates of the first and second charging PMOS transistors are connected to the first and second level clock signals, respectively. The source of the first charging PMOS transistor is connected to the power supply voltage. The source of the second PMOS transistor and the input of the second logic AND-NOT pull-up network are connected to the drain of the second charging PMOS transistor. The drain of the second PMOS transistor is connected to the input of the second logic OR-NOT pull-up network. The output of the second logic OR-NOT pull-up network is connected to the drain of the second discharging NMOS transistor. The drain of the first discharging NMOS transistor is connected to the intermediate connection between the first logic OR-NOT pull-up network and the first PMOS transistor. The source of the first discharging NMOS transistor is grounded. The drain of the fourth discharging NMOS transistor is connected to the intermediate connection between the second logic OR-NOT pull-up network and the second PMOS transistor. The source of the fourth discharging NMOS transistor is grounded. The output of the second logic OR-NOT pull-up network outputs the calculation result signal.

[0034] The beneficial effects of the technical solutions provided in some embodiments of this application include at least the following:

[0035] 1. While ensuring computational accuracy and output signal margin, the number of transistors required for the multiply-accumulate unit is reduced, the hardware resource overhead of the addition tree is reduced, and the surface efficiency and energy efficiency of the digital in-memory computing chip are maximized.

[0036] 2. Fewer transistors are used compared to static complementary CMOS design circuits. This is because each static complementary logic computing unit requires both pull-up and pull-down networks to output the result, while the dynamic logic computing unit uses "charge + discharge" transistors to replace one set of computing circuits in the two networks, thereby reducing the overall transistor count and lowering the static power consumption of the computing unit.

[0037] 3. Compared to multiply-accumulate unit circuits designed based on transmission transistor logic, dynamic logic calculation units have a larger signal margin and more accurate calculation results. This is because in transmission transistor logic, when the input signal enters from the source / drain, the transistor performs voltage division, resulting in the upper limit of the output signal voltage being one voltage lower than the input signal.th This means that if the transmission transistor logic is cascaded, the upper voltage limit of the output signal will decrease by one level after each stage of the circuit. If the voltage needs to be restored, it will bring more inverter overhead. In dynamic logic, because the output signal of the computing unit drives the gate of the transistor, the output signal will not produce a continuous voltage drop, ensuring the accuracy of the signal and the calculation result.

[0038] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the application. The objectives and other advantages of this application are realized and obtained through the structures particularly pointed out in the description, claims and drawings.

[0039] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings.

[0040] The advantages of this application in its additional aspects will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0041] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a circuit wiring diagram of the static complementary logic full adder shown in the embodiment of this application;

[0043] Figure 2 This is a preliminary circuit wiring diagram of the dynamic pull-down logic full adder shown in the embodiments of this application;

[0044] Figure 3 This is the final circuit wiring diagram of the dynamic pull-down logic full adder shown in the embodiment of this application;

[0045] Figure 4 This is a timing diagram of the dynamic pull-down logic full adder signal shown in an embodiment of this application;

[0046] Figure 5 This is a wiring diagram of a dynamic pull-down logic half-adder circuit as shown in an embodiment of this application;

[0047] Figure 6 This is a wiring diagram of a dynamic pull-down logic multiplier circuit as shown in an embodiment of this application;

[0048] Figure 7 This is a wiring diagram of a dynamic pull-up logic half-adder circuit as shown in an embodiment of this application;

[0049] Figure 8 This is a wiring diagram of a dynamic pull-up logic multiplier circuit as shown in an embodiment of this application;

[0050] Figure 9 This is a wiring diagram of a dynamic pull-up logic full adder circuit as shown in an embodiment of this application. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0052] In the following description, when referring to the accompanying drawings, the same numbers in different drawings denote the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of methods and systems consistent with some aspects of this application as detailed in the appended claims.

[0053] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances. Furthermore, in the description of this application, unless otherwise stated, "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship.

[0054] With the rapid development of large-scale AI models, the parameters and computational types of these models are becoming increasingly complex, which translates to greater memory and power consumption for traditional chip architectures. In-memory computing (IMC) architecture, breaking away from the traditional von Neumann architecture, integrates storage and computation in hardware, significantly increasing computational bandwidth while reducing data transfer. This offers substantial advantages in terms of memory and power consumption for computationally intensive networks like large-scale AI models. However, there are limits to how architecture can accelerate network performance. To achieve a comprehensive improvement in digital chip performance based on IMC architecture, corresponding optimizations to the underlying multiply-accumulate unit structure and computational logic are still needed.

[0055] The multiply-accumulate unit is the core module of a digital in-memory computing array and a major source of power consumption and latency. Improving the logic and computational structure of the multiply-accumulate unit will effectively enhance the energy efficiency and area efficiency of the digital in-memory computing core. This application proposes to use dynamic logic to design the computing unit in the digital in-memory computing chip: on the one hand, the dynamic CMOS logic circuit design uses independent pull-up / pull-down networks to achieve the same addition function as static complementary logic, reducing the number of transistors by half; on the other hand, dynamic CMOS logic has been widely used in memory readout circuits, which can increase the stability of data storage and readout, support higher frequencies, and is feasible.

[0056] The technical solution of this application is described in detail below:

[0057] This application discloses a digital in-memory computing chip based on dynamic logic calculation, comprising a multiplier circuit and / or a half-adder circuit and / or a first full adder circuit and / or a second full adder circuit, including:

[0058] The primary and secondary circuits, including pull-up and / or pull-down networks, are used to implement basic logic calculations; the primary circuit is started by the primary clock signal; the secondary circuit is started by the secondary clock signal.

[0059] In the specific implementation process, the drop-down network includes: first logic AND drop-down network, second logic AND drop-down network, first logic OR drop-down network, second logic OR drop-down network, and third logic OR drop-down network;

[0060] The first logic AND pull-down network, the first logic OR pull-down network, and the third logic OR pull-down network each include two NMOS transistors, with the gates of the two NMOS transistors connected to signals A and B, respectively. The second logic AND pull-down network and the second logic OR pull-down network each include three NMOS transistors, with the gates of the three NMOS transistors connected to signals A, B, and C, respectively. i Signal.

[0061] Charging transistors and discharging transistors; switched on and off according to a primary clock signal or a secondary clock signal, used to implement the calculation control of pull-up or pull-down networks and output the calculation results of the primary circuit to the secondary circuit for logic calculation.

[0062] Specifically, in this embodiment, the charging transistor is a PMOS transistor, including a first charging PMOS transistor, a second charging PMOS transistor, a third charging PMOS transistor, and a fourth charging PMOS transistor; the discharging transistor is an NMOS transistor, including a first discharging NMOS transistor, a second discharging NMOS transistor, and a third discharging NMOS transistor.

[0063] In the specific design process, by referring to the basic CMOS cell structure under static complementary logic, circuit analysis was completed for basic logic units such as simple gate circuits, multipliers, half adders, and full adders. Then, the core logic calculation circuit was extracted, and a new logic calculation unit was built using dynamic logic design methods. This unit consists of a pull-up network (PUN) / pull-down network (PDN) + charging transistor + discharging transistor, which can significantly reduce the number of transistors required for the adder. Finally, the obtained dynamic logic unit was simulated in an analog environment to try to optimize the circuit structure to ensure functional correctness and increase signal margin.

[0064] Taking a full adder as an example, the logical expression of a full adder can be written in the following form:

[0065] C o =A×B+C i (A+B)

[0066]

[0067] The obtained static complementary logic full adder structure is as follows: Figure 1 As shown;

[0068] right Figure 1 The circuit structure was analyzed, and the circuit structures used to calculate S and Co both used pull-up networks (PUN) and pull-down networks (PDN). Under dynamic logic design, only one set of networks can be selected. This application adopted a structure of "pull-down network + charging transistor + discharging transistor" to build the circuit structure of the initial version of the dynamic pull-down logic full adder (second full adder circuit), as follows. Figure 2 As shown,

[0069] Specifically, the first-stage circuit of the second full adder circuit includes: a first logic AND pull-down network, a first logic OR pull-down network, a first NMOS transistor, a first charging PMOS transistor, and a first discharging NMOS transistor; the second-stage circuit includes: a second logic AND pull-down network, a second logic OR pull-down network, a second NMOS transistor, a second charging PMOS transistor, and a second discharging NMOS transistor.

[0070] The outputs of the first logic AND pull-down network, the second logic AND pull-down network, the first logic OR pull-down network, and the second logic OR pull-down network are respectively connected to the drains of the first discharge NMOS transistor and the second NMOS transistor. The sources of the first discharge NMOS transistor and the second NMOS transistor are respectively grounded. The gates of the first discharge NMOS transistor and the second NMOS transistor are respectively connected to the clock signal. The input of the first logic NOT pull-down network is connected to the source of the first NMOS transistor, and the gate of the first NMOS transistor is connected to C. iThe signal is generated as follows: the drain of the first NMOS transistor is connected to the drain of the first charging PMOS transistor, the input of the first logic AND pull-down network, and the gate of the second NMOS transistor. The gates of the first and second charging PMOS transistors are connected to the clock signal, and the sources of the first and second charging PMOS transistors are connected to the power supply voltage. The drain of the second NMOS transistor is connected to the drain of the second charging PMOS transistor, and the input of the second logic AND pull-down network is connected to the drain of the second charging PMOS transistor. The source of the second NMOS transistor is connected to the input of the second logic OR pull-down network, and the output of the second logic OR pull-down network is connected to the drain of the second discharging NMOS transistor. The gate of the second discharging NMOS transistor is connected to the clock signal, and the source of the second discharging NMOS transistor is grounded. The input of the second logic OR pull-down network outputs the calculation result signal.

[0071] After completing the circuit structure design of the dynamic pull-down logic full adder, it was functionally tested and verified in a simulation environment. Testing revealed that the initial version of the dynamic full adder was prone to charge leakage at the parasitic capacitance used to store computational information. To address this issue, two measures were taken: firstly, the less prone-to-leakage transistor was moved closer to the charging transistor to increase the parasitic capacitance below the charging transistor used to store charge; secondly, a charging transistor was added to the intermediate node to ensure that the potentials on both sides of the leakage-prone transistor remained balanced, thus reducing the leakage of charge stored at the parasitic capacitance to the intermediate node. Furthermore, because the full adder is a two-stage structure, the signal calculated by the preceding stage requires a certain time delay to transmit to the following stage. Since the following stage circuit is only allowed to perform one calculation within one clock cycle, the clock delay between the following stage and the preceding stage must be greater than the calculation and transmission delay to ensure that the signal received by the following stage is the result of the preceding stage's calculation.

[0072] After improvement, it was obtained Figure 3 The dynamic pull-down logic full adder (first full adder circuit) shown is described in detail below:

[0073] The first stage circuit of the first full adder circuit includes: a first NMOS transistor, a first logic AND pull-down network, a first logic OR pull-down network, a first charging PMOS transistor, a second charging PMOS transistor, and a first discharging NMOS transistor; the second stage circuit includes: a second NMOS transistor, a second logic AND pull-down network, a second logic OR pull-down network, a third charging PMOS transistor, a fourth charging PMOS transistor, and a second discharging NMOS transistor.

[0074] The source of the first charging PMOS transistor is connected to the power supply voltage, the gate is connected to a primary clock signal, and the drain is connected to the drain of the first NOMS transistor. The gate of the first NOMS transistor is connected to C. i The signal is as follows: the source of the first NMOS transistor is connected to the drain of the first discharge NMOS transistor, the gate of the first discharge NMOS transistor is connected to a clock signal, and the source of the first discharge NMOS transistor is grounded.

[0075] The source of the second charging PMOS transistor is connected to the power supply voltage, the gate is connected to a first-level clock signal, and the drain is connected to the input of the first logic OR pull-down network, the input of the first logic AND pull-down network, and the gate of the second NMOS transistor. The output of the first logic OR pull-down network is connected to the drain of the first charging PMOS transistor and the drain of the first NMOS transistor. The output of the first logic AND pull-down network is connected to the drain of the first discharging NMOS transistor and the source of the second discharging NMOS transistor.

[0076] The source of the third charging PMOS transistor is connected to the power supply voltage, the gate is connected to the secondary clock signal, and the drain is connected to the input of the second logic OR pull-down network and the input of the second logic AND pull-down network, respectively. The output of the second logic OR pull-down network is connected to the drain of the second NMOS transistor and the drain of the fourth charging PMOS transistor, respectively. The gate of the fourth charging PMOS transistor is connected to the secondary clock signal, and the source is connected to the power supply voltage.

[0077] The output of the second logic and pull-down network and the source of the second NMOS transistor are respectively connected to the drain of the second discharge NMOS transistor, and the gate of the second discharge NMOS transistor is connected to the second-level clock signal.

[0078] The clock signal and input signal should satisfy the following: Figure 4 The timing sequence shown:

[0079] Among them, the input signals A, B and C i The signal is established before the rising edge of the first-stage clock, and after a certain delay (determined by the rise time, calculation delay, and propagation delay), the output signal C of the first-stage circuit is obtained. o The rising edge of the secondary clock needs to be obtained from C. o Then arrives, at which time input signals A, B, and C... i Still in the maintenance phase, A, B, C i and C o Together they participate in the operation of the secondary circuit, and after a certain delay (determined by rise time, calculation delay and transmission delay), the output signal S of the secondary circuit is obtained.

[0080] Similarly, the circuit structure designs for dynamic pull-down logic half-adders and dynamic pull-down logic multipliers can be obtained, such as... Figure 5 and Figure 6 As shown.

[0081] The logical expression for a dynamic pull-down logic half-adder can be written in the following form:

[0082]

[0083] The logical expression for a dynamic pull-down logic multiplier can be written in the following form:

[0084]

[0085] Detailed introduction is as follows:

[0086] The first-stage circuit of the half-adder circuit includes: a first logic AND pull-down network, a first charging PMOS transistor, a second charging PMOS transistor, a fourth charging PMOS transistor, and a first discharging NMOS transistor; the second-stage circuit includes: a first NMOS transistor, a first logic OR pull-down network, a third charging PMOS transistor, and a second discharging NMOS transistor.

[0087] The sources of the first, second, third, and fourth charging PMOS transistors are connected to the power supply voltage. The gates of the first, second, and fourth charging PMOS transistors are connected to a first-level clock signal, and the gate of the third charging PMOS transistor is connected to a second-level clock signal. The drain of the first charging PMOS transistor is connected to the midpoint of the two series-connected NMOS transistors in the first logic and pull-down network. The drain of the second charging PMOS transistor is connected to the input of the first logic and pull-down network and the gate of the first NMOS transistor. The output of the first logic and pull-down network is connected to the drain of the first discharging NMOS transistor and the source of the second discharging NMOS transistor. The gate of the first discharging NMOS transistor is connected to the first-level clock signal, and its source is grounded. The gate of the second discharging NMOS transistor is connected to the second-level clock signal, and its drain is connected to the source of the first NMOS transistor. The drain of the first NMOS transistor is connected to the output of the first logic or pull-down network and the drain of the fourth charging PMOS transistor. The input of the first logic or pull-down network is connected to the drain of the third charging PMOS transistor.

[0088] The first-stage circuit of the multiplier circuit includes: a first logic AND pull-down network, a first logic OR pull-down network, a first charging PMOS transistor, a second charging PMOS transistor, a first discharging NMOS transistor, and a second discharging NMOS transistor; the second-stage circuit includes: a second charging PMOS transistor, a third logic OR pull-down network, and a third discharging NMOS transistor.

[0089] The source of the first charging PMOS transistor is connected to the power supply voltage, the gate is connected to the first-level clock signal, and the drain is connected to the input of the first logic and pull-down network. At the same time, it is inverted by an inverter and connected to the gate of an NMOS transistor in the third logic or pull-down network. The output of the first logic and pull-down network is connected to the drain of the first discharging NMOS transistor. The gate of the first discharging NMOS transistor is connected to the first-level clock signal, and the source of the first discharging NMOS transistor is grounded.

[0090] The source of the second charging PMOS transistor is connected to the power supply voltage, the gate is connected to the first-level clock signal, and the drain is connected to the input of the first logic or pull-down network, and is also connected to the gate of another NMOS transistor in the third logic or pull-down network; the output of the first logic or pull-down network is connected to the drain of the second discharging NMOS transistor, the gate of the second discharging NMOS transistor is connected to the first-level clock signal, and the source of the second discharging NMOS transistor is grounded.

[0091] The source of the third charging PMOS transistor is connected to the power supply voltage, the gate is connected to the secondary clock signal, the drain is connected to the input of the third logic OR pull-down network, the output of the third logic OR pull-down network is connected to the drain of the third discharging NMOS transistor, the gate of the third discharging NMOS transistor is connected to the secondary clock signal, and the source of the third discharging NMOS transistor is grounded.

[0092] The logic expressions for the half-adder circuit, full-adder circuit, and multiplier circuit of dynamic pull-up logic are the same as those described above, and will not be repeated here.

[0093] Similarly, the dynamic pull-up logic circuits designed based on the above expressions, such as half-adder circuits, full-adder circuits, and multiplier circuits, are as follows: Figure 7 , Figure 8 , Figure 9 As shown, the details are as follows:

[0094] The first-stage circuit of the dynamic pull-up logic half-adder circuit includes: a first logic NAND pull-up network, a first charging PMOS transistor, a first discharging NMOS transistor, and a second discharging NMOS transistor; the second-stage circuit includes: a first logic OR NOT pull-up network, a second charging PMOS transistor, a third discharging NMOS transistor, and a fourth discharging NMOS transistor.

[0095] The drains of the first, second, third, and fourth discharge NMOS transistors are grounded; the gates of the first, first, second, and fourth discharge NMOS transistors are connected to a first-level clock signal, and the gates of the second-level charging PMOS transistor and the third discharge NMOS transistor are connected to a second-level clock signal; the source of the first discharge NMOS transistor is connected to the midpoint of the two series-connected PMOS transistors in the first logic and non-pull-up network, and the source of the second discharge NMOS transistor is connected to both the first logic and non-pull-up network. The input terminal of the network is connected to the gate of the first PMOS transistor. The output terminal of the first logic AND non-pull-up network is connected to the drain of the first charging PMOS transistor and the source of the second charging PMOS transistor, respectively. The gate of the first charging PMOS transistor is connected to a first-level clock signal, and the source is grounded. The gate of the second charging PMOS transistor is connected to a second-level clock signal, and the drain is connected to the source of the first PMOS transistor. The drain of the first NMOS transistor is connected to the output terminal of the first logic OR non-pull-up network and the source of the fourth discharging NMOS transistor, respectively. The input terminal of the first logic OR non-pull-up network is connected to the source of the third discharging NMOS transistor.

[0096] The first-stage circuit of the dynamic pull-up logic multiplier circuit includes: a first logic NOR pull-up network, a first logic AND pull-up network, a first charging PMOS transistor, a second charging PMOS transistor, a first discharging NMOS transistor, and a second discharging NMOS transistor; the second-stage circuit includes: a third charging PMOS transistor, a third logic AND pull-up network, and a third discharging NMOS transistor.

[0097] The source of the first charging PMOS transistor is connected to the power supply voltage, the gate is connected to a first-level clock signal, and the drain is connected to the input of the first logic or non-pull-up network. At the same time, it is inverted by an inverter and connected to the gate of a PMOS transistor in the third logic or non-pull-up network. The output of the first logic or non-pull-up network is connected to the drain of the first discharging NMOS transistor. The gate of the first discharging NMOS transistor is connected to a first-level clock signal, and the source of the first discharging NMOS transistor is grounded.

[0098] The source of the second charging PMOS transistor is connected to the power supply voltage, the gate is connected to the first-level clock signal, and the drain is connected to the input of the first logic AND non-pull-up network, and is also connected to the gate of another PMOS transistor in the third logic AND non-pull-up network; the output of the first logic AND non-pull-up network is connected to the drain of the second discharging NMOS transistor, the gate of the second discharging NMOS transistor is connected to the first-level clock signal, and the source of the second discharging NMOS transistor is grounded.

[0099] The source of the third charging PMOS transistor is connected to the power supply voltage, the gate is connected to the secondary clock signal, and the drain is connected to the input of the third logic AND pull-up network. The output of the third logic AND pull-up network is connected to the drain of the third discharging NMOS transistor. The gate of the third discharging NMOS transistor is connected to the secondary clock signal, and the source of the third discharging NMOS transistor is grounded.

[0100] The first-stage circuit of the dynamic pull-up logic full adder circuit includes: a first logic NOR pull-up network, a first logic AND pull-up network, a first PMOS transistor, a first charging PMOS transistor, a first discharging NMOS transistor, and a second discharging NMOS transistor; the second-stage circuit includes: a second logic NOR pull-up network, a second logic AND pull-up network, a second PMOS transistor, a second charging PMOS transistor, a third discharging NMOS transistor, and a fourth discharging NMOS transistor.

[0101] The gates of the first logic NOR pull-up network, the first logic AND pull-up network, and the second PMOS transistor are connected to the drain of the second discharge NMOS transistor; the outputs of the second logic NOR pull-up network and the second logic AND pull-up network are connected to the drain of the third discharge NMOS transistor; the sources of the second and third discharge NMOS transistors are grounded, and the gates of the second and third discharge NMOS transistors are connected to the first and second stage clock signals, respectively; the input of the first logic NOR pull-up network is connected to the drain of the first PMOS transistor, and the gate of the first PMOS transistor is connected to C. i The signal is generated as follows: the source of the first PMOS transistor is connected to the drain of the first charging PMOS transistor, the input of the first logic AND-NOT pull-up network, and the source of the second charging PMOS transistor. The gates of the first and second charging PMOS transistors are connected to the first and second level clock signals, respectively. The source of the first charging PMOS transistor is connected to the power supply voltage. The source of the second PMOS transistor and the input of the second logic AND-NOT pull-up network are connected to the drain of the second charging PMOS transistor. The drain of the second PMOS transistor is connected to the input of the second logic OR-NOT pull-up network. The output of the second logic OR-NOT pull-up network is connected to the drain of the second discharging NMOS transistor. The drain of the first discharging NMOS transistor is connected to the intermediate connection between the first logic OR-NOT pull-up network and the first PMOS transistor. The source of the first discharging NMOS transistor is grounded. The drain of the fourth discharging NMOS transistor is connected to the intermediate connection between the second logic OR-NOT pull-up network and the second PMOS transistor. The source of the fourth discharging NMOS transistor is grounded. The output of the second logic OR-NOT pull-up network outputs the calculation result signal.

[0102] This application proposes a novel multiply-add unit scheme based on dynamic logic, primarily focusing on structural optimizations and improvements to the multiplier and adder. The optimized multiplier and adder significantly reduce the number of transistors used, while also improving key performance indicators such as latency and power consumption. This addresses the issues of excessive power consumption and area footprint in digital in-memory computing chips designed for large AI models.

[0103] Although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0104] In the description of this application, it should be noted that relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, invention, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, invention, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, invention, article, or apparatus that includes said element.

[0105] Therefore, the above description is only a preferred embodiment of this application and is not intended to limit the scope of this application; that is, all equivalent modifications made in accordance with the scope of the claims of this application shall be within the protection scope of the claims of this application.

[0106] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The scope of protection of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0107] The applicant has provided a detailed description of the implementation examples of this application in conjunction with the accompanying drawings. However, those skilled in the art should understand that the above implementation examples are merely preferred embodiments of this application. The detailed description is only intended to help readers better understand the spirit of this application and is not intended to limit the scope of protection of this application. On the contrary, any improvements or modifications made based on the inventive spirit of this application should fall within the scope of protection of this application.

Claims

1. A digital in-memory computing chip based on dynamic logic calculation, characterized in that, The digital in-memory computing chip consists of a first full adder circuit, including: The primary and secondary circuits, including pull-up and / or pull-down networks, are used to implement basic logic calculations; the primary circuit is started by the primary clock signal; the secondary circuit is started by the secondary clock signal. Charging transistors and discharging transistors; switched on and off according to a primary clock signal or a secondary clock signal, used to implement the calculation control of pull-up or pull-down networks and output the calculation results of the primary circuit to the secondary circuit for logic calculation; The first stage circuit of the first full adder circuit includes: a first NMOS transistor, a first logic AND pull-down network, a first logic OR pull-down network, a first charging PMOS transistor, a second charging PMOS transistor, and a first discharging NMOS transistor; the second stage circuit includes: a second NMOS transistor, a second logic AND pull-down network, a second logic OR pull-down network, a third charging PMOS transistor, a fourth charging PMOS transistor, and a second discharging NMOS transistor. The source of the first charging PMOS transistor is connected to the power supply voltage, the gate is connected to a primary clock signal, and the drain is connected to the drain of the first NOMS transistor. The gate of the first NOMS transistor is connected to... C i The signal is as follows: the source of the first NMOS transistor is connected to the drain of the first discharge NMOS transistor, the gate of the first discharge NMOS transistor is connected to a clock signal, and the source of the first discharge NMOS transistor is grounded. The source of the second charging PMOS transistor is connected to the power supply voltage, the gate is connected to a first-level clock signal, and the drain is connected to the input of the first logic OR pull-down network, the input of the first logic AND pull-down network, and the gate of the second NMOS transistor. The output of the first logic OR pull-down network is connected to the drain of the first charging PMOS transistor and the drain of the first NMOS transistor. The output of the first logic AND pull-down network is connected to the drain of the first discharging NMOS transistor and the source of the second discharging NMOS transistor. The source of the third charging PMOS transistor is connected to the power supply voltage, the gate is connected to the secondary clock signal, and the drain is connected to the input of the second logic OR pull-down network and the input of the second logic AND pull-down network, respectively. The output of the second logic OR pull-down network is connected to the drain of the second NMOS transistor and the drain of the fourth charging PMOS transistor, respectively. The gate of the fourth charging PMOS transistor is connected to the secondary clock signal, and the source is connected to the power supply voltage. The output of the second logic and pull-down network and the source of the second NMOS transistor are respectively connected to the drain of the second discharge NMOS transistor, and the gate of the second discharge NMOS transistor is connected to the second-level clock signal.

2. A digital in-memory computing chip based on dynamic logic calculation, characterized in that, The digital in-memory computing chip consists of a multiplier circuit, including: The primary and secondary circuits, including pull-up and / or pull-down networks, are used to implement basic logic calculations; the primary circuit is started by the primary clock signal; the secondary circuit is started by the secondary clock signal. Charging transistors and discharging transistors; switched on and off according to a primary clock signal or a secondary clock signal, used to implement the calculation control of pull-up or pull-down networks and output the calculation results of the primary circuit to the secondary circuit for logic calculation; The first-stage circuit of the multiplier circuit includes: a first logic AND pull-down network, a first logic OR pull-down network, a first charging PMOS transistor, a second charging PMOS transistor, a first discharging NMOS transistor, and a second discharging NMOS transistor; the second-stage circuit includes: a third charging PMOS transistor, a third logic OR pull-down network, and a third discharging NMOS transistor. The source of the first charging PMOS transistor is connected to the power supply voltage, the gate is connected to the first-level clock signal, and the drain is connected to the input of the first logic and pull-down network. At the same time, it is inverted by an inverter and connected to the gate of an NMOS transistor in the third logic or pull-down network. The output of the first logic and pull-down network is connected to the drain of the first discharging NMOS transistor. The gate of the first discharging NMOS transistor is connected to the first-level clock signal, and the source of the first discharging NMOS transistor is grounded. The source of the second charging PMOS transistor is connected to the power supply voltage, the gate is connected to the first-level clock signal, and the drain is connected to the input of the first logic or pull-down network, and is also connected to the gate of another NMOS transistor in the third logic or pull-down network; the output of the first logic or pull-down network is connected to the drain of the second discharging NMOS transistor, the gate of the second discharging NMOS transistor is connected to the first-level clock signal, and the source of the second discharging NMOS transistor is grounded. The source of the third charging PMOS transistor is connected to the power supply voltage, the gate is connected to the secondary clock signal, the drain is connected to the input of the third logic OR pull-down network, the output of the third logic OR pull-down network is connected to the drain of the third discharging NMOS transistor, the gate of the third discharging NMOS transistor is connected to the secondary clock signal, and the source of the third discharging NMOS transistor is grounded.

3. A digital in-memory computing chip based on dynamic logic calculation, characterized in that, The digital in-memory computing chip consists of a half-adder circuit, including: The primary and secondary circuits, including pull-up and / or pull-down networks, are used to implement basic logic calculations; the primary circuit is started by the primary clock signal; the secondary circuit is started by the secondary clock signal. Charging transistors and discharging transistors; switched on and off according to a primary clock signal or a secondary clock signal, used to implement the calculation control of pull-up or pull-down networks and output the calculation results of the primary circuit to the secondary circuit for logic calculation; The first-stage circuit of the half-adder circuit includes: a first logic AND pull-down network, a first charging PMOS transistor, a second charging PMOS transistor, a fourth charging PMOS transistor, and a first discharging NMOS transistor; the second-stage circuit includes: a first NMOS transistor, a first logic OR pull-down network, a third charging PMOS transistor, and a second discharging NMOS transistor. The sources of the first, second, third, and fourth charging PMOS transistors are connected to the power supply voltage. The gates of the first, second, and fourth charging PMOS transistors are connected to a first-level clock signal, and the gate of the third charging PMOS transistor is connected to a second-level clock signal. The drain of the first charging PMOS transistor is connected to the midpoint of the two series-connected NMOS transistors in the first logic and pull-down network. The drain of the second charging PMOS transistor is connected to the input of the first logic and pull-down network and the gate of the first NMOS transistor. The output of the first logic and pull-down network is connected to the drain of the first discharging NMOS transistor and the source of the second discharging NMOS transistor. The gate of the first discharging NMOS transistor is connected to the first-level clock signal, and its source is grounded. The gate of the second discharging NMOS transistor is connected to the second-level clock signal, and its drain is connected to the source of the first NMOS transistor. The drain of the first NMOS transistor is connected to the output of the first logic or pull-down network and the drain of the fourth charging PMOS transistor. The input of the first logic or pull-down network is connected to the drain of the third charging PMOS transistor.

4. A digital in-memory computing chip based on dynamic logic calculation, characterized in that, The digital in-memory computing chip consists of a second full adder circuit, including: The primary and secondary circuits, including pull-up and / or pull-down networks, are used to implement basic logic calculations; the primary circuit is started by the primary clock signal; the secondary circuit is started by the secondary clock signal. Charging transistors and discharging transistors; switched on and off according to a primary clock signal or a secondary clock signal, used to implement the calculation control of pull-up or pull-down networks and output the calculation results of the primary circuit to the secondary circuit for logic calculation; The first-stage circuit of the second full adder circuit includes: a first logic AND pull-down network, a first logic OR pull-down network, a first NMOS transistor, a first charging PMOS transistor, and a first discharging NMOS transistor; the second-stage circuit includes: a second logic AND pull-down network, a second logic OR pull-down network, a second NMOS transistor, a second charging PMOS transistor, and a second discharging NMOS transistor. The outputs of the first logic AND pull-down network, the second logic AND pull-down network, the first logic OR pull-down network, and the second logic OR pull-down network are respectively connected to the drains of the first discharge NMOS transistor and the second NMOS transistor. The sources of the first discharge NMOS transistor and the second NMOS transistor are respectively grounded. The gates of the first discharge NMOS transistor and the second NMOS transistor are respectively connected to the clock signal. The input of the first logic NOT pull-down network is connected to the source of the first NMOS transistor, and the gate of the first NMOS transistor is connected to... C i The signal is generated as follows: the drain of the first NMOS transistor is connected to the drain of the first charging PMOS transistor, the input of the first logic AND pull-down network, and the gate of the second NMOS transistor. The gates of the first and second charging PMOS transistors are connected to the clock signal, and the sources of the first and second charging PMOS transistors are connected to the power supply voltage. The drain of the second NMOS transistor is connected to the drain of the second charging PMOS transistor, and the input of the second logic AND pull-down network is connected to the drain of the second charging PMOS transistor. The source of the second NMOS transistor is connected to the input of the second logic OR pull-down network, and the output of the second logic OR pull-down network is connected to the drain of the second discharging NMOS transistor. The gate of the second discharging NMOS transistor is connected to the clock signal, and the source of the second discharging NMOS transistor is grounded. The input of the second logic OR pull-down network outputs the calculation result signal.

5. A digital in-memory computing chip based on dynamic logic calculation, characterized in that, The digital in-memory computing chip consists of a half-adder circuit, including: The primary and secondary circuits, including pull-up and / or pull-down networks, are used to implement basic logic calculations; the primary circuit is started by the primary clock signal; the secondary circuit is started by the secondary clock signal. Charging transistors and discharging transistors; switched on and off according to a primary clock signal or a secondary clock signal, used to implement the calculation control of pull-up or pull-down networks and output the calculation results of the primary circuit to the secondary circuit for logic calculation; The first-stage circuit of the half-adder circuit includes: a first logic NAND pull-up network, a first charging PMOS transistor, a first discharging NMOS transistor, and a second discharging NMOS transistor; the second-stage circuit includes: a first logic OR pull-up network, a second charging PMOS transistor, a third discharging NMOS transistor, and a fourth discharging NMOS transistor. The drains of the first, second, third, and fourth discharge NMOS transistors are grounded; the gates of the first, first, second, and fourth discharge NMOS transistors are connected to a first-level clock signal, and the gates of the second-level charging PMOS transistor and the third discharge NMOS transistor are connected to a second-level clock signal; the source of the first discharge NMOS transistor is connected to the midpoint of the two series-connected PMOS transistors in the first logic and non-pull-up network, and the source of the second discharge NMOS transistor is connected to both the first logic and non-pull-up network. The input terminal of the network is connected to the gate of the first PMOS transistor. The output terminal of the first logic AND non-pull-up network is connected to the drain of the first charging PMOS transistor and the source of the second charging PMOS transistor, respectively. The gate of the first charging PMOS transistor is connected to a first-level clock signal, and the source is grounded. The gate of the second charging PMOS transistor is connected to a second-level clock signal, and the drain is connected to the source of the first PMOS transistor. The drain of the first NMOS transistor is connected to the output terminal of the first logic OR non-pull-up network and the source of the fourth discharging NMOS transistor, respectively. The input terminal of the first logic OR non-pull-up network is connected to the source of the third discharging NMOS transistor.

6. A digital in-memory computing chip based on dynamic logic calculation, characterized in that, The digital in-memory computing chip consists of a multiplier circuit, including: The primary and secondary circuits, including pull-up and / or pull-down networks, are used to implement basic logic calculations; the primary circuit is started by the primary clock signal; the secondary circuit is started by the secondary clock signal. Charging transistors and discharging transistors; switched on and off according to a primary clock signal or a secondary clock signal, used to implement the calculation control of pull-up or pull-down networks and output the calculation results of the primary circuit to the secondary circuit for logic calculation; The multiplier circuit includes: a first logic NOR pull-up network, a first logic AND pull-up network, a first charging PMOS transistor, a second charging PMOS transistor, a first discharging NMOS transistor, and a second discharging NMOS transistor; the second circuit includes: a third charging PMOS transistor, a third logic AND pull-up network, and a third discharging NMOS transistor. The source of the first charging PMOS transistor is connected to the power supply voltage, the gate is connected to a first-level clock signal, and the drain is connected to the input of the first logic or non-pull-up network. At the same time, it is inverted by an inverter and connected to the gate of a PMOS transistor in the third logic or non-pull-up network. The output of the first logic or non-pull-up network is connected to the drain of the first discharging NMOS transistor. The gate of the first discharging NMOS transistor is connected to a first-level clock signal, and the source of the first discharging NMOS transistor is grounded. The source of the second charging PMOS transistor is connected to the power supply voltage, the gate is connected to the first-level clock signal, and the drain is connected to the input of the first logic AND non-pull-up network, and is also connected to the gate of another PMOS transistor in the third logic AND non-pull-up network; the output of the first logic AND non-pull-up network is connected to the drain of the second discharging NMOS transistor, the gate of the second discharging NMOS transistor is connected to the first-level clock signal, and the source of the second discharging NMOS transistor is grounded. The source of the third charging PMOS transistor is connected to the power supply voltage, the gate is connected to the secondary clock signal, and the drain is connected to the input of the third logic AND pull-up network. The output of the third logic AND pull-up network is connected to the drain of the third discharging NMOS transistor. The gate of the third discharging NMOS transistor is connected to the secondary clock signal, and the source of the third discharging NMOS transistor is grounded.

7. A digital in-memory computing chip based on dynamic logic calculation, characterized in that, The digital in-memory computing chip consists of a full adder circuit, including: The primary and secondary circuits, including pull-up and / or pull-down networks, are used to implement basic logic calculations; the primary circuit is started by the primary clock signal; the secondary circuit is started by the secondary clock signal. Charging transistors and discharging transistors; switched on and off according to a primary clock signal or a secondary clock signal, used to implement the calculation control of pull-up or pull-down networks and output the calculation results of the primary circuit to the secondary circuit for logic calculation; The first-stage circuit of the full adder circuit includes: a first logic NOR pull-up network, a first logic AND pull-up network, a first PMOS transistor, a first charging PMOS transistor, a first discharging NMOS transistor, and a second discharging NMOS transistor; the second-stage circuit includes: a second logic NOR pull-up network, a second logic AND pull-up network, a second PMOS transistor, a second charging PMOS transistor, a third discharging NMOS transistor, and a fourth discharging NMOS transistor. The gates of the first logic NOR pull-up network, the first logic AND pull-up network, and the second PMOS transistor are connected to the drain of the second discharge NMOS transistor; the outputs of the second logic NOR pull-up network and the second logic AND pull-up network are connected to the drain of the third discharge NMOS transistor; the sources of the second and third discharge NMOS transistors are grounded, and the gates of the second and third discharge NMOS transistors are connected to the first and second stage clock signals, respectively; the input of the first logic NOR pull-up network is connected to the drain of the first PMOS transistor, and the gate of the first PMOS transistor is connected to... C i The signal is generated as follows: the source of the first PMOS transistor is connected to the drain of the first charging PMOS transistor, the input of the first logic AND-NOT pull-up network, and the source of the second charging PMOS transistor. The gates of the first and second charging PMOS transistors are connected to the first and second level clock signals, respectively. The source of the first charging PMOS transistor is connected to the power supply voltage. The source of the second PMOS transistor and the input of the second logic AND-NOT pull-up network are connected to the drain of the second charging PMOS transistor. The drain of the second PMOS transistor is connected to the input of the second logic OR-NOT pull-up network. The output of the second logic OR-NOT pull-up network is connected to the drain of the second discharging NMOS transistor. The drain of the first discharging NMOS transistor is connected to the intermediate connection between the first logic OR-NOT pull-up network and the first PMOS transistor. The source of the first discharging NMOS transistor is grounded. The drain of the fourth discharging NMOS transistor is connected to the intermediate connection between the second logic OR-NOT pull-up network and the second PMOS transistor. The source of the fourth discharging NMOS transistor is grounded. The output of the second logic OR-NOT pull-up network outputs the calculation result signal.

8. A digital in-memory computing chip based on dynamic logic calculation, characterized in that, The digital in-memory computing chip is composed of at least two of the following circuits: the first full adder circuit of claim 1, the multiplier circuit of claim 2, the half adder circuit of claim 3, the second full adder circuit of claim 4, the half adder circuit of claim 5, the multiplier circuit of claim 6, and the full adder circuit of claim 7.

9. The digital in-memory computing chip based on dynamic logic calculation according to any one of claims 1 to 8, characterized in that, The drop-down network includes: a first logical AND drop-down network, a second logical AND drop-down network, a first logical OR drop-down network, a second logical OR drop-down network, and a third logical OR drop-down network; The first logic AND pull-down network, the first logic OR pull-down network, and the third logic OR pull-down network each include two NMOS transistors, with the gates of the two NMOS transistors connected to signals A and B, respectively. The second logic AND pull-down network and the second logic OR pull-down network each include three NMOS transistors, with the gates of the three NMOS transistors connected to signals A, B, and C, respectively. C i Signal.

10. The digital in-memory computing chip based on dynamic logic calculation according to any one of claims 1 to 8, characterized in that, The charging transistor is a PMOS transistor, including a first charging PMOS transistor, a second charging PMOS transistor, a third charging PMOS transistor, and a fourth charging PMOS transistor; the discharging transistor is an NMOS transistor, including a first discharging NMOS transistor, a second discharging NMOS transistor, and a third discharging NMOS transistor.

11. The digital in-memory computing chip based on dynamic logic calculation according to any one of claims 1 to 8, characterized in that, The delay time between the secondary clock signal and the primary clock signal is greater than the startup and operation time of the primary circuit.

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