Method and device for transmitting and receiving messages of ISSU (Inter-Service Software Unit)

Abstract

The invention provides a message receiving and transmitting method and device for an ISSU. The method comprises the steps that an original drive program is configured to not respond to an interrupt notification sent by a network card chip; polling the receiving descriptor queue by using the packet receiving task process in the first container, and reading the message in the corresponding DMA buffer area under the condition that the existence of the target descriptor is determined; creating a second container, and installing and operating the target drive program in the second container; under the condition that the target driving program completes chip initialization and data synchronization, controlling a packet receiving task process to stop polling a receiving descriptor queue, and controlling the target driving program to initialize a DMA (Direct Memory Access) buffer area and the receiving descriptor queue; and processing an interrupt notification sent by the network card chip by utilizing the target driving program based on the initialized DMA buffer area and the receiving descriptor queue. By applying the embodiment of the invention, the packet receiving and sending performance in the ISSU upgrading process can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and in particular to a method and device for sending and receiving messages of a single ISSU. Background Art

[0002] ISSU (In-Service Software Upgrade) is a highly reliable way to upgrade the startup software of a device. ISSU upgrade can ensure that services are not interrupted or the interruption time is short during the upgrade process.

[0003] Existing ISSU technology is no longer limited to stacked networking, but has developed to implement ISSU software upgrades on a single network device with the help of containers. Its core idea is to separate programs and data, and the program runs in the container. During the ISSU upgrade, the program in the container is replaced and upgraded as a whole, while the data remains unchanged, so as to achieve the upgrade effect without interrupting the business.

[0004] A key performance indicator of ISSU technology is the packet loss duration. The shorter the packet loss duration, the smaller the impact on the service. How to improve the packet receiving and sending performance during the ISSU upgrade process becomes the primary consideration. Summary of the invention

[0005] The present invention provides a single-machine ISSU message receiving and sending method and device, so as to solve the problem of long packet loss time during the single-machine ISSU upgrade process in the prior art.

[0006] According to a first aspect of an embodiment of the present invention, a method for sending and receiving a message of a single-machine ISSU is provided, comprising:

[0007] The original driver of the DMA device in the first container is configured not to respond to the interrupt notification sent by the network card chip;

[0008] Polling the receiving descriptor queue by using the packet receiving task process in the first container, and when it is determined that the receiving descriptor queue has a target descriptor, reading the message in the corresponding DMA buffer according to the target descriptor;

[0009] Creating a second container, and installing and running a target driver of the DMA device in the second container;

[0010] Using the target driver to initialize the chip of the network card, and completing data synchronization with the original driver;

[0011] When the target driver completes chip initialization and completes data synchronization with the original driver, the packet receiving task process is controlled to stop polling the receiving descriptor queue, and the target driver is controlled to initialize the DMA buffer and the receiving descriptor queue;

[0012] The target driver is used to process the interrupt notification sent by the network card chip based on the initialized DMA buffer and the receive descriptor queue.

[0013] According to a second aspect of an embodiment of the present invention, a stand-alone ISSU message receiving and sending device is provided, including:

[0014] A message receiving unit, configured to configure the original driver of the DMA device in the first container to not respond to the interrupt notification sent by the network card chip;

[0015] The message receiving unit is further used to poll the receiving descriptor queue by using the packet receiving task process in the first container, and when it is determined that there is a target descriptor in the receiving descriptor queue, read the message in the corresponding direct memory access DMA buffer according to the target descriptor;

[0016] An initialization unit, used to create a second container, and install and run a target driver of a DMA device in the second container; use the target driver to initialize the chip of the network card chip, and complete data synchronization with the original driver;

[0017] The message receiving unit is further used to control the packet receiving task process to stop polling the receiving descriptor queue when the target driver completes chip initialization and completes data synchronization with the original driver;

[0018] The initialization unit is further used to control the target driver to initialize the DMA buffer and the receive descriptor queue when the target driver completes chip initialization and completes data synchronization with the original driver;

[0019] The message receiving unit is also used to process the interrupt notification sent by the network card chip based on the initialized DMA buffer and the receiving descriptor queue by using the target driver.

[0020] By applying the technical solution disclosed in the present invention, when an ISSU upgrade instruction is received, on the one hand, the original driver of the DMA device in the first container is configured not to respond to the interrupt notification sent by the network card chip, and the packet receiving task process in the first container is used to poll the receiving descriptor queue. When it is determined that the target descriptor exists in the receiving descriptor queue, the message is read in the corresponding DMA buffer according to the target descriptor; on the other hand, a second container is created, and the target driver of the DMA device is installed and run in the second container, the chip of the network card chip is initialized by the target driver, and data synchronization is completed with the original driver. When the target driver completes the chip initialization and the data synchronization with the original driver, the packet receiving task process is controlled to stop polling the receiving descriptor queue, and the target driver is controlled to initialize the DMA buffer and the receiving descriptor queue. By establishing a polling packet receiving mechanism for the old container and shifting the DMA buffer and descriptor initialization of the new container backward, the packet loss time in the single-machine ISSU upgrade process is reduced, and the packet receiving and sending performance in the ISSU upgrade process is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a flowchart of a method for sending and receiving a message of a single-machine ISSU provided in an embodiment of the present invention;

[0022] Figure 2 It is a flowchart of another method for sending and receiving a single-machine ISSU message provided by an embodiment of the present invention;

[0023] Figure 3 It is a flowchart of a method for sending and receiving a message of a single-machine ISSU provided in an embodiment of the present invention;

[0024] Figure 4 It is a structural schematic diagram of a stand-alone ISSU message receiving and sending device provided by an embodiment of the present invention;

[0025] Figure 5 The present invention is a schematic diagram of another stand-alone ISSU message transceiver device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to enable persons skilled in the art to better understand the technical solutions in the embodiments of the present invention, a message receiving and sending mechanism based on DMA (Direct Memory Access) is briefly described below.

[0027] In network communications, especially in high-performance network environments, DMA is an efficient mechanism for sending and receiving messages. It allows the DMA controller to transfer data to and from the system memory without passing through the CPU (Center Process Unit). This significantly improves data transfer efficiency and reduces the burden on the CPU, allowing the system to handle more concurrent connections and higher data throughput.

[0028] Taking message reception as an example, the DMA-based message sending and receiving mechanism may include:

[0029] 1) Initialization:

[0030] 1.1. Host memory allocation: The operating system or device driver pre-allocates buffers in the host memory for receiving messages. These buffers need to be physically continuous or mapped to physically continuous addresses through the IOMMU (input and output memory management unit).

[0031] 1.2. DMA buffer (also called DMA buffer) configuration: The physical address and size information of these buffers are configured into the receive descriptor queue of the DMA controller.

[0032] 2) Receive descriptor queue:

[0033] 2.1. Descriptor Queue: DMA controller usually uses a descriptor queue to manage the buffer of received data packets. Each descriptor contains the physical address, size and other information of the buffer.

[0034] 2.2. Descriptor linked list: These descriptors are organized into linked lists or ring buffers. The DMA controller uses these descriptors to determine which memory buffers the received data packets are placed into.

[0035] 3) Message reception:

[0036] 3.1. NIC hardware reception: When the NIC receives a message, the hardware writes the message into a pre-configured host memory buffer. This step is completed through DMA transfer, bypassing the CPU.

[0037] 3.2. Update descriptor: When the message is successfully written into the DMA buffer, the DMA controller will update the corresponding descriptor to mark that the message has been received.

[0038] 4) Notify the CPU:

[0039] 4.1. Interrupt notification: When there is a new message in the receive buffer, the DMA controller usually triggers an interrupt to notify the CPU to process the new message.

[0040] 4.2. Driver processing: The CPU responds to the interrupt, the device driver reads the receive descriptor queue, obtains the memory address and size of the message, and then performs corresponding data processing, such as passing the data to the network protocol stack.

[0041] Based on the above DMA-based message sending and receiving mechanism, during the single-machine ISSU upgrade process, there will be two containers accessing the same network card chip, which means that two DMA device drivers need to share a DMA controller. However, the current chip DMA implementation mechanism does not support multiple device drivers sharing a DMA controller. The network card chip may include a MAC chip, for example.

[0042] In this context, when initializing the DMA buffer and descriptor of the new container, you need to first turn off the packet receiving and sending function of the original container. After the new container has initialized the DMA buffer and descriptor, the business module is not ready in the new container and still cannot process the message, resulting in a single-machine ISSU upgrade packet loss time of more than 30 seconds.

[0043] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and easy to understand, the technical solutions in the embodiments of the present invention are further described in detail below with reference to the accompanying drawings.

[0044] See also Figure 1 , is a flow chart of a method for sending and receiving ISSU messages of a single machine provided by an embodiment of the present invention. The method can be applied to network devices such as switches or routers. Figure 1 As shown, the single-machine ISSU message sending and receiving method may include the following steps:

[0045] Step 101: Configure the original driver of the DMA device in the first container to not respond to the interrupt notification sent by the network card chip.

[0046] Step 102: poll the receiving descriptor queue using the packet receiving task process in the first container, and when it is determined that the receiving descriptor queue has a target descriptor, read the message in the corresponding DMA buffer according to the target descriptor.

[0047] In an embodiment of the present invention, in order to reduce the packet loss time during the ISSU upgrade process of a single machine, before the program (such as a driver and a service module) in the new container has the ability to send and receive messages, the program in the old container can send and receive messages.

[0048] In addition, if the driver of the DMA device in the old container still receives messages in response to the interrupt notification sent by the network card chip, then when the old and new containers coexist, the interrupt notification of message reception may be sent to the driver of the DMA device in the new container, resulting in failure of message reception.

[0049] Therefore, during the ISSU upgrade of a single machine, before the program in the new container has the ability to send and receive messages, the driver of the old container DMA device (which can be called the original driver) can no longer respond to the interrupt notification sent by the network card chip, but can use other methods to receive messages. This can reduce the impact on the initialization of the driver in the new container.

[0050] Exemplarily, for an old container, a polling receiving descriptor queue may be used to determine whether message receiving processing is required.

[0051] Accordingly, in an embodiment of the present invention, when an ISSU upgrade instruction is received, the packet receiving task process in the old container (which may be called the first container) may be used to poll the receiving descriptor queue to determine whether there is a target descriptor in the receiving descriptor queue.

[0052] Exemplarily, the existence of a target descriptor in the receiving descriptor queue indicates that there is a message to be read in the DMA buffer corresponding to the target descriptor.

[0053] When it is determined that the target descriptor exists in the receiving descriptor queue, the message can be read in the corresponding DMA buffer according to the target descriptor.

[0054] Optionally, in addition to configuring the original driver in the first container not to respond to the interrupt notification sent by the network card chip, the connection between the first container and the network card chip can also be actively disconnected to further reduce the impact on the initialization of the driver in the new container.

[0055] Step 103: Create a second container, and install and run the target driver of the DMA device in the second container.

[0056] Step 104: Use the target driver to initialize the chip of the network card and complete data synchronization with the original driver.

[0057] In the embodiment of the present invention, when an ISSU upgrade instruction is received, a new container (which may be called a second container, and the second container is a mirror container of the first container) may also be created.

[0058] When the second container is created, the driver of the DMA device (which may be called the target driver) may be installed and run in the second container, and the target driver is the upgraded original driver. The target driver is used to initialize the chip of the network card chip and complete data synchronization with the original driver.

[0059] Exemplarily, the chip initialization of the network card chip may include hardware resource allocation and network card register initialization, etc.

[0060] In the embodiment of the present invention, considering that the first container cannot receive messages when the second container completes the initialization of the DMA buffer and descriptor, in this case, before the service module in the second container is ready, the message cannot be received, resulting in packet loss.

[0061] Therefore, in order to reduce the occurrence of packet loss, in the process of using the target driver to initialize the chip of the network card, the initialization of the DMA buffer and the descriptor may not be performed, that is, the initialization of the DMA buffer and the descriptor may be skipped first.

[0062] Step 105: When the target driver completes chip initialization and completes data synchronization with the original driver, the packet receiving task process is controlled to stop polling the receiving descriptor queue, and the target driver is controlled to initialize the DMA buffer and the receiving descriptor queue.

[0063] In the embodiment of the present invention, when the target driver completes chip initialization and completes data synchronization with the original driver, the service module in the second container enters a ready state, and the program in the second container can send and receive messages.

[0064] Accordingly, when the target driver completes chip initialization and completes data synchronization with the original driver, on the one hand, the packet receiving task process in the first container can be controlled to stop polling the receive descriptor queue; on the other hand, the target driver can be controlled to initialize the DMA buffer and the receive descriptor queue.

[0065] Step 106: Using the target driver to process the interrupt notification sent by the network card chip based on the initialized DMA buffer and the receive descriptor queue.

[0066] In the embodiment of the present invention, when the target driver completes the initialization of the DMA buffer and the descriptor queue, the program in the second container can normally send and receive messages.

[0067] In this case, the target driver can be used to process the interrupt notification sent by the network card chip based on the initialized DMA buffer and the receive descriptor queue.

[0068] It can be seen that in Figure 1 In the method flow shown, when an ISSU upgrade instruction is received, on the one hand, the original driver of the DMA device in the first container is configured not to respond to the interrupt notification sent by the network card chip, and the packet receiving task process in the first container is used to poll the receiving descriptor queue. When it is determined that the target descriptor exists in the receiving descriptor queue, the message is read in the corresponding DMA buffer according to the target descriptor; on the other hand, a second container is created, and the target driver of the DMA device is installed and run in the second container, and the chip of the network card chip is initialized by the target driver, and data synchronization is completed with the original driver. When the target driver completes the chip initialization and the data synchronization with the original driver, the packet receiving task process is controlled to stop polling the receiving descriptor queue, and the target driver is controlled to initialize the DMA buffer and the receiving descriptor queue. By establishing a polling packet receiving mechanism for the old container and shifting the DMA buffer and descriptor initialization of the new container to a later stage, the packet loss time in the single-machine ISSU upgrade process is reduced, and the packet receiving and sending performance in the ISSU upgrade process is improved.

[0069] In some embodiments, the polling of the receiving descriptor queue by the packet receiving task process in the first container may include:

[0070] A packet receiving task process is created and run in the first container, and a receiving descriptor queue is polled by using the packet receiving task process in the first container to determine whether there is a descriptor including a target status flag in the receiving descriptor queue, and if there is a descriptor including a target status flag in the receiving descriptor queue, the descriptor including the target status flag is determined as a target descriptor; wherein the target status flag is used to indicate that there is a message to be read in a DMA buffer corresponding to the target descriptor; the above-mentioned control of the packet receiving task process to stop polling the receiving descriptor queue may include:

[0071] End the packet receiving task process in the first container.

[0072] In this embodiment, in order to implement polling packet collection of the first container, when an ISSU upgrade instruction is received, a packet collection task process may be created and run in the first container.

[0073] During the running of the packet receiving task process, the receiving descriptor queue may be polled to determine whether there is a descriptor including a target status flag in the receiving descriptor queue.

[0074] Exemplarily, the target status flag is used to indicate that there is a message to be read in the DMA buffer corresponding to the descriptor.

[0075] When it is determined that there is a descriptor including a target status flag in the receiving descriptor queue, the descriptor including the target status flag may be used as a target descriptor, and the message is read in the corresponding DMA buffer according to the target descriptor.

[0076] Exemplarily, when the target driver completes chip initialization and completes data synchronization with the original driver, the packet receiving task process of the first container can be terminated, so that the message reception is handled by the program in the new container.

[0077] In some embodiments, when the target driver completes chip initialization and completes data synchronization with the original driver, before the above-mentioned control of the target driver to initialize the DMA buffer and the receive descriptor queue may also include:

[0078] Disable the queue packet sending register of the CPU interface on the NIC chip side;

[0079] After the above control target driver performs initialization of the DMA buffer and the receive descriptor queue, it may also include:

[0080] After the initialization of the DMA buffer and descriptor is completed, the queue packet sending register of the CPU interface on the network card chip side is enabled.

[0081] Exemplarily, since during the process of the target driver initializing the DMA buffer and the receive descriptor queue, the data written into the DMA buffer according to the DMA buffer and the receive descriptor queue initialized by the original driver cannot be accurately read after the second container completes the initialization of the DMA buffer and the receive descriptor queue. Therefore, in order to avoid the data being written into the DMA buffer during the process of the target driver initializing the DMA buffer and the receive descriptor queue, after the target driver completes the chip initialization and completes the data synchronization with the original driver, before the target driver initializes the DMA buffer and the receive descriptor queue, the queue packet sending register of the CPU interface on the network card chip side can be disabled. Thus, during the process of the target driver initializing the DMA buffer and the receive descriptor queue, data cannot be written into the DMA buffer.

[0082] In addition, in order to ensure that the target driver can receive messages normally after completing the initialization of the DMA buffer and the receive descriptor queue, the queue packet sending register of the CPU port on the network card chip side can be re-enabled when the target driver completes the initialization of the DMA buffer and the receive descriptor queue.

[0083] In some embodiments, Figure 2 As shown, the single-machine ISSU message receiving and sending method provided by the embodiment of the present invention may also include:

[0084] When the message to be sent generated by the network protocol stack of the operating system is obtained, the state of the shared lock in the shared memory is read;

[0085] When the shared lock is in an unlocked state, the shared lock is updated to a locked state.

[0086] Write the message to be sent into the corresponding DMA buffer, and when the writing is completed, write a specified flag into the message sending register, so that the DMA controller can perform message sending processing when reading the specified flag in the message sending register;

[0087] Restores the state of a shared lock to unlocked.

[0088] For example, before the program in the new container can normally send and receive messages, the message sending also needs to be processed by the program in the old container, and during the message sending process of the program in the old container, it will be necessary to write registers through the PCIE (Peripheral Component Interconnect Express) channel. In addition, during the initialization of the new container, there will also be a need to write registers through the PCIE channel. Programs in different containers writing registers through the PCIE channel at the same time will have an impact on the PCIE channel.

[0089] Taking the above problems into consideration, in an embodiment of the present invention, the operation of writing the register may be controlled by a shared lock (shared between the new and old containers).

[0090] Accordingly, when a message to be sent generated by the operating system network protocol stack is obtained, for example, a program in the old container has a message sending demand, or a program in the new container has a message sending demand, the state of the shared lock in the shared memory can be read first.

[0091] Exemplarily, the state of the shared lock may include a locked state or an unlocked state.

[0092] Among them, the shared lock is in a locked state, indicating that there is a write register operation currently being executed;

[0093] The shared lock state is unlocked, indicating that there is no write register operation being executed.

[0094] In this embodiment, when it is determined that the state of the shared lock in the shared memory is an unlocked state, the state of the shared lock can be updated to a locked state, and the message to be sent can be written into the corresponding DMA buffer. When the writing is completed, a specified flag can be written into the message sending register.

[0095] The designated flag may be used to indicate that there is a message in the DMA buffer of the DMA controller that needs to be sent.

[0096] When the DMA controller reads the specified flag in the message sending register, it can read the message from the DMA buffer and perform message sending processing.

[0097] When the register write operation is completed, the state of the shared lock can be restored to an unlocked state.

[0098] In some embodiments, Figure 2 As shown, the single-machine ISSU message receiving and sending method provided by the embodiment of the present invention may also include:

[0099] When the message to be sent generated by the network protocol stack of the operating system is obtained, the state of the shared lock in the shared memory is read;

[0100] When the shared lock is in the locked state, the message sending waiting state is entered, and the shared lock state is read periodically;

[0101] When the state of the shared lock is restored to the unlocked state, the state of the shared lock is updated to the locked state;

[0102] Write the message to be sent into the corresponding DMA buffer, and when the writing is completed, write a specified flag into the message sending register, so that the DMA controller can perform message sending processing when reading the specified flag in the message sending register;

[0103] Restores the state of a shared lock to unlocked.

[0104] Exemplarily, when a message to be sent generated by the operating system network protocol stack is obtained and the state of the shared lock in the shared memory is locked, in order to avoid impacting the PCIE channel, the message sending waiting state can be entered and the state of the shared lock can be read periodically.

[0105] For example, the state of the shared lock in the shared memory is read once every preset time.

[0106] When it is determined that the state of the shared lock in the shared memory is restored to the unlocked state, the message sending state may be entered.

[0107] The state of the shared lock can be updated to a locked state, and the message to be sent can be written into the corresponding DMA buffer. When the writing is completed, a specified flag can be written into the message sending register.

[0108] The designated flag may be used to indicate that there is a message in the DMA buffer of the DMA controller that needs to be sent.

[0109] When the DMA controller reads the specified flag in the message sending register, it can read the message from the DMA buffer and perform message sending processing.

[0110] When the register write operation is completed, the state of the shared lock can be restored to an unlocked state.

[0111] In an embodiment of the present invention, when the target driver completes initialization and is synchronized with the original driver data, the program in the first container can also be controlled to stop sending messages, so that the target driver can take over the message sending and receiving processing authority after completing the synchronization of the DMA buffer and the receiving descriptor queue.

[0112] In the embodiment of the present invention, in order to save system resources, when the program in the second container takes over the message sending and receiving processing authority, the network device can recycle resources of the first container, that is, notify the first container to exit and release resources.

[0113] For example, an ISSU completion event may be issued to each process of the first container, and each process in the first container cleans up the backup data files generated by the process to prevent resource leakage.

[0114] When each process completes its own resource recovery, the docker stop command (a command used to stop a running container) can be executed for the first container, and wait for each process in the first container to terminate execution. When each process in the first container terminates execution, the first container is deleted, or, when the set timeout period is reached, the SIGKILL signal (a signal that notifies a process to terminate immediately and release its resources) is used to forcibly terminate each process in the first container and delete the first container.

[0115] In order to enable those skilled in the art to better understand the technical solution provided by the embodiment of the present invention, the technical solution provided by the embodiment of the present invention is described below in conjunction with specific application scenarios.

[0116] In this embodiment, considering that during the stand-alone ISSU upgrade process, after the driver of the DMA device in the new container completes the initialization of the DMA buffer and the receive descriptor queue, and before the service module of the new container is ready, the program in the new container will be unable to send and receive messages, which will cause packet loss.

[0117] Therefore, in order to reduce packet loss during the stand-alone ISSU upgrade process, the DMA buffer and receive descriptor queue initialization of the new container can be postponed. After the new container completes other initializations (other initializations except DMA buffer and descriptor initialization) and completes data synchronization with the old container, the DMA buffer and receive descriptor queue initialization can be performed. In this way, the new container does not need to wait for the service module to be ready after completing the DMA buffer and receive descriptor queue initialization.

[0118] In addition, considering that before the program in the new container has the ability to send and receive messages, if the driver of the DMA device in the old container still uses interrupt notification to trigger message reception, then due to the coexistence of new and old containers in the network device, the interrupt notification may be sent to the new container, resulting in the old container being unable to receive messages, resulting in packet loss. Therefore, before the program in the new container has the ability to send and receive messages, the old container can use a polling packet receiving mechanism to receive messages.

[0119] In this embodiment, if Figure 3 As shown in the figure, in order to optimize the performance of packet sending and receiving during the single-machine ISSU and reduce the packet loss duration, the message sending and receiving implementation process of the single-machine ISSU can be as follows:

[0120] 1. When receiving the ISSU upgrade instruction, configure the original driver of the DMA device in the first container not to respond to the interrupt notification sent by the network card chip.

[0121] 2. Create and run a packet receiving task process in the first container, use the packet receiving task process to poll the receiving descriptor queue, and when it is determined that there is a target descriptor in the receiving descriptor queue, read the message in the corresponding DMA buffer according to the target descriptor.

[0122] 3. Create a second container, install and run the target driver of the DMA device in the second container, use the target driver to initialize the chip of the network card chip, and complete data synchronization with the original driver.

[0123] 4. When the target driver completes chip initialization and completes data synchronization with the original driver, end the packet receiving task process in the first container, disable the queue packet sending register of the CPU port on the network card chip side, control the target driver to initialize the DMA buffer and the receive descriptor queue, and enable the queue packet sending register of the CPU interface on the network card chip side after completing the initialization of the DMA buffer and the descriptor.

[0124] During the ISSU upgrade process of a single machine, when a message to be sent generated by the network protocol stack of the operating system is obtained, the state of the shared lock in the shared memory is read.

[0125] When the state of the shared lock is unlocked, the state of the shared lock is updated to a locked state; the message to be sent is written into the corresponding DMA buffer, and when the writing is completed, a specified flag is written into the message sending register, so that the DMA controller performs the message sending process when the specified flag in the message sending register is read; the state of the shared lock is restored to an unlocked state.

[0126] When the shared lock is in a locked state, enter the message sending waiting state and read the shared lock state periodically; when the shared lock is restored to an unlocked state, update the shared lock state to a locked state; write the message to be sent into the corresponding DMA buffer, and when the writing is completed, write a specified flag into the message sending register so that the DMA controller can perform the message sending process when the specified flag in the message sending register is read; restore the shared lock state to an unlocked state.

[0127] See also Figure 4 , is a structural diagram of a stand-alone ISSU message receiving and sending device provided by an embodiment of the present invention, such as Figure 4 As shown, the stand-alone ISSU message receiving and sending device may include:

[0128] The message receiving unit 410 is used to configure the original driver of the DMA device in the first container to not respond to the interrupt notification sent by the network card chip;

[0129] The message receiving unit 410 is further configured to poll the receiving descriptor queue using the packet receiving task process in the first container, and when it is determined that there is a target descriptor in the receiving descriptor queue, read the message in the corresponding direct memory access DMA buffer according to the target descriptor;

[0130] The initialization unit 420 is used to create a second container, and install and run a target driver of the DMA device in the second container; use the target driver to initialize the chip of the network card chip, and complete data synchronization with the original driver;

[0131] The message receiving unit 410 is further used to control the packet receiving task process to stop polling the receiving descriptor queue when the target driver completes chip initialization and completes data synchronization with the original driver;

[0132] The initialization unit 420 is further used to control the target driver to initialize the DMA buffer and the receive descriptor queue when the target driver completes chip initialization and completes data synchronization with the original driver;

[0133] The message receiving unit 410 is further configured to process the interrupt notification sent by the network card chip using the target driver based on the initialized DMA buffer and the receiving descriptor queue.

[0134] In some embodiments, the message receiving unit 410 uses the packet receiving task process in the first container to poll the receiving descriptor queue, including:

[0135] Creating and running a packet receiving task process in the first container, polling a receiving descriptor queue using the packet receiving task process in the first container, determining whether there is a descriptor including a target status flag in the receiving descriptor queue, and if there is a descriptor including a target status flag in the receiving descriptor queue, determining the descriptor including the target status flag as the target descriptor; wherein the target status flag is used to indicate that there is a message to be read in the DMA buffer corresponding to the target descriptor;

[0136] The message receiving unit controls the packet receiving task process to stop polling the receiving descriptor queue, including:

[0137] End the packet receiving task process in the first container.

[0138] In some embodiments, when the target driver completes chip initialization and completes data synchronization with the original driver, before the initialization unit 420 controls the target driver to initialize the DMA buffer and the receive descriptor queue, it also includes:

[0139] Deactivate the queue packet sending register of the central processing unit CPU interface on the media access control network card chip side;

[0140] After the initialization unit controls the target driver to initialize the DMA buffer and the receive descriptor queue, the initialization unit further includes:

[0141] After completing the initialization of the DMA buffer and descriptor, enable the queue packet sending register of the CPU port on the network card chip side.

[0142] In some embodiments, Figure 5 As shown, the device also includes:

[0143] The message sending unit 430 is used to read the state of the shared lock in the shared memory when the message to be sent generated by the operating system network protocol stack is obtained; when the state of the shared lock is an unlocked state, update the state of the shared lock to a locked state; write the message to be sent into the corresponding DMA buffer, and when the writing is completed, write a specified flag in the message sending register so that the DMA controller performs the message sending process when the specified flag in the message sending register is read; and restore the state of the shared lock to an unlocked state.

[0144] In some embodiments, the message sending unit 430 is also used to read the state of the shared lock in the shared memory when the message to be sent generated by the operating system network protocol stack is obtained; when the state of the shared lock is a locked state, enter the message sending waiting state, and periodically read the state of the shared lock; when the state of the shared lock is restored to an unlocked state, update the state of the shared lock to a locked state; write the message to be sent into the corresponding DMA buffer, and when the writing is completed, write a specified flag in the message sending register, so that the DMA controller performs message sending processing when the specified flag in the message sending register is read; restore the state of the shared lock to an unlocked state.

[0145] An embodiment of the present invention further provides an electronic device, including a processor and a memory, wherein the memory is used to store a computer program; and the processor is used to implement the above-described single-machine ISSU message receiving and sending method when executing the program stored in the memory.

[0146] The memory mentioned in this article can be any electronic, magnetic, optical or other physical storage device that can contain or store information, such as executable instructions, data, etc. For example, the machine-readable storage medium can be: RAM (RadomAccess Memory, random access memory), volatile memory, non-volatile memory, flash memory, storage drive (such as hard disk drive), solid state drive, any type of storage disk (such as CD, DVD, etc.), or similar storage medium, or a combination thereof.

[0147] An embodiment of the present invention further provides a machine-readable storage medium, such as the above-mentioned memory, in which machine-executable instructions are stored, and when the machine-executable instructions are executed by a processor, the message sending and receiving method of the single-machine ISSU described above is implemented. For example, the machine-readable storage medium can be a ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage device, etc.

[0148] An embodiment of the present invention further provides a computer program product, which stores a computer program. When a processor executes the computer program, the processor is prompted to execute the message receiving and sending method of the single-machine ISSU described above.

Claims

1. A method for sending and receiving ISSU messages of a single machine, characterized in that: include: The original driver of the DMA device in the first container is configured not to respond to the interrupt notification sent by the network card chip; Polling a receiving descriptor queue using the packet receiving task process in the first container, and when determining that a target descriptor exists in the receiving descriptor queue, reading a message in a corresponding direct memory access DMA buffer according to the target descriptor; Creating a second container, and installing and running a target driver of the DMA device in the second container; Using the target driver to initialize the chip of the network card, and completing data synchronization with the original driver; When the target driver completes chip initialization and completes data synchronization with the original driver, the packet receiving task process is controlled to stop polling the receiving descriptor queue, and the target driver is controlled to initialize the DMA buffer and the receiving descriptor queue; The target driver is used to process the interrupt notification sent by the network card chip based on the initialized DMA buffer and the receive descriptor queue.

2. The method according to claim 1, characterized in that The polling the receiving descriptor queue by using the packet receiving task process in the first container includes: Creating and running a packet receiving task process in the first container, polling a receiving descriptor queue using the packet receiving task process in the first container, determining whether there is a descriptor including a target status flag in the receiving descriptor queue, and if there is a descriptor including a target status flag in the receiving descriptor queue, determining the descriptor including the target status flag as the target descriptor; wherein the target status flag is used to indicate that there is a message to be read in the DMA buffer corresponding to the target descriptor; The controlling the packet receiving task process to stop polling the receiving descriptor queue includes: End the packet receiving task process in the first container.

3. The method according to claim 1, characterized in that When the target driver completes chip initialization and completes data synchronization with the original driver, before controlling the target driver to initialize the DMA buffer and the receive descriptor queue, the method further includes: Deactivate the queue packet sending register of the central processing unit CPU interface on the media access control network card chip side; After the target driver is controlled to initialize the DMA buffer and the receive descriptor queue, the method further includes: After the initialization of the DMA buffer and descriptor is completed, the queue packet sending register of the CPU interface on the network card chip side is enabled.

4. The method according to claim 1, characterized in that: The method further comprises: When the message to be sent generated by the network protocol stack of the operating system is obtained, the state of the shared lock in the shared memory is read; When the state of the shared lock is in an unlocked state, updating the state of the shared lock to a locked state; Writing the message to be sent into the corresponding DMA buffer, and when the writing is completed, writing a specified flag into the message sending register, so that the DMA controller performs message sending processing when reading the specified flag in the message sending register; Restore the state of the shared lock to an unlocked state.

5. The method according to claim 1, characterized in that The method further comprises: When the message to be sent generated by the network protocol stack of the operating system is obtained, the state of the shared lock in the shared memory is read; When the state of the shared lock is a locked state, entering a message sending waiting state, and periodically reading the state of the shared lock; When the state of the shared lock is restored to an unlocked state, updating the state of the shared lock to a locked state; Writing the message to be sent into the corresponding DMA buffer, and when the writing is completed, writing a specified flag into the message sending register, so that the DMA controller performs message sending processing when reading the specified flag in the message sending register; Restore the state of the shared lock to an unlocked state.

6. A stand-alone ISSU message transceiver, characterized in that: include: A message receiving unit, configured to configure the original driver of the DMA device in the first container to not respond to the interrupt notification sent by the network card chip; The message receiving unit is further used to poll the receiving descriptor queue by using the packet receiving task process in the first container, and when it is determined that there is a target descriptor in the receiving descriptor queue, read the message in the corresponding direct memory access DMA buffer according to the target descriptor; An initialization unit, used to create a second container, and install and run a target driver of a DMA device in the second container; use the target driver to initialize the chip of the network card chip, and complete data synchronization with the original driver; The message receiving unit is further used to control the packet receiving task process to stop polling the receiving descriptor queue when the target driver completes chip initialization and completes data synchronization with the original driver; The initialization unit is further used to control the target driver to initialize the DMA buffer and the receive descriptor queue when the target driver completes chip initialization and completes data synchronization with the original driver; The message receiving unit is also used to process the interrupt notification sent by the network card chip based on the initialized DMA buffer and the receiving descriptor queue by using the target driver.

7. The device according to claim 6, characterized in that The message receiving unit polls the receiving descriptor queue by using the packet receiving task process in the first container, including: Creating and running a packet receiving task process in the first container, polling a receiving descriptor queue using the packet receiving task process in the first container, determining whether there is a descriptor including a target status flag in the receiving descriptor queue, and if there is a descriptor including a target status flag in the receiving descriptor queue, determining the descriptor including the target status flag as the target descriptor; wherein the target status flag is used to indicate that there is a message to be read in the DMA buffer corresponding to the target descriptor; The message receiving unit controls the packet receiving task process to stop polling the receiving descriptor queue, including: End the packet receiving task process in the first container.

8. The device according to claim 6, characterized in that When the target driver completes chip initialization and completes data synchronization with the original driver, before the initialization unit controls the target driver to initialize the DMA buffer and the receive descriptor queue, it also includes: Deactivate the queue packet sending register of the central processing unit CPU interface on the media access control network card chip side; After the initialization unit controls the target driver to initialize the DMA buffer and the receive descriptor queue, the initialization unit further includes: After completing the initialization of the DMA buffer and descriptor, enable the queue packet sending register of the CPU port on the network card chip side.

9. The device according to claim 6, characterized in that The device also includes: A message sending unit is used to read the state of a shared lock in a shared memory when a message to be sent generated by a network protocol stack of an operating system is obtained; update the state of the shared lock to a locked state when the state of the shared lock is an unlocked state; write the message to be sent into a corresponding DMA buffer, and when the writing is completed, write a specified flag in a message sending register so that the DMA controller performs message sending processing when the specified flag in the message sending register is read; and restore the state of the shared lock to an unlocked state.

10. The device according to claim 9, characterized in that The message sending unit is further used to read the state of the shared lock in the shared memory when there is a message sending demand; enter the message sending waiting state when the state of the shared lock is a locked state, and read the state of the shared lock regularly; update the state of the shared lock to a locked state when the state of the shared lock is restored to an unlocked state; write the message to be sent into the corresponding DMA buffer, and write a specified flag into the message sending register when the writing is completed, so that the DMA controller performs message sending processing when the specified flag in the message sending register is read; Restore the state of the shared lock to an unlocked state.

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