A message transceiving method and device of a single ISSU

Abstract

The application provides a packet transceiving method and device for single machine ISSU, and the method comprises the following steps: configuring an original driver to not respond to an interrupt notification sent by a network card chip; polling a receiving descriptor queue by using a packet receiving task process in a first container, and performing packet reading in a corresponding DMA buffer zone when it is determined that there is a target descriptor; creating a second container, and installing and running a target driver in the second container; stopping the polling of the receiving descriptor queue by the packet receiving task process, and controlling the target driver to initialize the DMA buffer zone and the receiving descriptor queue when the target driver completes chip initialization and data synchronization; and processing the interrupt notification sent by the network card chip based on the initialized DMA buffer zone and the receiving descriptor queue by using the target driver. The application can improve the packet transceiving performance in the ISSU upgrading process.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data processing, and in particular to a message transceiving method and device for single-machine ISSU. BACKGROUND

[0002] ISSU (In-Service Software Upgrade) is a high-reliability way to upgrade the software of a device. Through ISSU upgrade, it can be ensured that the service is not interrupted or the interruption time is short during the upgrade.

[0003] The existing ISSU technology is not limited to stacked networking, but has developed to implement ISSU software upgrade on a single network device with the help of a container. The core idea is to separate programs and data, run the program in the container, and replace the whole program in the container during ISSU upgrade, while keeping the data unchanged, so as to achieve the effect of service uninterrupted upgrade.

[0004] A key performance indicator of the ISSU technology is the packet loss time. The shorter the packet loss time is, the smaller the impact on the service is. Therefore, how to improve the packet transceiving performance during the ISSU upgrade has become a primary consideration. SUMMARY

[0005] The present application provides a message transceiving method and device for single-machine ISSU, to solve the problem of long packet loss time during the single-machine ISSU upgrade in the prior art.

[0006] According to a first aspect of an embodiment of the present application, a message transceiving method for single-machine ISSU is provided, comprising:

[0007] configuring an original driver of a DMA device in a first container to not respond to an interrupt notification sent by a network card chip;

[0008] polling a receive descriptor queue by using a packet receiving task process in the first container, and in a case where it is determined that there is a target descriptor in the receive descriptor queue, performing message reading in a corresponding DMA buffer according to the target descriptor;

[0009] creating a second container, and installing and running a target driver of the DMA device in the second container;

[0010] performing chip initialization of the network card chip by using the target driver, and completing data synchronization with the original driver;

[0011] in the case that the target driver completes chip initialization and data synchronization with the original driver, the packet receiving task process is controlled to stop polling the receiving descriptor queue, and the target driver is controlled to initialize the DMA buffer and the receiving descriptor queue;

[0012] the target driver is used to process the interrupt notification sent by the network card chip based on the initialized DMA buffer and the receiving descriptor queue.

[0013] According to a second aspect of the embodiment of the present application, a packet transceiving device for single machine ISSU is provided, comprising:

[0014] a packet receiving unit, configured to configure an original driver of a DMA device in a first container to not respond to an interrupt notification sent by a network card chip;

[0015] the packet receiving unit is further configured to poll a receiving descriptor queue by using a packet receiving task process in the first container, and in the case that a target descriptor exists in the receiving descriptor queue, perform packet reading in a corresponding direct memory access (DMA) buffer according to the target descriptor;

[0016] an initialization unit, configured to create a second container, and install and run a target driver of a DMA device in the second container; use the target driver to perform chip initialization of a network card chip, and complete data synchronization with the original driver;

[0017] the packet receiving unit is further configured to, in the case that the target driver completes chip initialization and data synchronization with the original driver, control the packet receiving task process to stop polling the receiving descriptor queue;

[0018] the initialization unit is further configured to, in the case that the target driver completes chip initialization and data synchronization with the original driver, control the target driver to initialize the DMA buffer and the receiving descriptor queue;

[0019] the packet receiving unit is further configured to use the target driver to process the interrupt notification sent by the network card chip based on the initialized DMA buffer and the receiving descriptor queue.

[0020] With the technical solution disclosed in the application, in the case of receiving an ISSU upgrade instruction, on the one hand, the original driver of the DMA device in the first container is configured to not respond to the interrupt notification sent by the network card chip, and the packet receiving task process in the first container is used to poll the receiving descriptor queue, and in the case of determining that there is a target descriptor in the receiving descriptor queue, packet reading is performed in the corresponding DMA buffer according to the target descriptor; on the other hand, a second container is created, and the target driver of the DMA device is installed and run in the second container, the target driver is used to perform chip initialization of the network card chip, and data synchronization is completed with the original driver, in the case of completing chip initialization by the target driver and completing data synchronization with the original driver, the packet receiving task process is controlled to stop polling the receiving descriptor queue, and the target driver is controlled to initialize the DMA buffer and the receiving descriptor queue, by establishing a polling packet receiving mechanism for the old container and moving the initialization of the DMA buffer and the descriptor of the new container, the packet loss time in the single-machine ISSU upgrade process is reduced, and the packet receiving and sending performance in the ISSU upgrade process is improved. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 is a flowchart of a packet receiving and sending method of single-machine ISSU provided by an embodiment of the application;

[0022] Figure 2 is a flowchart of another packet receiving and sending method of single-machine ISSU provided by an embodiment of the application;

[0023] Figure 3 is a flowchart of a packet receiving and sending method of single-machine ISSU provided by an embodiment of the application;

[0024] Figure 4 is a structural diagram of a packet receiving and sending device of single-machine ISSU provided by an embodiment of the application;

[0025] Figure 5 is a structural diagram of another packet receiving and sending device of single-machine ISSU provided by an embodiment of the application. DETAILED DESCRIPTION

[0026] In order to make the person skilled in the art better understand the technical solutions in the embodiments of the application, the packet receiving and sending mechanism based on DMA (Direct Memory Access) is briefly described as follows.

[0027] In network communication, especially in high-performance network environments, DMA is an efficient mechanism for sending and receiving packets. It allows the DMA controller to transfer data with the system memory without going through the CPU (Center Process Unit). This significantly improves data transfer efficiency and reduces the burden on the CPU, enabling the system to handle more concurrent connections and higher data throughput.

[0028] Taking packet reception as an example, the DMA-based packet sending and receiving mechanism can include:

[0029] 1) Initialization:

[0030] 1.1, Host memory allocation: The operating system or device driver pre-allocates buffer areas for receiving packets in the host memory. These buffers need to be physically continuous, or mapped into physically continuous addresses by IOMMU (Input-Output Memory Management Unit).

[0031] 1.2, DMA buffer (also known as DMA buffer) configuration: The physical address and size information of these buffers are configured into the receive descriptor queue of the DMA controller.

[0032] 2) Receive descriptor queue:

[0033] 2.1, Descriptor queue: The DMA controller usually uses a descriptor queue (Descriptor Queue) to manage the buffer areas for receiving packets. Each descriptor contains the physical address, size, and other information of the buffer.

[0034] 2.2, Descriptor linked list: These descriptors are organized into a linked list or ring buffer, and the DMA controller determines which memory buffer to put the received packet into according to these descriptors.

[0035] 3) Packet reception:

[0036] 3.1, Network card hardware reception: When the network card receives a packet, the hardware writes the packet into the pre-configured host memory buffer. This step is completed through DMA transmission, bypassing the CPU.

[0037] 3.2, Update descriptor: The DMA controller updates the corresponding descriptor when the packet is successfully written into the DMA buffer, marking that the packet has been received.

[0038] 4) Notify CPU:

[0039] 4.1, Interrupt notification: When there is a new packet in the receiving buffer, the DMA controller usually triggers an interrupt (Interrupt) to notify the CPU to process the new packet.

[0040] 4.2, Driver processing: CPU responds to the interrupt, the device driver reads the receive descriptor queue, obtains the memory address and size of the message, and then performs corresponding data processing, such as passing the data to the network protocol stack.

[0041] Based on the above DMA-based message receiving and sending mechanism, during the single-machine ISSU upgrade process, two containers will access the same network card chip, which means that two DMA device drivers need to share one DMA controller. However, the current chip DMA implementation mechanism does not support multiple device drivers sharing one DMA controller. The network card chip may include a MAC chip, for example.

[0042] In this context, when initializing the DMA buffer and descriptor of the new container, the original container's packet receiving and sending function needs to be closed first. When the new container initializes the DMA buffer and descriptor, the service module cannot process the message before the new container is ready, resulting in a packet loss time of more than 30S during the current single-machine ISSU upgrade.

[0043] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more apparent and easy to understand, the technical solutions in the embodiments of the present application will be further described in detail below with reference to the drawings.

[0044] Please refer to Figure 1 A flowchart of a single-machine ISSU message receiving and sending method provided by an embodiment of the present application. The method can be applied to network devices such as switches or routers, etc. As shown in the figure, the single-machine ISSU message receiving and sending method can include the following steps: Figure 1

[0045] Step 101, configure the original driver of the DMA device in the first container to not respond to the interrupt notification sent by the network card chip.

[0046] Step 102, poll the receive descriptor queue using the packet receiving task process in the first container, and in the case where it is determined that there is a target descriptor in the receive descriptor queue, perform message reading in the corresponding DMA buffer according to the target descriptor.

[0047] In the embodiments of the present application, in order to reduce the packet loss time during the single-machine ISSU upgrade process, before the programs (such as drivers and service modules) in the new container have the message receiving and sending capability, the programs in the old container can perform message receiving and sending.

[0048] ​In addition, if the driver of the DMA device in the old container still receives the packet according to the interrupt notification sent by the network card chip, in the case of coexistence of the new and old containers, the interrupt notification of packet reception can be sent to the driver of the DMA device in the new container, resulting in failure of packet reception.

[0049] Therefore, during the single-machine ISSU upgrade, before the program in the new container has the packet transmission and reception capability, the driver of the DMA device in the old container (which can be referred to as an original driver) can no longer respond to the interrupt notification sent by the network card chip, but can implement packet reception in other ways. Thus, the influence on the initialization of the driver in the new container can be reduced.

[0050] For example, for the old container, whether packet reception processing is needed can be determined by polling the receive descriptor queue.

[0051] Correspondingly, in the embodiment of the application, when the ISSU upgrade instruction is received, the receive descriptor queue can be polled by the packet receiving task process in the old container (which can be referred to as a first container) to determine whether there is a target descriptor in the receive descriptor queue.

[0052] For example, the existence of the target descriptor in the receive descriptor queue indicates that there is a to-be-read packet in the DMA buffer corresponding to the target descriptor.

[0053] When it is determined that there is a target descriptor in the receive descriptor queue, packet reading can be performed in the corresponding DMA buffer according to the target descriptor.

[0054] Optionally, in addition to configuring the original driver in the first container to not respond to the interrupt notification sent by the network card chip, the connection between the first container and the network card chip can be actively disconnected, further reducing the influence on the initialization of the driver in the new container.

[0055] Step 103, creating a second container and installing and running the target driver of the DMA device in the second container.

[0056] Step 104, performing chip initialization of the network card chip by using the target driver, and completing data synchronization with the original driver.

[0057] In the embodiment of the application, when the ISSU upgrade instruction is received, a new container (which can be referred to as a second container, and the second container is a mirror container of the first container) can also be created.

[0058] With a second container created, the DMA device driver (which can be called the target driver) can be installed and run within the second container. The target driver is the upgraded original driver. The target driver is used to initialize the network card chip and synchronize data with the original driver.

[0059] For example, the chip initialization of the aforementioned network interface card (NIC) chip may include hardware resource allocation and NIC register initialization, etc.

[0060] In this embodiment of the invention, considering that the first container will be unable to receive packets once the second container completes the initialization of the DMA buffer and descriptor, packet reception will be impossible until the service module in the second container is ready, resulting in packet loss.

[0061] Therefore, in order to reduce packet loss, the initialization of the DMA buffer and descriptors can be skipped during the initialization of the network card chip using the target driver.

[0062] Step 105: After the target driver completes chip initialization and data synchronization with the original driver, control the packet receiving task process to stop polling the receive descriptor queue, and control the target driver to initialize the DMA buffer and receive descriptor queue.

[0063] In this embodiment of the invention, after the target driver completes chip initialization and data synchronization with the original driver, the service module in the second container enters a ready state, and can send and receive messages by the program in the second container.

[0064] Accordingly, once the target driver has completed chip initialization and data synchronization with the original driver, on the one hand, the packet receiving task process in the first container can be controlled to stop polling the receive descriptor queue; on the other hand, the target driver can be controlled to initialize the DMA buffer and the receive descriptor queue.

[0065] Step 106: Use the target driver to process the interrupt notification sent by the network card chip based on the initialized DMA buffer and receive descriptor queue.

[0066] In this embodiment of the invention, once the target driver completes the initialization of the DMA buffer and descriptor queue, the program in the second container can normally send and receive messages.

[0067] In this case, the target driver can utilize the initialized DMA buffer and receive descriptor queue to handle interrupt notifications sent by the network card chip.

[0068] It can be seen that, in Figure 1 In the illustrated method flow, upon receiving an ISSU upgrade command, on the one hand, the original driver for the DMA device in the first container is configured not to respond to interrupt notifications sent by the network card chip, and the receiving task process in the first container polls the receive descriptor queue. If a target descriptor is found in the receive descriptor queue, the packet is read from the corresponding DMA buffer based on the target descriptor. On the other hand, a second container is created, and the target driver for the DMA device is installed and run in the second container. The target driver is used to initialize the network card chip and synchronize data with the original driver. Once the target driver has completed chip initialization and data synchronization with the original driver, the receiving task process is controlled to stop polling the receive descriptor queue, and the target driver is controlled to initialize the DMA buffer and the receive descriptor queue. By establishing a polling packet receiving mechanism for the old container and shifting the initialization of the DMA buffer and descriptor in the new container, the packet loss time during the single-machine ISSU upgrade process is reduced, and the packet sending and receiving performance during the ISSU upgrade process is improved.

[0069] In some embodiments, the above-described polling of the receive descriptor queue using the packet receiving task process in the first container may include:

[0070] A packet receiving task process is created and run in the first container. This process polls the receive descriptor queue to determine if a descriptor containing a target status flag exists. If such a descriptor exists, it is identified as the target descriptor. The target status flag indicates that a packet to be read exists in the DMA buffer corresponding to the target descriptor. Controlling the packet receiving task process to stop polling the receive descriptor queue can include:

[0071] The packet receiving task process in the first container is terminated.

[0072] In this embodiment, in order to achieve the polling and packet receiving of the first container, a packet receiving task process can be created and run in the first container upon receiving an ISSU upgrade instruction.

[0073] During the execution of this packet receiving task, the receive descriptor queue can be polled to determine whether there is a descriptor in the receive descriptor queue that includes the target status flag.

[0074] For example, the target status flag is used to indicate that there is a message to be read in the DMA buffer corresponding to the descriptor.

[0075] In a case where it is determined that there is a descriptor including the target status flag bit in the receiving descriptor queue, the descriptor including the target status flag bit can be taken as a target descriptor, and packet reading is performed in the corresponding DMA buffer according to the target descriptor.

[0076] For example, in a case where the target driver completes chip initialization and data synchronization with the original driver, the packet receiving task process in the first container can be ended, so that packet receiving is performed by the program in the new container.

[0077] In some embodiments, in a case where the target driver completes chip initialization and data synchronization with the original driver, the above-mentioned control of the target driver to perform initialization of the DMA buffer and the receiving descriptor queue can further include:

[0078] deactivating the queue packet sending register of the CPU interface on the network card chip side;

[0079] The above-mentioned control of the target driver to perform initialization of the DMA buffer and the receiving descriptor queue can further include:

[0080] in a case where the initialization of the DMA buffer and the descriptor is completed, enabling the queue packet sending register of the CPU interface on the network card chip side.

[0081] For example, since the data written in the DMA buffer according to the DMA buffer and the receiving descriptor queue initialized by the original driver will not be accurately read after the second container completes initialization of the DMA buffer and the receiving descriptor queue during the initialization of the DMA buffer and the receiving descriptor queue by the target driver, in order to avoid data from being written in the DMA buffer during the initialization of the DMA buffer and the receiving descriptor queue by the target driver, in a case where the target driver completes chip initialization and data synchronization with the original driver, the queue packet sending register of the CPU interface on the network card chip side can be deactivated before the target driver performs initialization of the DMA buffer and the receiving descriptor queue, so that data cannot be written in the DMA buffer during the initialization of the DMA buffer and the receiving descriptor queue by the target driver.

[0082] In addition, in order to ensure that the target driver can normally perform packet receiving after completing initialization of the DMA buffer and the receiving descriptor queue, in a case where the target driver completes initialization of the DMA buffer and the receiving descriptor queue, the queue packet sending register of the CPU interface on the network card chip side can be re-enabled.

[0083] In some embodiments, as shown in Figure 2 The packet receiving and sending method of the single ISSU provided by the embodiment of the present application can further include:

[0084] In the case where the to-be-sent message generated by the operating system network protocol stack is acquired, the state of the shared lock in the shared memory is read;

[0085] In the case where the state of the shared lock is in the non-locked state, the state of the shared lock is updated to the locked state;

[0086] The to-be-sent message is written into the corresponding DMA buffer, and in the case where the writing is completed, a specified flag is written into the message sending register, so that the DMA controller performs the message sending processing in the case where the specified flag in the message sending register is read;

[0087] The state of the shared lock is restored to the unlocked state.

[0088] For example, it is considered that the message sending also needs to be processed by the program in the old container before the program in the new container normally performs the message transceiving, and the program in the old container needs to write the register through the PCIE (Peripheral Component Interconnect Express, Peripheral Component Interconnect Express) channel during the process of performing the message sending. In addition, there is also a demand for writing the register through the PCIE channel during the process of initializing the new container, and the programs in different containers simultaneously writing the register through the PCIE channel will impact the PCIE channel.

[0089] In view of the above problems, in the embodiment of the application, the operation of writing the register can be controlled through the shared lock (shared between the new and old containers).

[0090] Correspondingly, in the case where the to-be-sent message generated by the operating system network protocol stack is acquired, for example, the program in the old container has a demand for message sending, or the program in the new container has a demand for message sending, the state of the shared lock in the shared memory can be read first.

[0091] For example, the state of the shared lock can include a locked state or a non-locked state.

[0092] The shared lock in the locked state indicates that there is currently an ongoing write register operation;

[0093] The shared lock in the non-locked state indicates that there is currently no ongoing write register operation.

[0094] In this embodiment, in the case where it is determined that the state of the shared lock in the shared memory is in the non-locked state, the state of the shared lock can be updated to the locked state, and the to-be-sent message is written into the corresponding DMA buffer, and in the case where the writing is completed, a specified flag is written into the message sending register.

[0095] The specified flag can be used to indicate that there is a message in the DMA buffer of the DMA controller that needs to be sent.

[0096] The DMA controller can read the message from the DMA buffer and perform message sending processing in the case of reading the specified flag in the message sending register.

[0097] In the case of completing the register write operation, the state of the shared lock can be restored to the unlocked state.

[0098] In some embodiments, as shown in Figure 2 The message transceiving method for single ISSU provided by the embodiments of the present application can further include the following steps:

[0099] In the case of obtaining the to-be-sent message generated by the network protocol stack of the operating system, the state of the shared lock in the shared memory is read;

[0100] In the case of the state of the shared lock being the locked state, the message sending waiting state is entered, and the state of the shared lock is read in a timing manner;

[0101] In the case of the state of the shared lock being restored to the unlocked state, the state of the shared lock is updated to the locked state;

[0102] The to-be-sent message is written into the corresponding DMA buffer, and in the case of completing the writing, the specified flag is written into the message sending register, so that the DMA controller performs message sending processing in the case of reading the specified flag in the message sending register;

[0103] The state of the shared lock is restored to the unlocked state.

[0104] For example, in the case of obtaining the to-be-sent message generated by the network protocol stack of the operating system and the state of the shared lock in the shared memory being the locked state, in order to avoid impacting the PCIE channel, the message sending waiting state can be entered, and the state of the shared lock is read in a timing manner.

[0105] For example, the state of the shared lock in the shared memory is read every preset time.

[0106] In the case of determining that the state of the shared lock in the shared memory is restored to the unlocked state, the message sending state can be entered.

[0107] The state of the shared lock can be updated to the locked state, and the to-be-sent message is written into the corresponding DMA buffer, and in the case of completing the writing, the specified flag is written into the message sending register.

[0108] The specified flag can be used to indicate that there is a message in the DMA buffer of the DMA controller that needs to be sent.

[0109] The DMA controller can read the packet from the DMA buffer and perform the packet sending processing in the case of reading the specified flag in the packet sending register.

[0110] In the case of completing the register write operation, the state of the shared lock can be restored to the unlocked state.

[0111] In the case of completing the initialization of the target driver and synchronizing with the original driver data, the program in the first container can also be controlled to stop the packet sending, so that the target driver can take over the packet transceiving processing right in the case of completing the synchronization of the DMA buffer and the receiving descriptor queue.

[0112] In the case of taking over the packet transceiving processing right by the program in the second container, the network device can perform resource recycling on the first container, that is, notify the first container to exit and release the resources, in order to save system resources.

[0113] For example, an ISSU completion event can be issued to each process of the first container, and each process in the first container cleans up the backup data file generated by the process itself, to prevent resource leakage.

[0114] In the case of completing the resource recycling of each process, a docker stop command (a command for stopping a running container) can be executed for the first container, and the execution of each process in the first container is waited for termination, in the case of terminating the execution of each process in the first container, the first container is deleted, or in the case of reaching a set timeout, each process in the first container is forcibly terminated by a SIGKILL signal (a signal for notifying a process to terminate immediately and release its resources), and the first container is deleted.

[0115] In order for those skilled in the art to better understand the technical solutions provided by the embodiments of the present application, the technical solutions provided by the embodiments of the present application will be described below in conjunction with specific application scenarios.

[0116] In this embodiment, considering that in the single-machine ISSU upgrade process, the program in the new container cannot perform packet transceiving before the service module of the new container is ready after the driver of the DMA device in the new container completes the initialization of the DMA buffer and the receiving descriptor queue, packet loss will be caused.

[0117] Therefore, in order to reduce the packet loss in the single-machine ISSU upgrade process, the initialization of the DMA buffer and the receiving descriptor queue of the new container can be postponed until the new container completes other initialization (other than the initialization of the DMA buffer and the descriptor) and completes data synchronization with the old container, so that the new container does not need to wait for the service module to be ready in the case of completing the initialization of the DMA buffer and the receiving descriptor queue.

[0118] In addition, considering that the program in the new container does not have the packet transmission and reception capability before the initialization of the DMA buffer and the receiving descriptor queue, if the driver of the DMA device in the old container still triggers packet reception by using the interrupt notification mode, the interrupt notification can be sent to the new container due to the coexistence of the old and new containers in the network device, so that the old container cannot perform packet reception, resulting in packet loss. Therefore, before the program in the new container has the packet transmission and reception capability, the old container can use the polling packet reception mechanism to perform packet reception.

[0119] In this embodiment, as shown in FIG. 6, to optimize the performance of packet transmission and reception during single-machine ISSU and reduce the packet loss duration, the packet transmission and reception implementation process of single-machine ISSU can be as follows: Figure 3

[0120] 1. In the case of receiving an ISSU upgrade instruction, the original driver of the DMA device in the first container is configured to not respond to the interrupt notification sent by the network card chip.

[0121] 2. A packet receiving task process is created and run in the first container, and the packet receiving task process is used to poll the receiving descriptor queue. In the case where a target descriptor exists in the receiving descriptor queue, packet reading is performed in the corresponding DMA buffer according to the target descriptor.

[0122] 3. A second container is created, and a target driver of the DMA device is installed and run in the second container. The target driver is used to perform chip initialization of the network card chip and complete data synchronization with the original driver.

[0123] 4. In the case where the target driver completes the chip initialization and completes the data synchronization with the original driver, the packet receiving task process in the first container is ended, the queue packet sending register of the CPU interface of the network card chip is disabled, and the target driver is controlled to perform the initialization of the DMA buffer and the receiving descriptor queue. In the case of completing the initialization of the DMA buffer and the descriptor, the queue packet sending register of the CPU interface of the network card chip is enabled.

[0124] In the single-machine ISSU upgrade process, the state of the shared lock in the shared memory is read in the case of obtaining the to-be-sent packet generated by the operating system network protocol stack. ​

[0125] In the case that the state of the shared lock is the non-locked state, the state of the shared lock is updated to the locked state; the to-be-sent packet is written into the corresponding DMA buffer, and in the case that the writing is completed, a specified flag is written into the packet sending register, so that the DMA controller performs packet sending processing in the case that the specified flag in the packet sending register is read; and the state of the shared lock is restored to the non-locked state.

[0126] In the case that the state of the shared lock is the locked state, the packet sending waiting state is entered, and the state of the shared lock is read in a timing manner; in the case that the state of the shared lock is restored to the non-locked state, the state of the shared lock is updated to the locked state; the to-be-sent packet is written into the corresponding DMA buffer, and in the case that the writing is completed, a specified flag is written into the packet sending register, so that the DMA controller performs packet sending processing in the case that the specified flag in the packet sending register is read; and the state of the shared lock is restored to the non-locked state.

[0127] Please refer to Figure 4 A structure schematic diagram of a packet transceiving device of a single machine ISSU is provided for an embodiment of the present application, as Figure 4 indicated, the packet transceiving device of the single machine ISSU can comprise:

[0128] The packet receiving unit 410 is configured to configure an original driver of a DMA device in a first container to not respond to an interrupt notification sent by a network card chip;

[0129] The packet receiving unit 410 is further configured to poll a receiving descriptor queue by using a packet receiving task process in the first container, and in the case that it is determined that a target descriptor exists in the receiving descriptor queue, perform packet reading in a corresponding direct memory access (DMA) buffer according to the target descriptor;

[0130] The initialization unit 420 is configured to create a second container, and install and run a target driver of the DMA device in the second container; perform chip initialization of the network card chip by using the target driver, and complete data synchronization with the original driver;

[0131] The packet receiving unit 410 is further configured to, in the case that the target driver completes the chip initialization and completes the data synchronization with the original driver, control the packet receiving task process to stop polling the receiving descriptor queue;

[0132] The initialization unit 420 is further configured to, in the case that the target driver completes the chip initialization and completes the data synchronization with the original driver, control the target driver to perform initialization of a DMA buffer and a receiving descriptor queue;

[0133] The packet receiving unit 410 is further configured to process an interrupt notification sent by the network card chip based on the initialized DMA buffer and the receive descriptor queue by using the target driver.

[0134] In some embodiments, the packet receiving unit 410 polls the receive descriptor queue by using a packet receiving task process in the first container, including:

[0135] creating and running a packet receiving task process in the first container, polling the receive descriptor queue by using the packet receiving task process in the first container, determining whether there is a descriptor including a target state flag bit in the receive descriptor queue, and if there is a descriptor including a target state flag bit in the receive descriptor queue, determining the descriptor including the target state flag bit as the target descriptor; wherein the target state flag is used to indicate that there is a packet to be read in the DMA buffer corresponding to the target descriptor;

[0136] The packet receiving unit controls the packet receiving task process to stop polling the receive descriptor queue, including:

[0137] ending the packet receiving task process in the first container.

[0138] In some embodiments, before the initialization unit 420 controls the target driver to initialize the DMA buffer and the receive descriptor queue, in the case that the target driver completes chip initialization and data synchronization with the original driver, the initialization unit 420 further includes:

[0139] deactivating a queue packet sending register of a media access control network card chip side central processing unit (CPU) interface;

[0140] After the initialization unit controls the target driver to initialize the DMA buffer and the receive descriptor queue, the initialization unit 420 further includes:

[0141] In the case of completing the initialization of the DMA buffer and the descriptor, enabling the queue packet sending register of the network card chip side CPU interface.

[0142] In some embodiments, as shown in FIG. 8, the apparatus further includes: Figure 5

[0143] ​The message sending unit 430 is configured to read the state of the shared lock in the shared memory when obtaining a to-be-sent message generated by the operating system network protocol stack; update the state of the shared lock to a locked state when the state of the shared lock is in an unlocked state; write the to-be-sent message into a corresponding DMA buffer, and write a specified flag into a message sending register when the writing is completed, so that the DMA controller performs message sending processing when reading the specified flag in the message sending register; and restore the state of the shared lock to an unlocked state.

[0144] In some embodiments, the message sending unit 430 is further configured to read the state of the shared lock in the shared memory when obtaining a to-be-sent message generated by the operating system network protocol stack; enter a message sending waiting state and perform timed reading on the state of the shared lock when the state of the shared lock is in a locked state; update the state of the shared lock to a locked state when the state of the shared lock is restored to an unlocked state; write the to-be-sent message into a corresponding DMA buffer, and write a specified flag into a message sending register when the writing is completed, so that the DMA controller performs message sending processing when reading the specified flag in the message sending register; and restore the state of the shared lock to an unlocked state.

[0145] The embodiment of the present application further provides an electronic device, including a processor and a memory, wherein the memory is used for storing a computer program; and the processor is used for executing the program stored in the memory to realize the single-machine ISSU message transceiving method described above.

[0146] The memory mentioned herein can be any electronic, magnetic, optical or other physical storage device, and can contain or store information such as executable instructions, data, etc. For example, the machine-readable storage medium can be RAM (Random Access Memory), volatile memory, non-volatile memory, flash memory, storage drives (such as hard disk drives), solid state drives, any type of storage disk (such as optical disks, DVDs, etc.), or similar storage media, or a combination thereof.

[0147] The embodiment of the present application further provides a machine-readable storage medium, such as the above-mentioned memory, which stores machine-executable instructions, and the machine-executable instructions are executed by a processor to realize the single-machine ISSU message transceiving method described above. For example, the machine-readable storage medium can be a ROM, a RAM, a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0148] The embodiment of the present application also provides a computer program product, which stores a computer program and causes a processor to execute the packet transceiving method of the single ISSU described above when the processor executes the computer program.

Claims

1. A message transmission and reception method for a standalone ISSU, characterized in that, include: Configure the original driver for the DMA device in the first container to not respond to interrupt notifications sent by the network card chip; The receiving task process in the first container polls the receiving descriptor queue. If a target descriptor is found in the receiving descriptor queue, the packet is read from the corresponding direct memory access DMA buffer according to the target descriptor. Create a second container, and install and run the target driver for the DMA device in the second container; The target driver is used to initialize the network card chip and synchronize data with the original driver. After the target driver completes chip initialization and data synchronization with the original driver, the packet receiving task process is controlled to stop polling the receive descriptor queue, and the target driver is controlled to initialize the DMA buffer and the receive descriptor queue. The target driver uses the initialized DMA buffer and receive descriptor queue to process the interrupt notification sent by the network card chip.

2. The method according to claim 1, characterized in that, The step of polling the receive descriptor queue using the packet receiving task process in the first container includes: A packet receiving task process is created and run in the first container. The packet receiving task process in the first container polls the receive descriptor queue to determine whether there is a descriptor including a target status flag in the receive descriptor queue. If there is a descriptor including a target status flag in the receive descriptor queue, the descriptor including the target status flag is determined as the target descriptor. The target status flag is used to indicate that there is a packet to be read in the DMA buffer corresponding to the target descriptor. The step of controlling the packet receiving task process to stop polling the receive descriptor queue includes: The packet receiving task process in the first container is terminated.

3. The method according to claim 1, characterized in that, Before the initialization of the DMA buffer and receive descriptor queue by controlling the target driver to initialize, after the target driver has completed chip initialization and data synchronization with the original driver, the method further includes: Disable the queue packet register of the CPU interface on the Media Access Control network card chip side; After the target driver initializes the DMA buffer and receive descriptor queue, the method further includes: After completing the initialization of the DMA buffer and descriptor, enable the queue packet sending register of the CPU interface on the network card chip side.

4. The method according to claim 1, characterized in that, The method further includes: Upon obtaining the message to be sent generated by the operating system's network protocol stack, read the state of the shared lock in the shared memory; If the shared lock is in an unlocked state, update the shared lock to a locked state. The message to be sent is written to the corresponding DMA buffer, and upon completion of the writing, a specified flag is written to the message sending register so that the DMA controller can perform message sending processing upon reading the specified flag in the message sending register. Restore the shared lock to an unlocked state.

5. The method according to claim 1, characterized in that, The method further includes: Upon obtaining the message to be sent generated by the operating system's network protocol stack, read the state of the shared lock in the shared memory; When the shared lock is in a locked state, the system enters a message sending waiting state and periodically reads the state of the shared lock. If the shared lock is restored to an unlocked state, the shared lock is updated to a locked state. The message to be sent is written to the corresponding DMA buffer, and upon completion of the writing, a specified flag is written to the message sending register so that the DMA controller can perform message sending processing upon reading the specified flag in the message sending register. Restore the shared lock to an unlocked state.

6. A message transceiver device for a standalone ISSU, characterized in that, include: The message receiving unit is used to configure the original driver of the DMA device in the first container to not respond to interrupt notifications sent by the network card chip; The message receiving unit is further configured to poll the receiving descriptor queue using the packet receiving task process in the first container, and if it is determined that there is a target descriptor in the receiving descriptor queue, to read the message in the corresponding direct memory access DMA buffer according to the target descriptor. An initialization unit is used to create a second container, install and run the target driver for the DMA device in the second container, perform chip initialization of the network card chip using the target driver, and complete data synchronization with the original driver. The message receiving unit is also configured to control the packet receiving task process to stop polling the receive descriptor queue when the target driver has completed chip initialization and data synchronization with the original driver. The initialization unit is also used to control the target driver to initialize the DMA buffer and the receive descriptor queue when the target driver has completed chip initialization and data synchronization with the original driver. The message receiving unit is also used to process the interrupt notification sent by the network card chip using the target driver based on the initialized DMA buffer and receive descriptor queue.

7. The apparatus according to claim 6, characterized in that, The message receiving unit uses the packet receiving task process in the first container to poll the receive descriptor queue, including: A packet receiving task process is created and run in the first container. The packet receiving task process in the first container polls the receive descriptor queue to determine whether there is a descriptor including a target status flag in the receive descriptor queue. If there is a descriptor including a target status flag in the receive descriptor queue, the descriptor including the target status flag is determined as the target descriptor. The target status flag is used to indicate that there is a packet to be read in the DMA buffer corresponding to the target descriptor. The message receiving unit controls the packet receiving task process to stop polling the receive descriptor queue, including: The packet receiving task process in the first container is terminated.

8. The apparatus according to claim 6, characterized in that, Before the initialization unit controls the target driver to initialize the DMA buffer and receive descriptor queue, after the target driver has completed chip initialization and data synchronization with the original driver, the method further includes: Disable the queue packet register of the CPU interface on the Media Access Control network card chip side; After the initialization unit controls the target driver to initialize the DMA buffer and receive descriptor queue, it further includes: After completing the initialization of the DMA buffer and descriptor, enable the queue packet register of the CPU port on the network card chip side.

9. The apparatus according to claim 6, characterized in that, The device further includes: The message sending unit is configured to, upon receiving a message to be sent generated by the operating system network protocol stack, read the state of the shared lock in the shared memory; if the shared lock is in an unlocked state, update the state of the shared lock to a locked state; write the message to be sent into the corresponding DMA buffer, and upon completion of the write operation, write a specified flag into the message sending register so that the DMA controller can perform message sending processing upon reading the specified flag in the message sending register; and restore the state of the shared lock to an unlocked state.

10. The apparatus according to claim 9, characterized in that, The message sending unit is further configured to: read the state of the shared lock in the shared memory when there is a message sending requirement; enter a message sending waiting state when the shared lock is in a locked state, and periodically read the state of the shared lock; update the state of the shared lock to a locked state when the shared lock is restored to an unlocked state; write the message to be sent into the corresponding DMA buffer, and write a specified flag into the message sending register when the writing is completed, so that the DMA controller can perform message sending processing when it reads the specified flag in the message sending register; Restore the shared lock to an unlocked state.

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