Debugging system

Abstract

The embodiment of the invention provides a debugging system. The debugging system comprises an instruction self-checking control module and a feedback control module, the instruction self-checking control module is connected with the feedback control module; the instruction self-checking control module is used for acquiring a debugging instruction of a debugger, checking the debugging instruction, and outputting a control signal indicating that the instruction is abnormal to the feedback control module under the condition that the debugging instruction is checked to be abnormal; and the feedback control module is used for responding to the control signal representing the instruction exception and outputting a first feedback signal representing the instruction exception to the debugger, so that the debugger adjusts the debugging instruction. The instruction self-checking control module is arranged to check the debugging instruction, and when it is checked that the debugging instruction is abnormal, the feedback control module is controlled to return the instruction abnormal information to the debugger, so that the debugger adjusts the debugging instruction according to the instruction abnormal information, and the problem of hanging up of a debugging system can be reduced.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a debugging system. Background Art

[0002] When a current processing unit "hangs" internally (a hang means that when the processing unit is executing a program, it cannot continue to execute instructions due to some reason, so that the entire system or device cannot work normally), it is necessary to use a debugging system to debug the processing unit, obtain the on-site information of the processing unit hang, and configure the internal configuration registers of the processing unit.

[0003] In the related art, the processing unit is usually debugged through a debugger or a debugging device integrated with a hardware control circuit. However, when the debugging instructions are transmitted, debugging errors may occur due to problems such as abnormal debugging configuration of the host computer and data fluctuations of the debugging instructions, which may cause the debugging system to "hang". Summary of the invention

[0004] The purpose of the embodiment of the present application is to provide a debugging system to reduce the "hanging" problem of the debugging system. The specific technical solution is as follows:

[0005] In a first aspect, an embodiment of the present application provides a debugging system, the system comprising:

[0006] Instruction self-check control module, feedback control module;

[0007] The instruction self-check control module is connected to the feedback control module;

[0008] The instruction self-check control module is used to obtain the debugging instruction of the debugger, check the debugging instruction, and output a control signal indicating the instruction abnormality to the feedback control module when the debugging instruction is found to be abnormal;

[0009] The feedback control module is used to output a first feedback signal indicating an instruction abnormality to the debugger in response to the control signal indicating an instruction abnormality, so that the debugger adjusts the debugging instruction.

[0010] In a possible implementation, the system further includes a debugging conversion control module;

[0011] The debugging conversion control module is connected to the instruction self-checking control module;

[0012] The instruction self-check control module is further used to output the debugging instruction to the debugging conversion control module when the debugging instruction is detected to be normal;

[0013] The debugging conversion control module is used to receive the debugging instruction and transmit the debugging instruction to the device to be debugged.

[0014] In a possible implementation manner, the instruction self-check control module is further configured to output a control signal indicating that the instruction is normal to the feedback control module when the debugging instruction is detected to be normal;

[0015] The feedback control module is further configured to output a second feedback signal indicating that the instruction is normal to the debugger in response to the control signal indicating that the instruction is normal.

[0016] In a possible implementation, the instruction self-check control module is specifically used to obtain the debug instruction, check whether the debug instruction belongs to a target category, and output a first control signal to the feedback control module when it is checked that the debug instruction does not belong to the target category; wherein the target category includes: single write access of a configuration address, continuous write access of a configuration address, write access of a page address, single read access of a configuration address, continuous read access of a configuration address, and read access of a page address;

[0017] The feedback control module is specifically configured to output a first feedback signal indicating an abnormal debugging instruction category to the debugger in response to the first control signal.

[0018] In a possible implementation manner, the instruction self-check control module is specifically configured to, when it is detected that the debug instruction belongs to the target category, check whether the access address of the debug instruction is in the expected address domain segment, and when it is detected that the access address of the debug instruction is not in the expected address domain segment, output a second control signal to the feedback control module;

[0019] The feedback control module is specifically configured to output a first feedback signal indicating that the debug instruction address is out of bounds to the debugger in response to the second control signal.

[0020] In a possible implementation manner, the feedback control module is connected to the debugging conversion control module;

[0021] The instruction self-check control module is specifically used to output the access address of the page accessed by the debug instruction set by itself to the debug conversion control module when it is detected that the access address of the debug instruction is in the expected address domain segment and the debug instruction is a write access of the page address, and count the number of words of the write configuration data of the debug instruction; when the number of words is less than the expected number of configuration data, output a third control signal to the feedback control module;

[0022] The feedback control module is specifically configured to output a first feedback signal indicating that the debug instruction write configuration is abnormal to the debugger in response to the third control signal;

[0023] The feedback control module is further configured to output the write configuration data corresponding to the debug instruction set by itself to the debug conversion control module in response to the write configuration data update signal output by the instruction self-check control module;

[0024] The instruction self-check control module is specifically used to delete the part of the write configuration data that exceeds the normal number of words when the number of words exceeds the expected number of configuration data, output the write configuration data with the normal number of words after deletion to the debugging conversion control module, and output the third control signal to the feedback control module;

[0025] The feedback control module is specifically configured to output a first feedback signal indicating that the debug instruction write configuration is abnormal to the debugger in response to the third control signal.

[0026] In a possible implementation manner, the instruction self-check control module is specifically configured to output the write configuration data of the debug instruction to the debug conversion control module and output a fourth control signal to the feedback control module when the number of words matches the expected number of configuration data;

[0027] The feedback control module is specifically configured to respond to the fourth control signal and output a second feedback signal to the debugger indicating that the debug instruction write configuration is normal.

[0028] In a possible implementation manner, the instruction self-check control module is specifically configured to output the access address and read access length data of the page accessed by the debug instruction set by itself to the debug conversion control module, and output a fifth control signal to the feedback control module, when it is detected that the access address of the debug instruction is in the expected address domain segment and the debug instruction is a read access of a page address;

[0029] The feedback control module is specifically configured to respond to the fifth control signal and output a second feedback signal to the debugger indicating that the debug instruction read configuration is normal.

[0030] In a possible implementation manner, the instruction self-check control module is specifically used to check whether the access address of the debug instruction is aligned according to 4 bytes when it is checked that the debug instruction belongs to the target category, and if it is checked that the access address of the debug instruction is not aligned according to 4 bytes, perform a 4-byte alignment operation on the access address of the debug instruction and then output it to the debug conversion control module, and output a sixth control signal to the feedback control module;

[0031] The feedback control module is specifically configured to output a first feedback signal indicating a debug instruction address misalignment to the debugger in response to the sixth control signal.

[0032] In a possible implementation manner, the instruction self-check control module is specifically used to check whether the length of the read access length data of the debug instruction is 0 when it is checked that the access address of the debug instruction is in the expected address domain segment, and when the debug instruction is any one of a single read access of a configuration address and a continuous read access of a configuration address, and when it is checked that the length of the read access length data of the debug instruction is 0, output the read access length data with a length of 1 set by itself to the debug conversion control module, and output a seventh control signal to the feedback control module;

[0033] The feedback control module is specifically configured to output a first feedback signal indicating that the debug instruction read configuration is abnormal to the debugger in response to the seventh control signal.

[0034] In one possible implementation, the instruction self-check control module is specifically used to obtain the debugging instruction, and when the encoding method of the 8-bit access control data of the debugging instruction is a one-hot code, the 8-bit access control data of the debugging instruction is bit-wise judged, and when the result of the bitwise addition is constantly 1 and the upper 2 bits are constantly 0, it is determined that the debugging instruction belongs to the target category; otherwise, it is determined that the debugging instruction does not belong to the target category.

[0035] In a possible implementation, the instruction self-check control module is specifically used to check the boundary value of the access address of the debug instruction when it is detected that the debug instruction belongs to the target category, and when the boundary value is within the expected address domain, determine that the access address of the debug instruction is within the expected address domain; otherwise, determine that the access address of the debug instruction is not within the expected address domain.

[0036] In a possible implementation, the system further includes a multiplexing module;

[0037] The control end of the multiplexing module is connected to the instruction self-checking control module, the first input end of the multiplexing module is connected to the feedback control module, and the second input end of the multiplexing module is connected to the debugging conversion control module;

[0038] The instruction self-check control module is further used to output the first level signal or the second level signal to the control end of the multiplexing module;

[0039] The multiplexing module is used to, when its own control end receives a first level signal, turn on the first channel corresponding to its own first input end, so that the feedback control module outputs a first feedback signal indicating an abnormal instruction and a second feedback signal indicating a normal instruction to the debugger; when its own control end receives a second level signal, turn on the second channel corresponding to its own second input end, so that the debugging conversion control module returns the read data information to the debugger.

[0040] Beneficial effects of the embodiments of the present application:

[0041] A debugging system provided by an embodiment of the present application includes: an instruction self-check control module and a feedback control module; the instruction self-check control module is connected to the feedback control module; the instruction self-check control module is used to obtain the debugging instruction of the debugger, check the debugging instruction, and output a control signal indicating the instruction abnormality to the feedback control module when the debugging instruction is detected to be abnormal; the feedback control module is used to respond to the control signal indicating the instruction abnormality and output a first feedback signal indicating the instruction abnormality to the debugger, so that the debugger adjusts the debugging instruction. By setting the instruction self-check control module, checking the debugging instruction, and controlling the feedback control module to return the instruction abnormality information to the debugger when the debugging instruction is detected to be abnormal, so that the debugger adjusts the debugging instruction according to the instruction abnormality information, the "hanging" problem of the debugging system can be reduced.

[0042] Of course, implementing any product or method of the present application does not necessarily require achieving all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0044] Figure 1 A schematic diagram of the first structure of the debugging system provided in the embodiment of the present application;

[0045] Figure 2 A second structural diagram of the debugging system provided in an embodiment of the present application;

[0046] Figure 3 A third structural diagram of the debugging system provided in the embodiment of the present application;

[0047] Figure 4 A schematic diagram of 4-byte alignment of access address in the related art;

[0048] Figure 5 A schematic diagram of signal interaction between a debugging system and a debugger provided in an embodiment of the present application;

[0049] Figure 6 A schematic diagram of different address domains corresponding to different instructions in the related art;

[0050] Figure 7 A fourth structural diagram of the debugging system provided in an embodiment of the present application;

[0051] Figure 8 A fifth structural diagram of the debugging system provided in an embodiment of the present application;

[0052] Fig. 9 A sixth structural diagram of the debugging system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field based on the present application belong to the scope of protection of the present application.

[0054] When a current processing unit "hangs up" internally, a debugging system needs to be used to debug the processing unit, obtain on-site information of the processing unit hanging up, and configure the internal configuration registers of the processing unit.

[0055] In the related art, the processing unit is usually debugged through a debugger or a debugging device integrated with a hardware control circuit. However, when the debugging instructions are transmitted, debugging errors may occur due to abnormal debugging configuration of the host computer, data fluctuations of the debugging instructions, and other problems. The debugging stability is poor, which may cause the debugging system to "hang".

[0056] In order to solve at least one of the above problems, the present application embodiment provides a debugging system 1, see Figure 1 The debugging system 1 includes: an instruction self-checking control module 12 , a feedback control module 13 and a debugging conversion control module 14 .

[0057] The instruction self-checking control module 12 is connected to the debugging conversion control module 14 and the feedback control module 13 respectively.

[0058] The instruction self-check control module 12 is used to obtain the debugging instruction of the debugger, check the debugging instruction, and output a control signal indicating the instruction abnormality to the feedback control module 13 when the debugging instruction is found to be abnormal.

[0059] The feedback control module 13 is used for outputting a first feedback signal indicating an instruction abnormality to the debugger in response to the control signal indicating an instruction abnormality, so that the debugger adjusts the debugging instruction.

[0060] The first feedback signal indicating an instruction abnormality may include: a signal indicating a debug instruction category abnormality, a signal indicating a debug instruction address out of bounds, a signal indicating a debug instruction write configuration abnormality, a signal indicating a debug instruction address misalignment, a signal indicating a debug instruction read configuration abnormality, etc.

[0061] The instruction self-checking control module 12 is further configured to output the debugging instruction to the debugging conversion control module 14 when the debugging instruction is found to be normal.

[0062] The debugging conversion control module 14 is used to receive the debugging instruction and transmit the debugging instruction to the device to be debugged (processing unit).

[0063] In the embodiment of the present application, an instruction self-check control module 12 is set to check the debugging instructions. When the debugging instruction is detected to be abnormal, the control feedback control module 13 is controlled to send instruction exception information back to the debugger, so that the debugger can adjust the debugging instruction according to the instruction exception information. This can reduce the problem of debugging errors, improve the stability of debugging, and further reduce the "hanging" problem of the debugging system.

[0064] In one possible implementation, see Figure 1 The instruction self-check control module 12 is also used to output a control signal indicating that the instruction is normal to the feedback control module 13 when it is detected that the debugging instruction is normal.

[0065] The feedback control module 13 is further configured to output a second feedback signal indicating that the instruction is normal to the debugger in response to the control signal indicating that the instruction is normal.

[0066] The second feedback signal indicating that the instruction is normal may include: a signal indicating that the debug instruction write configuration is normal, and a signal indicating that the debug instruction read configuration is normal.

[0067] In the embodiment of the present application, the instruction self-check control module 12 will not only control the feedback control module 13 to return instruction exception information to the debugger, but also control the feedback control module 13 to return instruction normal information to the debugger. Compared with the traditional debugging method of confirming whether the write configuration is refreshed normally through the write-first-read-then operation method, the present application improves the debugging efficiency of the debugging system through the debugging self-feedback mode.

[0068] In one possible implementation, see Figure 2 , the debugging system 1 further includes: an instruction transceiver module 11;

[0069] The instruction transceiver module 11 is connected to the debugger, the instruction self-check control module 12 and the feedback control module 13 respectively.

[0070] The instruction transceiver module 11 is used to obtain the initial debugging instruction sent by the debugger, perform format conversion on the initial debugging instruction, and obtain the debugging instruction after format conversion.

[0071] The instruction transceiver module 11 may include a serial-to-parallel conversion control submodule, a parallel-to-serial conversion control submodule, and an instruction decoding control submodule. The host computer issues the initial debugging instruction in a serial transmission (a data transmission mode in which the binary code of data is transmitted bit by bit in time sequence on a physical channel. The characteristic of serial transmission is that only one bit is transmitted each time) through the debugger. After receiving the initial debugging instruction, the instruction transceiver module 11 may convert the single bit (bit is a data storage unit. In computer data storage, the basic unit of data storage is byte, and the smallest unit is The instruction decoding control submodule receives 8-bit instruction data and can decode the instruction data into 8-bit read and write access control instruction data cfg_cmd, 16-bit read and write access address data cfg_addr, 8-bit read access length data cfg_length and 32-bit write configuration data cfg_wdata (debug instruction).

[0072] For a write access operation, the debug instruction includes: cfg_cmd+cfg_addr+cfg_wdata; for a read access operation, the debug instruction includes: cfg_cmd +cfg_addr+cfg_length.

[0073] The instruction self-check control module 12 is used to obtain the debugging instruction, check the debugging instruction, and output a control signal indicating the instruction abnormality to the feedback control module 13 when the debugging instruction is found to be abnormal.

[0074] The feedback control module 13 is used to output a first feedback signal indicating an instruction abnormality to the instruction transceiver module 11 in response to the control signal indicating an instruction abnormality.

[0075] The instruction transceiver module 11 is further used to perform format conversion on the first feedback signal, and transmit the format-converted first feedback signal back to the debugger, so that the debugger can adjust the initial debugging instruction.

[0076] After receiving the first feedback signal, the instruction transceiver module 11 can convert the first feedback signal transmitted in parallel into the first feedback signal transmitted in serial through its own parallel-to-serial conversion control submodule, and then transmit the first feedback signal back to the debugger.

[0077] The instruction self-checking control module 12 is further configured to output the debugging instruction to the debugging conversion control module 14 when the debugging instruction is found to be normal.

[0078] The debugging conversion control module 14 is used to receive the debugging instruction, perform timing conversion on the debugging instruction, and transmit the debugging instruction after timing conversion to the device to be debugged.

[0079] After receiving the debugging instruction, the debugging conversion control module 14 can perform timing conversion on the debugging instruction, convert it into a standard timing protocol, and then transmit it to the device to be debugged (processing unit) through the debugging bus.

[0080] In the embodiment of the present application, an instruction self-check control module 12 is set to check the debugging instructions. When a debugging instruction exception is detected, the control feedback control module 13 returns the instruction exception information to the debugger, so that the debugger adjusts the initial debugging instructions issued according to the instruction exception information. This can reduce the problem of debugging errors, improve the stability of debugging, and further reduce the "hanging" problem of the debugging system.

[0081] In a possible implementation, see Figure 2 The instruction self-check control module 12 is also used to output a control signal indicating that the instruction is normal to the feedback control module 13 when it is detected that the debugging instruction is normal.

[0082] The feedback control module 13 is further configured to output a second feedback signal indicating that the instruction is normal to the instruction transceiver module 11 in response to the control signal indicating that the instruction is normal.

[0083] The instruction transceiver module 11 is further used to perform format conversion on the second feedback signal, and transmit the second feedback signal after format conversion back to the debugger.

[0084] After receiving the second feedback signal, the instruction transceiver module 11 can convert the second feedback signal transmitted in parallel into the second feedback signal transmitted in serial through its own parallel-to-serial conversion control submodule, and then transmit the second feedback signal back to the debugger.

[0085] In the embodiment of the present application, the instruction self-check control module 12 will not only control the feedback control module 13 to return instruction exception information to the debugger, but also control the feedback control module 13 to return instruction normal information to the debugger. Compared with the traditional debugging method of confirming whether the write configuration is refreshed normally through the write-first-read-then operation method, the present application improves the debugging efficiency of the debugging system through the debugging self-feedback mode.

[0086] In a possible implementation, see Figure 2 The instruction self-check control module 12 is specifically used to obtain the debugging instruction, check whether the debugging instruction belongs to the target category, and output a first control signal to the feedback control module 13 when it is checked that the debugging instruction does not belong to the target category; wherein the target category includes: single write access of the configuration address, continuous write access of the configuration address, write access of the page address, single read access of the configuration address, continuous read access of the configuration address, and read access of the page address.

[0087] The feedback control module 13 is specifically configured to output a first feedback signal indicating that the debugging instruction type is abnormal to the instruction transceiver module 11 in response to the first control signal.

[0088] The debugging system 1 provided by the present application will first check the correctness of the debugging instructions through its own instruction self-checking control module 12. The debugging instructions are divided into two categories: one is the write configuration category, and the other is the read data category. The specific debugging instructions include the following six categories: single write access to the configuration address, continuous write access to the configuration address, write access to the page address, single read access to the configuration address, continuous read access to the configuration address, and read access to the page address. Different access instructions can be configured by the host computer according to different application scenarios.

[0089] The instruction self-check control module 12 checks whether the received debugging instruction belongs to the above six categories (target categories). If it is found that the debugging instruction does not belong to the above six categories, the feedback control module 13 is controlled to send a first feedback signal indicating that the debugging instruction category is abnormal to the debugger.

[0090] In the embodiment of the present application, the instruction self-check control module 12 is used to check whether the debug instruction belongs to the target category. When it is checked that the debug instruction does not belong to the target category, the control feedback control module 13 returns a first feedback signal indicating that the debug instruction category is abnormal to the debugger.

[0091] In a possible implementation, see Figure 2The instruction self-check control module 12 is specifically used to check whether the access address of the debug instruction is in the expected address domain segment when it is checked that the debug instruction belongs to the target category, and output a second control signal to the feedback control module 13 when it is checked that the access address of the debug instruction is not in the expected address domain segment;

[0092] The feedback control module 13 is specifically configured to output a first feedback signal indicating that the debug instruction address is out of bounds to the instruction transceiver module 11 in response to the second control signal.

[0093] When the instruction self-check control module 12 detects that the debugging instruction belongs to the target category, it will perform a logical self-check on the access address of the debugging instruction. For different debugging instructions, the allocated access address domain segments are different. The instruction self-check control module 12 can determine whether the access address of the debugging instruction is in the expected address domain segment based on the boundary value of the access address domain segment.

[0094] When it is detected that the access address of the debug instruction is not in the expected address domain, the control feedback control module 13 returns a first feedback signal indicating that the debug instruction address is out of bounds to the debugger.

[0095] In an embodiment of the present application, the instruction self-check control module 12 is used to check whether the access address of the debug instruction belongs to the expected address domain. When it is checked that the access address of the debug instruction is not in the expected address domain, the control feedback control module 13 returns a first feedback signal to the debugger indicating that the debug instruction address is out of bounds.

[0096] In a possible implementation, see Figure 3 , the feedback control module 13 is connected to the debug conversion control module 14; the instruction self-check control module 12 is specifically used to output the access address of the page accessed by the debug instruction set by itself to the debug conversion control module 14 when it is detected that the access address of the debug instruction is in the expected address domain and the debug instruction is a write access of the page address, and count the number of words of the write configuration data of the debug instruction; when the number of words is less than the expected number of configuration data, output a third control signal to the feedback control module 13.

[0097] The feedback control module 13 is specifically configured to output a first feedback signal indicating that the debug instruction write configuration is abnormal to the instruction transceiver module 11 in response to the third control signal.

[0098] The feedback control module 13 is further configured to output the write configuration data corresponding to the debug instruction set by itself to the debug conversion control module 14 in response to the write configuration data update signal output by the instruction self-check control module 12 .

[0099] The instruction self-check control module 12 is specifically used to delete the part of the write configuration data that exceeds the normal number of words when the number of words exceeds the expected number of configuration data, output the write configuration data with the normal number of words after deletion to the debugging conversion control module 14, and output the third control signal to the feedback control module 13.

[0100] The feedback control module 13 is specifically configured to output a first feedback signal indicating that the debug instruction write configuration is abnormal to the instruction transceiver module 11 in response to the third control signal.

[0101] When the instruction self-check control module 12 detects that the access address of the debug instruction is in the expected address domain and that the debug instruction is a write access to the page address, since the access address and access length of the debug instruction are fixed, the instruction self-check control module 12 will update the default page access address to the debug conversion control module 14. At this time, the access address of the debug instruction issued by the debugger is not output to the debug conversion control module 14. At the same time, when updating the write configuration data, the number of words (number of words) of the write configuration data will be counted.

[0102] If the word count is less than the number of data expected to be configured at the access address, the instruction self-check control module 12 will control the feedback control module 13 to return a first feedback signal indicating an abnormal debug instruction write configuration to the debugger, and will also control the feedback control module 13 to input default write configuration data to the debug conversion control module 14 to prevent the debug system 1 from hanging.

[0103] If the word count exceeds the number of data expected to be configured at the access address, the instruction self-check control module 12 will not output the excess write configuration data to the debug conversion control module 14, and will control the feedback control module 13 to return a first feedback signal indicating an abnormal debug instruction write configuration to the debugger.

[0104] In an embodiment of the present application, the word count of the write configuration data of the write access of the page address is checked through the instruction self-check control module 12. When the word count does not match the expected number of configured data, the feedback control module 13 is controlled to return a first feedback signal indicating a write configuration abnormality to the debugger. When the word count is less than the expected number of configuration data, the feedback control module 13 is also controlled to input default write configuration data to the debug conversion control module 14 to prevent the debug system 1 from hanging.

[0105] In a possible implementation, see Figure 2 The instruction self-check control module 12 is specifically used to output the write configuration data of the debug instruction to the debug conversion control module 14 and output a fourth control signal to the feedback control module 13 when the number of words matches the expected number of configuration data.

[0106] The feedback control module 13 is specifically configured to respond to the fourth control signal and output a second feedback signal indicating that the debug instruction write configuration is normal to the instruction transceiver module 11 .

[0107] In the embodiment of the present application, when the write access instruction of the page address is normal, the instruction self-check control module 12 controls the feedback control module 13 to return a second feedback signal indicating that the write configuration is normal to the debugger.

[0108] In a possible implementation, see Figure 2 The instruction self-check control module 12 is specifically used to output the access address and read access length data of the page accessed by the debug instruction set by itself to the debug conversion control module 14, and output a fifth control signal to the feedback control module 13, when it is detected that the access address of the debug instruction is in the expected address domain and the debug instruction is a read access of the page address.

[0109] The feedback control module 13 is specifically configured to respond to the fifth control signal and output a second feedback signal indicating that the debug instruction read configuration is normal to the instruction transceiver module 11 .

[0110] When the instruction self-check control module 12 detects that the access address of the debug instruction is in the expected address domain and that the debug instruction is a read access of the page address, since the access address and access length of the debug instruction are fixed, the instruction self-check control module 12 will output the default page access address and the default read access length data to the debug conversion control module 14. At this time, the access address and read access length data of the debug instruction issued by the debugger are not output to the debug conversion control module 14.

[0111] In the embodiment of the present application, when the read access instruction of the page address is normal, the instruction self-check control module 12 controls the feedback control module 13 to return a second feedback signal indicating that the read configuration is normal to the debugger.

[0112] In a possible implementation, see Figure 2 The instruction self-check control module 12 is specifically used to check whether the access address of the debug instruction is aligned according to 4 bytes when it is checked that the debug instruction belongs to the target category, and to perform a 4-byte alignment operation on the access address of the debug instruction and output it to the debug conversion control module 14 after checking that the access address of the debug instruction is not aligned according to 4 bytes, and to output a sixth control signal to the feedback control module 13.

[0113] The feedback control module 13 is specifically configured to output a first feedback signal indicating that the debug instruction address is misaligned to the instruction transceiver module 11 in response to the sixth control signal.

[0114] In an example, when debugging configuration, operations are performed in units of Word. One word consists of 4 bytes, and the access address must be 4-byte aligned, that is, the starting address of the data in the memory is a multiple of 4, such as Figure 4 As shown, the access address changes in the following order: 0x000, 0x004, 0x008, 0x00C... This alignment method can improve the efficiency of data access, especially when processing fixed-length data types such as integers and floating-point numbers. The processor is usually faster when accessing aligned data.

[0115] Assume that during debugging, it is necessary to write a word to the access address 0x000, but the access address sent is one of 0x001, 0x002, and 0x003, which is not 4-byte aligned. At this time, the instruction self-check control module 12 will process the data of the access address and complete the 4-byte alignment operation. Assuming that the data of the access address sent is addr_data[15:0], the instruction self-check control module 12 will automatically input {addr_data[15:2], 2'b00} to the debug conversion control module 14 to complete the 4-byte alignment operation.

[0116] In the embodiment of the present application, the instruction self-check control module 12 will perform 4-byte alignment self-check and error correction on the access address to ensure that the debugging system performs debugging operations completely in units of words, and will also control the feedback control module 13 to return a first feedback signal indicating that the debugging instruction address is misaligned to the debugger.

[0117] In a possible implementation, see Figure 2 The instruction self-check control module 12 is specifically used to check whether the length of the read access length data of the debug instruction is 0 when it is checked that the access address of the debug instruction is in the expected address domain segment, and when the debug instruction is any of the single read access of the configuration address and the continuous read access of the configuration address, and when it is checked that the length of the read access length data of the debug instruction is 0, output the read access length data with a length of 1 set by itself to the debug conversion control module 14, and output the seventh control signal to the feedback control module 13;

[0118] The feedback control module 13 is specifically configured to output a first feedback signal indicating that the debug instruction read configuration is abnormal to the instruction transceiver module 11 in response to the seventh control signal.

[0119] In the embodiment of the present application, when the debugging instruction is any of the following types: a single read access of a configuration address or a continuous read access of a configuration address, the instruction self-check control module 12 will perform error correction of the read access length data by "checking 0 and verifying 1" to ensure normal read debugging. At the same time, when the length of the read access length data is 0, the feedback control module 13 will be controlled to return a first feedback signal to the debugger indicating that the debug instruction read configuration is abnormal.

[0120] In a possible implementation, see Figure 2 The instruction self-check control module 12 is specifically used to output the access address and write configuration data of the debug instruction set by itself to the debug conversion control module 14, and output the eighth control signal to the feedback control module 13 when it is detected that the access address of the debug instruction is in the expected address domain segment and when the debug instruction is any of the single write access and continuous write access of the configuration address.

[0121] The feedback control module 13 is specifically configured to respond to the eighth control signal and output a second feedback signal indicating that the debug instruction write configuration is normal to the instruction transceiver module 11 .

[0122] In summary, see Figure 5 The feedback signals returned to the debugger include: a signal indicating that the debug instruction category is abnormal, a signal indicating that the debug instruction address is out of bounds, a signal indicating that the debug instruction write configuration is abnormal, a signal indicating that the debug instruction address is misplaced, a signal indicating that the debug instruction read configuration is abnormal, a signal indicating that the debug instruction write configuration is normal, and a signal indicating that the debug instruction read configuration is normal.

[0123] In a possible implementation, the instruction self-check control module 12 is specifically used to obtain the debugging instruction, and when the encoding method of the 8-bit access control data cmd of the debugging instruction is a one-hot code, the 8-bit access control data cmd of the debugging instruction is bit-wise judged, and when the result of the bitwise addition is constantly 1 and the upper 2 bits are constantly 0, it is determined that the debugging instruction belongs to the target category, otherwise it is determined that the debugging instruction does not belong to the target category.

[0124] As mentioned above, there are six types of debugging instructions cmd, including: single write access to configuration address, continuous write access to configuration address, write access to page address, single read access to configuration address, continuous read access to configuration address, and read access to page address. Assuming that the encoding is performed according to One-Hot Code (a coding method characterized by the number of bits as many as the number of states, and only one bit is 1 at any time, and the rest of the bits are 0), the 8-bit cmd data only needs to use the lower 6 bits. When the instruction self-check control module 12 performs self-check, the 8-bit cmd is bit-judged. If the result of the bitwise addition is always 1, and the high 2 bits of the 8-bit cmd data are always 0, it can be confirmed that the debugging instruction cmd issued by the debugger is normal (the debugging instruction belongs to the target category), otherwise it is abnormal (the debugging instruction does not belong to the target category). In the case where the encoding method is other encoding methods, it can also be checked by bit judgment, but the judgment conditions are different.

[0125] In a possible implementation, the instruction self-check control module 12 is specifically used to check the boundary value of the access address of the debug instruction when it is detected that the debug instruction belongs to the target category, and when the boundary value is within the expected address domain, determine that the access address of the debug instruction is within the expected address domain; otherwise, determine that the access address of the debug instruction is not within the expected address domain.

[0126] Different debugging instructions correspond to different access address domain segments. Figure 6 To illustrate, assume that there are two debugging instructions, cmd1 and cmd2, the access address domain corresponding to cmd1 is 0x000-0x100 (expected address domain), and the access address domain corresponding to cmd2 is 0x100-0x200 (expected address domain). After receiving cmd1, the instruction self-check control module 12 will perform boundary value judgment on the access address of cmd1. If the boundary value of the access address of cmd1 is not in the range of 0x000-0x100, it is determined that the access address of cmd1 is not in the expected address domain.

[0127] In one possible implementation, based on Figure 1 The debugging system structure shown in Figure 7 The debugging system 1 also includes a multiplexing module 15.

[0128] The control end of the multiplexing module 15 is connected to the instruction self-checking control module 12 , the first input end of the multiplexing module 15 is connected to the feedback control module 13 , and the second input end of the multiplexing module 15 is connected to the debugging conversion control module 14 .

[0129] The instruction self-check control module 12 is further used to output the first level signal or the second level signal to the control end of the multiplexing module 15 .

[0130] The multiplexing module 15 is used to, when its own control end receives a first level signal, turn on the first channel corresponding to its own first input end, so that the feedback control module 13 outputs a first feedback signal indicating an abnormal instruction and a second feedback signal indicating a normal instruction to the debugger; when its own control end receives a second level signal, turn on the second channel corresponding to its own second input end, so that the debugging conversion control module 14 returns the read data information to the debugger.

[0131] In the embodiment of the present application, the multiplexing module 15 is selected so that the feedback control module 13 returns the first feedback signal and the second feedback signal to the debugger, so that the debugging conversion control module 14 returns the read data information to the debugger.

[0132] In one possible implementation, based on Figure 2 The debugging system structure shown in Figure 8 The debugging system 1 also includes a multiplexing module 15; the control end of the multiplexing module 15 is connected to the instruction self-check control module 12, the first input end of the multiplexing module 15 is connected to the feedback control module 13, the second input end of the multiplexing module 15 is connected to the debugging conversion control module 14, and the output end of the multiplexing module 15 is connected to the instruction transceiver module 11.

[0133] The instruction self-check control module 12 is further used to output the first level signal or the second level signal to the control end of the multiplexing module 15 .

[0134] The multiplexing module 15 is used to connect its first input terminal and output terminal when its control terminal receives a first level signal, so that the feedback control module 13 outputs a first feedback signal indicating an abnormal instruction and a second feedback signal indicating a normal instruction to the instruction transceiver module 11; when its control terminal receives a second level signal, its second input terminal and output terminal are connected.

[0135] The debugging conversion control module 14 is further configured to return the read data information to the instruction transceiver module 11 through the second input terminal of the multiplexing module 15 .

[0136] In the embodiment of the present application, the multiplexing module 15 is selected so that the feedback control module 13 returns the first feedback signal and the second feedback signal to the debugger, so that the debugging conversion control module 14 returns the read data information to the debugger.

[0137] In one possible implementation, based on Figure 8 The debugging system structure shown in Fig. 9 The instruction transceiver module 11 includes a serial-to-parallel conversion control submodule 111, a parallel-to-serial conversion control submodule 112, and an instruction decoding control submodule 113; the serial-to-parallel conversion control submodule 111 is respectively connected to the debugger and the instruction decoding control submodule 113, the parallel-to-serial conversion control submodule 112 is respectively connected to the debugger and the multiplexing module 15, and the instruction decoding control submodule 113 is connected to the instruction self-check control module 12.

[0138] The serial-to-parallel conversion control submodule 111 obtains the initial debugging instruction, converts the initial debugging instruction of serial transmission into a parallel transmission mode, and then obtains the debugging instruction through decoding and analysis by the instruction decoding control submodule 113 .

[0139] The parallel-to-serial conversion control submodule 112 obtains the first feedback signal, converts the first feedback signal transmitted in parallel into the first feedback signal transmitted in serial, and transmits the first feedback signal transmitted in serial back to the debugger.

[0140] The parallel-to-serial conversion control submodule 112 obtains the second feedback signal, converts the second feedback signal transmitted in parallel into the second feedback signal transmitted in serial, and transmits the second feedback signal transmitted in serial back to the debugger.

[0141] In the embodiment of the present application, the serial-to-parallel conversion control submodule 111 converts the initial debugging instruction of serial transmission into a parallel transmission mode, and then the instruction decoding control submodule 113 performs decoding and parsing operations to obtain the debugging instruction; the parallel-to-serial conversion control submodule 112 converts the first feedback signal of parallel transmission into the first feedback signal of serial transmission, and converts the second feedback signal of parallel transmission into the second feedback signal of serial transmission. The above submodules realize the format conversion of each signal.

[0142] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0143] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0144] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A debugging system, characterized in that: The system comprises: Instruction self-check control module, feedback control module; The instruction self-check control module is connected to the feedback control module; The instruction self-check control module is used to obtain the debugging instruction of the debugger, check the debugging instruction, and output a control signal indicating the instruction abnormality to the feedback control module when the debugging instruction is found to be abnormal; The feedback control module is used to output a first feedback signal indicating an instruction abnormality to the debugger in response to the control signal indicating an instruction abnormality, so that the debugger adjusts the debugging instruction.

2. The system according to claim 1, characterized in that The system also includes a debugging conversion control module; The debugging conversion control module is connected to the instruction self-checking control module; The instruction self-check control module is further used to output the debugging instruction to the debugging conversion control module when the debugging instruction is detected to be normal; The debugging conversion control module is used to receive the debugging instruction and transmit the debugging instruction to the device to be debugged.

3. The system according to claim 1, characterized in that The instruction self-check control module is further used to output a control signal indicating that the instruction is normal to the feedback control module when the debugging instruction is detected to be normal; The feedback control module is further configured to output a second feedback signal indicating that the instruction is normal to the debugger in response to the control signal indicating that the instruction is normal.

4. The system according to claim 1, characterized in that The instruction self-check control module is specifically used to obtain the debugging instruction, check whether the debugging instruction belongs to a target category, and output a first control signal to the feedback control module when it is checked that the debugging instruction does not belong to the target category; wherein the target category includes: single write access of a configuration address, continuous write access of a configuration address, write access of a page address, single read access of a configuration address, continuous read access of a configuration address, and read access of a page address; The feedback control module is specifically configured to output a first feedback signal indicating an abnormal debugging instruction category to the debugger in response to the first control signal.

5. The system according to claim 4, characterized in that The instruction self-check control module is specifically used to check whether the access address of the debug instruction is in the expected address domain segment when it is checked that the debug instruction belongs to the target category, and output a second control signal to the feedback control module when it is checked that the access address of the debug instruction is not in the expected address domain segment; The feedback control module is specifically configured to output a first feedback signal indicating that the debug instruction address is out of bounds to the debugger in response to the second control signal.

6. The system according to claim 5, characterized in that The feedback control module is connected to the debugging conversion control module; The instruction self-check control module is specifically used to output the access address of the page accessed by the debug instruction set by itself to the debug conversion control module when it is detected that the access address of the debug instruction is in the expected address domain segment and the debug instruction is a write access of the page address, and count the number of words of the write configuration data of the debug instruction; when the number of words is less than the expected number of configuration data, output a third control signal to the feedback control module; The feedback control module is specifically configured to output a first feedback signal indicating that the debug instruction write configuration is abnormal to the debugger in response to the third control signal; The feedback control module is further configured to output the write configuration data corresponding to the debug instruction set by itself to the debug conversion control module in response to the write configuration data update signal output by the instruction self-check control module; The instruction self-check control module is specifically used to delete the part of the write configuration data that exceeds the normal number of words when the number of words exceeds the expected number of configuration data, output the write configuration data with the normal number of words after deletion to the debugging conversion control module, and output the third control signal to the feedback control module; The feedback control module is specifically configured to output a first feedback signal indicating that the debug instruction write configuration is abnormal to the debugger in response to the third control signal.

7. The system according to claim 6, characterized in that The instruction self-check control module is specifically used to output the write configuration data of the debug instruction to the debug conversion control module and output a fourth control signal to the feedback control module when the number of words matches the expected number of configuration data; The feedback control module is specifically configured to respond to the fourth control signal and output a second feedback signal to the debugger indicating that the debug instruction write configuration is normal.

8. The system according to claim 5, characterized in that The instruction self-check control module is specifically used to output the access address and read access length data of the page accessed by the debug instruction set by itself to the debug conversion control module, and output a fifth control signal to the feedback control module when it is detected that the access address of the debug instruction is in the expected address domain segment and the debug instruction is a read access of the page address; The feedback control module is specifically configured to respond to the fifth control signal and output a second feedback signal to the debugger indicating that the debug instruction read configuration is normal.

9. The system according to claim 4, characterized in that The instruction self-check control module is specifically used to check whether the access address of the debug instruction is aligned according to 4 bytes when it is checked that the debug instruction belongs to the target category, and if it is checked that the access address of the debug instruction is not aligned according to 4 bytes, perform a 4-byte alignment operation on the access address of the debug instruction and then output it to the debug conversion control module, and output a sixth control signal to the feedback control module; The feedback control module is specifically configured to output a first feedback signal indicating a debug instruction address misalignment to the debugger in response to the sixth control signal.

10. The system according to claim 5, characterized in that The instruction self-check control module is specifically used to check whether the length of the read access length data of the debug instruction is 0 when it is checked that the access address of the debug instruction is in the expected address domain segment, and when the debug instruction is any one of a single read access of the configuration address and a continuous read access of the configuration address, and when it is checked that the length of the read access length data of the debug instruction is 0, output the read access length data with a length of 1 set by itself to the debug conversion control module, and output a seventh control signal to the feedback control module; The feedback control module is specifically configured to output a first feedback signal indicating that the debug instruction read configuration is abnormal to the debugger in response to the seventh control signal.

11. The system according to claim 4, characterized in that The instruction self-check control module is specifically used to obtain the debugging instruction, and when the encoding method of the 8-bit access control data of the debugging instruction is a one-hot code, the 8-bit access control data of the debugging instruction is bit-wise judged, and when the result of the bitwise addition is constantly 1 and the upper 2 bits are constantly 0, it is determined that the debugging instruction belongs to the target category, otherwise it is determined that the debugging instruction does not belong to the target category.

12. The system according to claim 5, characterized in that The instruction self-check control module is specifically used to check the boundary value of the access address of the debug instruction when it is detected that the debug instruction belongs to the target category. When the boundary value is located in the expected address domain, it is determined that the access address of the debug instruction is in the expected address domain; otherwise, it is determined that the access address of the debug instruction is not in the expected address domain.

13. The system according to claim 3, characterized in that The system also includes a multiplexing module; The control end of the multiplexing module is connected to the instruction self-checking control module, the first input end of the multiplexing module is connected to the feedback control module, and the second input end of the multiplexing module is connected to the debugging conversion control module; The instruction self-check control module is further used to output the first level signal or the second level signal to the control end of the multiplexing module; The multiplexing module is used to, when its own control end receives a first level signal, turn on the first channel corresponding to its own first input end, so that the feedback control module outputs a first feedback signal indicating an abnormal instruction and a second feedback signal indicating a normal instruction to the debugger; when its own control end receives a second level signal, turn on the second channel corresponding to its own second input end, so that the debugging conversion control module returns the read data information to the debugger.

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