Design method for generating electronic component symbols through multi-mode large language model

Abstract

The invention belongs to the field of electronic design automation, and provides a design method for generating electronic component symbols through a multi-mode large language model. The method aims at automatically processing and analyzing data tables in different formats by using a multi-modal large language model, and the problem of data table type isomerism is solved. Through an automated process, the MLLM automatically generates symbols based on the data table. The MLLM is guided to generate a more accurate result through a designed query process and a data set for providing context examples. In the symbol generation process, the model learns and creates a readable symbol file by considering factors such as the size of a polygon, interconnection between lines and polygons, the distance between the lines, a text format and the like. And finally, carrying out evaluation processing on the quality of the generated electronic component symbol to realize quantitative evaluation on the quality of the electronic component symbol.

Description

Technical Field

[0001] The invention belongs to the field of electronic design automation and provides a design method for generating electronic component symbols using a multi-modal large language model. Background Art

[0002] A complete and accurate PCB component library is the foundation of PCB design, providing designers with a set of predefined electronic components for circuit schematics and PCB layout. Such libraries provide a comprehensive set of resources, including data sheets, schematic symbols, and 3D models.

[0003] Traditionally, companies have manually created symbols from datasheets to build component libraries. However, this manual process is laborious and error-prone. In addition, datasheet formats vary widely from manufacturer to manufacturer, complicating the implementation of a standardized design process. The varying requirements of various electronic design automation (EDA) software further add to the challenge, making it difficult to reuse library resources across design platforms, thereby increasing development costs. With new components emerging on the market every year, a more efficient method for developing component libraries is essential to keep pace with technological advancements and market demands.

[0004] The heterogeneous format of datasheets and the lack of large-scale datasets make it difficult for traditional AI methods to capture component design details. However, multimodal large language models (MLLM) and hint engineering techniques provide a promising solution to extract key information from datasheets and generate accurate design files. Thanks to its extensive knowledge, MLLM can meet challenges without retraining. On the other hand, as electronic designs become more complex, AI-assisted PCB design points out an opportunity to significantly shorten the design cycle while ensuring high design quality. Automatic component library construction is a necessary foundation for MLLM to understand and create PCB designs.

[0005] Large language models (LLMs) with billions of parameters, such as GPT, Gemini, and LLama, have demonstrated impressive capabilities in handling complex tasks in a variety of domains, including code generation, mathematics, science, and electronic design automation (EDA). Advanced MLLMs, such as GPT-4 and Qwen-VL, extend their versatility by providing more flexible and user-friendly interfaces, enabling them to process and understand additional modalities, such as vision. Their ability to handle multimodal inputs enables MLLMs to interpret component specifications in various formats, including lists, tables, and images, making them well suited for processing component datasheets. However, PCB design has a low tolerance for errors in component libraries. Directly using MLLMs for component design generation may lead to unsatisfactory results, such as incorrect pin counts and inaccurate dimensions of created shapes. This demonstrates the importance of specific query flows and datasets that provide contextual examples that guide MLLMs to generate more accurate results.

[0006] In general, the defects of the prior art are as follows:

[0007] 1. The process of manually creating symbols is time-consuming and error-prone. Engineers need to extract detailed information from data sheets and then manually create symbols that are compatible with EDA software. This process is not only inefficient, but also prone to errors due to human factors.

[0008] 2. Heterogeneity of data table formats. The data table formats provided by different manufacturers vary greatly, which brings challenges to the construction of automated component libraries. Traditional AI methods have difficulty processing such heterogeneous data, which affects the accuracy and efficiency of the automation process.

[0009] 3. Lack of large-scale datasets. Due to the diversity and complexity of electronic components, it is a challenge to build a large dataset containing data on various components. The lack of such a dataset limits the ability of traditional AI methods to capture component design details.

[0010] 4. Limitations of directly using MLLM for component design generation. Although MLLM has potential in handling multimodal inputs, directly using MLLM for component design generation may lead to unsatisfactory results, such as incorrect pin counts and inaccurate sizes of generated symbols. Summary of the invention

[0011] This paper proposes a design method for generating electronic component symbols using a multimodal large language model (MLLM), aiming to solve the problems of low efficiency and error-proneness in the traditional manual symbol creation process, as well as the challenges brought by the heterogeneity of data table formats and the lack of large-scale data sets. At the specific technical implementation level, this paper solves the following key problems:

[0012] Data heterogeneity processing: By using a multimodal large language model (MLLM), it can process and parse data tables of different formats, thus solving the problem of data table format heterogeneity. MLLM can understand and process component specifications in various formats including lists, tables, and images.

[0013] Efficient and automated generation: In traditional methods, symbols for electronic components need to be created manually, which is inefficient and error-prone. This invention uses MLLM to automatically generate symbols based on data tables through an automated process, greatly improving efficiency.

[0014] Improved precision and accuracy: Directly using MLLM for component design generation may lead to unsatisfactory results, such as incorrect number of pins and inaccurate size of generated symbol shapes. The present invention guides MLLM to generate more accurate results by designing a specific query process and providing a data set of contextual examples.

[0015] Learning and optimization of logical and spatial position parameters: Learning to create readable symbol files during the symbol generation process by taking into account factors such as polygon size, interconnection between lines and polygons, spacing between lines, and text formatting.

[0016] In general, the present invention mainly solves key problems such as data heterogeneity processing, automatic generation, precision and accuracy improvement, logic and spatial parameter learning optimization, and quality assessment quantification at the technical implementation level.

[0017] The present invention provides a design method for generating electronic component symbols using a multimodal large language model, comprising the following steps:

[0018] Step 1: Collect and preprocess data: Collect data tables containing pin configuration and pin function description details from the Internet and electronic design automation (EDA) software;

[0019] Step 1.1, collect <data table, symbol> data pairs from the Internet and EDA software;

[0020] Step 1.2, select a diverse subset of components based on the number of pads and component types;

[0021] Step 2: Define the conditional text generation problem for electronic component symbol generation;

[0022] Step 2.1, define the component symbol generation task as a conditional text generation problem;

[0023] Step 2.2, automatically generate symbols based on the provided component data table;

[0024] Step 3: Develop a symbol generation design process based on a multimodal large language model;

[0025] Step 3.1: Use the dataset Where (x j ,y j ) is the jth sample of the dataset, a (input constraint, output text) pair, and M is the total number of samples;

[0026] Step 3.2: Provide k samples As an ICL example, where x j and j are constraint and target files, respectively, where ICL stands for contextual learning;

[0027] Step 3.3: Based on constraint x test The goal is to generate high-quality component library symbol files y test ;

[0028] Step 3.4, design the prompt P to integrate the input constraints, ICL examples, task description and other relevant information;

[0029] Step 3.5: Introduce Chain-of-Thought (CoT) in the prompt to enhance the model’s ability to logically process input information.

[0030] Step 3.6: Integrate the prompt P into the MLLM, where P = [R; x1; y1; ...; x k ;y k ;x test ], R is the task description, x1 to x k is the constraint of the ICL example, y1 to y k is the corresponding target file, x test is the constraint of the current input; Sub-step 2.7, generate the component library file y that meets the constraint by processing the integrated prompt P through MLLM test .

[0031] Step 4: Use MLLM to automatically parse the input data table, extract the spatial position parameters and pin types, and combine the prompt word engineering and MLLM to realize the symbol generation process;

[0032] Step 4.1, use MLLM to process the input and provide the necessary logical and spatial location parameters to generate a symbol file that meets the constraints;

[0033] Step 4.2, assemble a small number of ICL examples containing pin function descriptions, configurations and corresponding symbol files;

[0034] Step 4.3. Learn to create readable symbol files by considering aspects such as polygon size, interconnection between lines and polygons, spacing between lines, and text formatting;

[0035] Step 4.4: Include the chain of thought CoT in the prompt to guide the model to process the input information more logically and improve the accuracy of symbol generation;

[0036] Step 5: By evaluating the quality of the generated electronic component symbol, a quantitative evaluation of its quality is achieved;

[0037] Step 5.1, a set of evaluation metrics are defined to quantify the quality of the generated symbols, including ACCN and ACCT;

[0038] Step 5.1.1. Calculate the accuracy index ACCN, which is used to measure the ratio of the number of correctly identified pins to the total number in the generated symbol:

[0039]

[0040] Step 5.1.2. Calculate the accuracy indicator ACCT, which is used to measure the ratio of the number of correctly recognized shapes to the total number in the generation:

[0041]

[0042] This paper proposes a design method for generating electronic component symbols using a multimodal large language model (MLLM), aiming to solve the inefficiency and error-proneness of the traditional manual symbol creation process, as well as the challenges brought by the heterogeneity of data table formats and the lack of large-scale data sets. In terms of specific technical implementation, this paper solves the following key problems:

[0043] Data heterogeneity processing: By using a multimodal large language model (MLLM), it can process and parse data tables of different formats, thus solving the problem of data table format heterogeneity. MLLM can understand and process component specifications in various formats including lists, tables, and images.

[0044] Efficient and automated generation: In traditional methods, symbols for electronic components need to be created manually, which is inefficient and error-prone. The present invention greatly improves efficiency by automating the process and using MLLM to automatically generate symbols based on data tables.

[0045] Improved precision and accuracy: Directly using MLLM for component design generation may lead to unsatisfactory results, such as incorrect number of pins and inaccurate size of generated symbol shapes. The present invention guides MLLM to generate more accurate results by designing a specific query process and providing a data set of contextual examples.

[0046] Learning and optimization of logical and spatial position parameters: Learning to create readable symbol files during the symbol generation process by taking into account factors such as polygon size, interconnection between lines and polygons, spacing between lines, and text formatting.

[0047] Quantification of quality assessment: By evaluating the quality of the generated electronic component symbols, a quantitative assessment of their quality is achieved, including accuracy indicators ACCN and ACCT.

[0048] In general, the present invention mainly solves key problems such as data heterogeneity processing, automatic generation, precision and accuracy improvement, logic and spatial parameter learning optimization, and quality assessment quantification at the technical implementation level. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 :Comparison between traditional design method and SFgen of this application;

[0050] Figure 2 : An embodiment of a symbol generation process;

[0051] Figure 3 : Example of symbol generation prompt;

[0052] Figure 4 : Visualization results of the generated symbols. DETAILED DESCRIPTION

[0053] The following is a detailed description of the embodiments of the present invention. Although the present invention will be described and illustrated in conjunction with some specific embodiments, it should be noted that the present invention is not limited to these embodiments. On the contrary, modifications or equivalent substitutions made to the present invention should all be included in the scope of the claims of the present invention.

[0054] In addition, in order to better illustrate the present invention, numerous specific details are given in the following specific embodiments. It will be understood by those skilled in the art that the present invention can also be implemented without these specific details.

[0055] The present invention provides a design method for generating electronic component symbols using a multimodal large language model, comprising the following steps:

[0056] Step 1: Collect and preprocess data: Collect data tables containing pin configuration and pin function description details from the Internet and electronic design automation (EDA) software;

[0057] Step 1.1, collect <data table, symbol> data pairs from the Internet and EDA software;

[0058] Step 1.2, select a diverse subset of components based on the number of pads and component types;

[0059] Step 2: Define the conditional text generation problem for electronic component symbol generation;

[0060] Step 2.1, define the component symbol generation task as a conditional text generation problem;

[0061] Step 2.2, automatically generate symbols based on the provided component data table;

[0062] Step 3: Develop a symbol generation design process based on a multimodal large language model;

[0063] Step 3.1: Use the dataset Where (x j ,y j ) is the jth sample of the dataset, a (input constraint, output text) pair, and M is the total number of samples;

[0064] Step 3.2: Provide k samples As an ICL example, where x j and j They are constraint and target files respectively;

[0065] Step 3.3: Based on constraint x test The goal is to generate high-quality component library symbol files y test ;

[0066] Step 3.4, design the prompt P to integrate the input constraints, ICL examples, task description and other relevant information;

[0067] Step 3.5: Introduce Chain-of-Thought (CoT) in the prompt to enhance the model’s ability to logically process input information.

[0068] Step 3.6: Integrate the prompt P into the MLLM, where P = [R; x1; y1; ...; x k ;y k ;x test ], R is the task description, x1 to x k is the constraint of the ICL example, y1 to y k is the corresponding target file, x test is the constraint of the current input; Sub-step 2.7, generate the component library file y that meets the constraint by processing the integrated prompt P through MLLM test .

[0069] Step 4: Use MLLM to automatically parse the input data table, extract the spatial position parameters and pin types, and combine the prompt word engineering and MLLM to realize the symbol generation process;

[0070] Step 4.1, automatically generate corresponding symbols according to the input data table;

[0071] Step 4.2, use MLLM to process the input and provide the necessary logical and spatial location parameters to generate a symbol file that meets the constraints;

[0072] Step 4.3, assemble a small number of ICL examples containing pin function descriptions, configurations and corresponding symbol files;

[0073] Step 4.4. Learn to create readable symbol files by considering aspects such as polygon size, interconnection between lines and polygons, spacing between lines, and text formatting;

[0074] Step 4.5: Include the chain of thought CoT in the prompt to guide the model to process the input information more logically and improve the accuracy of symbol generation;

[0075] Step 5: By evaluating the quality of the generated electronic component symbol, a quantitative evaluation of its quality is achieved;

[0076] Step 5.1, a set of evaluation metrics are defined to quantify the quality of the generated symbols, including ACCN and ACCT;

[0077] Step 5.1.1. Calculate the accuracy index ACCN, which is used to measure the ratio of the number of correctly identified pins to the total number in the generated symbol:

[0078]

[0079] Step 5.1.2. Calculate the accuracy indicator ACCT, which is used to measure the ratio of the number of correctly recognized shapes to the total number in the generation:

[0080]

[0081] experiment

[0082] The present invention implements the SFgen framework and conducts experiments using the state-of-the-art MLLM, GPT4. All experiments are performed via API calls. The complete prompt is as follows Figure 3 .

[0083] Symbol generation results

[0084] As mentioned before, two metrics, ACCN and ACCT, are used to measure the quality of generated symbols.

[0085] Table 1 categorizes the components by their serial number prefix. “Num” indicates the number of components in each category. The results show that ACCN reaches 100%, indicating that SFgen accurately reflects the number of pins in the datasheet in the symbol file. The average ACCT is 98.6%, which shows that SFgen is able to identify the pin function in most cases.

[0086]

[0087]

[0088] Figure 4 An example of the comparison of the generated symbols with the true value (GT) is shown. The visualization verifies that the symbols generated by SFgen are visually consistent with the GT. At the same time, they are highly accurate in terms of functional layout. In addition, SFgen successfully addresses certain finer requirements, such as correct pin labels and locations, and ensures that the symbols are easy to read. The high level of consistency and accuracy demonstrates the reliability and effectiveness of SFgen in real-world applications, making it a promising tool to replace the laborious design process.

Claims

1. A design method for generating electronic component symbols using a multimodal large language model, characterized in that: The following steps are involved: Step 1. Collect and preprocess data: Collect data tables containing pin configuration, pin function description, pin name, location and type from the Internet and electronic design automation software; Step 2: Define the conditional text generation problem for electronic component symbol generation; Step 3: Develop a symbol generation design process based on a multimodal large language model; Step 4: Use MLLM to automatically parse the input data table, extract the spatial position parameters and pin types, and combine the prompt word engineering and MLLM to realize the symbol generation process; Step 5: By evaluating the quality of the generated electronic component symbol, a quantitative evaluation of its quality is achieved.

2. The design method for generating electronic component symbols using a multimodal large language model according to claim 1, characterized in that: Step 1 includes: Step 1.1, collect <data table, symbol> data pairs from the Internet and EDA software; Step 1.

2. Select a diverse subset of components based on the number of pads and component type.

3. The design method for generating electronic component symbols using a multimodal large language model according to claim 1, characterized in that: Step 2 includes: Step 2.1, define the component symbol generation task as a conditional text generation problem; Step 2.2: Automatically generate symbols based on the provided component datasheet.

4. The design method for generating electronic component symbols using a multimodal large language model according to claim 1, characterized in that: Step 3 includes: Step 3.1: Use the dataset Where (x j ,y j ) is the jth sample of the dataset, a (input constraint, output text) pair, and M is the total number of samples; Step 3.2: Provide k samples As an ICL example, where x j and j are constraint and target files, respectively, where ICL stands for contextual learning; Step 3.3: Based on constraint x test The goal is to generate high-quality component library symbol files y test ; Step 3.4, design the prompt P to integrate the input constraints, ICL examples, task description and other relevant information; Step 3.5: Introduce the chain of thought CoT in the prompt to enhance the model's ability to logically process input information; Step 3.6: Integrate the prompt P into the MLLM, where P = [R; x1; y1; ...; x k ;y k ;x test ], R is the task description, x1 to x k is the constraint of the ICL example, y1 to y k is the corresponding target file, x test is the constraint of the current input; Step 3.7: Process the integrated prompt P through MLLM to generate a component library file y that meets the constraints test .

5. The design method for generating electronic component symbols using a multimodal large language model according to claim 1, characterized in that: Step 4 includes: Step 4.1, use MLLM to process the input and provide the necessary logical and spatial location parameters to generate a symbol file that meets the constraints; Step 4.2, assemble a small number of ICL examples containing pin function descriptions, configurations and corresponding symbol files; Step 4.

3. Learn to create readable symbol files by considering aspects such as polygon size, interconnection between lines and polygons, spacing between lines, and text formatting; Step 4.4: Include the chain of thought CoT in the prompt to guide the model to process the input information more logically and improve the accuracy of symbol generation.

6. The design method for generating electronic component symbols using a multimodal large language model according to claim 1, characterized in that: The Mule 5 includes: Step 5.1, a set of evaluation metrics are defined to quantify the quality of the generated symbols, including ACCN and ACCT; Step 5.1.

1. Calculate the accuracy index ACCN, which is used to measure the ratio of the number of correctly identified pins to the total number in the generated symbol: Step 5.1.

2. Calculate the accuracy index ACCT, which is used to measure the ratio of the number of correctly recognized shapes to the total number of shapes in the generated symbols:

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