Data transfer circuit, SRAM (Static Random Access Memory) storage circuit, near storage convolution operation unit and chip system

Abstract

The invention provides a data transfer circuit, an SRAM (Static Random Access Memory) storage circuit, a near memory convolution operation unit and a chip system. The digital transfer circuit comprises a first transistor, a second transistor, a third transistor and a fourth transistor, a grid electrode of the first transistor is connected with a first bit line of the storage circuit; a grid electrode of the second transistor is connected with a second bit line of the storage circuit; the first electrode of the first transistor is connected with the first electrode of the fourth transistor; the first electrode of the second transistor is connected with the first electrode of the third transistor; the second electrode of the first transistor and the second electrode of the second transistor are respectively connected with the ground; a second electrode of the third transistor is connected with a first selection line of the storage circuit; a second electrode of the fourth transistor is connected with a second selection line of the storage circuit; the grid electrode of the third transistor and the grid electrode of the fourth transistor are connected with a first control signal.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to a data transfer circuit, an SRAM storage circuit, a near-memory convolution operation unit and a chip system. Background Art

[0002] The development of computing in memory (CIM) has not only overturned the traditional computing architecture, but also greatly promoted the progress of processors, computing architecture and computing models. It effectively solves the power consumption and speed bottlenecks caused by the separation of storage and computing in the von Neumann architecture, and realizes the design concept of integrated storage and computing. By shortening the distance between the computing unit and the memory, the computing in memory method gives the memory computing power, thereby effectively solving the energy efficiency problem caused by frequent data movement in the traditional computing architecture, and further breaking through the bottleneck of energy efficiency and memory access speed.

[0003] Therefore, exploring the in-memory computing implementation scheme of hybrid storage of MRAM (Magnetic Random Access Memory) or RRAM (Resistive Random-Access Memory) and SRAM (Static Random-Access Memory) has become a feasible computing architecture. This hybrid storage aims to take advantage of the non-volatility and high-density storage of MRAM or RRAM to achieve effective storage of weights; at the same time, it uses the high performance of SRAM and its natural compatibility with digital computing units to complete data caching and computing processes. Through this combination, it is expected to achieve a low-power, high-precision in-memory computing implementation method, providing new possibilities for future computing system architectures. Summary of the invention

[0004] In view of this, the present application provides a data transfer circuit and an SRAM storage circuit for providing an in-memory computing implementation method with low power consumption and high computing accuracy.

[0005] In the first aspect, an embodiment of the present application provides a data transfer circuit, which is used to assist a data storage circuit connected to the data transfer circuit in performing data transfer; the digital transfer circuit includes: a first transistor, a second transistor, a third transistor and a fourth transistor; the gate of the first transistor is connected to the first bit line of the storage circuit; the gate of the second transistor is connected to the second bit line of the storage circuit; the first electrode of the first transistor is connected to the first electrode of the fourth transistor; the first electrode of the second transistor is connected to the first electrode of the third transistor; the second electrode of the first transistor and the second electrode of the second transistor are respectively connected to the ground; the second electrode of the third transistor is connected to the first selection line of the storage circuit; the second electrode of the fourth transistor is connected to the second selection line of the storage circuit; the gates of the third transistor and the fourth transistor are respectively connected to the first control signal.

[0006] Optionally, the storage circuit includes: a magnetic random access memory and a static random access memory.

[0007] Optionally, the magnetic random access memory includes a transistor and a magnetic tunnel junction, the gate of the transistor is connected to the bit line of the storage circuit, the first end of the magnetic tunnel junction is connected to the word line of the storage circuit, and the second end of the magnetic tunnel junction is connected to the corresponding transistor.

[0008] Optionally, in the precharging stage, the voltages of the first bit line and the second bit line are precharged to the power supply voltage; the word line connected to the storage circuit and the first signal are turned on to establish a discharge path; the voltage difference formed by the discharge speed difference between the first bit line and the second bit line is the input voltage of the static random access memory.

[0009] Optionally, during the discharge process, the first transistor and the second transistor form negative feedback to generate a stable voltage difference; the gate voltage of the first transistor and the gate voltage of the second transistor are controlled to adjust the size of the channel current to achieve data amplification and transmission; the data is transmitted from the storage unit of the magnetic random access memory through the first transistor and the second to the input port of the static random access memory and written into the static random access memory.

[0010] In a second aspect, an embodiment of the present application provides an SRAM storage circuit, wherein data is transferred to the SRAM storage circuit using the data transfer circuit as described in the first aspect; the SRAM storage circuit comprises: a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor and a sixteenth transistor; the gate of the ninth transistor is connected to the first enable signal, the first electrode of the ninth transistor is respectively connected to the first electrode of the tenth transistor and the first electrode of the twelfth transistor; the second electrode of the tenth transistor is respectively connected to the first electrode of the eleventh transistor, the gate of the twelfth transistor, the fifteenth transistor and the sixteenth transistor The gate of the tenth transistor is connected to the gate of the fourteenth transistor, the second electrode of the twelfth transistor, the first electrode of the thirteenth transistor and the first electrode of the fifteenth transistor respectively; the gate of the eleventh transistor is connected to the word line, and the second electrode of the eleventh transistor is connected to the first bit line; the gate of the thirteenth transistor is connected to the word line, and the second electrode of the thirteenth transistor is connected to the second bit line; the second electrode of the fourteenth transistor is connected to the second electrode of the fifteenth transistor and the first electrode of the sixteenth transistor; the gate of the sixteenth transistor is connected to the second enable signal, and the second electrode of the sixteenth transistor is grounded.

[0011] Optionally, during data transmission, the word line in the SRAM storage circuit controls the first enable signal and the second enable signal to be turned on, and the generated voltage difference is latched into the SRAM storage circuit to complete the transfer of the data.

[0012] In a third aspect, an embodiment of the present application provides a near-memory convolution operation unit, which includes: a data transfer circuit as described in the first aspect and an SRAM storage circuit as described in the second aspect; the near-memory convolution operation unit uses the data transfer circuit to transfer data from the magnetic random access memory to the SRAM storage circuit.

[0013] Optionally, at least two near-memory convolution operation units as described in claim 8 are connected through an accumulator, and the operation result is output through the accumulator.

[0014] In a fourth aspect, an embodiment of the present application provides a chip system, comprising a near-memory convolution operation unit as described in any one of the third aspects, and the chip system is used to complete the convolution operation included in the chip system according to the near-memory convolution operation unit.

[0015] The data transfer circuit provided in the embodiment of the present application can achieve stable voltage difference output through the cross-coupling structure of transistors, reduce the complexity of timing design, and can generate more than twice the voltage difference of the traditional method, thereby significantly enhancing the accuracy of data transfer.

[0016] The SRAM storage circuit provided in the embodiment of the present application uses an 8T (transistor) SRAM structure to cut off the strong feedback connection of the end-to-end connected inverters during data transfer, thereby improving the stability and accuracy of data transfer. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1A It is a schematic diagram of data interaction between SRAM-NVM storage arrays provided in an embodiment of the present application;

[0018] Figure 1B It is a storage bit-level data interaction provided by an embodiment of the present application-nvSRAM (storage bit schematic diagram;

[0019] Figure 2 It is a schematic diagram of a neural network computing architecture provided in an embodiment of the present application;

[0020] Figure 3A Schematic diagram of a cross-coupling data transfer circuit in MRAM-SRAM data transfer provided by an embodiment of the present application;

[0021] Figure 3B 2T-2M is a schematic diagram of the MRAM storage bit structure provided in an embodiment of the present application;

[0022] Figure 3C It is a schematic diagram of the structure of an 8T SRAM provided in an embodiment of the present application;

[0023] Figure 4A is a schematic diagram of a working waveform of a data transfer process provided by an embodiment of the present application;

[0024] Figure 4B is a schematic diagram of the relationship between the BL voltage difference, the input voltage and the discharge time provided in the embodiment of the present application;

[0025] Figure 5 It is a schematic diagram of an MRAM-SRAM hybrid integrated integer quantization in-memory convolution operation unit provided in an embodiment of the present application;

[0026] Figure 6 It is a schematic diagram of an IQC-CIM extended near-memory convolution operation unit provided in an embodiment of the present application;

[0027] Fig. 7A Schematic diagram of the relationship between the pressure difference in the MRAM-SRAM data transfer process provided by the embodiment of the present application;

[0028] Figure 7B Schematic diagram of the relationship between power supply voltage and data transfer error rate provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] The development of computing in memory (CIM) has not only overturned the traditional computing architecture, but also greatly promoted the progress of processors, computing architecture and computing models. It effectively solves the power consumption and speed bottlenecks caused by the separation of storage and computing in the von Neumann architecture, and realizes the design concept of integrated storage and computing. By shortening the distance between the computing unit and the memory, the computing in memory method gives the memory computing power, thereby effectively solving the energy efficiency problem caused by frequent data movement in the traditional computing architecture, and further breaking through the bottleneck of energy efficiency and memory access speed.

[0030] Therefore, exploring the in-memory computing implementation scheme of hybrid storage of MRAM (Magnetic Random Access Memory) or RRAM (Resistive Random-Access Memory) and SRAM (Static Random-Access Memory) has become a feasible computing architecture. This hybrid storage aims to take advantage of the non-volatility and high-density storage of MRAM or RRAM to achieve effective storage of weights; at the same time, it uses the high performance of SRAM and its natural compatibility with digital computing units to complete data caching and computing processes. Through this combination, it is expected to achieve an in-memory computing implementation method with low standby power consumption and high computing accuracy, providing new possibilities for future computing system architectures.

[0031] There are two main approaches to heterogeneous integration of new non-volatile memory (MRAM or RRAM) and static random access memory (SRAM), see Figure 1A and Figure 1B . Figure 1A is a schematic diagram of data interaction between SRAM-NVM storage arrays provided in an embodiment of the present application, Figure 1B Schematic diagram of storage bit level data interaction - nvSRAM (non-volatile static random access memory) storage bit provided by the embodiment of the present application. Figure 1AAs can be seen from the data interaction between the SRAM-NVM storage arrays shown, the RRAM or MRAM storage array and the SRAM storage array are designed independently, and the data is transferred from the non-volatile memory (NVM, such as RRAM or MRAM) to the SRAM through the data readout mechanism. This method may be limited by the parallelism of data transfer when performing data interaction at the storage array level. This is because data transfer usually needs to be performed bit by bit or block by block between NVM and SRAM, rather than simultaneously with a higher degree of parallelism, which may affect the efficiency and speed of data transmission.

[0032] Figure 1B Schematic diagram of nvSRAM storage bit for storing bit-level data interaction, such as Figure 1B As shown, a form of nvSRAM is designed by heterogeneously integrating the storage bits of SRAM (static random access memory) with non-volatile memory devices (such as STT-MRAM, ie, spin transfer torque magnetoresistive random access memory, or RRAM). Figure 1B The method shown aims to directly give SRAM non-volatile characteristics, thereby realizing data interaction at the storage bit level. However, current devices such as STT-MRAM and RRAM require a large write current to complete the state flip during the write process, which requires the custom design of SRAM to be compatible with these high write current requirements, which poses a great challenge to storage area and power consumption control.

[0033] also, Figure 1A and Figure 1B The embodiments shown lack independent readout circuits in their designs, which may result in a loss of accuracy during data transfer. The readout circuit is crucial to ensure the integrity and accuracy of data transfer.

[0034] Spin transfer torque magnetic random access memory (STT-MRAM) has shown significant advantages in the implementation of computing-in-memory (CIM). Its core memory device, magnetic tunnel junction (MTJ), is highly compatible with complementary metal oxide semiconductor (CMOS) processes, making it a popular candidate for overcoming the "storage wall" and "power consumption wall" in artificial intelligence applications. In addition, STT-MRAM has also attracted much attention in terms of non-volatility, operating speed and storage density.

[0035] However, STT-MRAM also faces some challenges in the design and implementation of CIM. First, the computing power of standard storage bits is limited, which limits the overall performance of the CIM system. Second, process fluctuations may lead to reduced computing accuracy, which is an important issue for applications that require high-precision computing. Finally, the large area overhead of peripheral circuits also increases the cost and complexity of CIM systems.

[0036] Currently, optimization of the traditional von Neumann computing architecture mainly focuses on the storage core, see Figure 2 , Figure 2 is a schematic diagram of a neural network computing architecture provided in an embodiment of the present application, such as Figure 2 On the basis of separating the processor and memory through the bus, the digital computing logic is moved to the side close to the memory to form a digital near-memory computing (NMC) architecture. This design aims to reduce data transmission overhead, thereby improving the problem of low energy efficiency. Furthermore, in order to meet different computing needs, a hybrid design method combining digital and analog is adopted, and these functional units are integrated on the side close to the memory to achieve deep integration of storage and computing. Therefore, the overall development of in-memory computing shows a trend of transitioning from the separation of storage and computing units to integration, and the energy efficiency of access and computing is improved by reducing the number of accesses to the memory. However, this high energy efficiency often requires sacrificing a certain amount of computing flexibility, making it more suitable for specific computing scenarios.

[0037] In neural network reasoning operations, although single-bit quantization can complete most tasks through simple logical calculations, which is more friendly to hardware implementation, especially in-memory calculations, the loss of reasoning performance it brings is unacceptable for practical applications. Therefore, research on multi-bit quantization, especially 8-bit integer quantization, is crucial for memory technologies such as MRAM. However, the current MRAM is not suitable for direct multi-bit operations due to its device characteristics. Even if the magnetoresistance accumulation method is used, complex sampling sensing technology is required to read the accumulated results. In contrast, SRAM achieves storage through voltage, which is naturally highly compatible with digital computing.

[0038] Therefore, exploring the in-memory computing implementation of MRAM-SRAM hybrid storage has become a feasible computing architecture. This solution uses the non-volatility and high-density storage advantages of MRAM to store network weights, while using the high performance of SRAM and its easy coordination with digital computing units to complete data caching and computing. Through this hybrid architecture, low standby power consumption and high computing accuracy in-memory computing can be achieved to meet the growing computing needs.

[0039] The key to the implementation of the above heterogeneous integrated hybrid CIM lies in the design of storage bits and efficient data transfer methods. Figure 3A . Figure 3A Schematic diagram of a cross-coupling data transfer circuit in an MRAM-SRAM data transfer provided by an embodiment of the present application. Figure 3A As shown, the cross-coupled data transfer circuit includes: a first transistor 301, a second transistor 302, a third transistor 303 and a fourth transistor 304. The gate of the first transistor 301 is connected to the first bit line (BL[0]) of the storage circuit; the gate of the second transistor 302 is connected to the second bit line (BL[1]) of the storage circuit; the first electrode of the first transistor 301 is connected to the first electrode of the fourth transistor 304; the first electrode of the second transistor 302 is connected to the first electrode of the third transistor 303; the second electrode of the first transistor 301 and the second electrode of the second transistor 302 are respectively connected to the ground; the second electrode of the third transistor 303 is connected to the first selection line (SL) of the storage circuit; the second electrode of the fourth transistor 304 is connected to the second selection line (SLB) of the storage circuit; the gates of the third transistor 303 and the fourth transistor 304 are respectively connected to the first control signal (Ctr).

[0040] It should be noted that the first electrode of the transistor in the embodiment of the present application is one of the drain (S) and the drain (D), and the second electrode of the transistor is the other corresponding electrode.

[0041] It should also be noted that the correspondence between the first bit line (BL[0]) and the second bit line (BL[1]) is not specifically limited, that is, the first bit line can be (BL[1]) and the second bit line can be (BL[0]).

[0042] There is no specific limitation on the correspondence between the first selection line (SL) and the second selection line (SLB), that is, the first selection line may be (SLB) and the second selection line may be (SL).

[0043] Specifically, the gates of the first transistor 301 and the second transistor 302 are respectively connected to different control lines (such as the bit line BL), and their drains or sources are connected to each other and connected to one end of the storage circuit (such as MTJ), for example, in the embodiment shown in the present application, they can be connected to one end of the MTJ through SL. The source or drain of the transistor is connected to a reference voltage or a ground line. When a read operation is performed, the transistor is selected by controlling the word line (WL). Since the resistance of the MTJ varies according to the stored data bit (0 or 1), the current passing through the MTJ will also be different. When the resistance of an MTJ is low (indicating that "0" is stored), its corresponding transistor will turn on faster, causing the voltage on the bit line (BL) to drop faster. If the resistance of another MTJ is high (indicating that "1" is stored), the corresponding transistor turns on slower and the bit line voltage drops slower. Since the first transistor and the second transistor are cross-coupled (i.e., the drain of one transistor is connected to the source of the other transistor, or vice versa), when one transistor turns on quickly, it pulls down the gate voltage of the other transistor, thereby slowing down its turn-on speed. This cross-coupling effect helps amplify the voltage difference between the two bit lines, making the read operation more reliable and accurate.

[0044] By detecting the voltage on the bit line (BL), it is possible to determine which MTJ stores "0" and which stores "1". This voltage difference will be amplified and used for subsequent circuit processing or data transfer.

[0045] The following is an introduction to the MRAM storage bit in the storage circuit, see Figure 3B . Figure 3B 2T-2M is a schematic diagram of the MRAM storage bit structure provided by the embodiment of the present application. Figure 3B The MRAM storage bit shown is illustrated by taking 2T (transistor)-2M (magnetic tunnel junction) as an example, but the present application embodiment does not specifically limit the structure of the MRAM storage bit. Figure 3BThe MRAM storage bit shown is a 2T-2M (two transistors-two magnetic tunnel junctions) structure including: transistor M1, transistor M2, magnetic tunnel junction MTJ1, magnetic tunnel junction MTJ2, transistor M3, transistor M4, magnetic tunnel junction MTJ3, and magnetic tunnel junction MTJ4. In the 2T-2M structure, the gates (G) of transistor M1 and transistor M2 are connected to the word line (WL[0]); the gates (G) of transistor M3 and transistor M4 are connected to the word line (WL[1]) to control the on or off state of the transistors. One of the source (S) and drain (D) of transistor M1 and transistor M3 is connected to the source line (SL), and the other of transistor M1 and transistor M3 is connected to one end of the corresponding MTJ1 and MTJ3. One of the source (S) and drain (D) of transistor M2 and transistor M4 is connected to the source line (SLB), and the other of transistor M2 and transistor M4 is connected to one end of the corresponding MTJ2 and MTJ4. The other ends of MTJ1 and MTJ3 are connected to a bit line (BL[0]; the other ends of MTJ2 and MTJ4 are connected to a bit line (BL[1]). Figure 3B Only the structures of two storage bits are shown, and the structures of subsequent bits are similar and will not be described again here.

[0046] Each MTJ can store a data bit (0 or 1), depending on its magnetization direction. When data needs to be read or written, the corresponding transistor is selected by controlling the voltage of the word line (WL). When the transistor is turned on, a path is formed between the bit line (BL) and the MTJ, allowing current to pass through the MTJ. In the read operation, the resistance state of the MTJ is detected by measuring the current or voltage change on the bit line (BL), thereby determining the stored data bit. In the write operation, the magnetization direction of the MTJ is changed by applying a specific current or voltage pulse to the bit line (BL) and / or word line (WL), thereby achieving data writing.

[0047] It should be noted that, in order to ensure high storage density and readout window, the embodiment of the present application adopts the basic 2T-2M (two transistors, two magnetic tunnel junctions) storage bit design, but no specific restrictions are made. The 2T-2M configuration with mutual reference effectively improves the accuracy of data reading and simplifies the process of data transfer. Although this design sacrifices storage density to a certain extent, it provides a basis for subsequent iterations and optimizations (such as exploring 1T-1M high storage density solutions).

[0048] It should also be noted that Figure 3B The MRAM storage bit cell shown is connected to the Figure 3A The cross-coupled structure circuit connection shown is used to assist in transferring data from the MRAM memory to the SRAM memory.

[0049] The following is an introduction to the circuit structure of SRAM. Figure 3C . Figure 3C 8T SRAM structure diagram provided by the embodiment of the present application. Figure 3C As shown, the 8T SRAM structure includes a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15 and a sixteenth transistor M16. Among them, the gate of the ninth transistor M9 is connected to the first enable signal (ENB), the first electrode (one of the source (S) and the drain (D)) of the ninth transistor M9 is respectively connected to the first electrode (one of the source (S) and the drain (D)) of the tenth transistor M10 and the twelfth transistor M12; the other electrode (second electrode) of the tenth transistor M10 is respectively connected to the first electrode (one of the source (S) and the drain (D)) of the eleventh transistor M11, the gate of the twelfth transistor M12, the gate of the fifteenth transistor M15, and the first electrode (one of the source (S) and the drain (D)) of the fourteenth transistor M14; the gate of the tenth transistor M10 is respectively connected to the gate of the fourteenth transistor M14, the other electrode (second electrode) of the twelfth transistor M12, the first electrode (source (S) and the drain (D)) of the thirteenth transistor M13 ) and one of the drain (D)) and the first electrode (one of the source (S) and the drain (D)) of the fifteenth transistor M15; the gate of the eleventh transistor M11 is connected to the word line (WL), and the other electrode (second electrode) of the source and the drain of the eleventh transistor M11 is connected to the bit line (BL[0]); the gate of the thirteenth transistor M13 is connected to the word line (WL), and the other electrode (second electrode) of the thirteenth transistor M13 is connected to the bit line (BL[1]); the other electrode (second electrode) of the fourteenth transistor M14 is connected to the other electrode (second electrode) of the fifteenth transistor M15 and the first electrode (one of the source (S) and the drain (D)) of the sixteenth transistor M16; the gate of the sixteenth transistor M16 is connected to the second enable signal (EN), and the other electrode (second electrode) of the sixteenth transistor M16 is grounded.

[0050] like Figure 3CThe embodiment of the present application shown in the figure adds additional MOS transistors to the pull-up network and the pull-down network on the basis of the traditional 6-tube SRAM. This enables the strong feedback connection of the inverters connected end to end to be cut off during data transfer, thereby improving the stability and accuracy of data transfer. The read and write operations of the 8T SRAM are similar to those of the traditional 6-tube SRAM, but due to the addition of additional transistors, the read and write speeds may be slightly different. When reading data, the data is read from the storage cell (MRAM) through the access transistor; when writing data, the data is written to the storage cell (MRAM) through the access transistor. In addition, a pair of cross-coupled transistors are added to the MRAM storage array to assist in extracting data from the MRAM to the SRAM. When data needs to be extracted from the MRAM to the SRAM, the cross-coupled transistors will be activated. By controlling the gate voltage of the cross-coupled transistor, the size of the channel current can be adjusted to achieve data amplification and transmission. Data is transmitted from the storage cell of the MRAM to the input port of the SRAM through the cross-coupled transistor, and then written to the storage cell of the SRAM.

[0051] The following is an introduction to the MRAM-SRAM storage bit operating waveform provided in the embodiment of the present application, see Figure 4A and Figure 4B . Figure 4A is a schematic diagram of the working waveform of the data transfer process provided by the embodiment of the present application, Figure 4B Schematic diagram of the relationship between the BL voltage difference, input voltage and discharge time provided by the embodiment of the present application. Figure 4A As shown, in the precharge phase, two bit lines (BL), such as BL[0] and BL[1], are precharged to the power supply voltage (VDD). In the sampling phase (or transmission phase), when the word line (WL) and Ctr (control signal) signals are turned on, the discharge path is established. The voltage of the two BLs begins to drop, because the magnetic tunnel junction (MTJ) connected to them begins to discharge. Due to the different states of the two MTJs (2T-2M complementary), there are differences in the speed at which they discharge, resulting in a voltage difference maximum point on the BL. This voltage difference is the input voltage that the subsequent SRAM bit will read. Figure 4A The pre-charge phase (Pre-charge Phase, PRE), traditional V BL And the cross-coupled V provided in the embodiment of the present application BLThe working waveform diagram of SRAM. In the data sampling stage, the word line (WL) of SRAM is activated, and the enable signal EN / ENB is triggered at the same time. This operation effectively locks the generated voltage difference in the storage bit of SRAM, thereby completing the data transmission process. It should be noted that if one of the enable signals EN / ENB is VBB, the other is VSS (ground voltage). The significant advantage of using a cross-coupling structure is that a stable voltage difference output can be achieved without complex and precise design of the sampling moment, greatly reducing the complexity of the timing design. In addition, this structure can generate more than twice the voltage difference of the traditional method, significantly enhancing the accuracy of data transfer. It is worth mentioning that the data transfer speed of this technology can theoretically reach 5ns to 2ns (corresponding to a frequency range of 200MHz to 500MHz), which is comparable to the DRAM (Dynamic Random-Access Memory) reading speed of the DDR3 (Double Data Rate III Synchronous Dynamic Random-Access Memory, the third generation of double-rate synchronous dynamic random access memory) interface. More importantly, this technology can bypass the data bus and achieve large-scale parallel data transfer, thereby achieving extremely high data throughput and providing strong support for high-speed data processing.

[0052] like Figure 4B As shown in the figure, in the combination of 28nm CMOS process and 70nm MTJ process, when the power supply voltage is set to 0.6V, in the standard traditional mode, a slight increase in the initial input bias voltage can cause the signal transmission speed to increase rapidly from 300.0 microseconds / volt to 271.2 millivolts / nanoseconds. In the cross-coupling mode, the two transistors affect each other by forming a negative feedback mechanism. The fast discharge process of one transistor will promote the closure of the other transistor. This process is reflected in the figure as the signal transmission speed first increases and then decreases with the increase of the input bias voltage, and reaches a maximum value of 200.0 milliseconds / volt at a certain point. This design allows the system to reach and maintain a stable voltage difference faster. It is worth noting that in the cross-coupling mode, when the discharge process reaches 0.45 nanoseconds, the input voltage reaches a significant maximum value of about 126.8mV. Subsequently, this voltage difference continues to rise, and finally reaches another significant maximum value of about 271.2mV at about 3 nanoseconds. This feature is particularly prominent in the combination of 28nm CMOS and 70nm MTJ (i.e., CT model), demonstrating the potential of the cross-coupling structure in optimizing signal transmission and voltage stability.

[0053] The following describes a hybrid integrated integer quantization in-memory convolution operation unit including the above-mentioned MRAM_SRAM heterogeneous integrated digital computing circuit. Figure 5 , Figure 5 Schematic diagram of an MRAM-SRAM hybrid integrated integer quantization in-memory convolution operation unit provided in an embodiment of the present application, i.e., an in-memory convolution operation unit. Figure 5 As shown, the near-memory convolution operation circuit includes: a logic control circuit 501, a storage array 502, a register group 503 and a multiplication-accumulation calculation unit 504. The top-level logic control circuit 501 of the IQC-CIM architecture includes: a decoding circuit, a control circuit, and a level shifter. The decoding circuit is responsible for converting the input instructions or data into a format that the calculation unit can understand; the control circuit guides the operation of each part of the calculation unit according to the converted information; the level shifter handles the data conversion between different voltage levels to ensure that the data is correctly transmitted between different modules. The storage array is divided into multiple efficient MRAM-SRAM sub-array combinations. All sub-arrays share a set of logic control circuits to maximize the utilization of resources. Among them, MRAM is used to store weight data, while SRAM is used as an efficient cache mechanism to extract the weight data and convert it into a voltage signal to provide the digital operation circuit for MAC (multiplication-accumulation) operation. Among them, the multiplication-accumulation calculation unit 504 includes: a multiplier and an accumulator. In order to ensure that the data flow between sub-arrays is unimpeded, a driving compensation circuit is introduced between the sub-arrays. As shown Figure 5 As shown, the multiplication-accumulation calculation unit is arranged on one side close to the memory array to complete the multiplication-accumulation operation of the input data and the weight data. Among them, MRAM is used to store weight data, and SRAM is used as an efficient cache mechanism to extract the weight data and convert it into a voltage signal to provide a digital operation circuit for MAC (multiplication-accumulation) operation. In order to ensure that the data flow between sub-arrays is unimpeded, a driving compensation circuit is introduced between the sub-arrays. Different from the traditional serial data transfer method between arrays, the data between multiple sub-arrays in the embodiment of the present application is transferred in parallel, thereby significantly improving the data transfer efficiency and computing performance.

[0054] It should be noted that the cross-coupling data transfer circuit provided in the above embodiment can be used to transfer data in the MRAM to the SRAM.

[0055] In some embodiments, the 8T SRAM structure provided in the embodiments of the present application may be used, and the embodiments of the present application do not impose any specific limitation on the SRAM structure used.

[0056] Since the sub-array is relatively small and the voltage is weak, the digital signal from the SRAM can be directly sampled by the register group without the need for additional readout circuits, further simplifying the system structure and reducing energy consumption.

[0057] Advanced digital design methods are used in the design of the computing circuit to complete the operation of input data and weight data directly on the side close to the SRAM. This design not only speeds up the data processing speed, but also improves the accuracy and reliability of the calculation. As shown in the figure, the embodiment constructs a hybrid CIM (computational memory integration) unit consisting of 9 groups of MRAM-SRAM subarrays. Each subarray contains 4Kb of MRAM and 32bit SRAM, and the entire CIM unit integrates 36Kb of MRAM and 216bit SRAM. It can support 9×8bit input data and 9×8bit weight data, and can implement 3×3 integer quantized convolution operations with 20bit signed output.

[0058] The following is an introduction to the IQC-CIM extended in-memory computing architecture. Figure 6 . Figure 6 Schematic diagram of an IQC-CIM extended near-memory convolution operation unit provided in an embodiment of the present application. Figure 6 As shown, an additional accumulator is integrated at a central position of at least two groups of CIM units to connect the at least two groups of CIM units and output the results. Figure 6 As shown, the embodiment integrates an additional accumulator at the center of four groups of CIM units to form an extended near-memory convolution operation unit, which can significantly improve the scale and efficiency of MAC (multiply-accumulate) operations. The scale of MAC operations can be expanded to 36 accumulations, and flexible adjustment between 9-36 accumulations is provided to meet different computing requirements. In addition, the expanded CIM unit can generate up to 22-bit signed output, further enhancing its computing power and application range.

[0059] It should be noted that the embodiment of the present application does not impose any specific restriction on the number of CIMs included in the extended near-memory convolution operation unit.

[0060] Furthermore, the power consumption of the near memory computing architecture proposed in the embodiment of the present application is analyzed, see Fig. 7A . Fig. 7A Schematic diagram of the relationship between the pressure difference during the MRAM-SRAM data transfer process provided by the embodiment of the present application. Fig. 7A The relationship between the bit line voltage difference and the power supply voltage is shown. By implementing multi-process corner simulation analysis, it can be seen that even under the harsh condition of the power supply voltage dropping to 0.6V, when the TMR (tunnel magnetoresistance) ratio of the MTJ (magnetic tunnel junction) reaches 150%, a voltage difference of more than 240mV can still be successfully generated. In addition, in order to ensure reliable data transmission, we use the Monte Carlo simulation method to conduct a detailed evaluation of the potential data transfer error rate, see Figure 7B . Figure 7B Schematic diagram of the relationship between power supply voltage and data transfer error rate provided in the embodiment of the present application. Figure 7B As shown in the figure, under the extreme condition that the power supply voltage drops to 0.5V and the TMR ratio of MTJ reaches 150%, MTJ can still show excellent data transfer quality. In order to cope with the process fluctuation of MTJ TMR, it is recommended to use a power supply voltage of 0.7V as the balance point, which can ensure the high quality of data transfer while taking into account the needs of low power consumption and high energy efficiency.

[0061] In some embodiments, the near-memory convolution operation unit provided in the embodiments of the present application can be used in a chip system, and the chip system is used to complete the convolution operation included in the chip system based on the above-mentioned near-memory convolution operation unit.

[0062] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable storage medium may at least include: any entity or device that can carry the computer program code to the camera / terminal device, recording medium, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium. For example, USB flash drive, mobile hard disk, disk or optical disk. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electric carrier signals and telecommunication signals.

[0063] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0064] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0065] In the embodiments provided in the present application, it should be understood that the disclosed devices / equipment and methods can be implemented in other ways. For example, the device / equipment embodiments described above are merely schematic, for example, the division of the modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0066] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0067] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0068] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0069] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0070] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0071] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A data transfer circuit, characterized in that: The data transfer circuit is used to assist a data storage circuit connected to the data transfer circuit in data transfer; The digital transfer circuit comprises: a first transistor, a second transistor, a third transistor and a fourth transistor; The gate of the first transistor is connected to the first bit line of the storage circuit; The gate of the second transistor is connected to a second bit line of the storage circuit; The first electrode of the first transistor is connected to the first electrode of the fourth transistor; The first electrode of the second transistor is connected to the first electrode of the third transistor; The second electrode of the first transistor and the second electrode of the second transistor are respectively connected to the ground; The second electrode of the third transistor is connected to the first selection line of the storage circuit; A second electrode of the fourth transistor is connected to a second selection line of the storage circuit; The gates of the third transistor and the fourth transistor are respectively connected to the first control signal.

2. The data transfer circuit according to claim 1, characterized in that: The storage circuit includes: a magnetic random access memory and a static random access memory.

3. The data transfer circuit according to claim 2, characterized in that: The magnetic random access memory includes a transistor and a magnetic tunnel junction, wherein the gate of the transistor is connected to the bit line of the storage circuit, the first end of the magnetic tunnel junction is connected to the word line of the storage circuit, and the second end of the magnetic tunnel junction is connected to the corresponding transistor.

4. The data transfer circuit according to claim 1, characterized in that: Precharging the voltage of the first bit line and the second bit line to a power supply voltage in a precharging stage; Turning on the word line connected to the storage circuit and the first signal to establish a discharge path; A voltage difference formed by a discharge speed difference between the first bit line and the second bit line is an input voltage of the static random access memory.

5. The data transfer circuit according to claim 1, characterized in that: During the discharge process, the first transistor and the second transistor form a negative feedback to generate a stable voltage difference; Controlling the gate voltage of the first transistor and the gate voltage of the second transistor to adjust the magnitude of the channel current and realize data amplification and transmission; The data is transmitted from the storage unit of the magnetic random access memory to the input port of the static random access memory through the first transistor and the second transistor, and is written into the static random access memory.

6. A SRAM storage circuit, characterized in that: Using the data transfer circuit as claimed in claim 1 to transfer data to the SRAM storage circuit; The SRAM storage circuit includes: a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor and a sixteenth transistor; The gate of the ninth transistor is connected to the first enable signal, the first electrode of the ninth transistor is respectively connected to the first electrode of the tenth transistor and the first electrode of the twelfth transistor; the second electrode of the tenth transistor is respectively connected to the first electrode of the eleventh transistor, the gate of the twelfth transistor, the gate of the fifteenth transistor, and the first electrode of the fourteenth transistor; The gate of the tenth transistor is respectively connected to the gate of the fourteenth transistor, the second electrode of the twelfth transistor, the first electrode of the thirteenth transistor and the first electrode of the fifteenth transistor; The gate of the eleventh transistor is connected to the word line, and the second electrode of the eleventh transistor is connected to the first bit line; the gate of the thirteenth transistor is connected to the word line, and the second electrode of the thirteenth transistor is connected to the second bit line; the second electrode of the fourteenth transistor is connected to the second electrode of the fifteenth transistor and the first electrode of the sixteenth transistor; the gate of the sixteenth transistor is connected to the second enable signal, and the second electrode of the sixteenth transistor is grounded.

7. The SRAM storage circuit according to claim 6, characterized in that: During data transmission, the word line in the SRAM storage circuit controls the first enable signal and the second enable signal to be turned on, and the generated voltage difference is latched into the SRAM storage circuit to complete the transfer of the data.

8. A near-convolution operation unit, characterized in that: The near-memory convolution operation unit comprises: the data transfer circuit according to claim 1 and the SRAM storage circuit according to claim 6; The near-memory convolution operation unit uses the data transfer circuit to transfer data from the magnetic random access memory to the SRAM storage circuit.

9. The near-memory convolution operation unit according to claim 8, characterized in that: At least two near-memory convolution operation units as claimed in claim 8 are connected via an accumulator, and the operation result is output via the accumulator.

10. A chip system, characterized in that: Including the near-memory convolution operation unit as described in claim 8, the chip system is used to complete the convolution operation included in the chip system according to the near-memory convolution operation unit.

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