Vertical routing high-density POP packaging structure and packaging process

Abstract

The high-density POP packaging structure comprises a temporary bonding carrier, a plurality of layers of RDL redistribution lines are arranged on the temporary bonding carrier, openings are formed in the plurality of layers of RDL redistribution lines through photoresist exposure, copper columns are arranged at the photoresist openings, first chips are mounted on the plurality of layers of RDL redistribution lines, and second chips are mounted on the plurality of layers of RDL redistribution lines. A connecting circuit is arranged on the first chip, a first plastic package material wraps the outer walls of the first chip, the connecting circuit and the copper column, a high-density RDL is arranged at the outer ends of the copper column and the connecting circuit, a second chip is mounted on the high-density RDL in an inverted manner through micro bumps, a second plastic package material wraps the outer wall of the second chip, and the second plastic package material wraps the outer wall of the second chip. Balls are arranged on the back face of the multiple layers of RDL redistribution lines. According to the invention, the substrate is replaced by the wafer-level high-density RDL, so that the interconnection density is improved, and the packaging of multiple chips is realized; the vertical routing technology is adopted, the packaging size is reduced, parasitic capacitance and parasitic resistance generated by signal transmission are reduced, and the signal transmission efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, in particular to a vertically bonded high-density POP packaging structure and a packaging process. Background Art

[0002] Traditional wire bonding technology has the advantages of simple manufacturing, low cost, and strong flexibility. It is widely used in the electrical interconnection between various digital circuits, RF chips, and transmission lines in multi-chip hybrid circuit systems. However, with the increase of operating frequency, the parasitic parameters and skin effect of the bonding wire gradually increase. Wire bonding interconnection has high impedance characteristics, which will seriously deteriorate the transmission behavior and introduce unnecessary signal reflections. Therefore, there is an urgent need to compensate for impedance mismatch and improve the signal integrity of the bonding wire, especially in miniaturized, highly integrated system-level packaging.

[0003] Several techniques have been investigated to minimize bond wire discontinuities. Typically, gold bond ribbons with lower impedance are used instead of ordinary gold bond wires within semiconductor packages. In addition, in practical designs, reducing the distance between adjacent chips can also achieve lower inductance through shorter bond wires.

[0004] For high-density interconnection, in order to break through the process limitations of traditional FC-BGA substrate manufacturing (such as laser drilling, chemical copper plating or desmearing) and meet the needs of miniaturization and high-density interconnection, it is necessary to develop new substrate technologies with narrower spacing and finer wiring dimensions. However, the wiring capacity of the substrate is much smaller than that of the wafer-level RDL. Therefore, wafer-level RDL preparation has become an important process for high-density interconnection.

[0005] Various methods have been developed to improve signal interconnection, such as forming a 3D stacking structure through the TSV process, which greatly reduces the signal transmission distance and can directly form chip-to-chip signal transmission. TSV is the core of 3D silicon integration and 3D IC integration. It provides the shortest chip-to-chip interconnection and the smallest pad size and interconnection spacing. Compared with other interconnection technologies (such as wire bonding), the advantages of TSV include: (a) better electrical performance, (b) lower power consumption, (c) wider data width and bandwidth, (d) higher density, (e) smaller size, and (f) lighter weight. Due to its unique advantages, TSV will exist for a long time in high-bandwidth, high-performance and high-density applications. However, TSV technology requires a series of complex processes involving different equipment and materials, and the production cost is extremely high, which is not conducive to a wide range of product applications.

[0006] For a typical POP structure, it consists of a top package and a bottom package. The top package contains two chips, which are cross-stacked and wire-bonded on a package substrate, and the bottom package contains a chip, which is wire-bonded on another package substrate. All these chips are overmolded, and these substrates have solder balls, but the RDL signal transmission capability of the substrate is limited compared to the wafer-level RDL, which is not conducive to high-density signal transmission and chip integration.

[0007] Therefore, we proposed a high-density POP packaging structure and packaging process with vertical wire bonding. Summary of the invention

[0008] The purpose of the present invention is to provide a high-density POP packaging structure and packaging process for vertical bonding, which solves the problems raised in the background technology.

[0009] To achieve the above-mentioned purpose, the present invention provides the following technical solutions: a high-density POP packaging structure with vertical bonding, comprising: a temporary bonding carrier, a multi-layer RDL rewiring is arranged on the temporary bonding carrier, an opening is formed on the multi-layer RDL rewiring by photoresist exposure, a copper column is arranged at the photoresist opening, a first chip is mounted on the multi-layer RDL rewiring in a face-up manner, a vertical connection line is formed at the pad of the first chip by vertical bonding, the outer walls of the first chip, the connection line and the copper column are wrapped with a first plastic packaging material, the copper column and the connection line extend to the outside of the first plastic packaging material, a high-density RDL is arranged at the outer end of the copper column and the connection line, a second chip is mounted on the high-density RDL by micro-bumps in a flip-chip manner, the outer wall of the second chip is wrapped with a second plastic packaging material, and a planting ball is arranged on the back of the multi-layer RDL rewiring.

[0010] As a preferred embodiment of the present invention, the first chips are bonded together by a DAF film.

[0011] As a preferred embodiment of the present invention, the material of the connecting line is one of gold, silver, copper, gold-coated copper and platinum-coated copper.

[0012] As a preferred embodiment of the present invention, the material of the micro-bumps is one of Au, Cu, Sn, In, Pb-Sn, Au-Sn, Ag-Sn, Sn-Cu, and Ag-Sn-Cu.

[0013] As a preferred embodiment of the present invention, the material of the temporary bonding carrier is one of glass, ceramic, metal or silicon wafer.

[0014] The present invention also relates to a packaging process for a high-density POP packaging structure with vertical bonding, comprising the following method steps:

[0015] S1. Prepare a temporary bonding carrier, and prepare the first chip and the second chip to be mounted later;

[0016] S2. Perform multi-layer RDL rewiring on a temporary bonding carrier, with the number of layers being 3-6;

[0017] S3, making photoresist openings on the multi-layer RDL redistribution by coating, exposing, and developing;

[0018] S4, preparing copper pillars at the photoresist openings by electroplating;

[0019] S5, then mounting the prepared first chip on the multi-layer RDL redistribution wiring in a positive mounting manner, and bonding the first chips together through a DAF film;

[0020] S6, forming a vertical connection line at the pad of the stacked first chip by vertical bonding;

[0021] S7, plastic-encapsulating the wire-bonded structure, wrapping the first chip, the connecting wires and the copper pillars in a first plastic-encapsulating material;

[0022] S8, performing CMP grinding on the plastic cover of the plastic package structure to expose the copper pillars and connecting lines;

[0023] S9, high-density RDL is produced on the exposed copper pillars and connecting lines;

[0024] S10, mounting the second chip on the high-density RDL through micro-bumps in a flip-chip manner, and performing bottom filling;

[0025] S11, performing a second plastic encapsulation on the second chip on the flip-chip bonding so that the second chip is wrapped in a second plastic encapsulation material;

[0026] S12, temporarily debonding the packaging structure, removing the temporary bonding carrier, and performing ball planting on the back side of the multi-layer RDL rewiring to obtain a high-density POP packaging structure with vertical bonding.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] The present invention utilizes wafer-level high-density RDL to replace the substrate, improves the interconnection density, and realizes the packaging of multiple chips;

[0029] The present invention adopts vertical wire bonding technology to reduce the package size, reduce the parasitic capacitance and parasitic resistance generated by signal transmission, and improve signal transmission efficiency;

[0030] Since the process steps of vertical bonding are relatively simple, the process difficulty and cost are greatly reduced compared to TSV technology. Compared to substrate technology, high-density RDL greatly improves the interconnection density. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0032] Figure 1 Figure 2 is a bonding carrier diagram of the present invention;

[0033] Figure 2 It is a multi-layer RDL redistribution diagram of the present invention;

[0034] Figure 3 is a photoresist opening diagram of the present invention;

[0035] Figure 4 The copper pillar pattern is prepared at the photoresist opening for the present invention;

[0036] Figure 5 It is the chip bonding diagram of the present invention;

[0037] Figure 6 It is a vertical connection line diagram of the present invention;

[0038] Figure 7 This is a diagram showing that the chip, vertical lines and copper pillars of the present invention are all wrapped inside the plastic packaging material;

[0039] Figure 8 This is a diagram showing the copper pillars and vertical lines of the present invention;

[0040] Fig. 9 Produce a diagram for the high-density RDL of the present invention;

[0041] Fig.10 It is a connection diagram of the chip and high-density RDL of the present invention;

[0042] Fig.11 This is the secondary plastic sealing diagram of the present invention;

[0043] Fig.12 For the present invention, a ball implantation pattern is performed on the backside RDL. DETAILED DESCRIPTION

[0044] In order to make the technical means, creative features, objectives and effects achieved by the present invention easy to understand, the present invention is further explained below in conjunction with specific implementation methods.

[0045] Example

[0046] A vertically bonded high-density POP packaging structure comprises: a temporary bonding carrier 1, a multi-layer RDL rewiring 2 is arranged on the temporary bonding carrier 1, an opening is formed on the multi-layer RDL rewiring 2 by exposing a photoresist 3, a copper column 4 is arranged at the opening of the photoresist 3, a first chip 5 is mounted on the multi-layer RDL rewiring 2 in a face-up manner, a vertical connection line 6 is formed at a pad of the first chip 5 by vertical bonding, the outer walls of the first chip 5, the connection line 6 and the copper column 4 are wrapped with a first plastic packaging material 7, the copper column 4 and the connection line 6 extend to the outside of the first plastic packaging material 7, a high-density RDL 8 is arranged at the outer ends of the copper column 4 and the connection line 6, a second chip 9 is mounted on the high-density RDL 8 by a flip-chip manner through micro-bumps, the outer wall of the second chip 9 is wrapped with a second plastic packaging material 10, and a planting ball 11 is arranged on the back of the multi-layer RDL rewiring 2.

[0047] It should be understood that the vertical wire bonding process reduces the package volume, reduces parasitic capacitance and resistance, forms high-density interconnections through multi-layer RDL, and improves signal transmission capabilities.

[0048] A packaging process for a high-density POP packaging structure with vertical bonding includes the following process steps:

[0049] S1. Prepare a temporary bonding carrier 1, such as Figure 1 As shown, the carrier may be glass, ceramic, metal or silicon wafer, and the first chip 5 and the second chip 9 required for subsequent mounting are prepared, and the thickness of the chip can be ground and thinned according to product requirements;

[0050] S2, do multi-layer RDL rewiring 2 on the temporary bonding carrier, the number of layers can be 3-6 layers, such as Figure 2 shown.

[0051] S3, forming a photoresist 3 opening on the multi-layer RDL rewiring 2 by coating, exposing, and developing, such as Figure 3 shown.

[0052] S4, preparing copper pillars 4 at the openings of the photoresist 3 by electroplating, such as Figure 4 shown.

[0053] S5, then the prepared first chip 5 is mounted on the multi-layer RDL redistribution 2 in a positive mounting manner, and the first chips 5 can be bonded together by a DAF film, such as Figure 5 shown.

[0054] S6, forming a vertical connection line 6 at the pad of the stacked first chip 5 by vertical bonding, such as Figure 6 As shown, the diameter and height of the connection line 6 can be determined according to the overall package size, and the material of the connection line 6 can be gold, silver, copper, gold-coated copper, platinum-coated copper, etc.

[0055] S7, plastic encapsulate the wired structure, and wrap the chip, vertical wires and copper pillars in the first plastic encapsulation material 7, such as Figure 7 As shown, the first plastic packaging material 7 can be a liquid plastic packaging material or a solid plastic packaging material.

[0056] S8, CMP grinding is performed on the plastic cover of the plastic package structure to expose the copper pillar 4 and the connecting line 6, such as Figure 8 shown.

[0057] S9, high-density RDL8 is produced on the exposed copper pillars and vertical lines, such as Fig. 9 shown.

[0058] S10, by flip-chip method, mount the second chip 9 on the high-density RDL 8 through micro-bumps, and perform bottom filling. The micro-bump material can be pure metals such as Au, Cu, Sn, In, or alloys such as Pb-Sn, Au-Sn, Ag-Sn, Sn-Cu, Ag-Sn-Cu, etc. The second chip 9 can be a logic chip such as CPU, GPU or FPGA, or a sensor chip or SOC chip, etc. The number of chips can be one or more, such as Fig.10 shown.

[0059] S11, performing a second plastic encapsulation on the flip-chip chip so that the chip is wrapped in a second plastic encapsulation material 10. The second plastic encapsulation material 10 can be a liquid plastic encapsulation material or a solid plastic encapsulation material, such as Fig.11 shown.

[0060] S12, temporarily debonding the package structure, removing the temporary bonding carrier 1, and performing ball planting 11 on the back side of the multi-layer RDL redistribution 2, such as Fig.12 As shown;

[0061] Through the above steps, a high-density POP packaging structure with vertical bonding can be formed.

[0062] In summary, the present invention utilizes wafer-level high-density RDL to replace the substrate, improves the interconnection density, and realizes multi-chip packaging. It adopts vertical wiring technology to reduce the package size, reduce the parasitic capacitance and parasitic resistance generated by signal transmission, and improve signal transmission efficiency. Since the process steps of vertical wiring are relatively simple, compared with TSV technology, the process difficulty and cost are greatly reduced, and compared with substrate technology, high-density RDL greatly improves the interconnection density.

[0063] The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention. It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic features of the present invention. Therefore, no matter from which point of view, the embodiments should be regarded as exemplary and non-restrictive. The scope of the present invention is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims are included in the present invention.

[0064] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A high-density POP packaging structure with vertical bonding, characterized in that: include: A temporary bonding carrier (1), wherein a multi-layer RDL rewiring (2) is arranged on the temporary bonding carrier (1), an opening is formed on the multi-layer RDL rewiring (2) by exposing a photoresist (3), a copper column (4) is arranged at the opening of the photoresist (3), a first chip (5) is mounted on the multi-layer RDL rewiring (2) in a positive mounting manner, a vertical connection line (6) is formed at the pad of the first chip (5) by vertical bonding, and the first chip (5) and the connection line (6) are connected to each other. ) and the outer wall of the copper column (4) are wrapped with a first plastic encapsulation material (7), the copper column (4) and the connecting line (6) extend outside the first plastic encapsulation material (7), the outer ends of the copper column (4) and the connecting line (6) are provided with a high-density RDL (8), a second chip (9) is mounted on the high-density RDL (8) by means of a flip-chip method through micro-bumps, the outer wall of the second chip (9) is wrapped with a second plastic encapsulation material (10), and a planting ball (11) is provided on the back side of the multi-layer RDL redistribution (2).

2. A vertically bonded high-density POP packaging structure according to claim 1, characterized in that: The first chips (5) are bonded together by a DAF film.

3. The high-density POP packaging structure with vertical bonding according to claim 1, characterized in that: The material of the connecting line (6) is one of gold, silver, copper, gold-coated copper and platinum-coated copper.

4. The high-density POP packaging structure with vertical bonding according to claim 1, characterized in that: The material of the micro-bumps is one of Au, Cu, Sn, In, Pb-Sn, Au-Sn, Ag-Sn, Sn-Cu, and Ag-Sn-Cu.

5. The high-density POP packaging structure and packaging process of vertical bonding according to claim 1, characterized in that: The material of the temporary bonding carrier (1) is one of glass, ceramic, metal or silicon wafer.

6. A packaging process for a vertically bonded high-density POP packaging structure, applicable to the packaging process for a vertically bonded high-density POP packaging structure according to claims 1-5, characterized in that: The method comprises the following steps: S1, preparing a temporary bonding carrier (1), and preparing a first chip (5) and a second chip (9) to be mounted later; S2, performing multi-layer RDL rewiring (2) on the temporary bonding carrier, the number of layers may be 3-6 layers; S3, forming a photoresist (3) opening on the multi-layer RDL redistribution (2) by coating, exposing, and developing; S4, preparing a copper column (4) at the opening of the photoresist (3) by electroplating; S5, then mounting the prepared first chip (5) on the multi-layer RDL redistribution wiring (2) in a positive mounting manner, and bonding the first chips (5) together through a DAF film; S6, forming a vertical connection line (6) at the pad of the stacked first chip (5) by vertical bonding; S7, plastic-encapsulating the wire-bonded structure, wrapping the first chip (5), the connecting line (6) and the copper pillar (4) inside the first plastic encapsulation material (7); S8, performing CMP grinding on the plastic cover of the plastic package structure to expose the copper pillar (4) and the connecting line (6); S9, performing high-density RDL (8) fabrication on the exposed copper pillars (4) and connecting lines (6); S10, mounting the second chip (9) on the high-density RDL (8) by flip-chip mounting through micro-bumps, and performing bottom filling; S11, performing a second plastic encapsulation on the flip-chip-bonded second chip (9), so that the second chip (9) is encapsulated in a second plastic encapsulation material (10); S12, temporarily debonding the packaging structure, removing the temporary bonding carrier (1), and performing ball planting (11) on the back side of the multi-layer RDL redistribution wiring (2) to obtain a high-density POP packaging structure with vertical bonding.

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