A component decoding method of TURBO code, a decoding method of TURBO code and related equipment

Abstract

An embodiment of the present application provides a component decoding method for a TURBO code, a decoding method for a TURBO code, and related equipment, including: receiving and demodulating data to be decoded according to a scheduling configuration to obtain decoding input data; and calculating the code rate and modulation order of the decoding input data; calculating an adjustment value for the decoding input data and a bit width shift value of a decoder internal posterior probability branch metric parameter according to the modulation order and code rate of the decoding input data; adjusting the numerical value of the decoding input data by the adjustment value to obtain first decoding input data; component decoding the first decoding input data to obtain a calculation result of the decoder internal posterior probability branch metric; and shifting the calculation result of the decoder internal posterior probability branch metric by the bit width shift value to obtain a component decoding output value. The method has the beneficial effect of improving decoding performance and is applicable to the technical field of TURBO code decoding.

Description

Technical Field

[0001] The present application relates to the technical field of TURBO code decoding, and in particular to a TURBO code component decoding method, a TURBO code decoding method, and related equipment. Background Art

[0002] TURBO codes, also known as Parallel Concatenated Convolutional Codes (PCCC), combine convolutional codes with random interleavers, fully utilizing randomized coding conditions. They construct long codes from short codes through an interleaver and use soft-output iterative decoding to approximate maximum likelihood decoding, thereby achieving decoding performance that is almost close to the Shannon theoretical limit.

[0003] The TURBO code decoder primarily consists of two component decoders. The decoding process is an iterative process between the two component decoders, and the decoded output is finally determined through hard decision. Currently, each component decoder in a TURBO code decoder uses a soft-input-output decoding algorithm (SIS0) to calculate the decoded log-likelihood ratio (LLR). The LLR is calculated from internal variables such as the forward recursive probability alpha and the backward recursive probability beta.

[0004] During hardware implementation, for conventional TURBO code decoders, once the design is complete, the bit width of each internal variable data is fixed and will not change. The unchanged bit width of each variable data will result in a very limited data processing range. When the log-likelihood ratios (LLRs) of the three inputs of the TURBO code decoder (i.e., prior information, code information, and check information) are large, the internal variables are easily saturated during calculation, resulting in a decrease in decoding performance. For example, in the case of low bit rates, since the forward recursive probability alpha and the backward recursive probability beta variables are calculated in serial cascade in a recursive manner, even in the presence of an anti-saturation mechanism, since the effective information (referred to as soft information) of the three soft bits input at low bit rates accounts for a high proportion, the forward recursive probability alpha and the backward recursive probability beta will also be saturated when calculated step by step. Once the forward recursive probability alpha and the backward recursive probability beta variables are saturated at a certain moment, there is a high probability that the calculation results of the forward recursive probability alpha and the backward recursive probability beta at all subsequent moments will be saturated. This means that the forward and backward probabilities of all states calculated for each subsequent bit have no distinction, resulting in inaccurate calculated posterior probabilities for each bit, and ultimately leading to incorrect decoding results.

[0005] Furthermore, in the case of high-order modulation (such as 256QAM), log-likelihood ratio (LLR) demodulation is often used to increase the accuracy of the effective bit width of the decoded input and improve decoding performance. However, due to its high computational complexity, current systems may not yet support LLR-based demodulation, or the current decoder may be limited in the data range it can process and does not support the data range output by LLR-based demodulation. Therefore, the effective bit width of the LLR output when simplifying 256QAM demodulation is very limited. Moreover, when the system schedules 256QAM, the encoding bit rate is often very high, which means that the effective information of the soft bits in the check path during decoding is relatively small. When these two factors coexist, the Le accuracy of each iteration update in TURBO code decoding is very low, resulting in inaccurate prior information transmitted in each iteration, ultimately leading to a decrease in decoding performance.

[0006] Therefore, to simplify the demodulation method, the effective bit width of the decoder needs to be increased during demodulation. Increasing the effective bit width means that the LLR value becomes larger. Usually, at high bit rates, variables such as alpha and beta will not be saturated. However, due to the increase in the input log-likelihood ratio LLR value, if the parameter LLRbranch of the branch metric of the posterior probability inside the decoder is fixed at the beginning of the design and consistent with the bit width of variables such as alpha, beta, and gamma, then LLRbranch will have a high probability of saturation, resulting in the 8-way branch calculation results of the posterior probability being exactly the same under the base-2 algorithm. There is a 50% probability of error in the calculation of the posterior probability, resulting in a serious degradation of decoding performance and decoding errors under normal demodulation SNR. Summary of the Invention

[0007] The embodiments of the present application provide a component decoding method of a TURBO code, a decoding method of a TURBO code, and related equipment that can effectively improve decoding performance.

[0008] A first aspect of an embodiment of the present application provides a component decoding method for a TURBO code, comprising the following steps:

[0009] Receive and demodulate the data to be decoded according to the scheduling configuration to obtain decoded input data; and calculate the code rate and modulation order of the decoded input data;

[0010] Calculating, according to the modulation order and code rate of the decoded input data, an adjustment value of the decoded input data and a bit width shift value of a posterior probability branch metric parameter within the decoder;

[0011] Adjusting the numerical value of the decoded input data by using the adjustment value to obtain first decoded input data;

[0012] Performing component decoding on the first decoding input data to obtain calculation results of a posterior probability branch metric within the decoder;

[0013] The calculation result of the posterior probability branch metric inside the decoder is shifted by the bit width shift value to obtain a component decoding output value.

[0014] In an optional embodiment of the present application, calculating the code rate and modulation order of the decoded input data includes:

[0015] performing rate matching on the decoded input data and outputting a multi-channel soft information sequence;

[0016] Calculating a code rate of the decoded input data according to a length of an input sequence of the decoded input data before rate matching and a length of each soft information sequence output by rate matching;

[0017] The modulation order of the decoded input data is obtained according to the data symbol of the decoded input data in the scheduling configuration.

[0018] In an optional embodiment of the present application, calculating the adjustment value of the decoded input data and the bit width shift value of the posterior probability branch metric parameter within the decoder according to the modulation order and code rate of the decoded input data includes:

[0019] Determining the modulation order of the decoded input data;

[0020] If the modulation order of the decoded input data is a first high-order modulation order, determining whether the code rate of the decoded input data is greater than or equal to a first code rate threshold; if so, setting the adjustment value of the decoded input data equal to the first adjustment value, and setting the shift value of the branch metric parameter of the internal a posteriori probability of the decoder equal to the first shift value; otherwise, setting the adjustment value of the decoded input data and the shift value of the branch metric parameter of the internal a posteriori probability of the decoder to 0;

[0021] If the modulation order of the decoded input data is lower than the first higher-order modulation order, the shift value of the branch metric parameter of the posterior probability within the decoder is set to 0; and based on the modulation order and code rate value corresponding to the decoded input data, an adjustment value corresponding to the decoded input data is output; wherein: different modulation orders or code rate values ​​correspond to different adjustment values, and the lower the code rate or modulation order, the larger the corresponding adjustment value.

[0022] In an optional embodiment of the present application, outputting the adjustment value of the decoded input data according to the modulation order and code rate of the decoded input data includes:

[0023] Determine whether the modulation order of the decoded input data is the second highest modulation order, or whether the code rate of the decoded input data is greater than or equal to a second code rate threshold; if so, set the adjustment value of the decoded input data to 0; otherwise, execute the following steps;

[0024] Determine whether the modulation order of the decoded input data is a third high-order modulation order, or whether the code rate of the decoded input data is greater than or equal to a third code rate threshold and less than a second code rate threshold; if so, set the adjustment value of the decoded input data equal to the second adjustment value; otherwise, execute the following steps;

[0025] determining whether the modulation order of the decoded input data is a low-order modulation order, or whether the code rate of the decoded input data is less than a third code rate threshold; if so, setting the adjustment value of the decoded input data equal to the third adjustment value;

[0026] Wherein, the second high-order modulation order is greater than the third high-order modulation order, and the third high-order modulation order is greater than the low-order modulation order;

[0027] The third adjustment value is greater than the second adjustment value, and the second adjustment value is greater than the first adjustment value.

[0028] In an optional embodiment of the present application, the first shift value is equal to a negative first adjustment value.

[0029] In an optional embodiment of the present application, the demodulation method of the decoded input data is simplified demodulation; the bit-level processing bit width during the simplified demodulation is the same as the internal bit width of the TURBO decoder.

[0030] A second aspect of an embodiment of the present application provides a TURBO code decoding method, comprising: iterative calculation through two component decoders, and outputting an iterative calculation result; during the iterative calculation process, executing a TURBO code component decoding method as described above.

[0031] According to a third aspect of the present application, a component decoding device for a TURBO code is provided, including:

[0032] The demodulation module is used to receive and demodulate the data to be decoded according to the scheduling configuration to obtain decoded input data; and calculate the code rate and modulation order of the decoded input data;

[0033] A parameter calculation module, configured to calculate an adjustment value of the decoded input data and a bit width shift value of a posterior probability branch metric parameter within the decoder according to a modulation order and a code rate of the decoded input data;

[0034] a numerical value adjustment module, configured to adjust the numerical value of the decoded input data by using the adjustment value to obtain first decoded input data;

[0035] A decoding module, configured to perform component decoding on the first decoding input data to obtain a calculation result of a posterior probability branch metric within the decoder;

[0036] The bit width adjustment module is used to perform shift processing on the calculation result of the posterior probability branch metric inside the decoder by using the bit width shift value to obtain a component decoding output value.

[0037] According to a fourth aspect of the embodiments of the present application, a TURBO code decoding device is provided, comprising: a component decoding device, a deinterleaving module and a hard decision module, wherein the component decoding device is the TURBO code component decoding device as described above.

[0038] According to a fifth aspect of the embodiments of the present application, a computer device is provided, comprising: a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any of the above methods when executing the computer program.

[0039] According to a sixth aspect of the embodiments of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above methods are implemented.

[0040] The embodiments of the present application adopt the above technical solutions, which have the following technical effects:

[0041] 1. In the present application, for a TURBO code decoder with a fixed and non-expandable bit width in the prior art when memory space is limited, the numerical size of the decoding input data and the bit width of the posterior probability branch metric parameter within the decoder can be adjusted according to different code rates and modulation orders. After the numerical size of the decoding input data is adjusted, it is possible to avoid the problem that when the input value of the traditional TURBO code decoder is large, the internal variables are easily saturated during calculation, resulting in a decrease in decoding performance; after the bit width of the posterior probability branch metric parameter within the decoder is adjusted, it is possible to avoid the problem that the forward probability and backward probability calculation results are easily saturated during calculation within the decoder, and the decoding performance is affected by insufficient accuracy of external information updated in each iterative update of high-order modulation. This can effectively improve decoding performance and is extremely practical.

[0042] 2. In the present application, in order to reduce the saturation of the branch metric parameters of the posterior probability inside the decoder, according to the decoding input data received by the current scheduling configuration, when the modulation order of the decoding input data is not 256QAM, only the effective value of the decoding input data (the value operated is the log-likelihood ratio LLR) is adjusted; when the modulation order is 256QAM and the code rate is high, in order to prevent the branch metric parameters of the posterior probability inside the decoder from being saturated when the log-likelihood ratio of the decoding input data is large, the calculation results of the branch metric parameters of the posterior probability inside the decoder are dynamically shifted according to the adjustment value of the decoding input data to ensure that the calculation results of the 8 branches are not saturated and have obvious discrimination, thereby improving the decoding performance of high-order modulation and high code rate.

[0043] 3. In this application, according to the scheduling configuration, the decoder dynamically schedules the data to be decoded and calculates the code rate and modulation order; and based on this, calculates the adjustment value of the decoding input data under different scenarios (different code rates and modulation orders) and the bit width shift value of the branch metric parameter of the posterior probability inside the decoder, and performs corresponding numerical adjustment and shift processing to avoid the degradation of decoding performance caused by the fixed bit width of the posterior probability branch metric parameter output by the component decoder inside the prior art under saturation. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0045] Figure 1 It is a structural diagram of a TURBO decoder in the prior art;

[0046] Figure 2 A flowchart of a component decoding method for a TURBO code provided in one embodiment of the present application;

[0047] Figure 3 This is a flowchart of step S1 in a component decoding method of a TURBO code provided in one embodiment of the present application;

[0048] Figure 4 This is a flowchart of step S2 in a component decoding method of a TURBO code provided in one embodiment of the present application;

[0049] Figure 5 This is a flowchart of step S23 of a component decoding method for a TURBO code provided in one embodiment of the present application;

[0050] Figure 6A flowchart of calculating the adjustment value of the decoding input data and the bit width shift value of the posterior probability branch metric parameter inside the decoder in a TURBO decoding method in a specific implementation;

[0051] Figure 7 A schematic structural diagram of a component decoding device for a TURBO code provided in one embodiment of the present application;

[0052] Figure 8 A schematic diagram of the computer device structure provided in one embodiment of the present application;

[0053] In the picture:

[0054] 10 is a demodulation module, 20 is a parameter calculation module, 30 is a value adjustment module, 40 is a decoding module, and 50 is a bit width adjustment module. DETAILED DESCRIPTION

[0055] During the implementation of this application, the inventors discovered that, once the design of a current TURBO code decoder is complete, the bit widths of the variables processed internally are fixed and unchangeable. This fixed bit width results in a very limited data range for processing. Because the TURBO code decoder's decoding input data is the log-likelihood ratio (LLR) of the sampled data, when the input LLR value is large, the internal variables are easily saturated during calculation, resulting in a decrease in decoding performance.

[0056] To address the above problems, an embodiment of the present application provides a component decoding method for a TURBO code.

[0057] The solutions in the embodiments of the present application can be implemented using various computer languages, for example, the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0058] In order to make the technical solutions and advantages of the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, and are not an exhaustive list of all the embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other unless they conflict.

[0059] The following briefly describes the application environment of a component decoding method for a TURBO code provided in an embodiment of the present application. Figure 1During TURBO code decoding, existing TURBO code decoders typically consist of two component decoders with soft input and soft output, an interleaver, and a deinterleaver. The decoded output is obtained through alternating decoding of the input signal, multiple rounds of soft output decoding, and hard judgment. The decoder's internal posterior probability branch metric parameter, LLRbranch, refers to the posterior information output by the component decoder. During decoding, LLRbranch is calculated from the forward recursive probability alpha and the backward recursive probability beta. These alpha and beta variables are calculated recursively and serially.

[0060] At low bit rates, the input data ratio of the TURBO code decoder is very high, which will cause saturation of the alpha and beta variables during step-by-step calculation, resulting in inaccurate posterior probability of each bit calculated, and ultimately leading to incorrect decoding results.

[0061] See Figure 2 For example, an embodiment of the present application provides a component decoding method for a TURBO code, comprising the following steps:

[0062] S1, receiving and demodulating data to be decoded according to the scheduling configuration to obtain decoded input data; and calculating the code rate and modulation order of the decoded input data;

[0063] S2, calculating the adjustment value of the decoded input data and the bit width shift value of the posterior probability branch metric parameter within the decoder according to the modulation order and code rate of the decoded input data;

[0064] S3, adjusting the numerical value of the decoded input data by using the adjustment value to obtain first decoded input data;

[0065] S4, performing component decoding on the first decoding input data to obtain calculation results of the posterior probability branch metrics within the decoder;

[0066] S5, performing shift processing on the calculation result of the posterior probability branch metric inside the decoder by the bit width shift value to obtain a component decoding output value.

[0067] In this embodiment, for a conventional TURBO code decoder with a fixed and non-expandable bit width when memory space is limited, the numerical value of the decoded input data and the bit width of the decoder's internal posterior probability branch metric parameters can be adjusted according to different code rates and modulation orders. The adjustment of the numerical value of the decoded input data can avoid the problem of internal variables being easily saturated during calculation when the input value of the conventional TURBO code decoder is large, thereby reducing decoding performance. The adjustment of the bit width of the decoder's internal posterior probability branch metric parameters can also avoid the problem of forward probability and backward probability calculation results being easily saturated during calculation within the decoder, as well as the problem of decoding performance being affected by insufficient precision of external information updated in each iterative update of high-order modulation. This effectively improves decoding performance and is highly practical.

[0068] See Figure 3 , the calculating the code rate and modulation order of the decoded input data includes:

[0069] S11, performing rate matching on the decoded input data and outputting a multi-channel soft information sequence;

[0070] S12, calculating the bit rate of the decoded input data according to the length of the input sequence of the decoded input data before rate matching and the length of each soft information sequence output by rate matching;

[0071] S13, obtaining a modulation order of the decoded input data according to the data symbols of the decoded input data in the scheduling configuration.

[0072] In an optional embodiment of the present application, the acquisition of the modulation order can be achieved by:

[0073] According to the interface MCS level scheduled to the physical layer by the protocol stack, the modulation order is obtained by looking up Table 8.6.1-1 in protocol 36.213.

[0074] Table 8.6.1-1: PUSCH modulation, TBS index and redundancy version table

[0075]

[0076]

[0077] The Modulation and Coding Scheme (MCS) level is a parameter used to characterize the transmission rate and reliability of the physical layer in wireless communication systems. In the protocol stack, higher-level protocols select the appropriate MCS level for dispatch to the physical layer based on factors such as current channel conditions and data volume.

[0078] Specifically, the MCS level includes the modulation method (such as QPSK, 16-QAM, 64-QAM, etc.) and the coding rate (such as 1 / 2, 3 / 4, 5 / 6, etc.). Different combinations correspond to different transmission rates and anti-interference capabilities. Higher MCS levels generally mean higher transmission rates, but also have higher requirements for channel quality. Lower MCS levels have better anti-interference capabilities, but lower transmission rates.

[0079] Table 8.6.1-1: PUSCH modulation, TBS index, and redundancy version table defines the modulation order and TBS index corresponding to different MCS levels during uplink scheduling. The network side notifies the terminal (user side) of the determined MCS level through the indication information in the downlink control information DCI. The terminal uses the MCS level indicated in the indication information received in the PDCCH to obtain the modulation mode and coding rate used by the base station for the PUSCH scheduled by the terminal. Based on the corresponding relationship in Table 8.6.1-1, the terminal determines the modulation order and TBS index corresponding to the MCS level, determines the transport block size in the PUSCH, and encodes and modulates the corresponding data in the PUSCH.

[0080] In an optional embodiment of the present application, the calculation expression for calculating the code rate of the decoded input data may be:

[0081] R = K / E;

[0082] Wherein, R represents the code rate of the decoded input data, K represents the length of the input sequence of the decoded input data before rate matching, and E represents the length of each soft information sequence output by rate matching.

[0083] See also Figure 4 In an optional embodiment, step S2, calculating the adjustment value of the decoded input data and the bit width shift value of the decoder internal posterior probability branch metric parameter according to the modulation order and code rate of the decoded input data, includes:

[0084] S21, determining the modulation order of the decoded input data;

[0085] S22, if the modulation order of the decoded input data is the first high-order modulation order, determining whether the code rate of the decoded input data is greater than or equal to the first code rate threshold; if so, setting the adjustment value of the decoded input data equal to the first adjustment value, and setting the shift value of the branch metric parameter of the internal a posteriori probability of the decoder equal to the first shift value; otherwise, setting the adjustment value of the decoded input data and the shift value of the branch metric parameter of the internal a posteriori probability of the decoder to 0;

[0086] S23, if the modulation order of the decoded input data is lower than the first higher-order modulation order, setting the shift value of the branch metric parameter of the posterior probability within the decoder to 0; and outputting an adjustment value corresponding to the decoded input data based on the modulation order and code rate value corresponding to the decoded input data;

[0087] Different modulation orders or code rates correspond to different adjustment values, and the lower the code rate or modulation order, the larger the corresponding adjustment value.

[0088] In this embodiment, the first shift value is equal to a negative first adjustment value.

[0089] In this embodiment, to reduce the saturation of variables such as the forward recursive probability alpha, the backward recursive probability beta, and the branch metric LLRbranch of the posterior probability during internal calculations within the decoder, the code rate and modulation order of the decoded input data received according to the current scheduling configuration are calculated. When the modulation order is not 256QAM, only the effective value of the log-likelihood ratio (LLR) is adjusted. When the modulation order is 256QAM and the code rate is high, the effective bit width of the log-likelihood ratio (LLR) is increased. Furthermore, to prevent the branch metric LLRbranch of the posterior probability within the decoder from saturating when the log-likelihood ratio (LLR) value is large, the calculation results of the branch metric LLRbranch are dynamically shifted according to the shift value of the log-likelihood ratio (LLRbranch). This ensures that the calculation results of all eight branches are not saturated and have clear discrimination, thereby improving decoding performance for high-order modulation and high-code rates.

[0090] See also Figure 5 In a specific embodiment, in S23, outputting the adjustment value of the decoded input data according to the modulation order and code rate of the decoded input data includes:

[0091] S23-1, determining whether the modulation order of the decoded input data is the second highest modulation order, or the code rate of the decoded input data is greater than or equal to a second code rate threshold; if so, setting the adjustment value of the decoded input data to 0; otherwise, executing step S21-32;

[0092] S23-2, determining whether the modulation order of the decoded input data is a third higher-order modulation order, or whether the code rate of the decoded input data is greater than or equal to the third code rate threshold and less than the second code rate threshold; if so, setting the adjustment value of the decoded input data equal to the second adjustment value; otherwise, executing step S21-33;

[0093] S23-3, determining whether the modulation order of the decoded input data is a low modulation order, or whether the code rate of the decoded input data is less than a third code rate threshold; if so, setting the adjustment value of the decoded input data equal to the third adjustment value;

[0094] Wherein, the second high-order modulation order is greater than the third high-order modulation order, and the third high-order modulation order is greater than the low-order modulation order;

[0095] The third adjustment value is greater than the second adjustment value, and the second adjustment value is greater than the first adjustment value.

[0096] In this embodiment, according to the current scheduling configuration, the decoder dynamically schedules the data to be decoded and calculates the code rate and modulation order; and based on this, calculates the adjustment value of the decoding input data under different scenarios (code rate and modulation order) and the shift value of the branch metric parameter of the posterior probability inside the decoder, and performs corresponding numerical adjustment and shift processing to avoid the degradation of decoding performance caused by the fixed bit width of the posterior probability branch metric parameter output by the component decoder inside the prior art under saturation.

[0097] See Figure 6 , in a specific implementation, the first high-order modulation order is 256QAM, the second high-order modulation order is 64QM, the third high-order modulation order is 16QAM, and the low-order modulation order is QPSK;

[0098] The first bitrate threshold is 0.9, the second bitrate threshold is 0.7, and the third bitrate threshold is 0.5;

[0099] The first adjustment value is -1, the first shift value is 1; the second adjustment value is 1, and the third adjustment value is 2.

[0100] The specific values ​​of the first bit rate threshold, the second bit rate threshold, and the third bit rate threshold are determined based on a large number of simulation experiments and empirical values.

[0101] Different code rates (original information bit length / derate matching output bit length) represent the proportion of effective soft information to the three-way soft information. Therefore, the lower the code rate, the higher the proportion of effective soft information, and the more likely the internal processing of the decoder is to be saturated, so the shift value is larger.

[0102] In this embodiment, the adjustment value of the decoded input data and the shift value of the branch metric parameter of the internal posterior probability of the decoder can be assigned according to different scenarios to obtain a data bit width suitable for the internal variables of the decoder under different code rates and modulation orders, thereby improving the calculation accuracy.

[0103] Generally, the information stream input to the decoder is input in the order of system bit, first check bit, and second check bit. According to the scheduling configuration, when the demodulated valid data is input to the decoder, it is first demultiplexed and rate-matched to obtain three information streams.

[0104] In this embodiment, rate dematching is the inverse process of rate matching. The rate matching input data stream is the system bit, first check bit, and second check bit data obtained after Turbo encoding. The rate matching processing generally includes three processes: sub-block interleaving, bit aggregation, and bit selection.

[0105] At the receiving end, the data input to the rate dematching is the soft bit data after channel (e.g., QAM, QPSK) demodulation and descrambling (specifically, the decoded input data in this embodiment), and the three-way soft information generated by TURBO code encoding is recovered through rate dematching. The rate dematching processing flow generally includes three steps: debit selection, debit collection, and debit interleaving.

[0106] In an optional embodiment of the present application, the multi-channel soft information sequence output by the rate matching is numerically adjusted according to the adjustment value of the decoded input data to obtain the first decoded input data, and the calculation expression of the numerical adjustment is:

[0107] sys_1=sys / 2 M ;

[0108] parity_1=p1 / 2 M ;

[0109] parity_2=p2 / 2 M ;

[0110] Among them, sys, p1 and p2 are respectively the system bit information sequence, the first check bit information sequence and the second check bit information sequence output by rate matching; sys_1, parity_1 and parity_2 are respectively the three-way soft information sequences contained in the first decoding input data after numerical adjustment.

[0111] In an optional embodiment of the present application, the process of determining the adjustment value of the decoded input data (the operated data is the log-likelihood ratio LLR) and the calculation value of the branch metric LLRbranch of the internal posterior probability of the decoder based on the code rate and modulation order of the decoded input data is based on the fact that the demodulation method of the decoded input data is simplified demodulation; and the bit-level processing bit width during the simplified demodulation is the same as the internal bit width of the TURBO decoder.

[0112] Among them, the simplified demodulation is a demodulation method that simplifies the original LLR demodulation method. It omits the data range judgment internally and does not perform constellation scaling processing on the input data based on the SNR compared to the original LLR demodulation method. Therefore, the numerical range of the soft bits output by the simplified demodulation is relatively small and the confidence is relatively low.

[0113] Generally, when a turbo decoder performs decoding processing, it usually applies the MAX-log-MAP algorithm to the data to be decoded to calculate the gamma value (branch transfer variable value), alpha value and beta value, and calculates the log-likelihood ratio (LLR) of each bit for hard decision based on the gamma value, alpha value and beta value.

[0114] Specifically, the log-likelihood ratio (LLR) of the k-th bit for hard decision is calculated using the following formula:

[0115] llr(k)=llr 0(k) -llr 1(k)

[0116] Where llr(k) represents the log-likelihood ratio LLR of the k-th bit for hard decision; llr 0(k) represents the posterior probability that the kth bit is decoded to 0, llr 1(k) represents the posterior probability that the kth bit is decoded to 1.

[0117] According to the state transition relationship, the posterior probability llr that the kth bit is decoded to 0 0(k) The expression is:

[0118] llr 0(k) =max(LLRbranch k，0(m) , m=0,1...7)

[0119] The posterior probability llr that the kth bit is decoded to 1 1(k) for:

[0120] llr 0(k) =max(LLRbranch k，1(m) , m=0,1...7)

[0121] Where m represents the number of possible state conditions inside the component decoder;

[0122] LLRbranch k，0(m) The state transition probability of the mth case where the kth bit is decoded to 0 (which can be expressed by the calculation formula of the branch metric LLRbranch of the decoder's internal posterior probability below);

[0123] LLRbranch k，1(m) represents the state transition probability of the mth case when the kth bit is decoded to 1.

[0124] In specific implementation, when the base 2 algorithm calculates each bit decoded to 0, the calculation formula of the branch metric LLRbranch of the decoder's internal posterior probability is:

[0125]

[0126]

[0127]

[0128]

[0129]

[0130]

[0131]

[0132]

[0133] Among them, LLRbranch k，0 (0)~LLRbranch k，0 (7) represents the state transition probability when the kth bit is decoded to 0 when the state conditions are 0 to 7 respectively;

[0134] α k (0)~α k (7) represents the forward probability of the kth bit in states 0 to 7 respectively;

[0135] β k+1 (0)~β k+1 (7) respectively represent the backward probability of the k+1th bit when it is in state m;

[0136] γ k Indicates the branch transfer variable of the k-th bit, including four cases:

[0137] Specifically, when the base-2 algorithm calculates that each bit is decoded to 1, the calculation formula of the branch metric LLRbranch of the posterior probability inside the decoder is:

[0138]

[0139]

[0140]

[0141]

[0142]

[0143]

[0144]

[0145]

[0146] Among them, LLRbranch k，1 (0)~LLRbranch k，1 (7) represents the state transition probability when the kth bit is decoded to 1 when the state conditions are 0 to 7 respectively;

[0147] α k (0)~α k (7) represents the forward probability of the kth bit in states 0 to 7 respectively;

[0148] β k+1 (0)~β k+1 (7) respectively represent the backward probability of the k+1th bit when it is in state m;

[0149] γ k Indicates the branch transfer variable of the k-th bit, including four cases:

[0150] An embodiment of the present application further provides a TURBO code decoding method, comprising: performing iterative calculations through two component decoders and outputting iterative calculation results; during the iterative calculation process, executing any of the above-described TURBO code component decoding methods.

[0151] In an optional embodiment of the present application, in the above-mentioned TURBO code decoding method, when executing each iteration, after obtaining the output decoding information, first obtain the maximum initial state index and the maximum final state index corresponding to the maximum backward probability value of the initial state and the maximum forward probability value of the final state output by the decoder, respectively;

[0152] Then determine whether the maximum initial state index and the maximum final state index are consistent;

[0153] If they are consistent, the decoded information output by the decoder is verified, and then the decoding is terminated or the next iterative decoding is performed according to the verification result;

[0154] If they are inconsistent, the next iterative decoding will be performed directly.

[0155] In an optional embodiment of the present application, when the maximum initial state index and the maximum terminal state index are consistent, verifying the decoded information output by the decoder, and then ending decoding or continuing to perform the next iterative decoding based on the verification result, specifically includes:

[0156] Deinterleaving the decoded information output by the decoder to obtain deinterleaved information;

[0157] Performing hard decision processing on the deinterleaved information to obtain a hard decision result;

[0158] Perform CRC check on the hard decision result and make a judgment on the CRC check result;

[0159] If the CRC check passes, the hard decision result and CRC check result are output, and the decoding ends;

[0160] If the CRC check fails, determine whether the current number of iterations is equal to the maximum number of iterations. If so, output the hard decision result and CRC check result and end decoding. If not, continue to perform the next iterative decoding.

[0161] In an optional embodiment of the present application, when the maximum initial state index and the maximum final state index are inconsistent, directly continuing to perform the next iterative decoding specifically includes:

[0162] Determine whether the current number of iterations is equal to the maximum number of iterations;

[0163] If they are equal, first deinterleave the decoded information output by the decoder to obtain deinterleaved information, then perform hard decision processing on the deinterleaved information to obtain a hard decision result, then directly set the CRC check result of the hard decision result to CRC check failure, finally output the hard decision result and CRC check result, and end decoding;

[0164] If not, continue to perform the next iterative decoding.

[0165] In an optional embodiment of the present application, obtaining the maximum initial state index and the maximum final state index corresponding to the maximum backward probability value of the initial state and the maximum forward probability value of the final state output by the decoder, respectively, specifically includes:

[0166] Calculate the backward probability set of the initial state and the forward probability set of the terminal state output by the decoder;

[0167] Compare the backward probability set and the forward probability set respectively to obtain the maximum backward probability value in the backward probability set and the maximum forward probability value in the forward probability set;

[0168] According to the maximum backward probability value and the maximum forward probability value, the corresponding maximum initial state index and the maximum terminal state index are obtained.

[0169] In an optional embodiment of the present application, after obtaining the backward probability set of the initial state and the forward probability set of the terminal state output by the decoder, the backward probability set and the forward probability set are stored as one of the iterative information input into the decoder when performing the next iterative decoding.

[0170] See Figure 7, an embodiment of the present application further provides a component decoding device for a TURBO code, comprising:

[0171] The demodulation module 10 is used to receive and demodulate the data to be decoded according to the scheduling configuration to obtain decoded input data; and calculate the code rate and modulation order of the decoded input data;

[0172] A parameter calculation module 20 is configured to calculate an adjustment value of the decoded input data and a bit width shift value of a posterior probability branch metric parameter within the decoder according to the modulation order and code rate of the decoded input data;

[0173] a numerical value adjustment module 30, configured to adjust the numerical value of the decoded input data by using the adjustment value to obtain first decoded input data;

[0174] A decoding module 40 is configured to perform component decoding on the first decoding input data to obtain calculation results of a posterior probability branch metric within the decoder;

[0175] The bit width adjustment module 50 is configured to perform a bit width shift process on the calculation result of the posterior probability branch metric within the decoder by using the bit width shift value to obtain a component decoding output value.

[0176] An embodiment of the present application further provides a TURBO code decoding device, comprising: a component decoding device, a deinterleaving module, and a hard decision module. The component decoding device is the TURBO code component decoding device described above.

[0177] For the specific definitions of the aforementioned TURBO code decoding method, TURBO code component decoding device, and TURBO code decoding device, please refer to the definitions of the aforementioned TURBO code component decoding method and will not be repeated here. Each module in the aforementioned TURBO code component decoding device and TURBO code decoding device may be implemented in whole or in part via software, hardware, or a combination thereof. Each of the aforementioned modules may be embedded in or independent of a processor in a computer device in hardware form, or may be stored in a computer device memory in software form, so that the processor can call and execute the corresponding operations of each of the aforementioned modules.

[0178] In summary, when the bit width of the internal variables of the traditional decoder is fixed and cannot be modified, the present application can cope with different scenarios by simply adjusting the size of the input LLR of the decoder and performing simple shift processing inside the decoder, thereby avoiding internal variable overflow and improving calculation accuracy. The operation is simple and will not increase additional time or affect the overall timing arrangement inside the decoder.

[0179] At the same time, the present application can improve the fixed-point decoding performance of high-order modulation and high code rate under a fixed bit width decoder and a fixed demodulation scheme, and effectively reduce the storage space without affecting the decoding performance.

[0180] It should be understood that, although the various steps in the flowchart are shown in sequence as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps may be performed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily performed at the same time, but may be performed at different times. The execution order of these sub-steps or stages is not necessarily to be performed in sequence, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0181] In one embodiment, a computer device is provided. The internal structure diagram of the computer device can be as follows: Figure 8 As shown. The computer device includes a processor, a memory, a network interface and a database connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, it implements a TURBO decoding method as described above, including: a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, it implements any step in the TURBO code decoding method as described above.

[0182] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, any step in the above TURBO code decoding method can be implemented.

[0183] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0184] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0185] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0186] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0187] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0188] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A component decoding method for a TURBO code, characterized in that: The following steps are involved: Receive and demodulate the data to be decoded according to the scheduling configuration to obtain decoded input data; and calculating the code rate and modulation order of the decoded input data; According to the modulation order and code rate of the decoding input data, the adjustment value of the decoding input data and the bit width shift value of the branch metric parameter of the internal a posteriori probability of the decoder are calculated, including: judging the modulation order of the decoding input data; if the modulation order of the decoding input data is a first high-order modulation order, judging whether the code rate of the decoding input data is greater than or equal to a first code rate threshold, and if so, setting the adjustment value of the decoding input data equal to the first adjustment value, and the shift value of the branch metric parameter of the internal a posteriori probability of the decoder equal to the first shift value; otherwise, setting the adjustment value of the decoding input data and the shift value of the branch metric parameter of the internal a posteriori probability of the decoder to 0; if the modulation order of the decoding input data is lower than the first high-order modulation order, setting the shift value of the branch metric parameter of the internal a posteriori probability of the decoder to 0; judging whether the modulation order of the decoding input data is a second high-order modulation order, or whether the code rate of the decoding input data is greater than or equal to a second code rate threshold. ; If so, set the adjustment value of the decoded input data to 0; otherwise, execute the following steps: determine whether the modulation order of the decoded input data is a third high-order modulation order, or whether the code rate of the decoded input data is greater than or equal to the third code rate threshold and less than the second code rate threshold; if so, set the adjustment value of the decoded input data to be equal to the second adjustment value; otherwise, execute the following steps: determine whether the modulation order of the decoded input data is a low-order modulation order, or the code rate of the decoded input data is less than the third code rate threshold; if so, set the adjustment value of the decoded input data to be equal to the third adjustment value; wherein, the second high modulation order is greater than the third high-order modulation order, and the third high-order modulation order is greater than the low-order modulation order; the third adjustment value is greater than the second adjustment value, and the second adjustment value is greater than the first adjustment value; wherein: different modulation orders or code rate values ​​correspond to different adjustment values, and the lower the code rate or modulation order, the larger the corresponding adjustment value; Adjusting the numerical value of the decoded input data by using the adjustment value to obtain first decoded input data; Performing component decoding on the first decoding input data to obtain calculation results of a posterior probability branch metric within the decoder; The calculation result of the posterior probability branch metric inside the decoder is shifted by the bit width shift value to obtain a component decoding output value.

2. The component decoding method of a TURBO code according to claim 1, characterized in that: Calculating the code rate and modulation order of the decoded input data, including: performing rate matching on the decoded input data and outputting a multi-channel soft information sequence; Calculating a code rate of the decoded input data according to a length of an input sequence of the decoded input data before rate matching and a length of each soft information sequence output by rate matching; The modulation order of the decoded input data is obtained according to the data symbol of the decoded input data in the scheduling configuration.

3. The component decoding method of a TURBO code according to claim 1, characterized in that: The demodulation mode of the decoded input data is simplified demodulation; the bit-level processing width during the simplified demodulation is the same as the internal bit width of the TURBO decoder.

4. A method for decoding a TURBO code, comprising: Iterative calculation is performed through two component decoders to output iterative calculation results; it is characterized in that during the iterative calculation process, the component decoding method of TURBO code according to any one of claims 1 to 3 is executed.

5. A component decoding device for a TURBO code, characterized in that: include: A demodulation module (10) is used to receive and demodulate data to be decoded according to the scheduling configuration to obtain decoded input data; and calculating the code rate and modulation order of the decoded input data; The parameter calculation module (20) is used to calculate the adjustment value of the decoded input data and the bit width shift value of the decoder internal posterior probability branch metric parameter according to the modulation order and code rate of the decoded input data, including: judging the modulation order of the decoded input data; if the modulation order of the decoded input data is the first high-order modulation order, judging whether the code rate of the decoded input data is greater than or equal to the first code rate threshold, and if so, setting the adjustment value of the decoded input data equal to the first adjustment value, and the shift value of the decoder internal posterior probability branch metric parameter equal to the first shift value; otherwise, setting the adjustment value of the decoded input data and the shift value of the decoder internal posterior probability branch metric parameter to 0; if the modulation order of the decoded input data is lower than the first high-order modulation order, setting the shift value of the decoder internal posterior probability branch metric parameter to 0; judging whether the modulation order of the decoded input data is the second high-order modulation order, or whether the decoder input data code rate is greater than or equal to the first code rate threshold; at the second code rate threshold; if so, setting the adjustment value of the decoded input data to 0; otherwise, executing the following steps: determining whether the modulation order of the decoded input data is a third high-order modulation order, or whether the code rate of the decoded input data is greater than or equal to the third code rate threshold and less than the second code rate threshold; if so, setting the adjustment value of the decoded input data to be equal to the second adjustment value; otherwise, executing the following steps: determining whether the modulation order of the decoded input data is a low-order modulation order, or whether the code rate of the decoded input data is less than the third code rate threshold; if so, setting the adjustment value of the decoded input data to be equal to the third adjustment value; wherein, the second high-order modulation order is greater than the third high-order modulation order, and the third high-order modulation order is greater than the low-order modulation order; the third adjustment value is greater than the second adjustment value, and the second adjustment value is greater than the first adjustment value; wherein: different modulation orders or code rate values ​​correspond to different adjustment values, and the lower the code rate or modulation order, the larger the corresponding adjustment value; A numerical value adjustment module (30) is used to adjust the numerical value of the decoded input data by using the adjustment value to obtain first decoded input data; A decoding module (40) is used to perform component decoding on the first decoding input data to obtain a calculation result of a posterior probability branch metric within the decoder; The bit width adjustment module (50) is used to perform a shift process on the calculation result of the posterior probability branch metric inside the decoder by using the bit width shift value to obtain a component decoding output value.

6. A TURBO code decoding device, comprising: The component decoding device, the deinterleaving module and the hard decision module are characterized in that the component decoding device is a component decoding device of a TURBO code as claimed in claim 5.

7. A computer device comprising: The method comprises a memory and a processor, wherein the memory stores a computer program, and wherein the processor implements the steps of the component decoding method of a TURBO code according to any one of claims 1 to 3, or implements the steps of the decoding method of a TURBO code according to claim 4 when executing the computer program.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the computer program implements the steps of a component decoding method of a TURBO code according to any one of claims 1 to 3, or implements the steps of a decoding method of a TURBO code according to claim 4.

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