Semiconductor device

Abstract

A semiconductor device may include a substrate having a memory cell region including a first active region and a peripheral circuit region including a second active region; a capacitor structure including a first electrode connected to the first active region in the memory cell region, a second electrode including a silicon-containing layer surrounding the first electrode on the memory cell region, and a metal plate layer on the silicon-containing layer; an interlayer insulating layer on the peripheral circuit region; and a cap insulating layer covering the capacitor structure on the memory cell region and covering the interlayer insulating layer on the peripheral circuit region. The capacitor structure may include a capacitor dielectric layer between a first electrode and a second electrode. The metal plate layer may be on an upper surface of the silicon-containing layer and may not be on a side surface of the silicon-containing layer.

Description

Technical Field

[0001] The inventive concept relates to a semiconductor device and / or a method of manufacturing the same, and more particularly, to a semiconductor device including a capacitor and / or a method of manufacturing the same. Background Art

[0002] According to the development of the electronics industry and the needs of users, the shrinking of semiconductor devices has been rapidly progressing. Therefore, the area of ​​a unit cell included in a semiconductor device has been reduced, thereby reducing the area that a capacitor in the unit cell can occupy. Therefore, it is necessary to develop a semiconductor device having a structure in which a desired capacitance is obtained to maintain desired electrical characteristics even when the size of the capacitor is miniaturized. Summary of the invention

[0003] The inventive concepts provide semiconductor devices having improved productivity and / or structural reliability.

[0004] According to an embodiment of the inventive concept, a semiconductor device may include: a substrate including a memory cell region having a first active region and a peripheral circuit region having a second active region; a capacitor structure including a first electrode, a second electrode, and a capacitor dielectric layer between the first electrode and the second electrode, the first electrode being connected to the first active region in the memory cell region, the second electrode including a silicon-containing layer surrounding the first electrode on the memory cell region and a metal plate layer on the silicon-containing layer; an interlayer insulating layer on the peripheral circuit region; and a cap insulating layer covering the capacitor structure on the memory cell region and covering the interlayer insulating layer on the peripheral circuit region. The metal plate layer may be on an upper surface of the silicon-containing layer, and the metal plate layer may not be on a side surface of the silicon-containing layer.

[0005] According to an embodiment of the inventive concept, a semiconductor device may include: a substrate including a memory cell region having a first active region and a peripheral circuit region having a second active region; a capacitor structure including a first electrode, a second electrode, and a capacitor dielectric layer between the first electrode and the second electrode, the first electrode being connected to the first active region in the memory cell region, the second electrode including a silicon-containing layer surrounding the first electrode on the memory cell region and a metal plate layer on the silicon-containing layer; an interlayer insulating layer on the peripheral circuit region; and a cap insulating layer covering the capacitor structure on the memory cell region and covering the interlayer insulating layer on the peripheral circuit region. The upper surface of the silicon-containing layer and the upper surface of the interlayer insulating layer may be coplanar in a horizontal direction.

[0006] According to an embodiment of the inventive concept, a semiconductor device may include: a substrate including a memory cell region having a first active region and a peripheral circuit region having a second active region; a capacitor structure including a first electrode, a second electrode, and a capacitor dielectric layer between the first electrode and the second electrode, the first electrode being connected to the first active region on the memory cell region, the second electrode including a silicon germanium layer surrounding the first electrode on the memory cell region and a metal plate layer on the silicon germanium layer; an interlayer insulating layer on the peripheral circuit region and covering a side surface of the capacitor structure; and a cap insulating layer covering the capacitor structure on the memory cell region and covering the interlayer insulating layer on the peripheral circuit region. The metal plate layer may be on an upper surface of the silicon germanium layer, and the metal plate layer may not be on a side surface of the silicon germanium layer. The upper surface of the silicon germanium layer and the upper surface of the interlayer insulating layer may be coplanar. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0008] Figure 1 is a layout diagram of a semiconductor device according to an embodiment;

[0009] Figure 2 yes Figure 1 An enlarged view of region EX1;

[0010] Figure 3 It is along Figure 2 A cross-sectional view of the semiconductor device taken along line AA';

[0011] Figure 4 is a cross-sectional view of a semiconductor device according to some embodiments;

[0012] Figure 5 is a cross-sectional view of a semiconductor device according to some embodiments; and

[0013] Figures 6 to 18 is a cross-sectional view of a semiconductor device for explaining a method of manufacturing the semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0014] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the accompanying drawings, and repeated description thereof will be omitted.

[0015] Figure 1 is a layout diagram of the semiconductor device 10 according to the embodiment. Figure 2 yes Figure 1 An enlarged view of area EX1. Figure 3 It is along Figure 2 1 is a cross-sectional view of the semiconductor device 10 taken along line AA′.

[0016] refer to Figures 1 to 3 , the semiconductor device 10 may include a substrate 110 including a memory cell area MCA and a peripheral circuit area PCA surrounding the memory cell area MCA.

[0017] The memory cell area MCA may be a memory cell area of ​​a dynamic random access memory (DRAM). The memory cell area MCA may include a plurality of unit memory cells, each of which includes a transistor and a capacitor. The peripheral circuit area PCA may be a core area or a peripheral circuit area of ​​the DRAM. The peripheral circuit area PCA may be an area in which peripheral circuits for driving memory cells in the memory cell area MCA are arranged. For example, the peripheral circuit area PCA may include a peripheral circuit transistor PG, which is configured to transmit signals and / or power to the memory cell area MCA. In one embodiment, the peripheral circuit transistor PG may be included in various circuits such as a command decoder, a control logic, an address buffer, a row decoder, a column decoder, a sense amplifier, and a data input / output circuit.

[0018] The substrate 110 may include a device isolation trench 112T, and the device isolation trench 112T may include a device isolation layer 112. The device isolation layer 112 may include an oxide layer, a nitride layer, or a combination thereof. Through the device isolation layer 112, a plurality of first active regions AC1 may be defined on the substrate 110 in the memory cell area MCA, and a second active region AC2 may be defined on the substrate 110 in the peripheral circuit area PCA.

[0019] A plurality of first active regions AC1 may be arranged in the memory cell area MCA to have a long axis in an oblique direction relative to the first horizontal direction (X direction) and the second horizontal direction (Y direction). A plurality of word lines WL may cross the plurality of first active regions AC1 and extend parallel to the first horizontal direction (X direction). A plurality of bit lines BL may extend parallel to each other and above the plurality of word lines WL in the second horizontal direction (Y direction). The plurality of bit lines BL may be connected to the plurality of first active regions AC1 through a plurality of direct contacts DC.

[0020] A plurality of buried contacts BC may be formed between two adjacent bit lines BL among the plurality of bit lines BL. In some embodiments, the plurality of buried contacts BC may be arranged in a row along a first horizontal direction (X direction) and a second horizontal direction (Y direction). A plurality of landing pads LP may be arranged above the plurality of buried contacts BC. The plurality of buried contacts BC and the plurality of landing pads LP may connect the first electrode 182 of the capacitor structure 180 formed above the plurality of bit lines BL to the plurality of first active regions AC1. At least a portion of each of the plurality of landing pads LP may overlap with the buried contact BC in a vertical direction (Z direction).

[0021] The substrate 110 may include, for example, a semiconductor element such as silicon (Si) and germanium (Ge) or at least one compound semiconductor selected from silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). The substrate 110 may include a conductive region such as a well doped with impurities or a structure doped with impurities.

[0022] In the memory cell area MCA, a plurality of word line trenches (not shown) extending in the first horizontal direction (X direction) may be formed on the substrate 110, and a plurality of gate dielectric layers (not shown), a plurality of gate electrodes (not shown), and a plurality of cap insulating layers (not shown) may be formed in the plurality of word line trenches. The plurality of gate electrodes may correspond to Figure 2 Multiple word lines WL are shown. Multiple gate dielectric layers may include Si oxide, Si nitride, Si oxynitride, oxide / nitride / oxide (ONO), or a high-k dielectric material having a higher dielectric constant than Si oxide. Multiple gate electrodes may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), or a combination thereof. Multiple cap insulating layers may include Si oxide layers, Si nitride layers, Si oxynitride layers, or a combination thereof.

[0023] In the memory cell area MCA, a buffer layer 114 may be disposed on the substrate 110. The buffer layer 114 may include an oxide layer, a nitride layer, or a combination thereof.

[0024] A plurality of direct contacts DC may be formed in a plurality of direct contact holes DCH of the substrate 110. The direct contacts DC may extend to a height higher than the upper surface of the substrate 110. The plurality of direct contacts DC may be connected to the plurality of first active regions AC1. The plurality of direct contacts DC may include Si, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, or a combination thereof. In some embodiments, the plurality of direct contacts DC may each include doped polysilicon. For example, the plurality of direct contacts DC may include polysilicon including relatively high concentrations of impurities such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb).

[0025] A plurality of bit lines BL may extend in parallel with each other along the second horizontal direction (Y direction) on the substrate 110 and each of the plurality of direct contacts DC. The plurality of bit lines BL may be respectively connected to the plurality of first active regions AC1 through the plurality of direct contacts DC. The plurality of bit lines BL may each include a lower conductive layer 132A, an intermediate conductive layer 134A, and an upper conductive layer 136A sequentially stacked on the substrate 110. An upper surface of the lower conductive layer 132A may be arranged at the same vertical height as an upper surface of the direct contact DC, and a bottom surface of the intermediate conductive layer 134A may be in contact with an upper surface of the direct contact DC.

[0026] The lower conductive layer 132A may include doped polysilicon. The intermediate conductive layer 134A and the upper conductive layer 136A may each include Ti, TiN, TiSiN, W, WN, tungsten silicide (WSi x ), tungsten silicon nitride (WSi x N y ), Ru or a combination thereof. For example, the middle conductive layer 134A may include a TiN layer and / or TiSiN, and the upper conductive layer 136A may include a layer containing Ti, TiN, W, WN, WSi x N y , Ru or a combination thereof.

[0027] Figure 3 The plurality of bit lines BL are shown to each have a three-conductive layer structure including a lower conductive layer 132A, an intermediate conductive layer 134A, and an upper conductive layer 136A, but the inventive concept is not limited thereto. For example, the plurality of bit lines BL may have a structure including a single conductive layer or a stacked structure including a double conductive layer or four or more conductive layers.

[0028] The upper surfaces of the plurality of bit lines BL may be covered with a plurality of insulating capping layers 140A, respectively. The plurality of insulating capping layers 140A may be respectively disposed on the upper conductive layer 136A of the plurality of bit lines BL. The plurality of insulating capping layers 140A may respectively extend in the second horizontal direction (Y direction) on the plurality of bit lines BL. The plurality of insulating capping layers 140A may each include a Si nitride layer.

[0029] The insulating spacer 150A may be arranged on both side walls of each of the plurality of bit lines BL and each of the plurality of insulating capping layers 140A. The insulating spacer 150A may extend in the second horizontal direction (Y direction) on both side walls of the plurality of bit lines BL. Some of the insulating spacers 150A may further extend into the direct contact hole DCH and cover both side walls of the direct contact DC formed in the direct contact hole DCH.

[0030] In some areas of the substrate 110, a plurality of recessed spaces RS formed in the first active region AC1 may be filled with a plurality of contact plugs 152, respectively. The plurality of contact plugs 152 may extend from the recessed spaces RS in a vertical direction (Z direction), respectively. Each of the plurality of contact plugs 152 may contact the first active region AC1. The plurality of contact plugs 152 may be arranged in a row along a second horizontal direction (Y direction) between each of the plurality of bit lines BL. The plurality of contact plugs 152 may include Figure 2 The plurality of buried contacts BC are shown in FIG. The plurality of contact plugs 152 may include a semiconductor pattern doped with impurities, but is not limited thereto.

[0031] A plurality of insulating barriers (not shown) may be disposed between each of the plurality of contact plugs 152 arranged in a row along the second horizontal direction (Y direction). The plurality of contact plugs 152 may be insulated from each other by the plurality of insulating barriers (not shown). In some embodiments, the plurality of insulating barriers (not shown) may include a Si nitride layer.

[0032] A plurality of landing pads LP may be arranged above a plurality of contact plugs 152. A plurality of landing pads LP may extend in a vertical direction (Z direction) on the contact plugs 152, respectively. Each of the plurality of landing pads LP may include a conductive barrier layer 162A and a landing pad conductive layer 164A. In some embodiments, the conductive barrier layer 162A may include Ti, TiN, or a combination thereof, and the landing pad conductive layer 164A may include a metal, a metal nitride, a conductive polysilicon, or a combination thereof. The plurality of landing pads LP may have a planar Irish pattern shape. The plurality of landing pads LP may be electrically insulated from each other by insulating patterns 166 surrounding the plurality of landing pads LP, respectively.

[0033] A metal silicide layer (not shown) may be further disposed between the plurality of contact plugs 152 and the plurality of landing pads LP. The metal silicide layer may include, for example, cobalt silicide, nickel silicide, or manganese silicide.

[0034] In the peripheral circuit area PCA, the peripheral circuit transistor PG may be disposed on the second active area AC2. The peripheral circuit transistor PG may include a gate dielectric layer 116, a gate electrode PGS, and a gate capping layer 140B sequentially stacked on the second active area AC2.

[0035] The gate dielectric layer 116 may include at least one selected from Si oxide, Si nitride, Si oxynitride, or a high-k dielectric material having a higher dielectric constant than that of Si oxide.

[0036] The gate electrode PGS may include a lower conductive layer 132B, an intermediate conductive layer 134B, and an upper conductive layer 136B. Materials included in the lower conductive layer 132B, the intermediate conductive layer 134B, and the upper conductive layer 136B may be the same or substantially the same as materials included in the lower conductive layer 132A, the intermediate conductive layer 134A, and the upper conductive layer 136A included in the bit line BL arranged in the memory cell area MCA, respectively.

[0037] The gate capping layer 140B may include, for example, Si nitride.

[0038] In some embodiments, both sidewalls of the gate electrode PGS may be covered with gate spacers 150B, respectively. The gate spacers 150B may include, for example, Si oxide, Si nitride, or a combination thereof.

[0039] The peripheral circuit transistor PG may be covered with a first insulating layer 142. A second insulating layer 144 may be provided on the first insulating layer 142. In the peripheral circuit area PCA, a contact plug CP may be formed in a contact hole CPH that passes through the first insulating layer 142 and the second insulating layer 144 in a vertical direction (Z direction). The contact plug CP may include a conductive barrier layer 162B and a plug conductive layer 164B. The conductive barrier layer 162B and the plug conductive layer 164B of the contact plug CP may have a structure substantially the same as or similar to that of the conductive barrier layer 162A and the landing pad conductive layer 164A of the plurality of landing pads LP formed in the memory cell area MCA, and may include the same or substantially the same material as that of the conductive barrier layer 162A and the landing pad conductive layer 164A of the plurality of landing pads LP formed in the memory cell area MCA.

[0040] The upper insulating pattern 170 may be disposed on the insulating pattern 166 in the memory cell area MCA. The upper insulating pattern 170 may include a material having an etch selectivity with respect to the second insulating layer 144 and the insulating pattern 166. For example, the upper insulating pattern 170 may include Si nitride.

[0041] The capacitor structure 180 may be disposed on the upper insulating pattern 170 in the memory cell area MCA. The capacitor structure 180 may include a plurality of first electrodes 182, a capacitor dielectric layer 184, and a second electrode 186. The capacitor structure 180 may be formed only in the memory cell area MCA. That is, the plurality of first electrodes 182, the capacitor dielectric layer 184, and the second electrode 186 of the capacitor structure 180 may not be formed in the peripheral circuit area PCA.

[0042] A plurality of first electrodes 182 may be arranged above a plurality of landing pads LP. The plurality of first electrodes 182 may penetrate the upper insulating pattern 170 and extend in a vertical direction (Z direction) on the plurality of landing pads LP. The bottom surfaces of the plurality of first electrodes 182 may be in contact with one landing pad LP selected from the plurality of landing pads LP. The plurality of first electrodes 182 may be in contact with the landing pad LP and thus be connected to the landing pad LP. The plurality of first electrodes 182 may each include a metal, a conductive metal oxide, a conductive metal nitride, a conductive metal oxynitride, or a combination thereof. In some embodiments, the plurality of first electrodes 182 may each include Ti, Ti oxide, TiN, Ti oxynitride, Co, Co oxide, Co nitride (CoN), Co silicide, Nb, Nb oxide, Nb nitride (NbN), Nb oxynitride, Sn, tin dioxide (SnO 2 ), Sn nitride, Sn oxynitride, or a combination thereof. For example, each of the plurality of first electrodes 182 may include TiN, CoN, NbN, SnO 2 or combinations thereof, but are not limited thereto.

[0043] A plurality of support layers SPT may be on the sidewalls of the plurality of first electrodes 182. The plurality of support layers SPT may maintain a certain distance between two adjacent first electrodes 182, and may limit and / or prevent the plurality of first electrodes 182 from tilting or collapsing. The plurality of support layers SPT may be arranged at different vertical heights on the sidewalls of the plurality of first electrodes 182.

[0044] The capacitor dielectric layer 184 may be disposed between each of the plurality of first electrodes 182, the plurality of support layers SPT, and the upper insulating pattern 170, and the silicon-containing layer 181. The capacitor dielectric layer 184 may cover sidewalls of the plurality of first electrodes 182, upper and bottom surfaces of the support layer SPT, and an upper surface of the upper insulating pattern 170. The capacitor dielectric layer 184 may include zirconium oxide, hafnium oxide, titanium oxide, Nb oxide, Ta oxide, yttrium oxide, strontium titanium oxide, barium strontium titanium oxide, scandium oxide, lanthanide oxide, or a combination thereof.

[0045] The second electrode 186 may include a silicon-containing layer 181 and a metal plate layer 183. The silicon-containing layer 181 may be above the capacitor dielectric layer 184 and surround the plurality of first electrodes 182. A side surface 181S of the silicon-containing layer 181 may be in contact with the interlayer insulating layer 192. The silicon-containing layer 181 may include, for example, silicon germanium, but is not limited thereto, and the silicon-containing layer 181 may include, for example, polycrystalline silicon. In some embodiments, the upper surface of the silicon-containing layer 181 may be a flat surface flattened by a flattening process.

[0046] The metal plate layer 183 may be disposed on the upper surface of the silicon-containing layer 181. In some embodiments, the metal plate layer 183 may be disposed only on the upper surface of the silicon-containing layer 181. That is, the metal plate layer 183 may not be disposed on the side surface 181S of the silicon-containing layer 181. The side surface 183S of the metal plate layer 183 may be covered by the cover insulating layer 194. The side surface 183S of the metal plate layer 183 may be arranged on the same plane as the side surface 181S of the silicon-containing layer 181 in the vertical direction. The metal plate layer 183 may include, for example, W, but is not limited thereto.

[0047] By using the silicon-containing layer 181 and the metal plate layer 183 as the second electrode 186 of the capacitor structure 180 , a sensing margin in the capacitor structure 180 may be ensured.

[0048] In the peripheral circuit area PCA, an interlayer insulating layer 192 may be disposed on the second insulating layer 144 and the contact plug CP. The interlayer insulating layer 192 may cover the second insulating layer 144 and the contact plug CP. The interlayer insulating layer 192 may fill the space between the capacitor structures 180 respectively included in two adjacent memory cell areas MCA. Therefore, the interlayer insulating layer 192 may cover the side surface 181S of the silicon-containing layer 181. The bottom surface of the interlayer insulating layer 192 may be arranged at the same vertical height as the bottom surfaces of the plurality of first electrodes 182. The upper surface of the interlayer insulating layer 192 may be arranged on the same plane as the upper surface of the silicon-containing layer 181 in the horizontal direction. Therefore, the interlayer insulating layer 192 may not contact the metal plate layer 183. In some embodiments, the upper surface of the interlayer insulating layer 192 may be a flat surface flattened by a flattening process.

[0049] The cover insulating layer 194 may be disposed on the metal plate layer 183 in the memory cell area MCA and on the interlayer insulating layer 192 in the peripheral circuit area PCA. The cover insulating layer 194 may have different lengths in the vertical direction in the memory cell area MCA and the peripheral circuit area PCA to cover the step difference between the memory cell area MCA and the peripheral circuit area PCA. For example, a portion of the cover insulating layer 194 in the peripheral circuit area PCA may have a greater length in the vertical direction than a remaining portion of the cover insulating layer 194 in the memory cell area MCA. A portion of the cover insulating layer 194 in the peripheral circuit area PCA may cover the side surface 183S of the metal plate layer 183 and the upper surface of the interlayer insulating layer 192, and a remaining portion of the cover insulating layer 194 in the memory cell area MCA may cover the upper surface of the metal plate layer 183.

[0050] In some embodiments, the interlayer insulating layer 192 and the cover insulating layer 194 may each include an oxide. For example, the interlayer insulating layer 192 and the cover insulating layer 194 may each include tetraethyl orthosilicate (TEOS), low deposition tetraethyl orthosilicate (LD-TEOS), plasma enhanced tetraethyl orthosilicate (PE-TEOS), or a combination thereof. In some embodiments, the interlayer insulating layer 192 and the cover insulating layer 194 may include materials different from each other. For example, the interlayer insulating layer 192 may include an LD-TEOS material, and the cover insulating layer 194 may include a TEOS material.

[0051] A plurality of cell contacts MC may penetrate the cap insulating layer 194 to extend in the vertical direction (Z direction) in the memory cell area MCA. Bottom surfaces of the plurality of cell contacts MC may contact the metal plate layer 183 and thus be connected to the metal plate layer 183. The plurality of cell contacts MC may each include a cell conductive barrier layer MCL and a cell contact conductive layer MCC. The plurality of cell contacts MC may have a planar circular shape.

[0052] The peripheral circuit contact PC may penetrate the cover insulating layer 194 and the interlayer insulating layer 192 to extend in the vertical direction (Z direction) in the peripheral circuit area PCA. The peripheral circuit contact PC may have a planar circular shape. The bottom surface of the peripheral circuit contact PC may contact the contact plug CP and thus be connected to the contact plug CP. The peripheral circuit contact PC may be connected to the second active area AC2 through the contact plug CP.

[0053] The peripheral circuit contact PC may include a peripheral circuit conductive barrier layer PCL and a peripheral circuit contact conductive layer PCC. The peripheral circuit contact conductive layer PCC may partially protrude in the horizontal direction in a neighboring region AR adjacent to the boundary between the interlayer insulating layer 192 and the cover insulating layer 194. In this case, the neighboring region AR may be adjacent to the boundary between the interlayer insulating layer 192 and the cover insulating layer 194, and below the boundary in the figure (i.e., the region within the interlayer insulating layer 192). Therefore, the horizontal width of the peripheral circuit contact conductive layer PCC in the neighboring region (AR) may be greater than the horizontal width of the peripheral circuit contact conductive layer PCC in the remaining region except the neighboring region AR.

[0054] An upper wiring layer 196 and an upper insulating layer 198 covering the upper wiring layer 196 may be disposed on the plurality of cell contacts MC, the peripheral circuit contacts PC, and the cover insulating layer 194. A bottom surface of the upper wiring layer 196 may contact an upper surface of each of the plurality of cell contacts MC and the peripheral circuit contacts PC.

[0055] In some embodiments, the upper wiring layer 196 may include W, Cu, Al, Co, Mo, Ru, Ti, Ta, TiN, TaN, or a combination thereof. For example, the upper wiring layer 196 may include a Cu layer. In some embodiments, the upper insulating layer 198 may include a low dielectric layer having a low dielectric constant K of about 2.2 to about 3.0. For example, the upper insulating layer 198 may include a SiOC layer or a SiCOH layer.

[0056] As reference Figures 6 to 18 As described above, the semiconductor device 10 according to some embodiments may be manufactured by forming the silicon-containing layer 181 and the first insulating material layer 192P, planarizing the formed first insulating material layer 192P to form the interlayer insulating layer 192, forming the metal plate layer 183 on the silicon-containing layer 181, and performing subsequent processes. Thus, the metal plate layer 183 of the semiconductor device 10 may be formed only on the upper surface of the silicon-containing layer 181, and may not be formed on the side surface 181S of the silicon-containing layer 181. Therefore, when the metal plate layer 183 is not formed on the side surface 181S of the silicon-containing layer 181, since the area occupied by the metal plate layer 183 formed on the side surface 181S can be reduced, the number of semiconductor devices 10 that can be manufactured in one wafer can be increased.

[0057] In addition, in the manufacturing process of the semiconductor device 10, since the first insulating material layer 192P covering the silicon-containing layer 181 is formed before the metal plate layer 183 is formed, and the interlayer insulating layer 192 is formed by planarizing the first insulating material layer 192P formed, the silicon-containing layer 181 can be used as an etching stop layer in the planarization process. Therefore, without using a separate etching stop layer, the thickness variation of the interlayer insulating layer 192 formed by the planarization process can be improved. Therefore, the structural reliability of the semiconductor device 10 can be improved.

[0058] When a semiconductor device is manufactured by using a separate etch stop layer, after forming a metal plate layer 183 covering the silicon-containing layer 181 and then forming an etch stop layer on the metal plate layer 183, a planarization process can be performed by using the etch stop layer to form an interlayer insulating layer 192. In this case, during the planarization process, defects such as poor adhesion between the etch stop layer and the metal plate layer 183 and partial etch stop layer being torn off due to impurity degassing generated in the planarization process may be caused. On the other hand, since the semiconductor device 10 according to some embodiments is manufactured without a separate etch stop layer as described above, tearing defects can be limited and / or prevented during the manufacturing process of the semiconductor device 10. Therefore, the structural reliability of the semiconductor device 10 can be improved.

[0059] Figure 4is a cross-sectional view of a semiconductor device 10a according to some embodiments. Figure 4 Each component of the semiconductor device 10a is referenced Figures 1 to 3 Each component of the described semiconductor device 10 is substantially the same or similar, so the differences are mainly described below.

[0060] refer to Figure 4 , except that the semiconductor device 10a includes a Figures 1 to 3 The semiconductor device 10 a may include components that are substantially the same as or similar to those of the semiconductor device 10 , except for the peripheral circuit contact PCa having a structure different from that of the peripheral circuit contact PC of the semiconductor device 10 shown.

[0061] The peripheral circuit contact PCa of the semiconductor device 10a may penetrate the cap insulating layer 194 and the interlayer insulating layer 192 to extend in the vertical direction (Z direction) in the peripheral circuit area PCA. The bottom surface of the peripheral circuit contact PCa may contact and thus be connected to the contact plug CP.

[0062] The peripheral circuit contact PCa may include a peripheral circuit conductive barrier layer PCLa and a peripheral circuit contact conductive layer PCCa. The peripheral circuit contact conductive layer PCCa may be partially recessed in the horizontal direction in the adjacent region AR adjacent to the boundary between the interlayer insulating layer 192 and the cover insulating layer 194. Therefore, the horizontal width of the peripheral circuit contact conductive layer PCCa in the adjacent region AR may be smaller than the horizontal width of the peripheral circuit contact conductive layer PCCa in the remaining region except the adjacent region AR.

[0063] Figure 5 is a cross-sectional view of a semiconductor device 10b according to some embodiments. Figure 5 Each component of the semiconductor device 10b is connected to the reference Figures 1 to 3 Each component of the described semiconductor device 10 is substantially the same or similar, so the differences are mainly described below.

[0064] refer to Figure 5 , except that the semiconductor device 10b includes a Figures 1 to 3 The semiconductor device 10 b may include components substantially the same as or similar to those of the semiconductor device 10 except for the upper insulating layer 194 b having a different structure from the cap insulating layer 194 of the semiconductor device 10 shown.

[0065] In the peripheral circuit area PCA, the cover insulating layer 194b of the semiconductor device 10b may include a groove 194T on its upper surface. The vertical length t2 of the groove 194T may be the same or substantially the same as the vertical length t1 of the metal plate layer 183. Through the groove 194T, the upper surface of the cover insulating layer 194b in the memory cell area MCA may be arranged at a higher vertical height than the upper surface of the cover insulating layer 194b in the peripheral circuit area PCA. That is, the upper surface of the cover insulating layer 194b may include a step difference between the memory cell area MCA and the peripheral circuit area PCA having the same length as the vertical length t2 of the groove 194T. The groove 194T of the cover insulating layer 194b may be filled with the upper insulating layer 198.

[0066] The upper surface of the peripheral circuit contact PC of the semiconductor device 10b can be arranged at a lower vertical height than the upper surface of the cell contact MC. This is because, in the manufacturing process of the semiconductor device 10b, the cell contact MC penetrating in the vertical direction (Z direction) is formed in the memory cell area MCA, and the peripheral circuit contact PC is formed in the peripheral circuit area PCA without removing the step difference of the upper surface of the formed cover insulating layer 194b. In addition, since the upper surface of the peripheral circuit contact PC is located at a lower vertical height than the upper surface of the cell contact MC, the upper wiring layer 196 arranged on the peripheral circuit contact PC can be arranged at a lower vertical height than the upper wiring layer 196 arranged on multiple cell contacts MC.

[0067] Figures 6 to 18 is a cross-sectional view of a semiconductor device 10 for illustrating a method of manufacturing the semiconductor device 10 according to some embodiments. Specifically, Figures 6 to 18 1 is a cross-sectional view for describing operations of a method of fabricating a semiconductor device 10 , according to some embodiments.

[0068] refer to Figure 6 , a plurality of device isolation trenches 112T may be formed on the substrate 110 including the memory cell area MCA and the peripheral circuit area PCA. Subsequently, a plurality of device isolation layers 112 may be formed by filling the device isolation trenches 112T with an isolation material. Through the plurality of device isolation layers 112, a plurality of first active regions AC1 may be defined in the memory cell area MCA of the substrate 110, and a second active region AC2 may be defined in the peripheral circuit area PCA.

[0069] Subsequently, a buffer layer 114 may be formed on the substrate 110 in the memory cell area MCA, and a gate dielectric layer 116 may be formed on the substrate 110 in the peripheral circuit area PCA.

[0070] Subsequently, a portion of the substrate 110 may be removed by using a mask pattern (not shown) to form a direct contact hole DCH. The direct contact hole DCH may expose the first active region AC1. The mask pattern may include, for example, an oxide layer, a nitride layer, or a combination thereof, but is not limited thereto. Thereafter, a direct contact DC may be formed by removing the mask pattern and filling a conductive material in the direct contact hole DCH.

[0071] Subsequently, in the memory cell area MCA, a lower conductive layer 132A, an intermediate conductive layer 134A, an upper conductive layer 136A and an insulating cap layer 140A may be sequentially formed on the buffer layer 114 and the direct contact DC, and in the peripheral circuit area PCA, a lower conductive layer 132B, an intermediate conductive layer 134B, an upper conductive layer 136B and an insulating cap layer 140B may be sequentially formed on the peripheral circuit area PCA.

[0072] Subsequently, in the memory cell area MCA, a plurality of bit lines BL can be formed by etching a portion of each of the direct contact DC, the lower conductive layer 132A, the middle conductive layer 134A and the upper conductive layer 136A using the insulating cap layer 140A as an etching mask, and in the peripheral circuit area PCA, a gate electrode PGS can be formed by etching a portion of each of the lower conductive layer 132B, the middle conductive layer 134B and the upper conductive layer 136B using the insulating cap layer 140B as an etching mask.

[0073] Subsequently, an insulating spacer 150B may be formed on a sidewall of the gate electrode PGS, and a first insulating layer 142 covering the gate electrode PGS may be formed.

[0074] Next, in the memory cell area MCA, an insulating spacer 150A may be formed on the sidewall of each of the plurality of bit lines BL and the insulating capping layer 140A, and a plurality of insulating fences (not shown) may be formed between the plurality of bit lines BL. The insulating spacer 150A may conformally cover the sidewall of each of the plurality of bit lines BL and the insulating capping layer 140A.

[0075] Subsequently, a portion of the substrate 110 disposed at the bottom of the contact space (not shown) between the plurality of bit lines BL and between the plurality of insulating fences may be removed to form a plurality of recessed spaces RS exposing the first active region AC1 between the plurality of bit lines BL. In some embodiments, an anisotropic etching process or a combination of an anisotropic etching process and an isotropic etching process may be used to form the plurality of recessed spaces RS.

[0076] Subsequently, the plurality of recess spaces RS and portions of the contact spaces may be filled with a conductive material to form a plurality of contact plugs 152 .

[0077] Subsequently, a plurality of contact holes CPH exposing the second active region AC2 may be formed by etching the first insulating layer 142 in the peripheral circuit area PCA.

[0078] Subsequently, a conductive barrier layer (not shown) and a conductive layer (not shown) covering the exposed surface on the substrate 110 may be formed in the memory cell area MCA and the peripheral circuit area PCA. Subsequently, by patterning the conductive barrier layer and the conductive layer, a plurality of landing pads LP including the conductive barrier layer 162A and the landing pad conductive layer 164A may be formed in the memory cell area MCA, and a plurality of contact plugs CP including the conductive barrier layer 162B and the plug conductive layer 164B may be formed in the peripheral circuit area PCA.

[0079] Subsequently, an insulating pattern 166 surrounding sidewalls of the plurality of landing pads LP and a second insulating layer 144 covering sidewalls of the contact plugs CP may be formed.

[0080] refer to Figure 7 , an upper insulating pattern 170 may be formed on the insulating pattern 166 in the memory cell area MCA of the substrate 110. Subsequently, a mold structure (not shown) may be formed on the upper insulating pattern 170. The mold structure may include a first mold layer (not shown), a second mold layer (not shown), and a third mold layer (not shown) sequentially stacked on the upper insulating pattern 170.

[0081] In some embodiments, the support layer SPT may be optionally formed between the first mold layer and the second mold layer, between the second mold layer and the third mold layer, and on the third mold layer. Figure 7 An example of forming three supporting layers SPT is shown in FIG. 1 , but the inventive concept is not limited thereto, and the number of supporting layers SPT may be different according to the heights of the plurality of first electrodes 182 .

[0082] In some embodiments, the support layer SPT may be formed using a material having an etching selectivity relative to a material included in the mold structure. For example, the first to third mold layers may be formed using Si oxide, and the support layer SPT may be formed using Si nitride.

[0083] Subsequently, after forming a mask pattern (not shown) on the mold structure, an opening penetrating the mold structure may be formed by using the mask pattern as an etching mask, and then the opening may be filled with a conductive material, thereby forming a plurality of first electrodes 182. Each of the bottom surfaces of the plurality of first electrodes 182 may contact an upper surface of the conductive landing pad LP.

[0084] Subsequently, the mold structure may be removed in the memory cell area MCA, and the mold structure and the support layer SPT may be removed in the peripheral circuit area PCA. In the memory cell area MCA, the mold structure may be removed so that at least a portion of both side walls of the first electrode 182, the lower and upper surfaces of the support layer SPT, and the upper surface of the upper insulating pattern 170 may be exposed. In the peripheral circuit area PCA, the mold structure and the support layer SPT may be removed to expose the upper surface of the second insulating layer 144 and the upper surface of the contact plug CP.

[0085] refer to Figure 8 , a capacitor dielectric layer 184 may be formed on the upper insulating pattern 170, the plurality of first electrodes 182, and the support layer SPT. The capacitor dielectric layer 184 may conformally cover the upper surface of the upper insulating pattern 170, at least a portion of both side walls of the first electrode 182, and the upper and lower surfaces of the support layer SPT.

[0086] Next, a silicon-containing material layer 181P covering the capacitor dielectric layer 184, upper surfaces of the second insulating layer 144, and upper surfaces of the contact plugs CP may be formed. The silicon-containing material layer 181P may include, for example, SiGe or polysilicon.

[0087] refer to Fig. 9 , a first mask pattern M1 may be formed on an upper surface of the silicon-containing material layer 181P. The first mask pattern M1 may be, for example, a photoresist pattern including a photoresist material layer. The first mask pattern M1 may be formed on an upper surface of a portion of the silicon-containing material layer 181P arranged in the memory cell area MCA, and may not be formed in a remaining portion of the silicon-containing material layer 181P arranged in the peripheral circuit area PCA.

[0088] refer to Fig.10 , the first mask pattern M1 (reference Fig. 9 ) can be used as an etching mask to remove the silicon-containing material layer 181P (reference Fig. 9 ) disposed in the peripheral circuit area PCA. The portion of the silicon-containing material layer 181P disposed in the peripheral circuit area PCA may be removed so that the upper surface of the second insulating layer 144 and the upper surface of the contact plug CP may be exposed. In addition, the silicon-containing material layer 181P that is not removed and remains in the memory cell area MCA may be the silicon-containing layer 181 included in the second electrode 186 of the capacitor structure 180.

[0089] refer to Fig.11, the first insulating material layer 192P may cover the silicon-containing layer 181 in the memory cell area MCA and cover the second insulating layer 144 and the contact plug CP in the peripheral circuit area PCA. The first insulating material layer 192P may be formed by a deposition process. In some embodiments, the first insulating material layer 192P may include TEOS, PE-TEOS, LD-TEOS, or a combination thereof.

[0090] refer to Fig.12 , the first insulating material layer 192P (reference Fig.11 ) may be planarized by a planarization process. The planarization process may be, for example, a chemical mechanical polishing (CMP) process. When the planarization process is performed, the silicon-containing layer 181 may serve as an etch stop layer. Therefore, the planarization process may be performed until the upper surface of the first insulating material layer 192P is arranged on the same plane as the upper surface of the silicon-containing layer 181. The portion of the first insulating material layer 192P that remains and is not removed after the planarization process is performed may be the interlayer insulating layer 192.

[0091] refer to Fig.13 The metal material layer 183P may be formed on the interlayer insulating layer 192 and the silicon-containing layer 181 . The metal material layer 183P may include, for example, W. The metal material layer 183P may completely cover the upper surface of the interlayer insulating layer 192 and the upper surface of the silicon-containing layer 181 .

[0092] refer to Fig.14 , a second mask pattern M2 may be formed on the metal material layer 183P. The second mask pattern M2 may be formed on a portion of the metal material layer 183P arranged in the memory cell area MCA, but may not be formed on a remaining portion of the metal material layer 183P arranged in the peripheral circuit area PCA. Therefore, the remaining portion of the metal material layer 183P arranged in the peripheral circuit area PCA may be exposed by the second mask pattern M2. The second mask pattern M2 may be, for example, a photoresist pattern including a photoresist material layer.

[0093] refer to Fig.15 , the second mask pattern M2 (reference Fig.14 ) can be used as an etching mask to remove the metal material layer 183P (reference Fig.14) disposed in the peripheral circuit area PCA. The portion of the metal material layer 183P disposed in the peripheral circuit area PCA may be removed, resulting in the upper surface of the interlayer insulating layer 192 being exposed. In addition, the metal material layer 183P that is not removed and remains in the memory cell area MCA may be the metal plate layer 183 included in the second electrode 186 of the capacitor structure 180. In addition, a step difference may be generated between the memory cell area MCA in which the metal material layer 183P remains and the peripheral circuit area PCA in which the metal material layer 183P is removed.

[0094] refer to Fig.16 , the second insulating material layer 194P may cover the metal plate layer 183 in the memory cell area MCA and the interlayer insulating layer 192 in the peripheral circuit area PCA. The second insulating material layer 194P may be formed by a deposition process. In some embodiments, the second insulating material layer 194P may include TEOS, PE-TEOS, LD-TEOS, or a combination thereof. In some embodiments, the second insulating material layer 194P may include a different insulating material layer from the first insulating material layer 192P (refer to Fig.15 ). The second insulating material layer 194P may have a step difference in the memory cell area MCA and the peripheral circuit area PCA. For example, the upper surface of the portion of the second insulating material layer 194P arranged in the peripheral circuit area PCA may be arranged at a lower vertical height than the remaining portion of the second insulating material layer 194P in the memory cell area MCA.

[0095] refer to Fig.17 , the second insulating material layer 194P (reference Fig.16 ) may be planarized by a planarization process. The planarization process may be, for example, a chemical mechanical polishing (CMP) process. A portion of the second insulating material layer 194P may be removed by the planarization process, and the remaining second insulating material layer 194P may be the cap insulating layer 194. Through the planarization process, the upper surface of the cap insulating layer 194 may be arranged on the same plane in the memory cell area MCA and the peripheral circuit area PCA.

[0096] As reference Fig.11 , Fig.12 , Fig.16 and Fig.17 As described above, the interlayer insulating layer 192 and the cover insulating layer 194 may be formed by different processes, respectively. Therefore, the interlayer insulating layer 192 and the cover insulating layer 194 may not be integral with each other and may be divided into separate films by a boundary between the interlayer insulating layer 192 and the cover insulating layer 194 .

[0097] In some embodiments, reference may be omitted. Fig.17In this case, the second insulating material layer 194P is as shown in FIG. Fig.16 Once the description is formed, the reference Fig.18 The contact forming process described above does not remove the step difference of the second insulating material layer 194P. Thereafter, the following process may be performed to manufacture the Figure 5 The semiconductor device 10b is shown.

[0098] refer to Fig.18 , a plurality of metal contact holes (not shown) penetrating the cover insulating layer 194 may be formed in the memory cell area MCA, and a peripheral circuit contact hole (not shown) penetrating the cover insulating layer 194 and the interlayer insulating layer 192 may be formed in the peripheral circuit area PCA. The plurality of metal contact holes may expose the upper surface of the metal plate layer 183, and the peripheral circuit contact hole may expose the upper surface of the contact plug CP. The plurality of metal contact holes and the peripheral circuit contact hole may be formed by an etching process. In this case, the peripheral circuit contact hole formed by the etching process may partially protrude in the horizontal direction in an area adjacent to a boundary between the cover insulating layer 194 and the interlayer insulating layer 192. The partial protrusion of the peripheral circuit contact hole in the horizontal direction may be due to the interlayer insulating layer 192 and the cover insulating layer 194, which are etching target layers of the etching process, being formed as shown in FIG. Fig.17 The division into individual layers shown results.

[0099] In some embodiments, the peripheral circuit contact hole may be partially recessed in the horizontal direction in a region adjacent to the boundary between the cap insulating layer 194 and the interlayer insulating layer 192, depending on the conditions of the etching process. Figure 4 The semiconductor device 10 a shown in FIG. 1 can be manufactured by continuing subsequent processes which will be described later.

[0100] Next, a cell conductive barrier layer MCL conformally covering inner walls of the plurality of metal contact holes and a peripheral circuit conductive barrier layer PCL conformally covering inner walls of the peripheral circuit contact holes may be formed. The cell conductive barrier layer MCL and the peripheral circuit conductive barrier layer PCL may include Ti, TiN or a combination thereof, but are not limited thereto.

[0101] Subsequently, a unit contact conductive layer MCC filling multiple metal contact holes and a peripheral circuit contact conductive layer PCC filling peripheral circuit contact holes can be formed, and multiple metal contacts MC and peripheral circuit contacts PC can be formed by polishing the upper portions of the unit conductive barrier layer MCL and the peripheral circuit conductive barrier layer PCL and the upper portions of the unit contact conductive layer MCC and the peripheral circuit contact conductive layer PCC.

[0102] Later, in Fig.18As a result, the upper wiring layer 196 and the upper insulating layer 198 can be formed on the peripheral circuit contact PC, the metal contact MC and the cover insulating layer 194. Figures 1 to 3 A semiconductor device 10.

[0103] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

[0104] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0141403 filed in the Korean Intellectual Property Office on October 20, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: A substrate including a memory cell region having a first active region and a peripheral circuit region having a second active region; a capacitor structure comprising a first electrode, a second electrode and a capacitor dielectric layer between the first electrode and the second electrode, the first electrode being connected to the first active region in the memory cell region, the second electrode comprising a silicon-containing layer surrounding the first electrode on the memory cell region and a metal plate layer on the silicon-containing layer; an interlayer insulating layer on the peripheral circuit region; as well as A capping insulating layer covers the capacitor structure on the memory cell area and covers the interlayer insulating layer on the peripheral circuit area, wherein The metal plate layer is on an upper surface of the silicon-containing layer, and the metal plate layer is not on a side surface of the silicon-containing layer. 2 . The semiconductor device according to claim 1 , wherein a side surface of the metal plate layer and the side surface of the silicon-containing layer are coplanar in a vertical direction. 3 . The semiconductor device according to claim 1 , wherein the interlayer insulating layer covers the side surface of the silicon-containing layer. 4 . The semiconductor device according to claim 1 , wherein an upper surface of the interlayer insulating layer and the upper surface of the silicon-containing layer are coplanar in a horizontal direction. 5 . The semiconductor device according to claim 1 , wherein the cap insulating layer covers an upper surface and a side surface of the metal plate layer. The semiconductor device according to claim 1 , wherein the upper surface of the silicon-containing layer is flat. 7 . The semiconductor device according to claim 1 , wherein an upper surface of the cap insulating layer is flat. 8 . The semiconductor device according to claim 1 , wherein an upper surface of the capping insulating layer has a step difference between the memory cell region and the peripheral circuit region. 9 . The semiconductor device according to claim 8 , wherein a vertical length of the step difference on the upper surface of the cap insulating layer is equal to a vertical length of the metal plate layer.

10. The semiconductor device according to claim 8, further comprising: a cell contact on the memory cell region, the cell contact penetrating the cap insulating layer in a vertical direction and connected to the metal plate layer; as well as a peripheral circuit contact on the peripheral circuit region, the peripheral circuit contact penetrating the cover insulating layer and the interlayer insulating layer in the vertical direction and connected to the second active region, wherein The height of the upper surface of the peripheral circuit contact is a lower vertical height than the upper surface of the cell contact.

11. The semiconductor device according to claim 1, further comprising: a peripheral circuit contact penetrating the cover insulating layer and the interlayer insulating layer in a vertical direction and connected to the second active region, wherein The peripheral circuit contact partially protrudes in a horizontal direction in a region adjacent to a boundary between the cover insulating layer and the interlayer insulating layer.

12. The semiconductor device according to claim 1, further comprising: a peripheral circuit contact penetrating the cover insulating layer and the interlayer insulating layer in a vertical direction and connected to the second active region, wherein The peripheral circuit contact portion is recessed in a horizontal direction in a region adjacent to a boundary between the cover insulating layer and the interlayer insulating layer.

13. A semiconductor device comprising: A substrate including a memory cell region having a first active region and a peripheral circuit region having a second active region; a capacitor structure comprising a first electrode, a second electrode, and a capacitor dielectric layer between the first electrode and the second electrode, the first electrode being connected to the first active region in the memory cell region, the second electrode comprising a silicon-containing layer surrounding the first electrode on the memory cell region and a metal plate layer on the silicon-containing layer; an interlayer insulating layer on the peripheral circuit region; as well as A capping insulating layer covers the capacitor structure on the memory cell area and covers the interlayer insulating layer on the peripheral circuit area, wherein An upper surface of the silicon-containing layer and an upper surface of the interlayer insulating layer are coplanar in a horizontal direction.

14. The semiconductor device according to claim 13, wherein The metal plate layer is on the upper surface of the silicon-containing layer, and the metal plate layer is not on the side surface of the silicon-containing layer, and The interlayer insulating layer covers the side surface of the silicon-containing layer. 15 . The semiconductor device according to claim 13 , wherein a side surface of the metal plate layer and a side surface of the silicon-containing layer are coplanar in a vertical direction. 16 . The semiconductor device according to claim 13 , wherein the cap insulating layer covers an upper surface of the metal plate layer and side surfaces of the metal plate layer. 17 . The semiconductor device according to claim 13 , wherein the upper surface of the silicon-containing layer and the upper surface of the capping insulating layer are each flat.

18. The semiconductor device according to claim 13, wherein An upper surface of the capping insulating layer has a step difference between the memory cell region and the peripheral circuit region, and A length of the step difference on the upper surface of the cover insulating layer in a vertical direction is equal to a length of the metal plate layer in the vertical direction.

19. The semiconductor device according to claim 18, further comprising: a cell contact on the memory cell region, the cell contact penetrating the cover insulating layer in the vertical direction and connected to the metal plate layer; as well as a peripheral circuit contact on the peripheral circuit region, the peripheral circuit contact penetrating the cover insulating layer and the interlayer insulating layer in the vertical direction and connected to the second active region, wherein The height of the upper surface of the peripheral circuit contact is arranged at a lower vertical height than the upper surface of the cell contact.

20. A semiconductor device comprising: A substrate including a memory cell region having a first active region and a peripheral circuit region having a second active region; A capacitor structure, comprising a first electrode, a second electrode and a capacitor dielectric layer between the first electrode and the second electrode, wherein the first electrode is connected to the first active area in the memory cell area, and the second electrode comprises a silicon germanium layer surrounding the first electrode on the memory cell area and a metal plate layer on the silicon germanium layer; an interlayer insulating layer on the peripheral circuit region and covering a side surface of the capacitor structure; as well as A capping insulating layer covers the capacitor structure on the memory cell area and covers the interlayer insulating layer on the peripheral circuit area, wherein The metal plate layer is on the upper surface of the silicon germanium layer, and the metal plate layer is not on the side surface of the silicon germanium layer, and The upper surface of the silicon germanium layer and the upper surface of the interlayer insulating layer are coplanar.

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