Cell, power device, power electronic device, electric equipment and manufacturing method

Abstract

The invention provides a cell of a power device, the power device, a power electronic device, electric equipment and a manufacturing method. Each cell comprises a substrate formed by laminating different conductive layers and a gate structure in contact with the substrate; and the gate structure comprises a tunneling layer for electrons to pass through, a floating gate layer for adjusting electron concentration and a gate electrode for providing gate voltage, which are stacked in sequence. According to the embodiment of the invention, the tunneling layer and the floating gate layer are arranged in the gate structure in the cell of the power device, so that the inversion degree of a channel region in a switching-on process can be increased, lower switching-on power loss can be realized, the inversion degree of the channel region in a switching-off process can be reduced, and lower switching-off power loss can be realized. Therefore, by using the cellular structure, the power device can be compatible with lower turn-on power loss and turn-off power loss.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronics, and in particular relates to a cell, a power device, a power electronics device, an electrical equipment and a manufacturing method thereof. Background Art

[0002] In power electronics technology, various types of power devices such as MOSFET, IGBT, IGCT, etc. are widely used.

[0003] The switching power loss during the turn-on and turn-off processes of these power devices is one of the more important electrical parameters for measuring the performance of power devices.

[0004] Currently, the high switching power losses of these power devices make it difficult for their operating performance to meet usage requirements. Summary of the invention

[0005] In view of this, the embodiments of the present invention provide a cell, a power device, a power electronic device, an electrical equipment and a manufacturing method to solve the problem that the existing power devices have high switching power loss, resulting in their working performance being unable to meet usage requirements.

[0006] According to a first aspect of an embodiment of the present invention, a cell of a power device is provided, the cell comprising a substrate formed by stacking different conductive layers and a gate structure in contact with the substrate;

[0007] The gate structure includes a tunneling layer for electrons to pass through, a floating gate layer for adjusting the electron concentration, and a gate electrode for providing a gate voltage, which are stacked in sequence.

[0008] Optionally, the base includes a first conductive layer, a second conductive layer and a third conductive layer stacked in sequence on the front side of the substrate, wherein one of two adjacent conductive layers is a P-type conductive layer and the other is an N-type conductive layer.

[0009] Optionally, the gate structure further includes a gate trench, and the gate trench penetrates different conductive layers in the substrate;

[0010] The tunnel layer, the floating gate layer and the gate electrode are sequentially stacked on the inner wall of the gate trench.

[0011] Optionally, the gate trench sequentially penetrates the third conductive layer, the second conductive layer and the first conductive layer;

[0012] The tunneling layer is in contact with the third conductive layer, the second conductive layer, and the first conductive layer at the same time.

[0013] Optionally, the cross-sectional shape of the gate trench includes a rectangular trench, a trapezoidal trench or a U-shaped trench.

[0014] Optionally, the gate trench has a depth of 2 microns to 6 microns.

[0015] Optionally, a distance between the gate trenches of two adjacent cells is 1 micron to 10 microns.

[0016] Optionally, the gate structure extends along the surface of the substrate to form a planar gate.

[0017] Optionally, the tunneling layer contacts the third conductive layer.

[0018] Optionally, the gate structure further includes a gate oxide layer, and the gate oxide layer is disposed between the floating gate layer and the gate electrode.

[0019] Optionally, the gate oxide layer includes silicon oxide.

[0020] Optionally, the gate oxide layer has a thickness of 50 nm to 150 nm.

[0021] Optionally, the tunneling layer includes any one of silicon oxide, titanium oxide, aluminum oxide, hafnium oxide and silicon nitride.

[0022] Optionally, the tunneling layer has a thickness of 1 nm to 20 nm.

[0023] Optionally, the floating gate layer includes any one of silicon, inert metal, metal nitride and doped semiconductor.

[0024] Optionally, the floating gate layer has a thickness of 1 nm to 200 nm.

[0025] Optionally, the base further includes a fourth conductive layer, a fifth conductive layer and a back metal layer which are sequentially stacked on the back side of the substrate.

[0026] Optionally, the substrate further comprises an insulating layer and a front metal layer stacked in sequence;

[0027] The insulating layer and the third conductive layer are stacked, and the insulating layer is located on a side of the third conductive layer away from the substrate;

[0028] A portion of the front metal layer passes through the third conductive layer and is connected to the second conductive layer.

[0029] A second aspect of the embodiments of the present invention provides a power device, wherein the power device includes any one of the cells described in the first aspect of the embodiments of the present invention.

[0030] According to a third aspect of the embodiments of the present invention, a power electronic device is provided. The power electronic device includes the power device according to the second aspect of the embodiments of the present invention.

[0031] A fourth aspect of the embodiments of the present invention provides an electrical device, wherein the electrical device comprises the power device described in the second aspect of the embodiments of the present invention.

[0032] A fifth aspect of the embodiments of the present invention provides a method for manufacturing a power device, the method comprising:

[0033] Preparing a substrate of a power device, wherein the substrate comprises different conductive layers stacked together;

[0034] A tunneling layer for electrons to pass through, a floating gate layer for adjusting electron concentration, and a gate electrode for providing a gate voltage are formed on the substrate in sequence, wherein the tunneling layer is in contact with the substrate.

[0035] In the embodiment of the present invention, a tunneling layer and a floating gate layer are arranged in the gate structure in the cell of the power device. When a forward high voltage is applied to the gate electrode, the electrons in the channel region will be affected by the strong forward electric field of the gate electrode. Under the tunneling effect of the tunneling layer, the electrons in the channel region will pass through the tunneling layer and then be captured by the floating gate layer on the other side. At this time, the floating gate layer forms a shielding structure that can shield part of the gate electric field in the channel region, and the electron concentration in the channel region is reduced. Therefore, when the power device using this cell structure is turned off, the channel can be turned off faster, and accordingly, the power loss of the turn-off process is also lower. Conversely, when the power device is turned off and a reverse high voltage is applied to the gate electrode, the electrons previously captured by the floating gate layer will be affected by the reverse strong electric field. Under the tunneling effect of the tunneling layer, the floating gate layer releases the electrons, and the released electrons pass through the tunneling layer and return to the channel region again. At this time, the floating gate layer loses the electrons and its shielding effect disappears. At this time, when the power device is turned on, due to the weak shielding effect of the floating gate layer on the channel electric field, the channel region is more likely to be inverted, that is, the degree of inversion in the channel region is greater and the electron concentration is higher. Therefore, faster turn-on can be achieved, thereby reducing the power loss of the turn-on process. Therefore, the cell of the power device of the present invention can increase the degree of inversion in the channel region during the turn-on process, can achieve lower turn-on power loss, can reduce the degree of inversion in the channel region during the turn-off process, and can achieve lower turn-off power loss. It can be seen that the use of this cellular structure helps to achieve power devices compatible with lower turn-on power loss and turn-off power loss.

[0036] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0038] Figure 1 is a schematic diagram of a gate trench provided by an embodiment of the present invention;

[0039] Figure 2 is a schematic diagram of another gate trench provided by an embodiment of the present invention;

[0040] Figure 3 is a schematic diagram of a cell provided by an embodiment of the present invention;

[0041] Figure 4 It is a flow chart of a method for manufacturing a power device provided by an embodiment of the present invention.

[0042] Description of reference numerals:

[0043] Base 10, gate structure 20, back metal layer 101, fifth conductive layer 102, fourth conductive layer 103, substrate 104, first conductive layer 105, second conductive layer 106, third conductive layer 107, insulating layer 108, front metal layer 109, gate trench 201, tunneling layer 202, floating gate layer 203, gate electrode 204, gate oxide layer 205. DETAILED DESCRIPTION

[0044] The exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present invention and to enable the scope of the present invention to be fully communicated to those skilled in the art.

[0045] Reference Figure 1 , an embodiment of the present invention provides a cell of a power device, the cell comprising a substrate 10 formed by stacking different conductive layers and a gate structure 20 in contact with the substrate 10;

[0046] The gate structure 20 includes a tunneling layer 202 for electrons to pass through, a floating gate layer 203 for adjusting electron concentration, and a gate electrode 204 for providing a gate voltage, which are stacked in sequence.

[0047] Specifically, the cell in the embodiment of the present invention may be a cell designed to be applied to different types of power devices such as MOSFET, IGBT, etc. Figure 1As shown in the figure, the cell includes a substrate 10 and a gate structure 20 formed on the substrate 10. It should be noted that, for the substrate 10, as a structural carrier for forming the gate structure 20, it includes two different types of conductive layers, P-type and N-type, wherein the number of P-type conductive layers and N-type conductive layers is not limited, depending on the specific type of power device and electrical performance requirements. The gate structure 20 is directly processed on the substrate 10 to form an electrical connection with the substrate 10. The gate structure 20 may include a tunneling layer 202 for electrons to pass through, a floating gate layer 203 for adjusting the electron concentration, and a gate electrode 204 covering the floating gate layer 203 and providing a gate voltage.

[0048] for Figure 1 In the cell shown in the figure, when a positive high voltage is applied to the gate electrode 204, the electrons in the channel region will be affected by the strong positive electric field of the gate electrode 204. Under the action of the tunneling effect, the electrons in the channel region will pass through the tunneling layer 202 and then be captured by the floating gate layer 203 on the other side. At this time, the floating gate layer 203 forms a shielding structure that can shield part of the gate electric field in the channel region, and the electron concentration in the channel region is reduced. Therefore, when the power device using this cell structure is turned off, the channel can be turned off faster, and accordingly, the power loss during the turn-off process is also lower.

[0049] On the contrary, when the power device is turned off and a reverse high voltage is applied to the gate electrode 204, the electrons previously captured by the floating gate layer 203 will be affected by the reverse strong electric field. Under the action of the tunneling effect, the floating gate layer 203 releases the electrons, and the released electrons pass through the tunneling layer 202 and return to the channel region again. At this time, the floating gate layer 203 loses the electrons and its shielding effect disappears. At this time, when the power device is turned on, since the shielding effect of the floating gate layer 203 on the channel electric field is weak, the channel region is more likely to be inverted, that is, the degree of inversion in the channel region is greater and the electron concentration is higher. Therefore, faster turn-on can be achieved, thereby reducing the power loss of the turn-on process.

[0050] Therefore, the embodiment of the present invention can increase the inversion degree of the channel region during the turn-on process by setting a tunneling layer and a floating gate layer in the gate structure in the cell, thereby achieving lower turn-on power loss, and can reduce the inversion degree of the channel region during the turn-off process, thereby achieving lower turn-off power loss. It can be seen that the use of such a cell structure helps to achieve a power device compatible with lower turn-on power loss and turn-off power loss.

[0051] Optionally, refer to Figure 2 The base 10 includes a first conductive layer 105, a second conductive layer 106 and a third conductive layer 107 which are sequentially stacked on the front side of a substrate 104, wherein one of two adjacent conductive layers is a P-type conductive layer and the other is an N-type conductive layer.

[0052] Specifically, in one embodiment, Figure 2 As shown in FIG. 1 , the base 10 of the above embodiment may include: a substrate 104, and a first conductive layer 105 attached to the front of the substrate 104, a second conductive layer 106 covering the first conductive layer 105, and a third conductive layer 107 covering the second conductive layer 106. In each of the above conductive layers, one of the two adjacent conductive layers is a P-type conductive layer and the other is an N-type conductive layer. The material of the substrate 104 may be single crystal silicon or silicon carbide, the doping material in the P-type conductive layer may be boron or boron fluoride, and the doping material in the N-type conductive layer may be phosphorus, arsenic or hydrogen, and neither is specifically limited. Taking IGBT as an example, the above first conductive layer 105 may be a carrier storage layer, the substrate 104 may be of the same conductivity type as the first conductive layer 105, and the third conductive layer 107 may be an emitter region.

[0053] Optionally, refer to Figure 1 , the gate structure 20 further includes a gate trench 201, and the gate trench 201 penetrates different conductive layers in the substrate 10;

[0054] The tunnel layer 202 , the floating gate layer 203 , and the gate electrode 204 are sequentially stacked on the inner wall of the gate trench 201 .

[0055] Specifically, if Figure 1 As shown in FIG. 1 , the cell of the present invention can be designed and applied to the power of trench gates. The gate structure 20 of the cell further includes a gate trench 201. The gate trench 201 extends from top to bottom, passing through the third conductive layer 107, the second conductive layer 106 and the first conductive layer 105 in sequence.

[0056] Combination Figure 1 As shown in FIG. 2 , in the gate trench 201 of the embodiment of the present invention, the layer close to the inner wall is a tunneling layer 202 for electrons to pass through, followed by a floating gate layer 203 that can adjust the electron concentration, and a gate electrode 204 that provides a gate voltage is covered on the floating gate layer 203. For example, for a power device such as an IGBT, the gate trench 201 extends downward from the emitter region above to the carrier storage layer, realizing the movement of electrons between the emitter region and the carrier storage layer to form a current.

[0057] Combined with the diagram, it is easy to understand that when the gate groove 201 penetrates different conductive layers from top to bottom, the tunneling layer 202 arranged close to the inner wall of the gate groove 201 also contacts the third conductive layer 107, the second conductive layer 106 and the first conductive layer 105 from top to bottom at the same time, thereby realizing the control of the electron concentration of each conductive layer.

[0058] Optionally, the cross-sectional shape of the gate trench 201 includes a rectangular trench, a trapezoidal trench or a U-shaped trench.

[0059] Specifically, in one implementation, the cross-sectional shape of the gate trench 201 in the embodiment of the present invention can be any one of a rectangular groove, a trapezoidal groove and a U-shaped groove. Of course, the cross-sectional shape of the gate trench 201 can also be a groove of other polygonal shapes. When the lengths of the sides of the polygon are not exactly the same, an irregular shape is formed. The embodiment of the present invention does not impose any specific restrictions on the cross-sectional shape of the gate trench 201.

[0060] Optionally, the gate trench 201 has a depth of 2 micrometers to 6 micrometers.

[0061] Specifically, in the embodiment of the present invention, the depth of the gate trench 201 can be determined according to the thickness of each conductive layer in the substrate 10. In some implementations, the depth of the gate trench 201 can be any parameter between 2 micrometers and 6 micrometers.

[0062] Optionally, the distance between the gate trenches 201 of two adjacent cells is 1 micrometer to 10 micrometers.

[0063] Specifically, when two or more cells are arranged in an array, the spacing between the gate trenches 201 of two adjacent cells can be determined according to the horizontal extension size of each conductive layer and the electrical parameter design requirements of the corresponding power device. In some embodiments, the spacing between adjacent gate trenches 201 can be any parameter between 1 micron and 10 microns.

[0064] Optionally, the gate structure 20 extends along the surface of the substrate 10 to form a planar gate.

[0065] Specifically, the gate structure 20 with the tunneling layer 202 in the embodiment of the present invention can also be designed and applied in a power device with a conventional planar gate structure. Based on the same principle as the aforementioned trench gate, the switching power loss of the planar gate structure power device can also be reduced.

[0066] Optionally, the tunneling layer 202 contacts the third conductive layer 107 .

[0067] Specifically, when the gate structure 20 of an embodiment of the present invention is applied in a planar gate structure power device, since there is no gate trench 201 in the gate structure 20, the tunneling layer 202, the floating gate layer 203 and the gate electrode 204 all extend along the surface of the substrate 10 to form a planar gate. At this time, the tunneling layer 202 is located at the bottom layer of the gate structure 20 and contacts the third conductive layer 107 of the substrate 10.

[0068] Optionally, refer to Figure 3The gate structure 20 further includes a gate oxide layer 205 , and the gate oxide layer 205 is disposed between the floating gate layer 203 and the gate electrode 204 .

[0069] Specifically, if Figure 3 In one embodiment, in order to prevent the electric field shielding of the floating gate layer 203 and the tunneling layer 202 from being weak to the gate electrode 204, thereby affecting the threshold voltage, a gate oxide layer 205 can be further added between the floating gate layer 203 and the gate electrode 204 to enhance the electric field shielding effect on the gate electrode 204, which can further reduce the inversion degree of the channel region during the shutdown process and achieve lower shutdown power loss. At this time, since the shielding effect of the floating gate layer 203 is weak, it can also be called an electron capture layer.

[0070] Optionally, the gate oxide layer 205 includes silicon oxide.

[0071] Specifically, the gate oxide layer 205 made of silicon oxide can better block tunneling electrons and ensure that the floating gate layer 203 can capture electrons well.

[0072] Optionally, the gate oxide layer 205 has a thickness of 50 nm to 150 nm.

[0073] Specifically, with respect to the gate oxide layer 205, the thickness of the film layer should not be too thin or too thick. If the film layer is too thin, it cannot block the electrons captured in the floating gate layer 203, and if the film layer is too thick, it will affect the opening of the device channel. Therefore, the thickness of the film layer can be preferably 50nm to 150nm according to the threshold voltage requirements.

[0074] Optionally, the tunneling layer 202 includes any one of silicon oxide, titanium oxide, aluminum oxide, hafnium oxide and silicon nitride.

[0075] Specifically, in one embodiment, the tunneling layer 202 can be formed by processing any one of silicon oxide, titanium oxide, aluminum oxide, hafnium oxide and silicon nitride according to the electrical parameters and usage requirements of the corresponding type of power device, so as to construct different electron migration efficiencies and form cells with different tunneling effects. Among them, silicon oxide has the best compatibility with existing mainstream processes. At the same time, it is taken into account that electrons will cause a certain degree of damage to the tunneling layer 202 during the tunneling process. Therefore, in the process of film preparation, nitrogen-doped silicon oxide is preferred, and the growth temperature is preferably low-temperature growth, and the growth temperature is appropriately reduced to below 900°C through a hydrogen and oxygen atmosphere. Compared with conventional silicon oxide, this material has better film quality and lower trap density, and can avoid the formation of interface states and internal defects to a greater extent when capturing and releasing electrons.

[0076] Optionally, the tunneling layer 202 has a thickness of 1 nm to 20 nm.

[0077] Specifically, in one embodiment, a thin tunnel layer 202 can be formed by a thermal oxidation growth or deposition process, and the thickness of the tunnel layer 202 can be any parameter between 1nm and 20nm. From the perspective of practical application of power devices, the thicker the tunnel layer 202, the more conducive it is to a longer service life, and its thickness can be between 15nm and 20nm.

[0078] Optionally, the floating gate layer 203 includes any one of silicon, inert metal, metal nitride and doped semiconductor.

[0079] Specifically, in one embodiment, the floating gate layer 203 can be formed by using different materials to prepare the floating gate layer 203, so that the floating gate layer 203 has different shielding effects. Exemplarily, the floating gate layer 203 includes any one of silicon, an inert metal, a metal nitride, and a doped semiconductor. Silicon can be single crystal silicon or polycrystalline silicon, the inert metal can be Pt or Au, etc., the metal nitride can be tantalum nitride, etc., the doped semiconductor can be doped silicon or doped germanium, etc., and the materials of the floating gate layer 203 are not described one by one in the embodiment of the present invention. Since polycrystalline silicon has the best compatibility with existing mainstream processes and has little effect on the switching speed of power devices, it can be used as the preferred material for the floating gate layer 203.

[0080] Optionally, the floating gate layer 203 has a thickness of 1 nm to 200 nm.

[0081] Specifically, in one embodiment, similar to the method of preparing and forming the tunneling layer 202, a thin floating gate layer 203 can be formed by a thermal oxidation growth or deposition process, and the thickness of the floating gate layer 203 can be any parameter between 1nm and 200nm. From the perspective of the application of power devices, and to avoid affecting the switching speed of the power devices as much as possible, the thickness of the floating gate layer 203 should not be too thick, preferably 5nm to 10nm.

[0082] Optionally, refer to Figure 2 The base 10 further includes a fourth conductive layer 103 , a fifth conductive layer 102 and a back metal layer 101 which are sequentially stacked on the back side of the substrate 104 .

[0083] Specifically, in one embodiment, Figure 2, the base 10 of the above embodiment may further include a fourth conductive layer 103, a fifth conductive layer 102 and a back metal layer 101 located on the back of the substrate 104. The fourth conductive layer 103 is attached to the back of the substrate 104, the fifth conductive layer 102 covers the surface of the fourth conductive layer 103, the back metal layer 101 covers the surface of the fifth conductive layer 102, and one of the fourth conductive layer 103 and the fifth conductive layer 102 is a P-type conductive layer and the other is an N-type conductive layer. Exemplarily, for a power device such as an IGBT, the conductivity type of the fourth conductive layer 103 may be the same as the conductivity type of the first conductive layer 105, the conductivity type of the fifth conductive layer 102 may be the same as the conductivity type of the second conductive layer 106, and the back metal layer 101 serves as the collector of the IGBT device. It should be noted that in the embodiment of the present invention, one of the two parallel and divergent surfaces of the substrate 104 is the front side and the other is the back side. In combination with the above embodiment, it is easy to understand that the gate groove 20 is located on the front side of the substrate 104.

[0084] Optionally, refer to Figure 2 , the substrate 10 further includes an insulating layer 108 and a front metal layer 109 which are stacked in sequence;

[0085] The insulating layer 108 is stacked with the third conductive layer 107, and the insulating layer 108 is located on a side of the third conductive layer 107 away from the substrate 104;

[0086] A portion of the front metal layer 109 passes through the third conductive layer 107 and is connected to the second conductive layer 106 .

[0087] Specifically, in one embodiment, Figure 2 , the substrate 10 of the embodiment of the present invention further includes an insulating layer 108 and a front metal layer 109 stacked in sequence. The insulating layer 108 covers the third conductive layer 107, and the front metal layer 109 covers the insulating layer 108. A via is provided on the insulating layer 108, and the via penetrates the third conductive layer 107. A portion of the metal material of the front metal layer 109 extends downward through the via to connect with the second conductive layer 106. Thus, the front metal layer 109 forms other electrodes of the power device.

[0088] An embodiment of the present invention further provides a power device, characterized in that the power device includes the cell described in any of the above embodiments.

[0089] Based on the cells provided in the above embodiments, corresponding power devices can be designed and processed, and such power devices are not limited to planar gate or trench gate structures, and can use the above cells, so that the power devices can have lower turn-on and turn-off power losses.

[0090] An embodiment of the present invention further provides a power electronic device, which includes the power device provided by the above-mentioned embodiment.

[0091] By applying the above-mentioned power devices to power electronic devices such as switching power supplies, inverters, voltage stabilizers, motor drivers, etc., the stability and reliability of the power electronic devices can be improved.

[0092] An embodiment of the present invention further provides an electrical device, which is a power device of the aforementioned embodiment.

[0093] In the embodiments of the present invention, the aforementioned power device can also be used in electrical equipment such as vehicles and power storage devices to ensure the smooth and reliable operation of the electrical equipment.

[0094] like Figure 4 The present invention also provides a method for manufacturing a power device, the method comprising:

[0095] S101, preparing a substrate 10 of a power device, wherein the substrate 10 includes different conductive layers stacked together.

[0096] On a substrate 104 made of single crystal silicon or silicon carbide, a base 10 including different conductive layers is formed from bottom to top by ion implantation, diffusion, activation and other processes. Figure 3 As shown in FIG. 1 , from bottom to top, the base 10 may include a substrate 104 , a first conductive layer 105 , and a second conductive layer 106 .

[0097] S102, forming a tunneling layer 202 for electrons to pass through, a floating gate layer 203 for adjusting electron concentration, and a gate electrode 204 for providing a gate voltage on the substrate 10 in sequence, wherein the tunneling layer is in contact with the substrate.

[0098] A tunneling layer 202 and a floating gate layer 203 are sequentially prepared on the substrate 10 by a thermal oxidation growth or deposition process, and finally a gate electrode 204 is formed by depositing polysilicon. The tunneling layer 202, the floating gate layer 203 and the gate electrode 204 are stacked together, and the tunneling layer 202 is in contact with the substrate 10. When the gate structure 20 is a trench gate, the tunneling layer 202, the floating gate layer 203 and the gate electrode 204 are all deposited and formed inside the gate trench 201. When the gate structure 20 is a planar gate, the tunneling layer 202, the floating gate layer 203 and the gate electrode 204 are all flat on the surface of the substrate 10.

[0099] It should be noted that in each process of preparing and forming the tunneling layer 202 , the floating gate layer 203 and the gate electrode 204 , etching and trimming may be performed as needed.

[0100] In addition to the above-mentioned steps, in the embodiment of the present invention, after the gate electrode 204 is prepared, a third conductive layer 107 may be prepared on the second conductive layer 106, so that the gate groove 20 is exposed from the third conductive layer 107, and then an insulating layer 108 is deposited on the third conductive layer 107, and a contact hole is etched on the insulating layer 108, so that the contact hole penetrates the third conductive layer 107 and reaches the second conductive layer 106. Then, a front metal layer 109 is deposited on the insulating layer 108, and then an emitter region is formed by etching according to a pattern. Finally, after the substrate 104 is thinned, a fourth conductive layer 103 and a fifth conductive layer 102 are formed on the back thereof by injection, thermal activation and other processes, and a metal is evaporated on the surface of the fifth conductive layer 102 to form a back metal layer 101 as a collector region.

[0101] It should be noted that in some preparation processes, the conductivity type of the second conductive layer 106 and the fifth conductive layer 102 can be the same, and the second conductive layer 106 is lightly doped with a doping concentration of 10 12 cm -3 ~10 16 cm -3 The fifth conductive layer 102 is heavily doped, with a doping concentration of 10 16 cm -3 ~10 18 cm -3 The fourth conductive layer 103 and the third conductive layer 107 can have the same conductivity type, both of which are heavily doped, with a doping concentration of 10 16 cm -3 ~10 18 cm -3 The substrate 104 and the first conductive layer 105 can have the same conductivity type, both of which are lightly doped, with a doping concentration of 10 12 cm -3 ~10 16 cm -3 .

[0102] In the embodiment of the present invention, by using the above process method, a power device having a tunneling layer 202 and a floating gate layer 203 can be prepared. This power device has lower turn-on and turn-off power losses.

[0103] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0104] It is easy for a person skilled in the art to think that any combination of the above embodiments is feasible, so any combination of the above embodiments is an implementation scheme of the present invention. However, due to space limitations, this specification will not describe them in detail here.

[0105] In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0106] Similarly, it should be understood that in order to streamline the present invention and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed method should not be interpreted as reflecting the intention that the claimed invention requires more features than those expressly recited in each claim. Rather, as reflected in the claims, inventive aspects lie in less than all of the features of the individual embodiments previously disclosed. Therefore, the claims that follow the detailed description are hereby expressly incorporated into the detailed description, with each claim itself serving as a separate embodiment of the present invention.

[0107] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and in addition they may be divided into a plurality of submodules or subunits or subcomponents. Except that at least some of such features and / or processes or units are mutually exclusive, all features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed in this manner may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature providing the same, equivalent or similar purpose.

[0108] In addition, those skilled in the art will appreciate that, although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present invention and form different embodiments. For example, in the claims, any one of the claimed embodiments may be used in any combination.

[0109] It should be noted that the above embodiments illustrate the present invention rather than limit it, and that those skilled in the art may devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets shall not be construed as a limitation on the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "one" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present invention may be implemented by means of hardware comprising a number of different elements and by means of a suitably programmed computer. In a unit claim enumerating a number of devices, several of these devices may be embodied by the same hardware item. The use of the words first, second, and third, etc., does not indicate any order. These words may be interpreted as names.

Claims

1. A cell of a power device, characterized in that: The cell includes a substrate formed by stacking different conductive layers and a gate structure in contact with the substrate; The gate structure includes a tunneling layer for electrons to pass through, a floating gate layer for adjusting the electron concentration, and a gate electrode for providing a gate voltage, which are stacked in sequence.

2. The cell according to claim 1, characterized in that The base body comprises a first conductive layer, a second conductive layer and a third conductive layer which are sequentially stacked on the front side of the substrate, wherein one of two adjacent conductive layers is a P-type conductive layer and the other is an N-type conductive layer.

3. The cell according to claim 2, characterized in that The gate structure further includes a gate trench, and the gate trench penetrates different conductive layers in the substrate; The tunnel layer, the floating gate layer and the gate electrode are sequentially stacked on the inner wall of the gate trench.

4. The cell according to claim 3, characterized in that The gate trench sequentially penetrates the third conductive layer, the second conductive layer and the first conductive layer; The tunneling layer is in contact with the third conductive layer, the second conductive layer, and the first conductive layer at the same time.

5. The cell according to claim 3, characterized in that: The cross-sectional shape of the gate trench includes a rectangular trench, a trapezoidal trench or a U-shaped trench.

6. The cell according to claim 3, characterized in that: The depth of the gate trench is 2 micrometers to 6 micrometers.

7. The cell according to claim 3, characterized in that: The distance between the gate trenches of two adjacent cells is 1 micron to 10 microns.

8. The cell according to claim 2, characterized in that: The gate structure extends along the surface of the substrate to form a planar gate.

9. The cell according to claim 8, characterized in that The tunneling layer contacts the third conductive layer.

10. The cell according to any one of claims 1 to 9, characterized in that: The gate structure further includes a gate oxide layer, and the gate oxide layer is arranged between the floating gate layer and the gate electrode.

11. The cell according to claim 10, characterized in that The gate oxide layer includes silicon oxide.

12. The cell according to claim 10, characterized in that: The thickness of the gate oxide layer is 50nm to 150nm.

13. The cell according to any one of claims 1 to 9, characterized in that: The tunneling layer includes any one of silicon oxide, titanium oxide, aluminum oxide, hafnium oxide and silicon nitride.

14. The cell according to any one of claims 1 to 9, characterized in that: The thickness of the tunneling layer is 1 nm to 20 nm.

15. The cell according to any one of claims 1 to 9, characterized in that: The floating gate layer includes any one of silicon, inert metal, metal nitride and doped semiconductor.

16. The cell according to any one of claims 1 to 9, characterized in that: The floating gate layer has a thickness of 1 nm to 200 nm.

17. The cell according to claim 2, characterized in that: The base also includes a fourth conductive layer, a fifth conductive layer and a back metal layer which are sequentially stacked on the back side of the substrate.

18. The cell according to claim 2, characterized in that: The substrate also includes an insulating layer and a front metal layer stacked in sequence; The insulating layer and the third conductive layer are stacked, and the insulating layer is located on a side of the third conductive layer away from the substrate; A portion of the front metal layer passes through the third conductive layer and is connected to the second conductive layer.

19. A power device, characterized in that: The power device comprises the cell according to any one of claims 1 to 18.

20. A power electronic device, characterized in that: The power electronic device comprises the power device according to claim 19.

21. An electrical equipment, characterized in that: The electrical equipment comprises the power device according to claim 13.

22. A method for manufacturing a power device, characterized in that: The method comprises: Preparing a substrate of a power device, wherein the substrate comprises different conductive layers stacked together; A tunneling layer for electrons to pass through, a floating gate layer for adjusting electron concentration, and a gate electrode for providing a gate voltage are formed on the substrate in sequence, wherein the tunneling layer is in contact with the substrate.

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