A manufacturing method of an integrated semiconductor device

Abstract

The present invention discloses a manufacturing method of an integrated semiconductor device, belonging to the field of semiconductor technology. The manufacturing method includes: providing a substrate, and the substrate includes a high-voltage region, a medium-voltage region, and a low-voltage region; forming a high-voltage gate dielectric layer on the substrate; forming well regions in the high-voltage region and the medium-voltage region; removing the high-voltage gate dielectric layer on the medium-voltage region and the low-voltage region; forming a medium-voltage gate dielectric layer on the medium-voltage region and the low-voltage region; sequentially forming a first protective layer and a second protective layer on the medium-voltage gate dielectric layer and the high-voltage gate dielectric layer, and the first protective layer and the second protective layer have an etching selectivity ratio; forming a well region in the low-voltage region; removing the second protective layer and the first protective layer; removing the medium-voltage gate dielectric layer on the low-voltage region; forming a low-voltage gate dielectric layer on the low-voltage region. Through the manufacturing method of the integrated semiconductor device provided by the present invention, the quality of the medium-voltage gate dielectric layer can be improved, and the yield of the semiconductor device can be increased.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and particularly relates to a manufacturing method of an integrated semiconductor device. Background Art

[0002] An integrated semiconductor device is fabricated by integrating multiple types of devices. For example, transistors with different voltages and different types are fabricated on the same substrate, and different transistors are isolated by a shallow trench isolation structure. By fabricating different semiconductor devices on the same substrate, the fabrication efficiency of the semiconductor device can be improved, and the integration degree of the semiconductor device can be increased. However, during the fabrication process of different semiconductor devices, the threshold voltages of the semiconductor devices are different, and the requirements of high-frequency circuits and low-power circuits need to be met. Among them, during the fabrication of medium-voltage transistors, the thickness stability of the medium-voltage gate dielectric layer is extremely important, which will directly affect the manufacturing yield. During the fabrication process, sometimes multiple ion implantations are added according to different device design requirements for customization, thereby forcibly increasing the corresponding wet photoresist layer removal process, resulting in difficulty in controlling the final thickness of the medium-voltage gate dielectric layer. Summary of the Invention

[0003] The purpose of the present invention is to provide a manufacturing method of an integrated semiconductor device, which can simplify the manufacturing process of the integrated semiconductor device, and can avoid damage and loss to the medium-voltage gate dielectric layer during multiple ion implantations and photoresist layer removals according to the customization requirements of the semiconductor device after the medium-voltage gate dielectric layer is formed, thereby improving the quality of the medium-voltage gate dielectric layer, improving the yield of the semiconductor device, and reducing the impact on ion implantation at the same time.

[0004] To solve the above technical problems, the present invention provides a manufacturing method of an integrated semiconductor device, including:

[0005] Providing a substrate, and the substrate includes a high-voltage region, a medium-voltage region, and a low-voltage region;

[0006] Forming a high-voltage gate dielectric layer on the substrate;

[0007] Using the high-voltage gate dielectric layer as an ion implantation buffer layer to form well regions in the high-voltage region and the medium-voltage region;

[0008] Removing the high-voltage gate dielectric layer on the medium-voltage region and the low-voltage region;

[0009] Forming a medium-voltage gate dielectric layer on the medium-voltage region and the low-voltage region;

[0010] Sequentially forming a first protective layer and a second protective layer on the medium-voltage gate dielectric layer and the high-voltage gate dielectric layer, and the first protective layer and the second protective layer have an etching selectivity;

[0011] Form a well region within the low - voltage region;

[0012] Remove the second protective layer and the first protective layer;

[0013] Remove the medium - voltage gate dielectric layer on the low - voltage region; and

[0014] Form a low - voltage gate dielectric layer on the low - voltage region.

[0015] In an embodiment of the present invention, the first protective layer includes a silicon nitride layer, and the thickness of the first protective layer is 15 Å - 25 Å.

[0016] In an embodiment of the present invention, the second protective layer includes a polysilicon layer, and the thickness of the second protective layer is 40 Å - 50 Å.

[0017] In an embodiment of the present invention, the manufacturing method further includes:

[0018] Form a first patterned photoresist layer on the second protective layer, and the first patterned photoresist layer exposes the low - voltage N region on the low - voltage region;

[0019] Using the first patterned photoresist layer as a mask, and using the second protective layer, the first protective layer, and the medium - voltage gate dielectric layer as ion - implantation buffer layers for ion implantation, form a well region within the low - voltage N region;

[0020] Remove the first patterned photoresist layer by wet etching;

[0021] Form a second patterned photoresist layer on the second protective layer, and the second patterned photoresist layer exposes the low - voltage P region on the low - voltage region;

[0022] Using the second patterned photoresist layer as a mask, and using the second protective layer, the first protective layer, and the medium - voltage gate dielectric layer as ion - implantation buffer layers for ion implantation, form a well region within the low - voltage P region;

[0023] Remove the second patterned photoresist layer by wet etching.

[0024] In an embodiment of the present invention, the etching solution for removing the first patterned photoresist layer and / or the second patterned photoresist layer is each selected from at least one of SPM etching solution or SC1 etching solution.

[0025] In an embodiment of the present invention, the SPM etching solution or the SC1 etching solution does not etch the second protective layer.

[0026] In an embodiment of the present invention, when forming a well region in the low-voltage region, at the same ion concentration injection, the injection energy when using the second protective layer, the first protective layer, and the medium-voltage gate dielectric layer as the ion injection buffer layer is increased by 1% - 2.5% relative to the injection energy when using the medium-voltage gate dielectric layer as the ion injection buffer layer.

[0027] In an embodiment of the present invention, the second protective layer is removed by wet etching using a first etching solution, and the first etching solution is a mixed solution of hydrofluoric acid and nitric acid, and the volume ratio of hydrofluoric acid to nitric acid is, for example, 1:40 - 1:60.

[0028] In an embodiment of the present invention, the first protective layer is removed by wet etching using a second etching solution, and the second etching solution is phosphoric acid, the mass fraction of phosphoric acid is 86% - 95%, and the etching temperature is 150°C - 165°C.

[0029] In an embodiment of the present invention, the thickness of the high-voltage gate dielectric layer is greater than the thickness of the medium-voltage gate dielectric layer, and the thickness of the medium-voltage gate dielectric layer is greater than the thickness of the low-voltage gate dielectric layer.

[0030] In summary, the present invention provides a manufacturing method for an integrated semiconductor device. By improving the manufacturing method of the integrated semiconductor device, the unexpected technical effect of the present invention is that after forming the medium-voltage gate dielectric layer, according to the customized requirements of the semiconductor device, during multiple ion implantation and photoresist layer removal processes, damage and loss to the medium-voltage gate dielectric layer can be avoided, thereby improving the quality of the medium-voltage gate dielectric layer and the yield of the semiconductor device. The thickness of the first protective layer and the second protective layer can be reduced, reducing the influence on ion implantation. The first protective layer and the second protective layer can be independently removed, further avoiding damage to the medium-voltage gate dielectric layer and further improving the stability and yield of the semiconductor device. Process compatibility can be improved, thereby improving production efficiency and reducing costs, accurately controlling the doping concentration, protecting the well region in the low-voltage region, reducing leakage current, and improving the reliability of the device.

[0031] Of course, it is not necessary for any product implementing the present invention to achieve all the above-mentioned advantages simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for describing the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0033] Figure 1It is the intention to position the shallow trench isolation structure by forming a patterned photoresist layer on a substrate in an embodiment.

[0034] Figure 2 It is a schematic diagram of forming a shallow trench isolation structure and a high-voltage gate dielectric layer in an embodiment.

[0035] Figure 3 It is a schematic diagram of forming well regions in a high-voltage region and a medium-voltage region in an embodiment.

[0036] Figure 4 It is a schematic diagram of forming a medium-voltage gate dielectric layer, a first protective layer, and a second protective layer in an embodiment.

[0037] Figure 5 It is a schematic diagram of forming a first patterned photoresist layer and a fifth well region in an embodiment.

[0038] Figure 6 It is a schematic diagram of forming a second patterned photoresist layer and a sixth well region in an embodiment.

[0039] Figure 7 It is a schematic diagram after removing the second patterned photoresist layer in an embodiment.

[0040] Figure 8 It is a schematic diagram after removing the second protective layer in an embodiment.

[0041] Figure 9 It is a schematic diagram after removing the first protective layer in an embodiment.

[0042] Figure 10 It is a schematic diagram of the etching rates of various etching solutions on the medium-voltage gate dielectric layer, the first protective layer, and the second protective layer in an embodiment.

[0043] Figure 11 It is a schematic diagram of forming a low-voltage gate dielectric layer in an embodiment.

[0044] Figure 12 It is a schematic diagram of forming a gate structure in an embodiment.

[0045] Figure 13 It is a schematic diagram of forming a lightly doped region in an embodiment.

[0046] Figure 14 It is a schematic diagram of forming a heavily doped region in an embodiment.

[0047] Figure 15 It is a schematic diagram of an integrated semiconductor device in an embodiment.

[0048] Reference numeral description:

[0049] 10. Substrate; 11. Pad oxide layer; 12. Pad nitride layer; 13. Patterened photoresist layer; 131. Opening; 14. Shallow trench isolation structure; 15. High-voltage gate dielectric layer; 16. Medium-voltage gate dielectric layer; 17. First protective layer; 18. Second protective layer; 19. First patterned photoresist layer; 191. First recess; 20. Second patterned photoresist layer; 201. Second recess; 21. Low-voltage gate dielectric layer; 22. Gate structure; 23. Sidewall structure; 101. First well region; 102. Second well region; 103. Third well region; 104. Fourth well region; 105. Fifth well region; 106. Sixth well region; 111. First lightly doped region; 112. Second lightly doped region; 113. Third lightly doped region; 114. Fourth lightly doped region; 115. Fifth lightly doped region; 116. Sixth lightly doped region; 121. First heavily doped region; 122. Second heavily doped region; 123. Third heavily doped region; 124. Fourth heavily doped region; 125. Fifth heavily doped region; 126. Sixth heavily doped region. Detailed implementation manners

[0050] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0051] It should be noted that the drawings provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components during actual implementation. The type, quantity, and ratio of each component during actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0052] In the present invention, it should be noted that when terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or positional relationship indicated is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it cannot be understood as a limitation to the present application. In addition, when terms such as "first" and "second" appear, they are only used for descriptive and distinguishing purposes, and cannot be understood as indicating or implying relative importance.

[0053] The present invention provides a method for manufacturing an integrated semiconductor device, which can fabricate semiconductor devices with different functions in different regions of the same substrate, and each semiconductor device has excellent performance, capable of simultaneously meeting the usage requirements of high-frequency circuits and low-power circuits. Moreover, the manufacturing method of the integrated semiconductor device provided by the present invention is simple, highly controllable, and can reduce production costs, and can be used to fabricate semiconductor devices with different requirements.

[0054] Please refer to Figure 1 As shown, in an embodiment of the present invention, first, a substrate 10 is provided, and the substrate 10 can be any material suitable for formation, such as a silicon wafer, a germanium substrate, silicon germanium, silicon-on-insulator, or silicon-on-insulator stacked silicon, etc. The present invention does not limit the type and thickness of the substrate 10. In this embodiment, the substrate 10 is, for example, selected as a silicon wafer for illustration, and the substrate 10 is, for example, a P-type silicon wafer.

[0055] Please refer to Figure 1 As shown, in an embodiment of the present invention, a pad oxide layer 11 is formed on the substrate 10, and the pad oxide layer 11 is, for example, a material such as dense silicon oxide, etc. The pad oxide layer 11 can be prepared, for example, by thermal oxidation, in-situ steam generation (ISSG), or chemical vapor deposition (CVD), etc. A pad nitride layer 12 is formed on the pad oxide layer 11, and the pad nitride layer 12 is, for example, a silicon nitride layer, and the pad nitride layer 12 is formed, for example, by chemical vapor deposition, etc. During the formation of the shallow trench isolation structure, the pad oxide layer 11 can improve the stress between the substrate 10 and the pad nitride layer 12, and at the same time, during the shallow trench etching process, it can protect the substrate 10 and prevent the substrate 10 from being damaged by high-energy ions. A patterned photoresist layer 13 is formed on the pad nitride layer 12, and a plurality of openings 131 are provided on the patterned photoresist layer 13. The openings 131 are used to define the positions of the shallow trench isolation structure, and the openings 131 are, for example, equally spaced, and the openings 131 expose the pad nitride layer 12.

[0056] Please refer to Figures 1 to 2As shown, in an embodiment of the present invention, after forming the patterned photoresist layer 13, using the patterned photoresist layer 13 as a mask, for example, dry etching is performed in the direction of the substrate 10 to remove the pad nitride layer 12, the pad oxide layer 11, and a part of the substrate 10 exposed by the opening 131, forming a shallow trench. Among them, the etching gas includes, for example, one or several mixtures of chlorine (Cl2), trifluoromethane (CHF3), difluoromethane (CH2F2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), or hydrogen bromide (HBr). After forming the shallow trench, for example, a liner oxide layer (not shown in the figure) is formed in the shallow trench by thermal oxidation to repair the etching damage during the formation of the shallow trench and reduce the leakage of the integrated semiconductor device. In the shallow trench, an isolation medium is deposited, for example, by high-density plasma chemical vapor deposition (High Density Plasma CVD, HDP-CVD) or high aspect ratio process chemical vapor deposition (High Aspect Ratio Process CVD, HARP-CVD), and the isolation medium is, for example, an insulating material such as silicon oxide. After the deposition of the isolation medium is completed, the isolation medium and the pad nitride layer 12 are planarized, for example, by chemical mechanical polishing (Chemical Mechanical Polishing, CMP). Then, for example, the pad nitride layer 12 is removed by wet etching to form a shallow trench isolation structure 14, and a step is formed between the shallow trench isolation structure 14 and the pad oxide layers 11 on both sides, and the height of the step is selected according to the manufacturing requirements. Then, for example, the pad oxide layer 11 is removed by wet etching, and at the same time, a part of the isolation medium is removed, and the step between the shallow trench isolation structure 14 and the pad oxide layers 11 on both sides is transferred to between the shallow trench isolation structure 14 and the substrate 10.

[0057] Please refer to Figure 2As shown, in an embodiment of the present invention, after the formation of the shallow trench isolation structure 14, the shallow trench isolation structure 14 divides the substrate 10 into multiple regions, such as including a high-voltage region, a medium-voltage region, and a low-voltage region, etc. Among them, in each region, for example, at least one positive channel metal oxide semiconductor (PMOS) and at least one negative channel metal oxide semiconductor (NMOS) are provided. The region where the PMOS transistor is formed is defined as the P region, and the region where the NMOS transistor is formed is defined as the N region. In this embodiment, for example, taking the substrate 10 being divided into a sequentially distributed high-voltage N region (HVN), high-voltage P region (HVP), medium-voltage N region (MVN), medium-voltage P region (MVP), low-voltage N region (LVN), and low-voltage P region (LVP) as an example, the manufacturing method of the semiconductor device is described. After removing the pad oxide layer, a high-voltage gate dielectric layer 15 is formed on the substrate 10. Among them, the high-voltage gate dielectric layer 15 is, for example, a silicon oxide layer, and the high-voltage gate dielectric layer 15 can be formed, for example, by wet oxidation. In this embodiment, the thickness of the high-voltage gate dielectric layer 15 is, for example, 50 nm to 120 nm. In this application, the relative height between the high-voltage gate dielectric layer 15 and the shallow trench isolation structure 14 is not specifically limited in this application. In this embodiment, for the sake of simplicity of the figure, the heights of the high-voltage gate dielectric layer 15 and the shallow trench isolation structure 14 shown in the drawing are the same, but it does not represent the relationship between the heights in the actual manufacturing process. By simultaneously providing transistors with different types and operating voltages on the same substrate 10, and isolating adjacent transistors through the shallow trench isolation structure, the production efficiency can be improved and the production cost can be reduced.

[0058] Please refer to Figures 2 to 3As shown, in an embodiment of the present invention, after forming the high-voltage gate dielectric layer 15, a photoresist layer (not shown in the figure) is formed on the substrate 10. Using the photoresist layer as a mask and the high-voltage gate dielectric layer 15 as an ion implantation buffer layer, the substrate 10 is ion-implanted to form a well region. After forming one well region, the photoresist layer is removed, a new photoresist layer is formed, and ion implantation is performed again. In this embodiment, a doped region with a concentration higher than that of the substrate 10 is implanted with a high implantation energy. A first well region 101 is formed in the high-voltage N region, and a second well region 102 is formed in the high-voltage P region. Among them, the ions implanted in the first well region 101 are, for example, P-type ions such as boron (B) or gallium (Ga), and the ions implanted in the second well region 102 are, for example, N-type impurities such as phosphorus (P), arsenic (As), or antimony (Sb). Moreover, the implantation amounts of the first well region 101 and the second well region 102 are, for example, equal. A third well region 103 is formed in the medium-voltage N region, and a fourth well region 104 is formed in the medium-voltage P region. Among them, the ions implanted in the third well region 103 are, for example, P-type ions such as boron or gallium, and the ions implanted in the fourth well region 104 are, for example, N-type impurities such as phosphorus, arsenic, or antimony. Moreover, the implantation amounts of the third well region 103 and the fourth well region 104 are, for example, equal, or, for example, less than the implantation amounts of the first well region 101 and the second well region 102. When forming well regions in the high-voltage region and the low-voltage region, the high-voltage gate dielectric layer is used as an ion implantation buffer layer. However, the thickness of the high-voltage gate dielectric layer is relatively large, and the influence of the partial loss of the thickness of the high-voltage gate dielectric layer on high-voltage devices is relatively small.

[0059] Please refer to Figures 3 to 4 As shown, in an embodiment of the present invention, after forming well regions in the high-voltage region and the medium-voltage region, the high-voltage gate dielectric layer 15 on the medium-voltage region and the low-voltage region is removed. Specifically, a photoresist layer (not shown in the figure) is formed on the high-voltage region and the shallow trench isolation structures 14 on both sides. Using the photoresist layer as a mask, the high-voltage gate dielectric layer 15 on the medium-voltage region and the low-voltage region is removed by dry etching or wet etching. At the same time, part of the isolation dielectric in the shallow trench isolation structures 14 on the medium-voltage region and the low-voltage region is also etched. After etching, the shallow trench isolation structures 14 are still higher than the substrate 10.

[0060] Please refer to Figure 4As shown, in an embodiment of the present invention, after removing the high-voltage gate dielectric layer 15 on the medium-voltage region and the low-voltage region, a medium-voltage gate dielectric layer 16 is formed on the substrate 10 of the medium-voltage region and the low-voltage region. The medium-voltage gate dielectric layer 16 is, for example, a silicon oxide layer. In this embodiment, the medium-voltage gate dielectric layer 16 is obtained, for example, by one or a combination of methods such as in-situ vapor growth method, chemical vapor deposition, or hydrothermal oxidation method, and the thickness of the medium-voltage gate dielectric layer 16 is, for example, 15 nm to 25 nm. In an embodiment of the present invention, the medium-voltage gate dielectric layer 16 is formed, for example, by combining in-situ vapor growth method and chemical vapor deposition to improve the contact performance at the interface between the medium-voltage gate dielectric layer 16 and the substrate 10, and to improve the compactness and quality of the medium-voltage gate dielectric layer 16. After forming the medium-voltage gate dielectric layer 16, a first protective layer 17 and a second protective layer 18 are sequentially formed on the high-voltage gate dielectric layer 15 and the medium-voltage gate dielectric layer 16, and the first protective layer 17 and the medium-voltage gate dielectric layer 16 have an etching selectivity ratio, and the first protective layer 17 and the second protective layer 18 have an etching selectivity ratio.

[0061] Please refer to Figure 4 As shown, in an embodiment of the present invention, the first protective layer 17 includes, for example, a silicon nitride layer, etc., and the first protective layer 17 is obtained, for example, by methods such as Low Pressure Chemical Vapor Deposition (LPCVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD). The second protective layer 18 includes, for example, a polysilicon layer, etc., and the second protective layer 18 is obtained, for example, by methods such as low-pressure chemical vapor deposition. In this embodiment, the thickness of the first protective layer 17 is, for example, 15 Å to 25 Å, and the thickness of the second protective layer 18 is, for example, 40 Å to 50 Å. By controlling the thicknesses of the first protective layer 17 and the second protective layer 18, the total thickness of the protective layer can be reduced, thereby reducing the impact on subsequent ion implantation and improving the stability of the manufacturing process. At the same time, the materials of the first protective layer 17 and the second protective layer 18 are selected to improve the etching selectivity ratio between the adjacent medium-voltage gate dielectric layer 16, the first protective layer 17, and the second protective layer 18. During subsequent multiple ion implantation processes and during the photoresist removal process, damage and loss of the medium-voltage gate dielectric layer 16 can be avoided, and the quality and thickness stability of the medium-voltage gate dielectric layer 16 can be improved, thereby improving the yield of semiconductor devices.

[0062] Please refer to Figures 4 to 5As shown, in an embodiment of the present invention, after forming the second protective layer 18, a first patterned photoresist layer 19 is formed on the second protective layer 18. A first recess 191 is provided on the first patterned photoresist layer 19. The first recess 191 exposes, for example, the second protective layer 18 on the low-voltage N region. Using the first patterned photoresist layer 19 as a mask and using the protective layer and the medium-voltage gate dielectric layer 16 as an ion implantation buffer layer, ion implantation is performed to form a fifth well region 105. The ions implanted into the fifth well region 105 are, for example, P-type ions such as boron or gallium. In this embodiment, when forming the fifth well region 105, the implantation energy is, for example, 405 keV to 410 keV, and the implanted ion concentration is, for example, 3×10 13 atoms / cm 2 ~3.6×10 13 atoms / cm 2 . When there is no protective layer on the medium-voltage gate dielectric layer 16, when forming the fifth well region, the implanted ion concentration is, for example, 3×10 13 atoms / cm 2 ~3.6×10 13 atoms / cm 2 , and the implantation energy is 400 keV. Therefore, setting a protective layer on the medium-voltage gate dielectric layer 16 has basically no influence on ion implantation, so as to improve the stability of the manufacturing process.

[0063] Please refer to Figures 5 to 6 As shown, in an embodiment of the present invention, after forming the fifth well region 105, the first patterned photoresist layer 19 is removed, for example, by wet etching. The wet etching solution is, for example, a sulfuric acid hydrogen peroxide mixture (SPM) etching solution or a standard etching solution 1 (SC1), etc. It can avoid the loss of the second protective layer 18 when removing the first patterned photoresist layer 19. Among them, the SPM etching solution is a mixed solution of sulfuric acid and hydrogen peroxide (H2O2), and the SC1 etching solution is a mixed solution of deionized water, hydrogen peroxide, and ammonium hydroxide (NH4OH). After removing the first patterned photoresist layer 19, a second patterned photoresist layer 20 is formed on the second protective layer 18. A second recess 201 is provided on the second patterned photoresist layer 20. The second recess 201 exposes, for example, the second protective layer 18 on the low-voltage P region. Using the second patterned photoresist layer 20 as a mask and using the protective layer and the medium-voltage gate dielectric layer 16 as an ion implantation buffer layer, ion implantation is performed to form a sixth well region 106. The ions implanted into the sixth well region 106 are, for example, N-type impurities such as phosphorus, arsenic, or antimony. In this embodiment, when forming the sixth well region 106, the implantation energy is, for example, 405 keV to 410 keV, and the implanted ion concentration is, for example, 3×10 13 atoms / cm 2 ~3.6×10 13atoms / cm 2 When there is no protective layer on the medium - voltage gate dielectric layer 16, when forming the sixth well region, the ion concentration injected, for example, is 3×10 13 atoms / cm 2 ~3.6×10 13 atoms / cm 2 , and the injection energy is 400 KeV. Therefore, setting a protective layer on the medium - voltage gate dielectric layer 16 has basically no influence on ion implantation, so as to improve the stability of the manufacturing process. In this embodiment, the injection amounts in the sixth well region 106 and the fifth well region 105 are, for example, equal, or less than the injection amounts in the third well region 103 and the fourth well region 104. That is, after forming the protective layer, ion implantation is carried out. When forming a well region in a low - voltage area, at the same ion concentration injection, the injection energy when using the second protective layer, the first protective layer, and the medium - voltage gate dielectric layer as the ion - implantation buffer layer increases by 1% - 2.5% compared with the injection energy when using the medium - voltage gate dielectric layer as the ion - implantation buffer layer, and it basically does not affect the ion - implantation process.

[0064] Please refer to Figures 6 to 7 As shown, in an embodiment of the present invention, after forming the sixth well region 106, for example, the second pattern photoresist layer 20 is removed by wet etching, and the wet etching solution is, for example, SPM etching solution or SC1 etching solution, etc., which can avoid the loss of the second protective layer 18 when removing the second pattern photoresist layer 20. By using the medium - voltage gate dielectric layer 16 as the ion - implantation buffer layer for the well region in the low - voltage area, the process compatibility is improved, thereby improving the production efficiency and reducing the cost, being able to accurately control the doping concentration, protecting the well region in the low - voltage area, reducing the leakage current, and improving the reliability of the device.

[0065] Please refer to Figures 7 to 9 As shown, in an embodiment of the present invention, after removing the second pattern photoresist layer, the second protective layer 18 and the first protective layer 17 are removed in sequence. Among them, the second protective layer 18 is removed by wet etching using, for example, the first etching solution, and the first etching solution is, for example, a mixed solution of hydrofluoric acid and nitric acid. The volume ratio of hydrofluoric acid to nitric acid is, for example, 1:40 - 1:60, the mass fraction of hydrofluoric acid is, for example, 35% - 47%, and the mass fraction of nitric acid is, for example, 60% - 70%. In this embodiment, the first etching solution is, for example, selected as a mixture of 40% hydrofluoric acid and 65% nitric acid by a volume ratio of 1:50. During the etching process, the first etching solution does not react with silicon nitride. Therefore, during the process of removing the second protective layer 18, the first protective layer 17 is not lost, ensuring the integrity of the first protective layer 17.

[0066] Please refer to Figures 8 to 9As shown, in an embodiment of the present invention, after removing the second protective layer 18, the first protective layer 17 is removed. Among them, the first protective layer 17 is removed by wet etching using, for example, a second etching solution, and the second etching solution is, for example, hot phosphoric acid, the mass fraction of phosphoric acid is, for example, 86% - 95%, and the etching temperature is, for example, 150°C - 165°C. During the etching process, the second etching solution does not react with silicon oxide. Therefore, during the process of removing the first protective layer 17, the medium-voltage gate dielectric layer 16 is not damaged, ensuring the integrity of the medium-voltage gate dielectric layer 16, thereby improving the stability and yield of the semiconductor device.

[0067] Please refer to Figure 8 and Figure 10 As shown, in an embodiment of the present invention, different etching solutions have different etching rates for the medium-voltage gate dielectric layer 16, the first protective layer 17, and the second protective layer 18. Among them, the SPM etching solution or the SC1 etching solution does not etch polysilicon, the SPM etching solution can etch silicon nitride, and the SC1 etching solution can etch silicon nitride and silicon oxide, that is, the etching solution for removing the patterned photoresist layer does not etch the second protective layer. The first etching solution, which is a mixture of hydrofluoric acid and nitric acid, has a very fast etching rate for the second protective layer 18, and at the same time, it will also etch silicon oxide, and basically does not etch silicon nitride. The second etching solution, phosphoric acid, can etch silicon nitride, and does not etch silicon oxide and polysilicon. Therefore, in this application, after forming the first protective layer 17 and the second protective layer 18 on the medium-voltage gate dielectric layer 16, during the process of removing the photoresist layer after ion implantation, etching of the second protective layer 18 can be avoided, and etching of the protective layer due to too many photoresist layer removal times can be avoided, further avoiding damage to the medium-voltage gate dielectric layer 16. Thus, after forming the medium-voltage gate dielectric layer 16, according to the customization requirements of the semiconductor device, for example, using the medium-voltage gate dielectric layer 16 as an ion implantation buffer layer, multiple ion implantations can be performed. During the multiple ion implantations and photoresist layer removal processes, damage and loss of the medium-voltage gate dielectric layer 16 can be avoided, thereby improving the quality of the medium-voltage gate dielectric layer 16 and the yield of the semiconductor device. The first protective layer 17 and the second protective layer 18 can be independently removed, further avoiding damage to the medium-voltage gate dielectric layer 16 and improving the yield. By using a high etching selectivity ratio, the thickness of the first protective layer 17 and the second protective layer 18 can be reduced, and the influence on ion implantation can be reduced.

[0068] Please refer to Figure 9 and Figure 11As shown, in an embodiment of the present invention, after removing the first protective layer, the medium-voltage gate dielectric layer 16 on the low-voltage region is removed. Specifically, a photoresist layer (not shown in the figure) is formed on the high-voltage region, the medium-voltage region, and the shallow trench isolation structure 14 within the high-voltage region and the medium-voltage region. The photoresist layer exposes the low-voltage region. Using the photoresist layer as a mask, the medium-voltage gate dielectric layer 16 on the low-voltage region is removed by dry etching or wet etching. At the same time, a part of the isolation dielectric within the shallow trench isolation structure 14 on the low-voltage region is also etched. After etching, the shallow trench isolation structure 14 is still higher than the substrate 10.

[0069] Please refer to Figure 11 As shown, in an embodiment of the present invention, after removing the medium-voltage gate dielectric layer 16 on the low-voltage region, a low-voltage gate dielectric layer 21 is formed on the substrate 10 of the low-voltage region. The low-voltage gate dielectric layer 21 is, for example, a silicon oxide layer. In this embodiment, the low-voltage gate dielectric layer 21 is obtained, for example, by dry thermal oxidation, wet thermal oxidation, or in-situ steam generation methods, etc. In this embodiment, the thickness of the low-voltage gate dielectric layer 21 is, for example, 10 Å to 20 Å, that is, the thickness of the high-voltage gate dielectric layer 15 is greater than the thickness of the medium-voltage gate dielectric layer 16, and the thickness of the medium-voltage gate dielectric layer 16 is greater than the thickness of the low-voltage gate dielectric layer 21 to meet the manufacturing requirements of semiconductor devices with different threshold voltages.

[0070] Please refer to Figures 11 to 12 As shown, in an embodiment of the present invention, after forming the low-voltage gate dielectric layer 21, a gate structure 22 is formed on the gate dielectric layer. Specifically, a gate material layer (not shown in the figure) is formed on the substrate 10, and the gate material layer covers the shallow trench isolation structure 14, the high-voltage gate dielectric layer 15, the medium-voltage gate dielectric layer 16, and the low-voltage gate dielectric layer 21, etc. Among them, the gate material layer is, for example, polysilicon, etc., and doping or non-doping of the polysilicon can be carried out according to needs. Then a photoresist layer (not shown in the figure) is formed on the gate material layer to locate the position of the gate structure. Using the photoresist layer as a mask, the gate material layer exposed by the photoresist layer is removed, for example, by wet etching, dry etching, or a combination of wet etching and dry etching, etc., to form a plurality of gate structures 22. The gate structures 22 are respectively located on the high-voltage N region (HVN), the high-voltage P region (HVP), the medium-voltage N region (MVN), the medium-voltage P region (MVP), the low-voltage N region (LVN), and the low-voltage P region (LVP).

[0071] Please refer to Figures 12 to 13As shown, in an embodiment of the present invention, after the gate structure 22 is formed, lightly doped regions are formed in the substrate 10 on both sides of the gate structure 22. Among them, the lightly doped regions include, for example, a first lightly doped region 111, a second lightly doped region 112, a third lightly doped region 113, a fourth lightly doped region 114, a fifth lightly doped region 115, and a sixth lightly doped region 116. The first lightly doped region 111 is disposed in the high-voltage N region and has an N-type doping type. The second lightly doped region 112 is disposed in the high-voltage P region and has a P-type doping type. The third lightly doped region 113 is disposed in the medium-voltage N region and has an N-type doping type. The fourth lightly doped region 114 is disposed in the medium-voltage P region and has a P-type doping type. The fifth lightly doped region 115 is disposed in the low-voltage N region and has an N-type doping type. The sixth lightly doped region 116 is disposed in the low-voltage P region and has a P-type doping type. The present application does not limit the doping concentrations of the first lightly doped region 111, the second lightly doped region 112, the third lightly doped region 113, the fourth lightly doped region 114, the fifth lightly doped region 115, and the sixth lightly doped region 116, which are set according to device manufacturing requirements. During the formation of the lightly doped regions, a gate dielectric layer is disposed on the substrate, which can reduce the damage to the substrate caused by the implantation energy and improve the reliability and performance of the device.

[0072] Please refer to Figures 13 to 14 As shown, in an embodiment of the present invention, after the lightly doped regions are formed, spacer structures 23 are formed on both sides of the gate structure 22. Among them, the spacer structure 23 is, for example, a single-layer structure or a stacked structure. In this embodiment, the spacer structure 23 includes, for example, a stack of silicon oxide and silicon nitride to ensure the stability of the spacer structure. Specifically, a spacer dielectric layer (not shown in the figure) is formed on the substrate 10. The spacer dielectric layer covers the gate structure 22, the substrate 10, and the shallow trench isolation structure 14, and the material of the spacer dielectric layer is, for example, a stack of silicon oxide and silicon nitride. After the spacer dielectric layer is formed, an etching process such as dry etching can be used to remove the spacer dielectric layer and part of the gate dielectric layer located on the gate structure and part of the substrate 10, and retain part of the spacer dielectric layer on both sides of the gate structure to form the spacer structure 23, and the height of the spacer structure 23 is the same as the height of the gate structure. In this embodiment, the shape of the spacer structure 23 is, for example, an arc shape. In other embodiments, the spacer structure 23 can be of any shape.

[0073] Please refer to Figures 14 to 15As shown, in an embodiment of the present invention, after the sidewall structure 23 is formed, heavy doping is formed in the substrate 10 on both sides of the gate structure. The heavy doping regions are, for example, aligned with the side of the sidewall structure 23 away from the gate structure 22. Among them, the heavy doping regions include, for example, a first heavy doping region 121, a second heavy doping region 122, a third heavy doping region 123, a fourth heavy doping region 124, a fifth heavy doping region 125, and a sixth heavy doping region 126. The first heavy doping region 121 is disposed in the high-voltage N region, and the doping type is N-type doping. The second heavy doping region 122 is disposed in the high-voltage P region, and the doping type is P-type doping. The third heavy doping region 123 is disposed in the medium-voltage N region, and the doping type is N-type doping. The fourth heavy doping region 124 is disposed in the medium-voltage P region, and the doping type is P-type doping. The fifth heavy doping region 125 is disposed in the low-voltage N region, and the doping type is N-type doping. The sixth heavy doping region 126 is disposed in the low-voltage P region, and the doping type is P-type doping. The present application does not limit the doping concentrations of the first heavy doping region 121, the second heavy doping region 122, the third heavy doping region 123, the fourth heavy doping region 124, the fifth heavy doping region 125, and the sixth heavy doping region 126, which are set according to the device manufacturing requirements. After the heavy doping regions are formed, the interlayer dielectric layer, the metal connection structure, and the metal layer can be fabricated, which will not be elaborated here.

[0074] In summary, the present invention provides a manufacturing method for an integrated semiconductor device. By improving the manufacturing method of the integrated semiconductor device, the unexpected technical effect of the present invention is that after the medium-voltage gate dielectric layer is formed, according to the customization requirements of the semiconductor device, during the process of multiple ion implantations and photoresist layer removal, damage and loss to the medium-voltage gate dielectric layer can be avoided, thereby improving the quality of the medium-voltage gate dielectric layer and the yield of the semiconductor device. The thicknesses of the first protective layer and the second protective layer can be reduced, reducing the influence on ion implantation. The first protective layer and the second protective layer can be independently removed, further avoiding damage to the medium-voltage gate dielectric layer and further improving the stability and yield of the semiconductor device. The process compatibility can be improved, thereby improving the production efficiency and reducing the cost. The doping concentration can be accurately controlled, and the well region in the low-voltage area can be protected, reducing the leakage current and improving the reliability of the device.

[0075] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the content of this specification. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the present invention, so that those skilled in the art in the relevant technical field can well understand and utilize the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing an integrated semiconductor device, characterized in that: include: Providing a substrate, wherein the substrate comprises a high-pressure region, a medium-pressure region and a low-pressure region; forming a high voltage gate dielectric layer on the substrate; Using the high-voltage gate dielectric layer as an ion implantation buffer layer, forming well regions in the high-voltage region and the medium-voltage region; Removing the high-voltage gate dielectric layer on the medium-voltage region and the low-voltage region; forming a medium-voltage gate dielectric layer on the medium-voltage region and the low-voltage region; Sequentially forming a first protective layer and a second protective layer on the medium voltage gate dielectric layer and the high voltage gate dielectric layer, wherein the first protective layer and the second protective layer have an etching selectivity ratio; forming a well region in the low pressure region; removing the second protective layer and the first protective layer; Removing the medium voltage gate dielectric layer on the low voltage area; as well as A low-voltage gate dielectric layer is formed on the low-voltage region.

2. The method for manufacturing an integrated semiconductor device according to claim 1, characterized in that: The first protective layer includes a silicon nitride layer, and the thickness of the first protective layer is 15Å~25Å.

3. The method for manufacturing an integrated semiconductor device according to claim 1, characterized in that: The second protective layer includes a polysilicon layer, and the thickness of the second protective layer is 40Å~50Å.

4. The method for manufacturing an integrated semiconductor device according to claim 1, characterized in that: The manufacturing method further comprises: forming a first pattern photoresist layer on the second protective layer, wherein the first pattern photoresist layer exposes the low-voltage N region on the low-voltage area; Using the first patterned photoresist layer as a mask, the second protective layer, the first protective layer and the medium-voltage gate dielectric layer as an ion implantation buffer layer to perform ion implantation to form a well region in the low-voltage N region; removing the first pattern photoresist layer by wet etching; forming a second pattern photoresist layer on the second protective layer, wherein the second pattern photoresist layer exposes the low-voltage P region on the low-voltage area; Using the second patterned photoresist layer as a mask, the second protective layer, the first protective layer and the medium-voltage gate dielectric layer as an ion implantation buffer layer to perform ion implantation to form a well region in the low-voltage P region; The second pattern photoresist layer is removed by wet etching.

5. The method for manufacturing an integrated semiconductor device according to claim 4, characterized in that: The etching solution for removing the first pattern photoresist layer and / or the second pattern photoresist layer is selected from at least one of a sulfuric acid-hydrogen peroxide mixture etching solution or a standard etching solution 1, wherein the sulfuric acid-hydrogen peroxide mixture etching solution is a mixed solution of sulfuric acid and hydrogen peroxide, and the standard etching solution 1 is a mixed solution of deionized water, hydrogen peroxide and ammonium hydroxide.

6. The method for manufacturing an integrated semiconductor device according to claim 5, characterized in that: The sulfuric acid-hydrogen peroxide mixture etching solution or the standard etching solution 1 does not etch the second protective layer.

7. The method for manufacturing an integrated semiconductor device according to claim 4, characterized in that: When a well region is formed in the low-voltage region, at the same ion injection concentration, the injection energy when the second protective layer, the first protective layer and the medium-voltage gate dielectric layer are used as ion injection buffer layers is increased by 1% to 2.5% relative to the injection energy when the medium-voltage gate dielectric layer is used as the ion injection buffer layer.

8. The method for manufacturing an integrated semiconductor device according to claim 1, characterized in that: The second protective layer is removed by wet etching using a first etching solution, wherein the first etching solution is a mixed solution of hydrofluoric acid and nitric acid, and the volume ratio of the hydrofluoric acid to the nitric acid is 1:40 to 1:

60.

9. The method for manufacturing an integrated semiconductor device according to claim 1, characterized in that: The first protective layer is removed by wet etching using a second etching solution, and the second etching solution is phosphoric acid, the mass fraction of the phosphoric acid is 86%-95%, and the etching temperature is 150°C-165°C.

10. The method for manufacturing an integrated semiconductor device according to claim 1, characterized in that: The thickness of the high-voltage gate dielectric layer is greater than the thickness of the medium-voltage gate dielectric layer, and the thickness of the medium-voltage gate dielectric layer is greater than the thickness of the low-voltage gate dielectric layer.

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