Array substrate and display panel

Abstract

The invention discloses an array substrate and a display panel. The array substrate comprises a substrate as well as a first metal layer, a first insulating layer, a second metal layer and a flat layer which are sequentially stacked on the substrate, a first via hole and a second via hole are formed in the flat layer, the depth of the first via hole is larger than that of the second via hole, and the first via hole penetrates through the first insulating layer; the array substrate further comprises a first electrode, a second electrode and a second insulating layer, the first electrode corresponds to the first via hole and the second via hole in position and is laid on the first via hole and the second via hole, and the first electrode is connected with the first metal layer and the second metal layer through the first via hole and the second via hole. The second insulating layer is laid on the first electrode; the second electrode corresponds to the position of the first electrode, is arranged on the second insulating layer, and at least covers the first via hole; and the first electrode is electrically connected with the second electrode. The problem of electrochemical corrosion risk caused by potential difference between a floating electrode and a bridge electrode is solved.

Description

Technical Field

[0001] The present application relates to the field of display, and in particular to an array substrate and a display panel. Background Art

[0002] Currently, in some display panels that require pixel electrodes and common electrodes to be prepared on an array substrate, in order to achieve mutual conduction of signals between the first metal layer and the second metal layer, it is necessary to form bridge holes of varying depths at the GOA or VCOM and other transfer hole locations of the display panel.

[0003] In order to form the pixel electrode and the common electrode, two layers of indium tin oxide material need to be deposited on the array substrate so as to be etched to form the pixel electrode and the common electrode. At the same time, part of the indium tin oxide material is etched to serve as a bridging electrode for connecting the first metal layer and the second metal layer. In one prior art, only one layer of indium tin oxide material is retained as a bridging electrode at the corresponding bridging hole position, while the other layer of indium tin oxide material needs to be etched away. However, since the bridging hole is deep, the photoresist may not be etched completely, resulting in the other layer of indium tin oxide material not being etched completely at the bridging hole position, thereby causing the problem of poor panel uniformity.

[0004] The inventor has a technology that has been tested but not disclosed, that is, retaining another layer of indium tin oxide material as a floating electrode (not connected to other electrodes) corresponding to the bridge hole position, thereby improving the uniformity problem. However, the inventor soon discovered that this technology, due to the presence of the floating electrode, will accumulate static charge, resulting in a potential difference between the floating electrode and the bridge electrode, thereby increasing the risk of electrochemical corrosion. Summary of the invention

[0005] The present application discloses an array substrate and a display panel, the purpose of which is to improve the electrochemical risk problem caused by the potential difference between the floating electrode and the bridging electrode and to enhance the product performance.

[0006] The present application discloses an array substrate, comprising a base substrate, and a first metal layer, a first insulating layer, a second metal layer, and a flat layer stacked in sequence on the base substrate; a first via hole and a second via hole are formed on the flat layer, the depth of the first via hole is greater than the depth of the second via hole, and the first via hole penetrates the first insulating layer; the array substrate also comprises a first electrode, a second electrode, and a second insulating layer, the first electrode corresponds to the position of the first via hole and the second via hole, is laid on the first via hole and the second via hole, and the first electrode is connected to the first metal layer and the second metal layer respectively through the first via hole and the second via hole; the second insulating layer is laid on the first electrode; the second electrode corresponds to the position of the first electrode, is arranged on the second insulating layer, and the second electrode at least covers the first via hole; and the first electrode is electrically connected to the second electrode.

[0007] Optionally, an orthographic projection area of ​​the second electrode on the base substrate is smaller than or equal to an orthographic projection area of ​​the first electrode on the base substrate.

[0008] Optionally, the second insulating layer is provided with an opening corresponding to the bottom of the first via hole, and the second electrode passes through the opening and is connected to the first electrode.

[0009] Optionally, the second insulating layer is provided with a first opening corresponding to the bottom of the second via hole, and the second electrode passes through the first opening and is connected to the first electrode.

[0010] Optionally, the second insulating layer is provided with second openings at the bottoms of the first via hole and the second via hole corresponding to the first via hole, and the second electrodes pass through the second openings respectively to be connected to the first electrodes.

[0011] Optionally, the thickness of the second electrode is greater than the thickness of the first electrode.

[0012] Optionally, the thickness of the first electrode ranges from 300 angstroms to 1500 angstroms; the thickness of the second electrode ranges from 500 angstroms to 3500 angstroms.

[0013] Optionally, the inclination angles of the hole walls of the first via hole and the second via hole are both less than 60°.

[0014] Optionally, in the area of ​​the second insulating layer corresponding to the overlap of the first electrode and the second electrode, a third opening is opened at a position above the flat layer where no via hole is formed, the third opening penetrates the second insulating layer, and the second electrode is connected to the first electrode through the third opening.

[0015] The present application also discloses a display panel, including a color film substrate. The display panel also includes the above-mentioned array substrate. The color film substrate and the array substrate are stacked.

[0016] In the present application, the second insulating layer is opened at the bottom of at least one of the first via hole and the second via hole, so that the second electrode is directly connected to the first electrode through the bottom of the via hole; when the array substrate is powered on, the electrical signal obtained by the first electrode is simultaneously transmitted to the second electrode, and the second electrode obtains the same potential as the first electrode. Since the potentials between the first electrode and the second electrode are equal, there is no voltage difference between the first electrode and the second electrode, so that the first electrode and the second electrode are not prone to electrochemical reactions, thereby improving or even preventing the occurrence of electrochemical corrosion and improving product performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation methods of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0018] Figure 1 This is a schematic diagram of the first embodiment of the array substrate of the present application:

[0019] Figure 2 A schematic diagram of a second embodiment of an array substrate of the present application;

[0020] Figure 3 is a schematic diagram of a third embodiment of an array substrate of the present application;

[0021] Figure 4 is a schematic diagram of a fourth embodiment of an array substrate of the present application;

[0022] Figure 5 is a schematic diagram of a fifth embodiment of an array substrate of the present application;

[0023] Figure 6 is a schematic diagram of a sixth embodiment of an array substrate of the present application;

[0024] Figure 7 is a schematic diagram of a seventh embodiment of the array substrate of the present application;

[0025] Figure 8 is a schematic diagram of an eighth embodiment of the array substrate of the present application;

[0026] Fig. 9 FIG. 1 is a schematic diagram of an embodiment of a display panel of the present application.

[0027] Among them, 10, display panel; 100, array substrate; 200, color film substrate; 110, base substrate; 120, first metal layer; 130, first insulating layer; 140, second metal layer; 141, first electrode; 142, second electrode; 150, flat layer; 151, first via hole; 152, second via hole; 160, second insulating layer; 161, opening; 162, first opening; 163, second opening; 164, third opening; 170, third electrode; 180, display area. DETAILED DESCRIPTION

[0028] The present application is described in detail below with reference to the accompanying drawings and optional embodiments. It should be noted that, under the premise of no conflict, the embodiments or technical features described below can be arbitrarily combined to form new embodiments.

[0029] Figure 1 is a schematic diagram of a first embodiment of an array substrate of the present application, as shown Figure 1 As shown, the present application discloses an array substrate 100, including a base substrate 110, and a first metal layer 120, a first insulating layer 130, a second metal layer 140, and a flat layer 150 stacked in sequence on the base substrate 110; a first via hole 151 and a second via hole 152 are formed on the flat layer 150, the depth of the first via hole 151 is greater than the depth of the second via hole 152, and the first via hole 151 passes through the first insulating layer 130; the array substrate 100 also includes a first electrode 141, a second electrode 142 and a second insulating layer 160, the first electrode 120 and the second via hole 152 are formed on the flat layer 150, the depth of the first via hole 151 is greater than the depth of the second via hole 152, and the first via hole 151 passes through the first insulating layer 130; the array substrate 100 also includes a first electrode 141, a second electrode 142 and a second insulating layer 160, the first electrode The electrode 141 corresponds to the position of the first via hole 151 and the second via hole 152, and is laid on the first via hole 151 and the second via hole 152, and the first electrode 141 is connected to the first metal layer 120 and the second metal layer 140 respectively through the first via hole 151 and the second via hole 152; the second insulating layer 160 is laid on the first electrode 141; the second electrode 142 corresponds to the position of the first electrode 141, and is arranged on the second insulating layer 160, and the second electrode 142 at least covers the first via hole 151; the first electrode 141 is electrically connected to the second electrode 142.

[0030] The second electrode 142 is laid in both the first via hole 151 and the second via hole 152 in the present application, that is, the second electrode 142 is used to cover the deeper and shallower via holes at the same time. When the second electrode 142 is manufactured, the second electrode 142 in the first via hole 151 and the second via hole 152 is retained. Compared with the solution of etching the second electrode 142 at the via hole, which is likely to be incompletely etched, the second electrode 142 at the via hole is not etched in the present solution. Therefore, there will be no etching residue of the second electrode 142 material in the first via hole 151 and the second via hole 152; thereby further ensuring the uniformity of the display panel 10, preventing the second electrode 142 material from accumulating in the via hole and causing uneven exposure, thereby causing inspection problems; at the same time, the problem of etching liquid remaining in the via hole and causing panel defects is improved.

[0031] Furthermore, in order to ensure that the first electrode 141 is electrically connected to the second electrode 142, the second insulating layer 160 at the bottom of at least one of the first via hole 151 and the second via hole 152 may be opened (of course, other electrical connection methods may also be used. In the present application, it is not limited to the use of via holes to achieve electrical connection. Only the second insulating layer 160 at the bottom of the first via hole 151 or the second via hole 152 is opened as an example), so that the second electrode 142 is directly connected to the first electrode 141 through the bottom of the via hole, so that the second electrode 142 is directly connected to the first electrode 141 through the bottom of the via hole. 142 is connected to the first electrode 141; when the array substrate 100 is powered on, the electrical signal obtained by the first electrode 141 is simultaneously transmitted to the second electrode 142, and the second electrode 142 obtains a potential equal to that of the first electrode 141. Since the potentials between the first electrode 141 and the second electrode 142 are equal, there is no voltage difference between the first electrode 141 and the second electrode 142, so that the first electrode 141 and the second electrode 142 are not prone to electrochemical reactions, thereby improving or even preventing the occurrence of electrochemical corrosion, thereby enhancing the performance of the array substrate 100.

[0032] In addition, in the present application, the first metal layer 120 and the second metal layer 140 are made of copper, aluminum, molybdenum or their alloys, laminated metals and the like, with a total thickness between 1000 angstroms and 10000 angstroms, and the flat layer 150 is a composite film layer of a SiOn+SiNx composite layer plus an acrylic insulating flat layer 150, with a total thickness between 6000 angstroms and 35000 angstroms.

[0033] In addition, in this embodiment, the orthographic projection area of ​​the second electrode 142 on the base substrate 110 is less than or equal to the orthographic projection area of ​​the first electrode 141 on the base substrate 110. Figure 1 As shown, the width of the second electrode 142 is equal to or smaller than the width of the first electrode 141 .

[0034] When the orthographic projection area of ​​the second electrode 142 on the base substrate 110 is equal to the orthographic projection area of ​​the first electrode 141 on the base substrate 110, that is, the width of the second electrode 142 is equal to the width of the first electrode 141, when the second electrode 142 is connected to the first electrode 141, the second electrode 142 obtains the same potential as the first electrode 141, which can ensure that the current is distributed more evenly in the via hole, avoid excessive local current density, and ensure the display stability of the display panel 10; when the orthographic projection area of ​​the second electrode 142 on the base substrate 110 is smaller than the orthographic projection area of ​​the first electrode 141, the second electrode 142 is connected to the first electrode 141, and the second electrode 142 obtains the same potential as the first electrode 141. When the orthographic projection area of ​​the second electrode 141 on the base substrate 110, that is, when the width of the second electrode 142 is smaller than the width of the first electrode 141, the laying area of ​​the second electrode 142 can be effectively controlled, and the laying cost of the second electrode 142 can be controlled; and it can also ensure that the second electrode 142 completely covers the first via hole 151 and the second via hole 152 while preventing the second electrode 142 from contacting other structures on the same layer as the second electrode 142 on the flat layer 150, resulting in a short circuit, thereby further ensuring the stability and quality of the array substrate 100.

[0035] The present application connects the first electrode 141 and the second electrode 142 by opening the second insulating layer 160 at the bottom of at least one of the first via hole 151 and the second via hole 152, so that the second electrode 142 is directly connected to the first electrode 141 through the bottom of the via hole; in this way, when the array substrate 100 is powered on, the first electrode 141 can simultaneously transmit the obtained electrical signal to the second electrode 142, and the second electrode 142 obtains the same potential as the first electrode 141. Since the potentials between the first electrode 141 and the second electrode 142 are equal, there is no voltage difference between the first electrode 141 and the second electrode 142, so that the first electrode 141 and the second electrode 142 are not prone to electrochemical reaction, which improves or even prevents the occurrence of electrochemical corrosion and improves product performance. As follows, the example of opening the bottom of the first via hole 151 is used as an example for explanation.

[0036] like Figure 1 As shown, in this embodiment, the second insulating layer 160 is provided with an opening 161 corresponding to the bottom of the first via hole 151 , and the second electrode 142 passes through the opening 161 to connect with the first electrode 141 .

[0037] That is, the second insulating layer 160 used to isolate the first electrode 141 and the second electrode 142 is opened at the bottom of the deeper first via hole 151 to form an opening 161, so that the second electrode 142 is connected to the first electrode 141 through the opening 161 at the bottom of the first via hole 151; when the array substrate 100 is powered on, the electrical signal obtained by the first electrode 141 is simultaneously transmitted to the second electrode 142, and the second electrode 142 obtains the same potential as the first electrode 141. Since the potentials between the first electrode 141 and the second electrode 142 are equal, there is no voltage difference between the first electrode 141 and the second electrode 142, so that the first electrode 141 and the second electrode 142 are not prone to electrochemical reaction, thereby preventing electrochemical corrosion.

[0038] It should be noted that the first via 151 and the second via 152 of the present application can be located at a position where a transfer hole needs to be set in a non-display area such as GOA, or can be located at a position where a transfer hole needs to be set in the display area. In order to make it clearer, the following example is used to illustrate that, for example, the first via 151 and the second via 152 of the present application can be used for the transfer hole position of the common electrode electrode signal in the non-display area. At this time, the first metal layer 120 can be a common electrode layer for transmitting the common electrode signal, and the second metal layer 140 can be a metal layer formed in the same layer as the source and drain of the display area but not connected, and the first insulating layer 130 is used to separate the first metal layer 120 and the second metal layer 140; at the same time, the first electrode 141 and the second electrode 142 are used to realize the transmission of the common electrode signal between the first metal layer 120 and the second metal layer 140.

[0039] Of course, the first via hole 151 and the second via hole 152 of the present application can also be used in the display area to realize the cross-line or jumper requirements of signals such as common electrode signals, data signals and gate signals, and can be used not only for display panels of TOP Pixel structure, but also for array substrates of TOP COM. In addition, when the first via hole 151 and the second via hole 152 are located in the GOA area, they can also be used for the cross-line or jumper requirements of signals such as clock signals.

[0040] Figure 2 is a schematic diagram of a second embodiment of the array substrate of the present application, as shown Figure 2 As shown, Figure 2 The embodiment shown is different from Figure 1 The second insulating layer 160 is provided with a first opening 162 at the bottom of the second via hole 152 , and the second electrode 142 passes through the first opening 162 to connect with the first electrode 141 .

[0041] This embodiment is different from the previous embodiment in that a first opening 162 is provided at the bottom of the second insulating layer 160 corresponding to the shallower second via hole 152 , and no opening 161 is provided at a position corresponding to the deeper first via hole 151 , and the second electrode 142 is connected to the first electrode 141 through the first opening 162 . That is, the second insulating layer 160 used for isolating the first electrode 141 and the second electrode 142 is opened at the bottom of the second via hole 152 which is relatively shallow, so as to form a first opening 162, so that the second electrode 142 is connected to the first electrode 141 through the first opening 162 at the bottom of the second via hole 152, so that a connection is formed between the first electrode 141 and the second electrode 142; when the array substrate 100 is powered on, the electrical signal obtained by the first electrode 141 is simultaneously transmitted to the second electrode 142, and the second electrode 142 obtains the same potential as the first electrode 141; since the potentials between the first electrode 141 and the second electrode 142 are equal, there is no voltage difference between the first electrode 141 and the second electrode 142, so that the first electrode 141 and the second electrode 142 are not prone to electrochemical reaction, thereby preventing electrochemical corrosion; and since the second via hole is relatively shallow, the drilling difficulty is relatively low, and the yield rate will be higher.

[0042] Figure 3 is a schematic diagram of a third embodiment of the array substrate of the present application, as shown Figure 3 As shown, Figure 3 The illustrated embodiment is based on Figure 1 The second insulating layer 160 is improved by providing second openings 163 at the bottoms of the first via holes 151 and the second via holes 152 , and the second electrodes 142 pass through the second openings 163 to be connected to the first electrodes 141 .

[0043] The present embodiment is different from the previous embodiment in that the second insulating layer 160 is provided with second openings 163 at the bottoms of the deeper first via hole 151 and the shallower second via hole 152, and the second electrode 142 passes through the second openings 163 of the two via holes and is connected to the first electrode 141 at the same time; that is, the second insulating layer 160 used to isolate the first electrode 141 and the second electrode 142 is opened at the bottom positions of the first via hole 151 and the second via hole 152 to form the second opening 163, so that the second electrode 142 is connected to the first electrode 141 through the second opening 163 at the bottom of the second via hole 152, so that the first electrode 141 and the second electrode 142 are at least partially connected in parallel.

[0044] When the array substrate 100 is powered on, the electrical signal obtained by the first electrode 141 is simultaneously transmitted to the second electrode 142, and the second electrode 142 obtains a potential equal to that of the first electrode 141. Since the potentials between the first electrode 141 and the second electrode 142 are equal, there is no voltage difference between the first electrode 141 and the second electrode 142, so that the first electrode 141 and the second electrode 142 are not prone to electrochemical reactions, thereby preventing electrochemical corrosion. At the same time, the first electrode 141 and the second electrode 142 are at least partially connected in parallel, further reducing the impedance of the bridge via between the first electrode 141 and the second electrode 142, improving the burn-in problem caused by heating of the bridge hole position or even burning of the bridge hole due to high impedance, reducing the risk of burns during panel testing, and improving the performance of the array substrate 100.

[0045] Since the hole walls of the first via hole 151 and the second via hole 152 are steep after being formed, the second electrode 142 is easily broken when laid in the first via hole 151 and the second via hole 152; therefore, in this embodiment, the structure of the second electrode 142 is improved, and the specific improvements are as follows:

[0046] Figure 4 is a schematic diagram of a fourth embodiment of the array substrate of the present application, as shown Figure 4 As shown, the thickness of the second electrode 142 is greater than the thickness of the first electrode 141 .

[0047] The thickness of the second electrode 142 is greater than that of the first electrode 141, that is, by increasing the thickness of the second electrode 142 in the first via hole 151 and the second via hole 152, the structural strength of the second electrode 142 is increased, so that the second electrode 142 is not easily broken in the first via hole 151 and the second via hole 152, and the stability of the connection between the first electrode 141 and the second electrode 142 is enhanced, thereby enhancing the display quality of the display panel 10.

[0048] In addition, in order to ensure the connection stability between the first electrode 141 and the second electrode 142 and control the overall thickness of the array substrate 100, the present application also designs the thickness of the first electrode 141 and the second electrode 142 as follows:

[0049] The thickness of the first electrode 141 ranges from 300 angstroms to 1500 angstroms; the thickness of the second electrode 142 ranges from 500 angstroms to 3500 angstroms. For example, when the thickness of the first electrode 141 is 500 angstroms and the thickness of the second electrode 142 is 1500 angstroms, it is easier to form the first electrode 141 and the second electrode 142 on the film layer when manufacturing each film layer of the array substrate 100, and the second electrode 142 is not easy to break in the first via hole 151 and the second via hole 152, thereby enhancing the stability of the connection between the first electrode 141 and the second electrode 142, thereby enhancing the display quality of the display panel 10.

[0050] In addition, in order to further improve the problem of the second electrode 142 being broken due to being laid in the first via hole 151 and the second via hole 152, the present application also designs the structure of the first via hole 151 and the second via hole 152, as follows:

[0051] Figure 5 is a schematic diagram of a fifth embodiment of the array substrate of the present application, as shown Figure 5 As shown, the inclination angles of the hole walls of the first via hole 151 and the second via hole 152 are both less than 60°.

[0052] In this embodiment, after the first via hole 151 and the second via hole 152 are formed, the inclination angles of the hole walls of the first via hole 151 and the second via hole 152 are controlled to be less than 60°, so that the inclination of the hole walls of the first via hole 151 and the second via hole 152 is slowed down and the slope is not too steep. In this way, when the second electrode 142 is laid on the first via hole 151 and the second via hole 152, it is not easy to break in the first via hole 151 and the second via hole 152, and the stability of the connection between the first electrode 141 and the second electrode 142 is enhanced, thereby enhancing the display quality of the display panel 10.

[0053] Figure 6 is a schematic diagram of a sixth embodiment of the array substrate of the present application, as shown Figure 6 As shown, the array substrate 100 also includes a third electrode 170, which can be a pixel electrode. The material used to make the second electrode 142 can be the same as the material used to make the pixel electrode, both of which are made of indium tin oxide material. The third electrode 170 is located in the display area 180 of the array substrate 100; the third electrode 170 is arranged in the same layer as the second electrode 142 and is disconnected from the second electrode 142.

[0054] In this embodiment, the third electrode 170 is a pixel electrode located in the display area, and the second electrode 142 is located in the non-display area; the material used to make the second electrode 142 is the same as the material used to make the third electrode 170 in the display area 180 of the array substrate 100, both of which are indium tin oxide materials. In this way, when forming the pixel electrode in the display area 180 and the second electrode 142 in the non-display area 180, both can be made of pixel electrode materials, which simplifies the manufacturing process; during the manufacturing process, the pixel electrode material is laid on the flat layer 150 of the array substrate 100 in an entire layer. After the pixel electrode is formed in the display area 180 of the array substrate 100, the pixel electrode in the display area 180 of the array substrate 100 is disconnected from the second electrode 142 above the first via hole 151 and the second via hole 152, so as to avoid the pixel electrode in the display area 180 being connected to the pixel electrode in the non-display area 180 to form a short circuit after power is turned on, thereby ensuring the display quality of the display panel 10.

[0055] Furthermore, by laying the second electrode in the first via hole 151 and the second via hole 152, that is, by using the second electrode to cover the deeper and shallower via holes at the same time, when manufacturing the pixel electrode of the non-display area 180, the indium tin oxide material in the first via hole 151 and the second via hole 152 is retained. Compared with the solution in which the second electrode 142 at the via hole is etched but it is likely to be incompletely etched, the second electrode 142 at the via hole is not etched in this solution, so there will be no etching residue of indium tin oxide material in the first via hole 151 and the second via hole 152; thereby further ensuring the uniformity of the display panel 10, preventing the unevenness caused by the accumulation of indium tin oxide material in the first via hole 151 and the second via hole 152, and thus improving the inspection troubles or display problems caused by the unevenness.

[0056] In addition, the second insulating layer 160 used to isolate the first electrode 141 and the second electrode 142 is opened at the bottom of the deeper first via hole 151 to form an opening 161, so that the second electrode 142 is connected to the first electrode 141 through the opening 161 at the bottom of the first via hole 151, so that a connection is formed between the first electrode 141 and the second electrode 142; when the array substrate 100 is powered on, the electrical signal obtained by the first electrode 141 is simultaneously transmitted to the second electrode 142, and the second electrode 142 obtains the same potential as the first electrode 141. Since the potentials between the first electrode 141 and the second electrode 142 are equal, there is no voltage difference between the first electrode 141 and the second electrode 142, so that the first electrode 141 and the second electrode 142 are not prone to electrochemical reaction, thereby preventing electrochemical corrosion.

[0057] Figure 7 is a schematic diagram of a seventh embodiment of the array substrate of the present application, as shown Figure 7As shown, in the area of ​​the second insulating layer 160 corresponding to the overlap of the first electrode 141 and the second electrode 142, a third opening 164 is opened at a position above the flat layer 150 where no via hole is formed, and the third opening 164 penetrates the second insulating layer 160, and the second electrode 142 is connected to the first electrode 141 through the third opening 164.

[0058] Compared with the solution of setting the first opening 162 inside the first via hole 151, or setting the second opening 163 inside the second via hole 152, so that the first electrode 141 and the second electrode 142 are conductively connected to each other, the yield of the present application is higher, because if the connection point for conductively connecting the first electrode 141 and the second electrode 142 is set inside the first via hole 151 or the second via hole 152 or even at the bottom, due to the influence of the via formation process, when etching the flat layer 150 and the first insulating layer 130 to form the via hole, the flatness of the surface will decrease with the depth of the via hole, and the deeper the via hole, the worse the flatness of the inner wall and the bottom of the hole will be, which will cause the surface of the first electrode 141 to be uneven when it is formed inside the via hole, which may cause the shape of the film layer of the first opening 162 or the second opening 163 formed at the bottom of the via hole to change, and the conductive effect between the first electrode 141 and the second electrode 142 may be poor due to flatness reasons.

[0059] In this embodiment, a third opening 164 is opened in an area where the first via hole 151 and the second via hole 152 are located above the flat layer 150 and no via hole is formed, so that the first electrode 141 and the second electrode 142 are connected to each other. Due to the existence of the flat layer 150, the flatness of 141 formed above the flat layer will be very good. By forming the third opening 164 here, the connection effect between the first electrode 141 and the second electrode 142 here will be better.

[0060] Optionally, the third opening 164 may be provided in plurality, so that a plurality of connection points between the first electrode 141 and the second electrode 142 are connected to each other to form a parallel connection, so as to further reduce the connection impedance.

[0061] Figure 8 is a schematic diagram of an eighth embodiment of the array substrate of the present application, as shown Figure 8As shown, optionally, on the basis that the second electrode 142 is connected to the first electrode 141 through the third opening 164 opened in the area of ​​the second insulating layer 160 above the flat layer 150 where no via is formed, it can also be combined with the above-mentioned embodiments, and the first opening 162 and / or the second opening 163 are also opened in the second insulating layer 160 at the bottom of the first via 151 and the second via 152, so that a part of the second electrode 142 is connected to the first electrode 141 in the via, and the other part is connected to the first electrode 141 in the third opening 164 outside the via, so that there are multiple connection points between the first electrode 141 and the second electrode 142, which are interconnected and form a parallel connection to further reduce the connection impedance.

[0062] When the array substrate 100 is powered on, the electrical signal obtained by the first electrode 141 is simultaneously transmitted to the second electrode 142, and the second electrode 142 obtains the same potential as the first electrode 141. Since the potentials between the first electrode 141 and the second electrode 142 are equal, there is no voltage difference between the first electrode 141 and the second electrode 142, so that the first electrode 141 and the second electrode 142 are not prone to electrochemical reaction, thereby improving or even preventing electrochemical corrosion. At the same time, the first electrode 141 and the second electrode 142 are connected in parallel, further reducing the impedance of the bridge via between the first electrode 141 and the second electrode 142, reducing the risk of burns caused by excessive heating at the via during panel testing, and improving the performance of the array substrate 100. Moreover, since the via is conductive both inside and outside the via, the present solution can improve the problem of poor conductivity between the first electrode 141 and the second electrode 142 due to disconnection at the via, and at the same time, avoid the problem of parasitic capacitance caused by partial floating of the second electrode 142 due to disconnection.

[0063] Fig. 9 is a schematic diagram of an embodiment of a display panel of the present application, such as Fig. 9 As shown, the present application also discloses a display panel 10, including a color filter substrate 200, and the display panel 10 also includes the above-mentioned array substrate 100, and the color filter substrate 200 and the array substrate 100 are stacked. When manufacturing the display panel 10, the color filter substrate 200 is installed above the array substrate 100, and liquid crystal is encapsulated between the color filter substrate 200 and the array substrate 100 to form a complete display panel 10.

[0064] Because in the array substrate 100 of the display panel 10, the second electrode 142 is designed on top of the bridging via of the original first electrode 141 to reduce the progressive risk problem caused by electrode unevenness, the second electrode 142 above the first electrode 141 will accumulate static charge, resulting in a difference in potential between the first electrode 141 and the second electrode 142, which will increase the risk of electrochemical corrosion.

[0065] In response to the above problems, the present application opens up the bottom of at least one of the first via hole 151 and the second via hole 152 on the flat layer 150, so that the second electrode 142 is directly connected to the first electrode 141 through the bottom of the via hole, so that the second electrode 142 is connected in parallel with the first electrode 141; when the array substrate 100 is powered on, the electrical signal obtained by the first electrode 141 is simultaneously transmitted to the second electrode 142, and the second electrode 142 obtains the same potential as the first electrode 141. Since the potentials between the first electrode 141 and the second electrode 142 are equal, there is no voltage difference between the first electrode 141 and the second electrode 142, so that the first electrode 141 and the second electrode 142 are not prone to electrochemical reactions, thereby preventing electrochemical corrosion.

[0066] It should be noted that this embodiment only illustrates certain scenarios in which this solution can be implemented, but it does not mean that this application can only be applied to these scenarios recorded in this application. As long as it does not affect the normal function of the display panel and the location where the bridge hole is required, this application can be used. The inventive concept of this application can form a lot of embodiments, but the length of the application document is limited and it is impossible to list them one by one. Therefore, under the premise of no conflict, the embodiments or technical features described above can be arbitrarily combined to form a new embodiment. After the embodiments or technical features are combined, the original technical effects will be enhanced.

[0067] The above content is a further detailed description of the present application in combination with specific optional implementation methods, and it cannot be determined that the specific implementation of the present application is limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, several simple deductions or substitutions can be made without departing from the concept of the present application, which should be deemed to fall within the scope of protection of the present application.

Claims

1. An array substrate, comprising a base substrate, and a first metal layer, a first insulating layer, a second metal layer, and a planar layer sequentially stacked on the base substrate; A first via hole and a second via hole are formed on the planar layer, the depth of the first via hole is greater than the depth of the second via hole, and the first via hole passes through the first insulating layer; It is characterized in that The array substrate further includes a first electrode, a second electrode and a second insulating layer, the first electrode corresponds to the position of the first via hole and the second via hole, is laid on the first via hole and the second via hole, and the first electrode is connected to the first metal layer and the second metal layer respectively through the first via hole and the second via hole; The second insulating layer is laid on the first electrode; The second electrode corresponds to the position of the first electrode and is disposed on the second insulating layer. The second electrode at least covers the first via hole; and the first electrode is electrically connected to the second electrode.

2. The array substrate according to claim 1, characterized in that: The orthographic projection area of ​​the second electrode on the base substrate is smaller than or equal to the orthographic projection area of ​​the first electrode on the base substrate.

3. The array substrate according to claim 2, characterized in that: The second insulating layer is provided with an opening corresponding to the bottom of the first via hole, and the second electrode passes through the opening to be connected to the first electrode.

4. The array substrate according to claim 2, characterized in that: The second insulating layer is provided with a first opening corresponding to the bottom of the second via hole, and the second electrode passes through the first opening and is connected to the first electrode.

5. The array substrate according to claim 2, characterized in that: The second insulating layer is provided with second openings at the bottoms of the first via holes and the second via holes corresponding to the first via holes, and the second electrodes pass through the second openings respectively and are connected to the first electrodes.

6. The array substrate according to any one of claims 1 to 5, characterized in that: The thickness of the second electrode is greater than the thickness of the first electrode.

7. The array substrate according to claim 6, characterized in that: The thickness of the first electrode ranges from 300 angstroms to 1500 angstroms; the thickness of the second electrode ranges from 500 angstroms to 3500 angstroms.

8. The array substrate according to claim 7, characterized in that: The inclination angles of the hole walls of the first via hole and the second via hole are both less than 60°.

9. The array substrate according to claim 1, wherein: In the region of the second insulating layer corresponding to the overlap of the first electrode and the second electrode, a third opening is formed at a position above the planar layer where no via hole is formed, the third opening penetrates the second insulating layer, and the second electrode is connected to the first electrode through the third opening.

10. A display panel, comprising a color film substrate, characterized in that: The display panel further comprises an array substrate as claimed in any one of claims 1 to 9, and the color filter substrate and the array substrate are stacked.

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