Back-contact cell resistant to light-induced degradation, method for manufacturing the same, and photovoltaic module

Abstract

The present application provides a back-contact battery resistant to light-induced degradation, a manufacturing method thereof, and a photovoltaic module, relating to the technical field of back-contact batteries. The battery includes a silicon wafer, a first semiconductor layer, and a second semiconductor layer; the silicon wafer has a front side and a back side; the first semiconductor layer and the second semiconductor layer are alternately arranged on the back side of the silicon wafer; a second tunneling oxide layer, a hydrogenated amorphous silicon layer, a third tunneling oxide layer, and a silicon nitride layer are sequentially laid on the front side of the silicon wafer; the thickness of the second tunneling oxide layer is 1-3 nm, the thickness of the third tunneling oxide layer is 1.5-3 nm, and the hydrogen content of the hydrogenated amorphous silicon layer is 1e19-1e21 cm-3. The present application uses a structure of oxide + hydrogenated amorphous silicon layer + oxide + silicon nitride layer, and introduces a double-oxide layer structure as a barrier layer for hydrogen escape, which can effectively isolate the diffusion of hydrogen to bulk silicon and its outward overflow under light and heat conditions. At the same time, the excellent passivation effect of the tunneling oxide layer ensures that the passivation level is not affected, realizing a highly efficient back-contact solar cell resistant to light-induced degradation.

Description

Technical Field

[0001] This application relates to the technical field of back-contact batteries, and particularly to a back-contact battery resistant to light-induced degradation, a manufacturing method thereof, and a photovoltaic module. Background Art

[0002] In the prior art, there are mainly two methods for preparing the front structure of a back-contact battery using a tube-type device.

[0003] The first is to use tube-type ALD and PECVD to prepare an alumina passivation layer and a silicon nitride antireflection layer; the second is to directly use tube-type PECVD to prepare a hydrogenated amorphous silicon passivation layer and a silicon nitride antireflection layer.

[0004] Comparing the two methods, the structure of using tube-type PECVD to prepare a hydrogenated amorphous silicon passivation layer and a silicon nitride antireflection layer has significant advantages in terms of equipment cost. However, compared with the structure of an alumina passivation layer and a silicon nitride antireflection layer, the structure of a hydrogenated amorphous silicon passivation layer and a silicon nitride antireflection layer has severe attenuation in the light-induced degradation (LID) test.

[0005] The main reason for the above situation is that, in order to ensure the passivation level, the hydrogen content in the hydrogenated amorphous silicon passivation layer is relatively high, and under the photothermal conditions prepared by tube-type PECVD, the hydrogen in the hydrogenated amorphous silicon passivation layer will diffuse into the bulk silicon and spill outwards, resulting in a serious decline in the passivation effect.

[0006] Chinese Patent No. CN118398679A discloses a jointly passivated back-contact battery with specific passivation on the light-receiving surface, its manufacturing and application, including a silicon substrate, a first semiconductor layer and a second semiconductor layer alternately arranged on the back of the silicon substrate, and further including a second tunneling oxide layer, an ultra-thin amorphous silicon layer and an antireflection layer sequentially arranged on the light-receiving surface of the silicon substrate. The thickness of the ultra-thin amorphous silicon layer is 0.5 - 3 nm, and the thickness ratio of the second tunneling oxide layer to the ultra-thin amorphous silicon layer is 0.15 - 1:1.

[0007] However, the following points still need to be improved in this patent: In order to improve the light transmittance, this patent uses an ultra-thin amorphous silicon layer and further sets a tunneling oxide layer between the ultra-thin amorphous silicon layer and the light-receiving surface of the silicon substrate. However, under high-temperature conditions, because the thickness of the ultra-thin amorphous silicon layer is relatively small, it is more likely to spill hydrogen outwards to the silicon substrate and the outside. Although it sets a tunneling oxide layer to block the diffusion of hydrogen into the bulk silicon, there is still a situation where hydrogen will spill outwards, but this patent does not consider this technical problem.

[0008] The Chinese patent with the patent number CN118825140B discloses a manufacturing method of a back contact battery with multi-layer tunneling oxidation passivation and the back contact battery, including sequentially depositing a first oxide layer, a second oxide layer and an oxygen-doped amorphous silicon layer on the front side of a silicon wafer to form a passivation layer, and then depositing an anti-reflection layer; the first oxide layer is deposited by air thermal oxidation under the condition of not evacuating the vacuum by heating in air, the second oxide layer is formed by tube PECVD deposition under the vacuum state and the condition of introducing nitrous oxide, controlling the thickness ratio of the first oxide layer to the second oxide layer to be 1:(0.6 - 3.4), the thickness of the first oxide layer is 0.6 - 1.2 nm, and the ratio of the sum of the thicknesses of the first oxide layer and the second oxide layer to the thickness of the oxygen-doped amorphous silicon layer is 1:(0.3 - 10.8).

[0009] The following points need to be improved in this patent: In order to improve the passivation level of the tunneling oxide layer, this patent combines thermal oxidation + tube PECVD nitrous oxide oxidation. Although it mentions the thickness ratio of the oxide layer and the oxygen-doped amorphous silicon layer, its essential purpose is to improve the density of the tunneling oxide layer through a special deposition method of the tunneling oxide layer, thereby improving the passivation level. However, the density of the tunneling oxide layer has no significant effect on the escape of hydrogen. Therefore, there is still a situation where hydrogen escapes outward in this invention patent, and this invention patent does not consider the technical problem of light-induced degradation.

[0010] Therefore, there is an urgent need to provide a back contact battery to solve the above technical problems.

[0011] It should be noted that this part of the content of the present invention only provides the background technology related to the present invention, and does not necessarily constitute the prior art or the well-known technology. Summary of the Invention

[0012] In view of this, the purpose of this application is to provide an anti-light-induced degradation back contact battery, its manufacturing method and a photovoltaic module, so as to at least solve the problem of serious light-induced degradation of the structure of preparing a hydrogenated amorphous silicon passivation layer and a silicon nitride anti-reflection layer by tube PECVD in the prior art. This application uses the structure of an oxide layer + a hydrogenated amorphous silicon layer + an oxide layer + a silicon nitride layer, introducing a double-oxide layer structure as a barrier layer for hydrogen escape, which can effectively isolate the diffusion of hydrogen to the bulk silicon and its outward overflow under the conditions of light and heat. At the same time, the excellent passivation effect of the tunneling oxide layer makes the passivation level not affected, realizing a highly efficient and anti-light-induced degradation back contact solar cell.

[0013] In a first aspect, the present application provides a light-induced degradation-resistant back-contact battery, comprising a silicon wafer, a first semiconductor layer, and a second semiconductor layer; the silicon wafer has a front side and a back side; the first semiconductor layer and the second semiconductor layer are alternately arranged on the back side of the silicon wafer; a second tunneling oxide layer, a hydrogenated amorphous silicon layer, a third tunneling oxide layer, and a silicon nitride layer are sequentially laid on the front side of the silicon wafer; the thickness of the second tunneling oxide layer is 1-3 nm, the thickness of the third tunneling oxide layer is 1.5-3 nm, and the hydrogen content of the hydrogenated amorphous silicon layer is 1e19-1e21 cm -3 。

[0014] In some embodiments, the thickness of the hydrogenated amorphous silicon layer is 7-12 nm.

[0015] In some embodiments, the thickness of the silicon nitride layer is 80-120 nm.

[0016] In some embodiments, the first semiconductor layer includes a first tunneling oxide layer and a first doped silicon layer, the thickness of the first tunneling oxide layer is 1-2 nm, the thickness of the first doped silicon layer is 150-300 nm, and the effective doping concentration of the first doped silicon layer is 1e20-1e21 cm -3 。

[0017] In some embodiments, the second semiconductor layer includes an intrinsic amorphous silicon layer and a second doped silicon layer, the thickness of the intrinsic amorphous silicon layer is 5-15 nm, the thickness of the second doped silicon layer is 10-35 nm, and the effective doping concentration of the second doped silicon layer is 1e19-4e20 cm -3 。

[0018] In some embodiments, the thickness ratio of the hydrogenated amorphous silicon layer, the first tunneling oxide layer, and the intrinsic amorphous silicon layer is 1:(0.1-0.21):(0.5-1.43).

[0019] In some embodiments, the ratio of the hydrogen content of the hydrogenated amorphous silicon layer, the effective doping concentration of the first doped silicon layer, and the effective doping concentration of the second doped silicon layer is 1:(0.2-50):(0.02-10).

[0020] In some embodiments, there is a second semiconductor opening region between adjacent first semiconductor layers, and both ends of the second semiconductor layer located in the second semiconductor opening region extend a preset distance toward the surfaces of the adjacent first semiconductor layers and overlap with them to form an overlapping region.

[0021] In some embodiments, the light-induced degradation-resistant back-contact battery further includes a conductive film layer, the conductive film layer is laid on the first semiconductor layer and the second semiconductor layer, the thickness of the conductive film layer is 40-80 nm, and isolation grooves are provided at the positions of each overlapping region, and the width of the isolation grooves is 30-200 μm.

[0022] In some embodiments, the light-induced degradation resistant back contact cell further includes a first electrode and a second electrode, which are respectively disposed in a first semiconductor opening region and a second semiconductor opening region; the first semiconductor opening region is disposed in a portion of the first semiconductor layer outside the overlapping region.

[0023] Second, the present application provides a method for manufacturing a light-induced degradation resistant back contact cell, and the manufacturing method includes the following steps:

[0024] S1. Provide a double-sided polished silicon wafer;

[0025] S2. Deposit and form a first semiconductor layer and a mask layer on the back surface of the silicon wafer;

[0026] S3. Perform a first etching opening on the back surface obtained in S2 to form second semiconductor opening regions arranged at intervals;

[0027] S4. Remove the residual first semiconductor layer in the second semiconductor opening region by texturing, and at the same time form a textured surface on the front surface of the silicon wafer and in the second semiconductor opening region. Then, during the cleaning process of the textured surface, remove the mask layer outside the second semiconductor opening region on the back surface of the silicon wafer;

[0028] S5. Sequentially lay a second tunneling oxide layer, a hydrogenated amorphous silicon layer, a third tunneling oxide layer, and a silicon nitride layer on the front surface of the silicon wafer by using a tube-type PECVD through a chemical reaction;

[0029] Wherein, the thickness of the second tunneling oxide layer is 1 - 3 nm, the thickness of the third tunneling oxide layer is 1.5 - 3 nm, and the hydrogen content of the hydrogenated amorphous silicon layer is 1e19 - 1e21 cm -3 ;

[0030] S6. Remove the overplating deposited on the back surface of the silicon wafer in S5 and clean the second semiconductor opening region again;

[0031] S7. Deposit and form a second semiconductor layer on the back surface of the silicon wafer.

[0032] In some embodiments, in S5, the second tunneling oxide layer is formed by thermal oxidation with oxygen.

[0033] In some embodiments, in S5, the second tunneling oxide layer is formed by using a nitrous oxide plasma glow reaction, and the reaction conditions are: the reaction temperature is 400 - 450 °C, the reaction pressure is 100 - 3000 mtorr, and the reaction time is 10 - 120 seconds.

[0034] In some embodiments, in S5, the hydrogenated amorphous silicon layer is formed by a chemical reaction of silane, phosphine, hydrogen, and carbon dioxide under glow conditions. The reaction conditions are as follows: the reaction temperature is 400 - 450 °C, the flow rate of hydrogen is 3000 - 6000 sccm, the reaction time is 200 - 500 seconds, and the reaction pressure is 800 - 3000 mtorr.

[0035] In some embodiments, in S5, the third tunneling oxide layer is formed by using a nitrous oxide plasma glow reaction. The reaction conditions are as follows: the reaction temperature is 400 - 450 °C, the reaction pressure is 100 - 3000 mtorr, and the reaction time is 30 - 120 seconds.

[0036] In some embodiments, in S5, the silicon nitride layer is formed by a chemical reaction of silane and ammonia under glow conditions.

[0037] In some embodiments, the preparation method further includes:

[0038] S8. Perform a second etching opening on the second semiconductor layer to form a first semiconductor opening region that alternates and is spaced apart from the second semiconductor opening region;

[0039] S9. Deposit a conductive film layer on the back surface obtained in S8;

[0040] S10. Perform a third etching opening on a part of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove;

[0041] S11. Form a first electrode and a second electrode in the first semiconductor opening region and the second semiconductor opening region respectively.

[0042] In a third aspect, the present application also provides a photovoltaic module, which includes the aforementioned back contact battery with light-induced degradation resistance.

[0043] The beneficial effects that the present application can achieve are as follows:

[0044] 1. Compared with the prior art that directly uses a tube PECVD device to prepare a hydrogenated amorphous silicon passivation layer and a silicon nitride antireflection layer, the present application uses a structure of oxide + amorphous silicon + oxide + silicon nitride, and introduces a double-oxide layer structure as a barrier layer for hydrogen dissipation, which can effectively isolate the diffusion of hydrogen to bulk silicon and outward overflow under photothermal conditions. At the same time, the excellent passivation effect of the tunneling oxide layer does not affect the passivation level.

[0045] 2. The structure of a single tunneling oxide layer + ultra-thin amorphous silicon layer used in the prior art (CN118398679A) cannot prevent hydrogen from leaking outwards at high temperatures. The present application uses an amorphous silicon layer with a normal thickness, which can reduce the preparation difficulty and has better passivation performance than the ultra-thin amorphous silicon layer. The double oxide layer structure can effectively isolate the diffusion of hydrogen to the bulk silicon and its outward leakage under photothermal conditions, while avoiding affecting the passivation level. At the same time, the present application also finds that setting a tunneling oxide layer outside the amorphous silicon layer can reduce the light attenuation of the battery without affecting the performance of the battery itself. Further, subsequent experiments also prove that the ultra-thin amorphous silicon layer is not ideal in terms of passivation level and anti-photodarkening effect.

[0046] 3. The structure of tunneling oxide layer + amorphous silicon + tunneling oxide layer + silicon nitride used in the present application adopts an appropriate thickness of the tunneling oxide layer, which can effectively isolate the escape of hydrogen while avoiding affecting the optical performance of the front side of the battery. In addition, the thickness of the tunneling oxide layer in the present application is matched with the hydrogen content of the amorphous silicon layer to achieve an efficient and anti-photodarkening back-contact solar cell.

[0047] 4. There is a specific relationship between the thickness ratios of the hydrogenated amorphous silicon layer, the first tunneling oxide layer, and the intrinsic amorphous silicon layer in the present application. There is also a specific relationship between the hydrogen content of the hydrogenated amorphous silicon layer, the effective doping concentration of the first doped silicon layer, and the effective doping concentration of the second doped silicon layer. The parameters on the front and back sides of the present application have a synergistic effect, which is more conducive to improving the passivation effect of the battery and thus improving the conversion efficiency of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments. It should be understood that the following drawings only show some embodiments of the present application and should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0049] Figure 1 Shows a schematic structural diagram of an anti-photodarkening back-contact battery in step S1 of Embodiment 1 of the present application;

[0050] Figure 2 Shows a schematic structural diagram of an anti-photodarkening back-contact battery in step S2 of Embodiment 1 of the present application;

[0051] Figure 3 Shows a schematic structural diagram of an anti-photodarkening back-contact battery in steps S3 and S4 of Embodiment 1 of the present application;

[0052] Figure 4The schematic structural diagram of the light-induced degradation resistant back contact battery in steps S5 and S6 of Embodiment 1 of the present application is shown;

[0053] Figure 5 The schematic structural diagram of the light-induced degradation resistant back contact battery in steps S7 and S8 of Embodiment 1 of the present application is shown;

[0054] Figure 6 The schematic structural diagram of the light-induced degradation resistant back contact battery in steps S9 and S10 of Embodiment 1 of the present application is shown;

[0055] Figure 7 The schematic structural diagram of the light-induced degradation resistant back contact battery in step S11 of Embodiment 1 of the present application is shown.

[0056] Explanation of reference numerals:

[0057] 1. Silicon wafer; 2. First tunneling oxide layer; 3. N-type doped polysilicon layer; 4. Mask layer; 5. Second tunneling oxide layer; 6. Hydrogenated amorphous silicon layer; 7. Third tunneling oxide layer; 8. Silicon nitride layer; 9. Intrinsic amorphous silicon layer; 10. P-type doped amorphous silicon layer; 11. Conductive film layer. Detailed implementation manners

[0058] The terms "comprising", "including", "containing" or "characterized by" in the description, claims and drawings of the present application are synonymous, and are inclusive of endpoints or open-ended, and do not exclude additional unrecited elements or method steps. "Comprising" is a technical term used in claim language, meaning that the elements exist, but other elements can also be added and still form a structure or method within the scope of the claims.

[0059] It should be noted that: Similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. In addition, the terms "first", "second", "third", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance. The term "about" in the present application means including a small change (up to + / - 10%) of the value.

[0060] In a first aspect, the present application provides a light-induced degradation resistant back contact battery, including a silicon wafer, a first semiconductor layer and a second semiconductor layer; the silicon wafer has a front side and a back side; the first semiconductor layer and the second semiconductor layer are alternately arranged on the back side of the silicon wafer; a second tunneling oxide layer, a hydrogenated amorphous silicon layer, a third tunneling oxide layer and a silicon nitride layer are sequentially laid on the front side of the silicon wafer; the thickness of the second tunneling oxide layer is 1 - 3 nm, and can be 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm and any value therebetween.

[0061] The thickness of the third tunneling oxide layer is 1.5 - 3 nm, and it can be 1.5 nm, 2 nm, 2.5 nm, 3 nm, and any value between them.

[0062] The hydrogen content of the hydrogenated amorphous silicon layer is 1e19 - 1e21 cm -3 , and it can be 1e19 cm -3 , 5e19 cm -3 , 1e20 cm -3 , 5e20 cm -3 , 1e21 cm -3 , and any value between them.

[0063] The structure of tunneling oxide layer + amorphous silicon + tunneling oxide layer + silicon nitride used in this application adopts an appropriate thickness of the tunneling oxide layer, which can effectively isolate the escape of hydrogen while avoiding affecting the optical performance of the front of the battery. In addition, the thickness of the tunneling oxide layer in this application is matched with the hydrogen content of the amorphous silicon layer to achieve a highly efficient and light-induced degradation-resistant back-contact solar cell.

[0064] In some embodiments, the thickness of the hydrogenated amorphous silicon layer is 7 - 12 nm, and it can be 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, and any value between them. Compared with the ultra-thin amorphous silicon layer, the hydrogenated amorphous silicon layer above 7 nm is more compatible with the existing semiconductor manufacturing process during preparation, does not require precise control of the thickness of the amorphous silicon layer, and can reduce production costs and complexity. In addition, the thickness of the hydrogenated amorphous silicon layer is reasonably set in this application, which is beneficial to balancing the passivation effect and light absorption efficiency of the hydrogenated amorphous silicon layer, thereby improving the battery conversion efficiency.

[0065] In some embodiments, the thickness of the silicon nitride layer is 80 - 120 nm, and it can be 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, and any value between them.

[0066] It should be noted that the silicon nitride layer in this application is an antireflection layer. In addition to the silicon nitride layer, other silicon dielectric antireflection layers, more specifically silicon oxynitride, silicon oxide, etc., are also within the protection scope of this application.

[0067] In some embodiments, the first semiconductor layer includes a first tunneling oxide layer and a first doped silicon layer. The thickness of the first tunneling oxide layer is 1 - 2 nm, the thickness of the first doped silicon layer is 150 - 300 nm, and the effective doping concentration of the first doped silicon layer is 1e20 - 1e21 cm -3 . The first doped silicon layer is an N-type doped polysilicon layer.

[0068] This application uses appropriate thicknesses of the first tunneling oxide layer and the first doped silicon layer, and an appropriate effective doping concentration of the first doped silicon layer, which is more conducive to improving the battery conversion efficiency.

[0069] In some embodiments, the second semiconductor layer includes an intrinsic amorphous silicon layer and a second doped silicon layer. The thickness of the intrinsic amorphous silicon layer is 5 - 15 nm, the thickness of the second doped silicon layer is 10 - 35 nm, and the effective doping concentration of the second doped silicon layer is 1e19 - 4e20 cm -3 . The second doped silicon layer is a P-type doped amorphous silicon layer or a P-type doped microcrystalline silicon layer.

[0070] This application uses appropriate thicknesses of the second tunneling oxide layer and the second doped silicon layer, and an appropriate effective doping concentration of the second doped silicon layer, which is more conducive to improving the battery conversion efficiency.

[0071] In some embodiments, the thickness ratio of the hydrogenated amorphous silicon layer, the first tunneling oxide layer, and the intrinsic amorphous silicon layer is 1:(0.1 - 0.21):(0.5 - 1.43).

[0072] In some embodiments, the ratio of the hydrogen content of the hydrogenated amorphous silicon layer, the effective doping concentration of the first doped silicon layer, and the effective doping concentration of the second doped silicon layer is 1:(0.2 - 50):(0.02 - 10).

[0073] This application has a specific relationship between the thickness ratios of the hydrogenated amorphous silicon layer, the first tunneling oxide layer, and the intrinsic amorphous silicon layer, and there is also a specific relationship between the hydrogen content of the hydrogenated amorphous silicon layer, the effective doping concentration of the first doped silicon layer, and the effective doping concentration of the second doped silicon layer. The parameters on the front and back of this application have a synergistic effect, which is more conducive to improving the passivation effect of the battery and thus improving the battery conversion efficiency.

[0074] In some embodiments, there is a second semiconductor opening region between adjacent first semiconductor layers. The two ends of the second semiconductor layer located in the second semiconductor opening region extend a preset distance towards the surfaces of the adjacent first semiconductor layers and overlap with them to form an overlapping region.

[0075] In some embodiments, the light-induced degradation resistant back contact battery further includes a conductive film layer. The conductive film layer is laid on the first semiconductor layer and the second semiconductor layer. The thickness of the conductive film layer is 40 - 80 nm, and isolation grooves are provided at the positions of each overlapping region. The width of the isolation grooves is 30 - 200 μm.

[0076] The conductive film layer is deposited by physical vapor deposition technology (PVD) or reactive plasma deposition technology (RPD). The conductive film layer is an indium oxide-based thin film doped with tin, zinc, tungsten, titanium, etc. or a zinc oxide-based thin film doped with aluminum, boron, gallium, etc.

[0077] In some embodiments, the light-induced degradation resistant back contact cell further includes a first electrode and a second electrode, which are respectively disposed in a first semiconductor opening region and a second semiconductor opening region; the first semiconductor opening region is disposed in a portion of the first semiconductor layer outside the overlapping region.

[0078] It can be understood that the first electrode and the second electrode are divided into two polarities, and the polarities of the first electrode and the second electrode are different. The first electrode and the second electrode can be formed by printing silver paste to form a silver paste grid electrode, electroplating to form a grid electrode, etc.

[0079] In a second aspect, the present application provides a method for manufacturing a light-induced degradation resistant back contact cell, and the manufacturing method includes the following steps:

[0080] S1. Provide a double-sided polished silicon wafer;

[0081] The silicon wafer is an N-type single-crystalline silicon wafer, and the silicon wafer is a Czochralski single-crystalline silicon wafer or a cast single-crystalline silicon wafer.

[0082] S2. Deposit a first semiconductor layer and a mask layer on the back surface of the silicon wafer;

[0083] The first semiconductor layer includes a first tunneling oxide layer and a first doped silicon layer, and the first doped silicon layer is an N-type doped polysilicon layer. The first semiconductor layer can be formed by tube PECVD, LPCVD or PVD in-situ doping deposition annealing, and preferably tube PECVD in-situ doping is used.

[0084] The first tunneling oxide layer is formed by using nitrous oxide plasma glow reaction, and the reaction conditions are: the reaction temperature is 400 - 450 °C, the reaction pressure is 100 - 2000 mtorr, and the reaction time is 10 - 60 seconds.

[0085] The N-type doped polysilicon layer is formed by chemical reaction of silane, phosphine and hydrogen under glow conditions, and the reaction conditions are: the reaction temperature is 400 - 450 °C, the reaction time is 500 - 1500 seconds, and the reaction pressure is 100 - 2000 mtorr.

[0086] The thickness of the first tunneling oxide layer is 1 - 2 nm, the thickness of the first doped silicon layer is 150 - 300 nm, and the effective doping concentration of the first doped silicon layer is 1e20 - 1e21 cm -3 , the mask layer is at least one of silicon nitride, silicon oxynitride and silicon oxide, and the thickness of the mask layer is 50 - 200 nm.

[0087] S3. Perform a first etching opening on the back surface obtained in S2 to form second semiconductor opening regions arranged at intervals;

[0088] The width of the second semiconductor opening region is 0.3 - 0.6 mm, and the etching is laser etching or chemical etching. The laser is ultraviolet or green laser, and the pulse width is less than 100 ns.

[0089] S4. Remove the residual first semiconductor layer in the second semiconductor opening region by texturing, and at the same time form a textured surface on the front side of the silicon wafer and in the second semiconductor opening region. Then, during the cleaning process of the textured surface, remove the mask layer outside the second semiconductor opening region on the back side of the silicon wafer at the same time;

[0090] Hydrofluoric acid is used to remove the mask layer.

[0091] S5. Use a tube PECVD to sequentially deposit a second tunneling oxide layer, a hydrogenated amorphous silicon layer, a third tunneling oxide layer, and a silicon nitride layer on the front side of the silicon wafer through chemical reactions;

[0092] The second tunneling oxide layer is formed by thermal oxidation of oxygen or by using a nitrous oxide plasma glow reaction. The reaction conditions are: the reaction temperature is 400 - 450 °C, the reaction pressure is 100 - 3000 mtorr, and the reaction time is 10 - 120 seconds.

[0093] The hydrogenated amorphous silicon layer is formed by chemical reactions of silane, phosphine, hydrogen, and carbon dioxide under glow conditions. The reaction conditions are: the reaction temperature is 400 - 450 °C, the flow rate of hydrogen is 3000 - 6000 sccm, the reaction time is 200 - 500 seconds, and the reaction pressure is 800 - 3000 mtorr.

[0094] The third tunneling oxide layer is formed by using a nitrous oxide plasma glow reaction. The reaction conditions are: the reaction temperature is 400 - 450 °C, the reaction pressure is 100 - 3000 mtorr, and the reaction time is 30 - 120 seconds.

[0095] The silicon nitride layer is formed by chemical reactions of silane and ammonia under glow conditions.

[0096] Among them, the thickness of the second tunneling oxide layer is 1 - 3 nm, the thickness of the third tunneling oxide layer is 1.5 - 3 nm, the hydrogen content of the hydrogenated amorphous silicon layer is 1e19 - 1e21 cm -3 , and the thickness of the silicon nitride layer is 80 - 120 nm.

[0097] S6. Remove the overplating deposited on the back side of the silicon wafer in S5 and clean the second semiconductor opening region again;

[0098] S7. Deposit and form a second semiconductor layer on the back side of the silicon wafer.

[0099] The second semiconductor layer is formed by deposition through plasma enhanced chemical vapor deposition (PECVD) technology. The second semiconductor layer includes an intrinsic amorphous silicon layer and a second doped silicon layer. The thickness of the intrinsic amorphous silicon layer is 5 - 15 nm, the thickness of the second doped silicon layer is 10 - 35 nm, and the effective doping concentration of the second doped silicon layer is 1e19 - 4e20 cm -3 . The second doped silicon layer is a P-type doped amorphous silicon layer or a P-type doped microcrystalline silicon layer.

[0100] S8. Perform a second etching opening on the second semiconductor layer to form a first semiconductor opening region that alternates and is spaced apart from the second semiconductor opening region;

[0101] The width of the first semiconductor opening region is 0.1 - 0.3 mm, and the etching is laser etching or chemical etching. The laser is an ultraviolet or green laser, and the pulse width is less than 50 ns.

[0102] S9. Deposit a conductive film layer on the back surface obtained in S8;

[0103] The thickness of the conductive film layer is 40 - 80 nm. The conductive film layer is deposited through physical vapor deposition technology (PVD) or reactive plasma deposition technology (RPD). The conductive film layer is an indium oxide-based thin film doped with tin, zinc, tungsten, titanium, etc. or a zinc oxide-based thin film doped with aluminum, boron, gallium, etc.

[0104] S10. Perform a third etching opening on a part of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove;

[0105] The etching is laser etching or chemical etching, and the width of the isolation groove is 30 - 200 μm.

[0106] S11. Form a first electrode and a second electrode in the first semiconductor opening region and the second semiconductor opening region respectively.

[0107] The first electrode and the second electrode can form a silver grid electrode through screen printing process and low-temperature sintering, or can form electrodes through electroplating. Preferably, grid line electrodes are formed through electroplating.

[0108] Thirdly, the present application also provides a photovoltaic module, which includes the aforementioned back contact battery with light-induced attenuation resistance.

[0109] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present application.

[0110] References to "embodiments" in this specification mean that specific features, structures, or characteristics described in connection with the embodiments can be included in at least one embodiment of the present application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0111] Embodiment 1

[0112] As Figures 1 to 7 shown, a method for preparing a back-contact battery resistant to light-induced degradation, the preparation method comprising the following steps:

[0113] S1. As Figure 1 shown, provide a double-sided polished silicon wafer 1, the silicon wafer 1 is an N-type single-crystalline silicon wafer, and the silicon wafer 1 is a Czochralski single-crystalline silicon wafer.

[0114] S2. As Figure 2 shown, deposit and form a first semiconductor layer and a mask layer 4 on the back surface of the silicon wafer 1; the first semiconductor layer includes a first tunneling oxide layer 2 and an N-type doped polysilicon layer 3. The first semiconductor layer is formed by in-situ doping using a tube-type PECVD.

[0115] The first tunneling oxide layer 2 is formed by using a nitrous oxide plasma glow reaction, and the reaction conditions are: the reaction temperature is 450 °C, the reaction pressure is 1000 mtorr, and the reaction time is 30 seconds.

[0116] The N-type doped polysilicon layer 3 is formed by the chemical reaction of silane, phosphine, and hydrogen under glow conditions, and the reaction conditions are: the reaction temperature is 450 °C, the reaction time is 1000 seconds, and the reaction pressure is 1000 mtorr.

[0117] The thickness of the first tunneling oxide layer 2 is 1.5 nm, the thickness of the N-type doped polysilicon layer 3 is 150 nm, and the effective doping concentration of the N-type doped polysilicon layer 3 is 1e20 cm -3 , the mask layer 4 is silicon nitride, and the thickness of the mask layer 4 is 70 nm.

[0118] S3. As Figure 3 shown, perform a first etching opening on the back surface obtained in S2 by laser etching to form second semiconductor opening regions arranged at intervals;

[0119] The width S102 of the second semiconductor opening region is 0.4 mm, the laser is an ultraviolet laser, and the pulse width is less than 100 ns.

[0120] S4. As Figure 3As shown, the remaining first semiconductor layer in the second semiconductor opening area is removed by texturing, and at the same time, a textured surface is formed on the front surface of the silicon wafer 1 and in the second semiconductor opening area. Then, during the cleaning process of the textured surface, hydrofluoric acid is used to remove the mask layer 4 outside the second semiconductor opening area on the back surface of the silicon wafer 1.

[0121] S5. As Figure 4 shown, a second tunneling oxide layer 5, a hydrogenated amorphous silicon layer 6, a third tunneling oxide layer 7, and a silicon nitride layer 8 are sequentially deposited on the front surface of the silicon wafer 1 by using a tube-type PECVD through chemical reactions.

[0122] The second tunneling oxide layer 5 is formed by using a nitrous oxide plasma glow reaction. The reaction conditions are: the reaction temperature is 450 °C, the reaction pressure is 500 mtorr, and the reaction time is 60 seconds.

[0123] The hydrogenated amorphous silicon layer 6 is formed by chemical reactions of silane, phosphine, hydrogen, and carbon dioxide under glow conditions. The reaction conditions are: the reaction temperature is 450 °C, the flow rate of hydrogen is 5000 sccm, the reaction time is 300 seconds, and the reaction pressure is 1000 mtorr.

[0124] The third tunneling oxide layer 7 is formed by using a nitrous oxide plasma glow reaction. The reaction conditions are: the reaction temperature is 450 °C, the reaction pressure is 2000 mtorr, and the reaction time is 60 seconds.

[0125] The silicon nitride layer 8 is formed by chemical reactions of silane and ammonia under glow conditions.

[0126] Among them, the thickness of the second tunneling oxide layer 5 is 2 nm, the thickness of the third tunneling oxide layer 7 is 2.5 nm, the hydrogen content of the hydrogenated amorphous silicon layer 6 is 5e20 cm -3 , the thickness of the hydrogenated amorphous silicon layer 6 is 10 nm, and the thickness of the silicon nitride layer 8 is 120 nm.

[0127] S6. As Figure 4 shown, the over-deposited layer generated during the deposition on the back surface of the silicon wafer 1 in S5 is removed, and the second semiconductor opening area is cleaned again.

[0128] S7. As Figure 5 shown, a second semiconductor layer is deposited and formed on the back surface of the silicon wafer 1 by using a plasma-enhanced chemical vapor deposition (PECVD) technology.

[0129] The second semiconductor layer includes an intrinsic amorphous silicon layer 9 and a P-type doped amorphous silicon layer 10. The thickness of the intrinsic amorphous silicon layer 9 is 5 nm, the thickness of the P-type doped amorphous silicon layer 10 is 10 nm, and the effective doping concentration of the P-type doped amorphous silicon layer 10 is 1e19 cm -3 .

[0130] S8. AsFigure 5 As shown, a second etching opening is formed by laser etching on the second semiconductor layer, forming a first semiconductor opening region that alternates and is spaced apart from the second semiconductor opening region;

[0131] The width S101 of the first semiconductor opening region is 0.2 mm, the laser is an ultraviolet laser, and the pulse width is less than 50 ns.

[0132] S9. As Figure 6 shown, a conductive film layer 11 is deposited on the back surface obtained in S8;

[0133] The thickness of the conductive film layer 11 is 60 nm. The conductive film layer 11 is deposited by physical vapor deposition technology (PVD), and the conductive film layer 11 is an indium tin oxide-based thin film.

[0134] S10. As Figure 6 shown, a third etching opening is formed by laser etching on a part of the conductive film layer 11 located between the first semiconductor opening region and the second semiconductor opening region, forming an isolation groove;

[0135] The width of the isolation groove is 80 μm.

[0136] S11. As Figure 7 shown, a first electrode and a second electrode are respectively formed in the first semiconductor opening region and the second semiconductor opening region by electroplating.

[0137] Among them, the thickness ratio of the hydrogenated amorphous silicon layer, the first tunneling oxide layer, and the intrinsic amorphous silicon layer is 1:0.15:0.5.

[0138] The ratio of the hydrogen content of the hydrogenated amorphous silicon layer, the effective doping concentration of the first doped silicon layer, and the effective doping concentration of the second doped silicon layer is 1:0.2:0.02.

[0139] Example 2

[0140] Refer to the method of Example 1. The difference is that the thickness of the second tunneling oxide layer 5 is 1.5 nm, and the process parameters that need to be adjusted to meet this condition are: in S5, the reaction time for depositing the second tunneling oxide layer 5 is shortened to 40 seconds.

[0141] The thickness of the third tunneling oxide layer 7 is 2 nm, and the process parameters that need to be adjusted to meet this condition are: in S5, the reaction time for depositing the third tunneling oxide layer 7 is shortened to 30 seconds.

[0142] Example 3

[0143] It is carried out according to the method of Embodiment 1, except that the thickness of the second tunneling oxide layer 5 is 2.5 nm, and the process parameters that need to be adjusted to meet this condition are: in S5, the reaction time for depositing the second tunneling oxide layer 5 is increased to 90 seconds.

[0144] The thickness of the third tunneling oxide layer 7 is 3 nm, and the process parameters that need to be adjusted to meet this condition are: in S5, the reaction time for depositing the third tunneling oxide layer 7 is increased to 120 seconds.

[0145] Embodiment 4

[0146] It is carried out according to the method of Embodiment 1, except that the hydrogen content of the hydrogenated amorphous silicon layer 6 is 1e21 cm -3 , and the process parameters that need to be adjusted to meet this condition are: in S5, the flow rate of hydrogen gas for depositing the hydrogenated amorphous silicon layer 6 is increased to 6000 sccm.

[0147] Comparative Example 1

[0148] It is carried out according to the method of Embodiment 1, except that in S5, the passivation structure is a conventional hydrogenated amorphous silicon passivation layer and silicon nitride antireflection layer structure, specifically: a hydrogenated amorphous silicon layer and a silicon nitride layer are sequentially deposited on the front side of the silicon wafer by PECVD. The thickness of the hydrogenated amorphous silicon layer is 10 nm, the thickness of the silicon nitride layer is 120 nm, and the effective doping concentration of the hydrogenated amorphous silicon layer is 5e20 cm -3 .

[0149] Comparative Example 2

[0150] It is carried out according to the method of Embodiment 1, except that in S5, the second tunneling oxide layer 5 is not deposited.

[0151] Comparative Example 3

[0152] It is carried out according to the method of Embodiment 1, except that in S5, the third tunneling oxide layer 7 is not deposited.

[0153] Comparative Example 4

[0154] It is carried out according to the method of Embodiment 1, except that in S5, the thickness of the hydrogenated amorphous silicon layer 6 is 2 nm, which is formed by tube PECVD, the formation temperature is 450 °C, and the formation conditions include: introducing silane and hydrogen gas, the flow rate ratio of silane to hydrogen gas is 0.2:1, the process pressure is 300 Pa, the power is 10 kW, and after depositing to the preset thickness, the power supply is turned off and the gas is pumped out.

[0155] Comparative Example 5

[0156] It is carried out according to the method of Embodiment 1, except that the thickness of the second tunneling oxide layer 5 is 0.5 nm, and the process parameters that need to be adjusted to meet this condition are: in S5, the reaction time for depositing the second tunneling oxide layer 5 is shortened to 3 seconds.

[0157] The thickness of the third tunneling oxide layer 7 is 0.5 nm, and the process parameters that need to be adjusted to meet this condition are: in S5, the reaction time for depositing the third tunneling oxide layer 7 is shortened to 2 seconds.

[0158] Comparative Example 6

[0159] It is carried out according to the method of Embodiment 1, except that the thickness of the second tunneling oxide layer 5 is 4 nm, and the process parameters that need to be adjusted to meet this condition are: in S5, the reaction time for depositing the second tunneling oxide layer 5 is increased to 200 seconds.

[0160] The thickness of the third tunneling oxide layer 7 is 4 nm, and the process parameters that need to be adjusted to meet this condition are: in S5, the reaction time for depositing the third tunneling oxide layer 7 is increased to 180 seconds.

[0161] Test Example

[0162] The back-contact batteries obtained in the above embodiments and comparative examples are subjected to various performance tests, and the results are shown in Table 1. Among them, the specific test method for the LID attenuation performance index can be referred to GB / T 6495.11-2016.

[0163] Table 1

[0164]

[0165] From the above results, it can be seen that according to Embodiment 1 and Comparative Example 1, the present application uses a structure of oxide + hydrogenated amorphous silicon layer + oxide + silicon nitride layer, and introduces a double-oxide layer structure as a barrier layer for hydrogen escape, which can effectively isolate the diffusion of hydrogen to bulk silicon and outward spillage under photothermal conditions. At the same time, the excellent passivation effect of the tunneling oxide layer does not affect the passivation level, realizing a highly efficient and light-induced degradation-resistant back-contact solar cell.

[0166] Furthermore, according to Embodiment 1 and Comparative Example 2, the second tunneling oxide layer of the present application can effectively isolate the diffusion of hydrogen to bulk silicon under photothermal conditions, thereby ensuring the passivation effect of the battery.

[0167] Furthermore, according to Example 1 and Comparative Example 3, it can be seen that the third tunneling oxide layer of the present application can effectively isolate the outward overflow of hydrogen under photothermal conditions, thereby ensuring the passivation effect of the battery. At the same time, it can be seen that after depositing the third tunneling oxide layer 7, the current density, open circuit voltage, and battery conversion efficiency of the battery are still not affected. The third tunneling oxide layer of the present application can reduce the light-induced degradation of the battery without affecting the performance of the battery itself.

[0168] Furthermore, according to Example 1 and Comparative Example 4, it can be seen that the present application reasonably sets the thickness of the hydrogenated amorphous silicon layer, which is beneficial to balancing the passivation effect and light absorption efficiency of the hydrogenated amorphous silicon layer, thereby improving the battery conversion efficiency. The reason for the poor effect of Comparative Example 4 is speculated as follows: when the thickness of the hydrogenated amorphous silicon layer is relatively thin, it is unable to store enough hydrogen, affecting the chemical passivation level. At the same time, under high-temperature conditions, when the thickness of the hydrogenated amorphous silicon layer is relatively thin, it is more likely to generate hydrogen overflow to the silicon substrate and the outside, thereby making it more severely attenuated in the light-induced degradation (LID) test.

[0169] Furthermore, according to Example 1 and Comparative Example 5, when the thicknesses of the second tunneling oxide layer and the third tunneling oxide layer are too thin, they cannot isolate the escape of hydrogen in the hydrogenated amorphous silicon layer, and the passivation effect will still be damaged. However, the thickness of the tunneling oxide layer of the present application is matched with the hydrogen content of the hydrogenated amorphous silicon layer to achieve a highly efficient and light-induced degradation-resistant back-contact solar cell.

[0170] Furthermore, according to Example 1 and Comparative Example 6, when the thicknesses of the second tunneling oxide layer and the third tunneling oxide layer are too thick, it will seriously affect the optical performance of the front side of the battery and reduce the battery conversion efficiency. However, the thickness of the tunneling oxide layer of the present application is matched with the hydrogen content of the hydrogenated amorphous silicon layer to achieve a highly efficient and light-induced degradation-resistant back-contact solar cell.

[0171] Furthermore, according to Example 1 and Example 2, by adopting the preferred technical solution of the present application, the escape of hydrogen can be further isolated while avoiding affecting the optical performance of the front side of the battery, thereby improving the battery conversion efficiency.

[0172] Furthermore, according to Example 1 and Example 3, by adopting the preferred technical solution of the present application, the escape of hydrogen can be further isolated while avoiding affecting the optical performance of the front side of the battery, thereby improving the battery conversion efficiency.

[0173] Furthermore, according to Example 1 and Example 4, although increasing the hydrogen content of the hydrogenated amorphous silicon layer can improve the passivation performance, the isolation effect of the tunneling oxide layer has a limit. By adopting the preferred technical solution of the present application, the escape of hydrogen can be further isolated while avoiding affecting the optical performance of the front side of the battery, thereby improving the battery conversion efficiency.

[0174] The above has introduced the embodiments of the present application in detail. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for those of ordinary skill in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A back contact cell resistant to light-induced degradation, comprising: A silicon wafer having a front side and a back side; A first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer are alternately arranged on the back side of the silicon wafer; It is characterized by further comprising: A second tunneling oxide layer, a hydrogenated amorphous silicon layer, a third tunneling oxide layer and a silicon nitride layer are sequentially laid on the front side of the silicon wafer; The thickness of the second tunnel oxide layer is 1-3 nm, the thickness of the third tunnel oxide layer is 1.5-3 nm, and the hydrogen content of the hydrogenated amorphous silicon layer is 1e19-1e21 cm -3 ; The thickness of the hydrogenated amorphous silicon layer is 7-12 nm; The second tunnel oxide layer and the third tunnel oxide layer are used to isolate the hydrogen in the hydrogenated amorphous silicon layer from diffusing into the bulk silicon and overflowing outward under photothermal conditions.

2. The back contact cell against light-induced degradation according to claim 1, characterized in that: The thickness of the silicon nitride layer is 80-120 nm.

3. The back contact cell resistant to light-induced degradation according to claim 1, characterized in that: The first semiconductor layer includes a first tunneling oxide layer and a first doped silicon layer, the first tunneling oxide layer has a thickness of 1-2 nm, the first doped silicon layer has a thickness of 150-300 nm, and the effective doping concentration of the first doped silicon layer is 1e20-1e21 cm -3 ; and / or, The second semiconductor layer includes an intrinsic amorphous silicon layer and a second doped silicon layer, the thickness of the intrinsic amorphous silicon layer is 5-15 nm, the thickness of the second doped silicon layer is 10-35 nm, and the effective doping concentration of the second doped silicon layer is 1e19-4e20 cm -3 .

4. The back contact cell resistant to light-induced degradation according to claim 3, characterized in that: The thickness ratio of the hydrogenated amorphous silicon layer, the first tunneling oxide layer, and the intrinsic amorphous silicon layer is 1:(0.1-0.21):(0.5-1.43); and / or, The ratio of the hydrogen content of the hydrogenated amorphous silicon layer, the effective doping concentration of the first doped silicon layer, and the effective doping concentration of the second doped silicon layer is 1: (0.2-50): (0.02-10).

5. The back contact cell resistant to light-induced degradation according to claim 1, characterized in that: A second semiconductor opening region is provided between adjacent first semiconductor layers, and two ends of the second semiconductor layer located in the second semiconductor opening region respectively extend toward the surface of the adjacent first semiconductor layer by a preset distance and overlap with it to form an overlapping region.

6. The back contact cell resistant to light-induced degradation according to claim 5, characterized in that: The back contact cell resistant to light-induced degradation further comprises: A conductive film layer, the conductive film layer is laid on the first semiconductor layer and the second semiconductor layer, the thickness of the conductive film layer is 40-80 nm, the conductive film layer is provided with an isolation groove at the position of each overlapping region, and the width of the isolation groove is 30-200 μm; and / or, The back contact cell resistant to light-induced degradation further comprises: A first electrode and a second electrode, wherein the first electrode and the second electrode are respectively disposed in a first semiconductor opening region and a second semiconductor opening region; the first semiconductor opening region is disposed in a portion outside an overlapping region on the first semiconductor layer.

7. A method for preparing a back contact cell resistant to light-induced degradation, characterized in that: The preparation method is used to prepare a back contact cell resistant to light-induced degradation according to any one of claims 1 to 6, and the preparation method comprises the following steps: S1, provide double-sided polished silicon wafers; S2, depositing a first semiconductor layer and a mask layer on the back side of the silicon wafer; S3, performing a first etching opening on the back surface obtained in S2 to form a second semiconductor opening region arranged at intervals; S4, removing the first semiconductor layer remaining in the second semiconductor opening region by texturing, and forming a velvet surface on the front side of the silicon wafer and the second semiconductor opening region, and then removing the mask layer outside the second semiconductor opening region on the back side of the silicon wafer during the cleaning process of the velvet surface; S5, using tubular PECVD to sequentially lay a second tunnel oxide layer, a hydrogenated amorphous silicon layer, a third tunnel oxide layer and a silicon nitride layer on the front side of the silicon wafer through chemical reaction; The thickness of the second tunnel oxide layer is 1-3 nm, the thickness of the third tunnel oxide layer is 1.5-3 nm, and the hydrogen content of the hydrogenated amorphous silicon layer is 1e19-1e21 cm -3 ; S6, removing the plating layer deposited on the back side of the silicon wafer in S5 and cleaning the second semiconductor opening area again; S7. Depositing a second semiconductor layer on the back side of the silicon wafer.

8. The preparation method according to claim 7, characterized in that: In S5, a second tunnel oxide layer is formed by thermal oxidation with oxygen; and / or, In S5, the second tunnel oxide layer is formed by using a nitrous oxide plasma glow reaction, and the reaction conditions are: a reaction temperature of 400-450°C, a reaction pressure of 100-3000 mtorr, and a reaction time of 10-120 seconds.

9. The preparation method according to claim 7, characterized in that: In S5, the hydrogenated amorphous silicon layer is formed by chemical reaction of silane, phosphine, hydrogen and carbon dioxide under glow conditions, and the reaction conditions are: reaction temperature of 400-450°C, hydrogen flow rate of 3000-6000sccm, reaction time of 200-500 seconds, and reaction pressure of 800-3000mtorr.

10. The preparation method according to claim 7, characterized in that: In S5, the third tunnel oxide layer is formed by using a nitrous oxide plasma glow reaction, and the reaction conditions are: a reaction temperature of 400-450°C, a reaction pressure of 100-3000 mtorr, and a reaction time of 30-120 seconds.

11. The preparation method according to claim 7, characterized in that: In S5, the silicon nitride layer is formed by chemical reaction of silane and ammonia under glow conditions; and / or, The preparation method further comprises: S8, performing a second etching opening on the second semiconductor layer to form first semiconductor opening regions that are alternately arranged with and spaced from the second semiconductor opening regions; S9, depositing a conductive film layer on the back surface obtained in S8; S10, performing a third etching opening on a portion of the conductive film layer between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove; S11 , forming a first electrode and a second electrode in the first semiconductor opening region and the second semiconductor opening region respectively.

12. A photovoltaic module, characterized in that: It comprises the back contact cell resistant to light-induced degradation as claimed in any one of claims 1 to 6.

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