High-speed low-dark-current three-stage avalanche photodetector and preparation method thereof

Abstract

The application relates to a high-speed low-dark-current three-stage step structure avalanche photodetector and a preparation method thereof, and belongs to the technical field of semiconductor devices. The intrinsic InGaAs absorption layer 8 and the N-type InAlAs ohmic contact layer 2 are step structures to form a three-stage step structure of the photodetector; the application grows a 210nm-thick SiN x antireflection film with a refractive index of 1.85 on a light incidence surface, so that the reflectivity of incident light is less than 1%. For a 1550nm wavelength optical signal, the single light absorption quantum efficiency can reach 0.45.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor devices, in particular to a high-speed, low-dark-current avalanche photodetector with a three-stage step structure. BACKGROUND

[0002] With the increasing demand for information transmission, there is a higher requirement for the transmission speed and distance of optical communication. As an important receiving device in optical communication, the semiconductor photodetector plays an important role. The main indicators for evaluating the performance of the photodetector include 3dB bandwidth, dark current, responsivity and quantum efficiency, etc.

[0003] Compared with the PIN photodetector, the avalanche photodetector (APD) can improve the sensitivity of the receiver without the need for an amplifier due to its internal gain of the photoelectric current. Therefore, it is more and more applied in optical communication.

[0004] The commonly used high-speed avalanche photodetector adopts a separate absorption charge multiplication structure. In order to improve the response speed of the device, the depletion region length needs to be reduced to reduce the carrier transit time, but the reduction of the absorption region thickness will result in the decrease of the responsivity. In addition, in order to reduce the collision ionization time required for the APD to obtain the same gain, the multiplication layer thickness should be reduced, but when the multiplication layer thickness is reduced, the electric field strength required to trigger collision ionization will increase, which will increase the tunneling current of the multiplication region. Due to the existence of high electric field strength at the edge of the multiplication region, the requirement for the passivation layer is higher, and when the passivation effect is not good, it is easy to introduce leakage current and edge breakdown, which reduces the reliability of the device. Therefore, in order to obtain a high-speed, low-dark-current avalanche photodetector, not only the contradiction between the bandwidth and the responsivity and the dark current needs to be solved, but also a material with better density and electrical insulation needs to be used as the passivation layer. SUMMARY

[0005] Therefore, the purpose of the present application is to overcome the shortcomings and deficiencies of the prior art, optimize the epitaxy, structure and preparation process of the avalanche photodetector, and provide a three-stage step structure avalanche photodetector with high speed and low dark current, so as to obtain a high-speed, low-dark-current avalanche photodetector.

[0006] The present application achieves the above technical effects by adopting the following technical solutions:

[0007] A high-speed low-dark-current three-stage step structure avalanche photodetector, comprising, from bottom to top, an intrinsic InP substrate 1, an N-type InAlAs ohmic contact layer 2, an intrinsic InAlAs transition layer 3, an N-type InAlAs charge layer 4, an intrinsic InAlAs multiplication layer 5, a P-type InAlAs charge layer 6, an intrinsic InAlGaAs transition layer 7, an intrinsic InGaAs absorption layer 8, a gradient-doped P-type InGaAs absorption layer 9, and a P-type InAlAs ohmic contact layer 10;

[0008] The intrinsic InGaAs absorption layer 8 and the N-type InAlAs ohmic contact layer 2 are both step structures to form a three-stage step structure of the photodetector;

[0009] The upper surface of the P-type InAlAs ohmic contact layer 10 is provided with a passivation layer 14; a P electrode passes through the passivation layer 14 and contacts the upper surface of the P-type InAlAs ohmic contact layer 10;

[0010] The passivation layer 14 successively covers the side surface of the P-type InAlAs ohmic contact layer 10, the side surface of the gradient-doped P-type InGaAs absorption layer 9, the side surface and step surface of the intrinsic InGaAs absorption layer 8, the side surface of the intrinsic InAlGaAs transition layer 7, the side surface of the P-type InAlAs charge layer 6, the side surface of the intrinsic InAlAs multiplication layer 5, the side surface of the N-type InAlAs charge layer 4, the side surface of the intrinsic InAlAs transition layer 3, and the side surface and step surface above the step surface of the N-type InAlAs ohmic contact layer 2 from the upper surface of the P-type InAlAs ohmic contact layer 10;

[0011] The N electrode 12 passes through the passivation layer 14 and contacts the step surface of the N-type InAlAs ohmic contact layer 2.

[0012] Further, the P electrode is a circular ring structure.

[0013] Further, the area surrounded by the P electrode serves as an incident window.

[0014] Further, the N electrode 12 is an N electrode window.

[0015] A preparation method of a high-speed low-dark-current three-stage step structure avalanche photodetector, for preparing a high-speed low-dark-current three-stage step structure avalanche photodetector, the specific process being as follows:

[0016] Step 1: using an epitaxial growth process, growing an epitaxial structure of the avalanche photodetector on the intrinsic InP substrate 1;

[0017] Step 2: using a photolithography process, photolithographing a P electrode pattern on the top surface of the epitaxial structure and leaving an incident window 13, and sputtering the P electrode with adhesive; then, using a stripping process to prepare the P electrode 11;

[0018] Step 3, a photolithography process is used to pattern the first level step on the epitaxial structure; a wet etching process is used to etch the epitaxial structure from top to bottom until the intrinsic InGaAs absorption region stops, forming the first level step structure 15;

[0019] Step 4, a photolithography process is used to pattern the second level step on the epitaxial structure, the second level step has a larger radius than the first level step structure; a wet etching process is used to continue etching until the N-type InAlAs ohmic contact layer 2 stops, preparing the second level step structure 16;

[0020] Step 5, a photolithography process is used to pattern the third level step on the epitaxial front surface; a wet etching process is used to etch into the epitaxial substrate until it stops, forming the third level step structure; the etching depth into the epitaxial substrate should be greater than 0.3 μm to form good electrical isolation; the etching of the N-type InAlAs ohmic contact layer 2 uses phosphoric acid etching solution, and the etching of the InP epitaxial substrate uses bromine water etching solution;

[0021] Step 6, a plasma-enhanced chemical vapor deposition process is used to grow 100 nm of SiO2 and 210 nm of SiN x thin film as a passivation layer 14, SiN x also as an anti-reflection film for the incident window 13, the growth temperature is between 200-300 °C;

[0022] Step 7, a photolithography process is used to pattern the N-electrode window 18 and P-electrode window on the epitaxial structure; a wet etching process is used to etch away the SiO2 and SiN x , forming the N-electrode and P-electrode windows;

[0023] Step 8, a photolithography process is used to re-pattern the N-electrode window; Au / Ge / Ni / Au is sputtered with adhesive, and then the N-electrode 12 is peeled off;

[0024] Step 9, a photolithography process is used to pattern the N-electrode lead and P-electrode lead window on the epitaxial structure; Ti / Au is sputtered with adhesive, and then the N-electrode lead 19 and P-electrode lead 20 are peeled off;

[0025] Step 10, a rapid thermal annealing alloying process is used, with a temperature of 390 °C and a time of 40 s, to form a good ohmic contact between the semiconductor device and the metal;

[0026] Step 11, the back surface of the epitaxial structure is thinned and polished;

[0027] Step 12, the epitaxial wafer is cleaved and separated into individual devices.

[0028] Further, the etching liquid used in the step 3 and the step 4 is phosphoric acid etching liquid; the etching liquid selected in the step 7 is BOE etching liquid.

[0029] Compared with the prior art, the technical scheme of the present application has the following beneficial effects:

[0030] 1. The partial-doped InGaAs absorption region solves the contradiction between the APD bandwidth and responsivity. The partial-doped absorption region design can keep the total absorption layer thickness unchanged, i.e. the corresponding quantum efficiency unchanged, and by adjusting the ratio between the p-doped absorption region and the intrinsic absorption region, the carrier transit time required in the absorption region is minimized, thereby improving the device bandwidth. The absorption region is designed as a 0.3 μm p-type gradient-doped region and a 0.3 μm intrinsic region, with a total thickness of 0.6 μm. A 210 nm thick SiN x antireflection film with a refractive index of 1.85 is grown on the light incidence surface, which can make the reflectivity of the incident light less than 1%. For a 1550 nm wavelength optical signal, the single light absorption quantum efficiency can reach 0.45.

[0031] 2. The SAGCMCT structure can reduce the device capacitance while keeping the original carrier transit time unchanged, thereby improving the APD bandwidth. Since the electron collision ionization coefficient in InAlAs material is greater than that of the hole, in order to reduce the excess noise, the photo-generated electron injection multiplication region is used to trigger avalanche multiplication. The multiplied electrons generated by collision ionization drift to the N-type charge layer and the transit layer, while the multiplied holes drift to the P-type charge layer, the transition layer and the absorption layer; in the case of keeping the original absorption layer, transition layer, P-type charge layer and multiplication layer thickness unchanged, a 0.3 μm thick transit layer and a 70 nm thick N-type charge layer are used, so that the transit time of the multiplied electrons is less than that of the multiplied holes, i.e. the total transit time of the carriers remains unchanged. Moreover, the newly added N-type charge and transit layer can increase the thickness of the depletion region, thereby reducing the device capacitance and improving the bandwidth.

[0032] 3. The 0.12 μm thick InAlAs material is used as the multiplication region, which can improve the APD bandwidth while reducing the generation of tunneling current. The thinner the multiplication layer thickness, the shorter the time required for collision ionization to obtain the same gain, thereby improving the APD bandwidth, but the tunneling current of the multiplication region will also increase accordingly. Using a 0.12 μm thick InAlAs as the multiplication layer can reduce the collision ionization time while limiting the tunneling dark current before breakdown to within 0.5 μA.

[0033] 4. The PECVD process is used to grow SiO2 and SiN x as double passivation layers, instead of the traditional SiO2 and SiN xCompared with single passivation layer, the edge leakage current of APD mesa is effectively reduced, and the dark current of prepared APD is lower than 10nA at 0.9 times of breakdown voltage, which is far lower than that of the same type of high-speed avalanche photodetector.

[0034] 5. By using the three-step structure, the edge electric field intensity of the multiplication region is reduced. When the central electric field intensity of the multiplication layer is 770kV / cm, the edge electric field intensity of the multiplication layer is reduced to below 650kV / cm, which greatly reduces the edge leakage current, suppresses the occurrence of edge breakdown, and improves the reliability of the APD.

[0035] The SAGCMCT-APD prepared by the above technical scheme greatly reduces the dark current while improving the bandwidth of the device, so that the APD has excellent performance. The 3dB bandwidth is about 20GHz at 5 times of gain, and the dark current is 6.7nA at 0.9 times of breakdown voltage. The device is expected to be applied to high-speed and high-sensitivity optical communication receivers of 25Gbps. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 is a schematic diagram of the cross section of a three-step structure avalanche photodetector chip with high speed and low dark current.

[0037] Figure 2 is a schematic diagram of the structure of N mesa in the APD chip Figure 1 is a top view of the APD chip).

[0038] Figure 3 is a schematic diagram of the front structure of the APD chip.

[0039] In the figure: 1, intrinsic InP substrate; 2, N-type InAlAs ohmic contact layer; 3, intrinsic InAlAs transition layer; 4, N-type InAlAs charge layer; 5, intrinsic InAlAs multiplication layer; 6, P-type InAlAs charge layer; 7, intrinsic InAlGaAs transition layer; 8, intrinsic InGaAs absorption layer; 9, gradient-doped P-type InGaAs absorption layer; 10, P-type InAlAs ohmic contact layer; 11, P electrode, which is a circular ring structure; 12, N electrode; 13, incident window; 14, passivation layer. 11, P electrode, which is a circular ring structure; 13, incident window; 15, first step; 16, second step; 17, third step, i.e. N mesa; 18, N electrode window. 13, incident window; 15, first step; 16, second step; 17, third step, i.e. N mesa; 19, N electrode lead; 20, P electrode lead. DETAILED DESCRIPTION

[0040] In the following, the application will be further described in conjunction with the drawings.

[0041] The various performances of high-speed and low-dark-current avalanche photodetector are mutually restricted. The following problems need to be solved:

[0042] The contradiction between the bandwidth and the responsivity under unit gain. In order to improve the responsivity of the avalanche photodetector under unit gain, the thickness of the intrinsic absorption layer is usually increased. However, after the intrinsic absorption region is completely depleted, the carrier transit time is prolonged, which affects the 3dB bandwidth of the device.

[0043] The contradiction between the bandwidth and the dark current. The collision ionization time of the photo-generated carriers in the multiplication region increases with the increase of the gain. At high gain, the collision ionization time gradually becomes the main factor limiting the 3dB bandwidth of the device. For the same semiconductor material, the thinner the multiplication layer, the smaller the collision ionization time when the same gain is obtained, but the higher the electric field strength required for collision ionization, and the tunneling dark current will also increase.

[0044] The high-speed APD can improve the bandwidth by reducing the active area and thus reducing the device capacitance, so the mesa structure is usually adopted. However, in the commonly used mesa structure, the leakage current caused by defects and impurities at the edge of the multiplication layer will increase with the increase of the electric field strength, and edge breakdown is also easy to occur, which reduces the reliability of the device. Therefore, it is crucial to grow a passivation layer with good density and electrical insulation at the edge of the multiplication layer of the mesa structure device to reduce the electric field strength.

[0045] The purpose of the present application is to overcome the shortcomings and deficiencies of the prior art, optimize the epitaxy, structure and preparation process of the avalanche photodetector, and thus obtain a high-speed and low-dark-current avalanche photodetector.

[0046] In the first aspect, in order to solve the contradiction between the bandwidth and the responsivity under unit gain, a partially doped InGaAs absorption region is adopted, which includes a 0.3μm thick P-type doped absorption region and a 0.3μm thick intrinsic absorption region. The P-type doped absorption region adopts a gradient doping of 3 layers with a thickness of 0.1μm and a doping concentration of 2.0×10 18 cm -3 , 1.4×10 18 cm -3 , 8.0×10 17 cm -3 , respectively. In addition, a 210nm thick SiN x film with a refractive index of 1.85 is grown as an antireflection film at the light incident window.

[0047] Further, in order to improve the bandwidth of the APD, a new n-type charge layer and an intrinsic transit layer are added to the epitaxy of the APD on the basis of the separated absorption, transition, charge, multiplication structure, that is, a separated absorption, transition, charge (P-type doping), multiplication, charge (N-type doping), transit structure (SAGCMCT) is adopted. The transition layer adopts an intrinsic In0.53 Ga 0.35 Al 0.12 As、In 0.53 Ga 0.23 Al 0.24 As and In 0.52 Ga 0.12 Al 0.36 Materials: Both charge layers are made of 70nm thick InAlAs material, and the P-type charge layer doping concentration is 5.7×10 17 cm -3 , the doping concentration of the N-type charge layer is 5.0×10 17 cm -3 ; The transition layer uses 0.3μm intrinsic InAlAs material.

[0048] Furthermore, to address the trade-off between bandwidth and dark current, we used 0.12μm intrinsic InAlAs as the multiplication layer. Because InAlAs is lattice-matched to the InGaAs absorber material required for optical communications, it can mitigate the increase in dark current caused by lattice mismatch. Compared to InP, InAlAs has a lower impact ionization rate, k, which reduces the excess noise of the APD.

[0049] Furthermore, in order to reduce the edge leakage current of the APD mesa, 100nm thick SiO2 and 210nm thick SiN were grown on the surface of the APD chip using plasma enhanced chemical vapor deposition (PECVD) technology. x The growth temperature is between 200℃-300℃ to provide better electrical insulation.

[0050] Furthermore, to reduce the electric field strength at the edge of the multiplication layer, a three-step APD structure is used. The first step is etched into the intrinsic absorption layer, which can limit the active area of ​​the device; the second step is etched into the n-ohmic contact layer, which can reduce the electric field strength on the surface of the multiplication layer; and the third step is etched into the insulating substrate, which acts as an electrical isolation.

[0051] The cross-sectional structure of the high-speed, low dark current three-step structure avalanche photodetector chip in this embodiment is as follows: Figure 1 As shown; this embodiment includes, stacked from bottom to top, an intrinsic InP substrate 1, an N-type InAlAs ohmic contact layer 2, an intrinsic InAlAs transition layer 3, an N-type InAlAs charge layer 4, an intrinsic InAlAs multiplication layer 5, a P-type InAlAs charge layer 6, an intrinsic InAlGaAs transition layer 7, an intrinsic InGaAs absorption layer 8, a gradient-doped P-type InGaAs absorption layer 9, and a P-type InAlAs ohmic contact layer 10;

[0052] The intrinsic InGaAs absorption layer 8 and the N-type InAlAs ohmic contact layer 2 are step structures to form a three-step structure of the photodetector;

[0053] The upper surface of the P-type InAlAs ohmic contact layer 10 is provided with a passivation layer 14; the P electrode contacts the upper surface of the P-type InAlAs ohmic contact layer 10 through the passivation layer 14;

[0054] The passivation layer 14 covers the side surface of the P-type InAlAs ohmic contact layer 10, the side surface of the gradient-doped P-type InGaAs absorption layer 9, the side surface and step surface of the intrinsic InGaAs absorption layer 8, the side surface of the intrinsic InAlGaAs transition layer 7, the side surface of the P-type InAlAs charge layer 6, the side surface of the intrinsic InAlAs multiplication layer 5, the side surface of the N-type InAlAs charge layer 4, the side surface of the intrinsic InAlAs transition layer 3, and the side surface and step surface above the step surface of the N-type InAlAs ohmic contact layer 2 in sequence from the upper surface of the P-type InAlAs ohmic contact layer 10;

[0055] The N electrode 12 contacts the step surface of the N-type InAlAs ohmic contact layer 2 through the passivation layer 14.

[0056] The P electrode is a circular ring structure. The area surrounded by the P electrode serves as an incident window. The N electrode 12 is an N electrode window.

[0057] The specific preparation method of the detector chip comprises the following steps:

[0058] 1) An epitaxial growth process is adopted to grow the epitaxial structure 2-10 of the avalanche photodetector on the intrinsic InP substrate 1; wherein the transition layer 3 is 0.3 μm, the multiplication layer 5 is 0.12 μm, and the intrinsic absorption layer 8 and the gradient-doped P-type absorption layer 9 are both 0.3 μm.

[0059] 2) A photolithography process is adopted to photoetch the P electrode pattern on the epitaxial front surface; the P electrode is a circular ring structure, leaving an incident window 13; the P electrode is sputtered with glue, and the material is Ti / Au; and a stripping process is adopted to prepare the P electrode 11.

[0060] 3) A photolithography process is adopted to photoetch the first step pattern on the epitaxial front surface; a wet etching process is adopted to etch the epitaxial material outside the first step until the center of the intrinsic InGaAs absorption zone 8 stops, forming the first step 15, and the etching liquid is phosphoric acid etching liquid.

[0061] 4) A photolithography process is adopted to photoetch the second step pattern on the epitaxial front surface, and the radius of the pattern is slightly larger than that of the first step; a wet etching process is adopted to etch until the N-type InAlAs ohmic contact layer 2 stops, preparing the second step 16, and the etching liquid is phosphoric acid etching liquid.

[0062] 5) Using photolithography process, the third step pattern is photoetched on the epitaxial front surface; using wet etching process, the etching into the epitaxial substrate 1 is stopped, forming the third step, i.e. N step 17. The etching depth into the epitaxial substrate 1 should be greater than 0.3 μm, so as to form good electrical isolation; wherein, phosphoric acid etching solution is used for etching N-type InAlAs ohmic contact layer 2, and bromine water etching solution is used for etching InP epitaxial substrate 1.

[0063] 6) Using plasma enhanced chemical vapor deposition process, 100 nm SiO2 and 210 nm SiN x thin film with refractive index of 1.85 are grown on the epitaxial front surface as passivation layer 14 and antireflection film of incident window 13, respectively, and the growth temperature is between 200℃ and 300℃. x

[0064] 7) Using photolithography process, N electrode window 18 and P electrode window pattern are photoetched on the epitaxial front surface; using wet etching process, SiO2 and SiN x are etched away at the electrode window, forming N electrode and P electrode window; and BOE etching solution is used.

[0065] 8) Using photolithography process, N electrode window is re-etched; Au / Ge / Ni / Au is sputtered with adhesive, and then N electrode 12 is peeled off.

[0066] 9) Using photolithography process, N electrode lead and P electrode lead window are photoetched on the epitaxial front surface; Ti / Au is sputtered with adhesive, and then N electrode lead 19 and P electrode lead 20 are peeled off.

[0067] 10) Using rapid annealing alloying process, temperature 390℃, time 40s, good ohmic contact is formed between the semiconductor device and the metal.

[0068] 11) The epitaxial back surface is thinned and polished.

[0069] 12) The epitaxial wafer is cleaved and divided into independent devices.

[0070] Thus, the preparation of the high-speed, low-dark-current three-step structure avalanche photodetector is completed.

[0071] The present application adopts partial doping absorption region, 0.12 μm InAlAs multiplication region, and SiO2 and SiN x grown by PECVD as double passivation layer, so as to prepare three-step structure SAGCMCT-APD, which can improve the device bandwidth and greatly reduce the dark current, and thus the APD has excellent performance.

[0072] ​While embodiments of the application have been shown and described, it is to be understood that the embodiments described are merely exemplary of the principles and application of the present application. Numerous modifications and adaptions can be effected without departing from the spirit and scope of the present application, which is not limited to the exact construction and arrangement described. It is intended, therefore, to cover all modifications and adaptions that fall within the scope of the claims and their equivalents.

Claims

1. A high-speed, low-dark-current three-step-structure avalanche photodetector, characterized in that: The invention comprises an intrinsic InP substrate (1), an N-type InAlAs ohmic contact layer (2), an intrinsic InAlAs transition layer (3), an N-type InAlAs charge layer (4), an intrinsic InAlAs multiplication layer (5), a P-type InAlAs charge layer (6), an intrinsic InAlGaAs transition layer (7), an intrinsic InGaAs absorption layer (8), a gradient-doped P-type InGaAs absorption layer (9) and a P-type InAlAs ohmic contact layer (10) stacked from bottom to top; The intrinsic InGaAs absorption layer (8) and the N-type InAlAs ohmic contact layer (2) are both step structures to form a three-level step structure of the photodetector; A passivation layer (14) is provided on the upper surface of the P-type InAlAs ohmic contact layer (10); the P electrode passes through the passivation layer (14) and contacts the upper surface of the P-type InAlAs ohmic contact layer (10); The passivation layer (14) sequentially covers, from the upper surface of the P-type InAlAs ohmic contact layer (10), the side surface of the P-type InAlAs ohmic contact layer (10), the side surface of the gradient-doped P-type InGaAs absorption layer (9), the side surface and step surface of the intrinsic InGaAs absorption layer (8), the side surface of the intrinsic InAlGaAs transition layer (7), the side surface of the P-type InAlAs charge layer (6), the side surface of the intrinsic InAlAs multiplication layer (5), the side surface of the N-type InAlAs charge layer (4), the side surface of the intrinsic InAlAs transition layer (3), and the side surface and step surface above the step surface of the N-type InAlAs ohmic contact layer (2); The N electrode (12) passes through the passivation layer (14) and contacts the step surface of the N-type InAlAs ohmic contact layer (2); Using plasma enhanced chemical vapor deposition process, 100nm SiO2 and 210nm thick SiN with a refractive index of 1.85 are grown on the epitaxial structure. x Thin film, passivation layer (14), SiN x At the same time, it serves as an antireflection film for the incident window (13), and its growth temperature is between 200°C and 300°C.

2. The high-speed, low-dark-current three-step-structure avalanche photodetector according to claim 1, characterized in that: The P electrode is a circular ring structure.

3. The high-speed, low-dark-current three-step-structure avalanche photodetector according to claim 2, characterized in that: The area surrounded by the P electrode serves as an incident window.

4. The high-speed, low-dark-current three-step-structure avalanche photodetector according to claim 1, characterized in that: The N electrode (12) is located in the N electrode window.

5. The high-speed, low-dark-current three-step-structure avalanche photodetector according to claim 1, characterized in that: The N-type InAlAs ohmic contact layer comprises a stacked and integrally designed step upper portion and a step lower portion; the horizontal cross-sections of the step upper portion and the step lower portion both comprise a semicircle and a rectangle; the long side of the rectangle coincides with the diameter of the semicircle; the step surface of the N-type InAlAs ohmic contact layer (2) is a portion of the upper surface of the step lower portion; The cross section of the intrinsic InGaAs absorption layer is circular.

6. A method for preparing a high-speed, low-dark-current, three-step-structure avalanche photodetector, for preparing the high-speed, low-dark-current, three-step-structure avalanche photodetector according to any one of claims 1 to 5, wherein the specific process is as follows: Step 1, using an epitaxial growth process to grow an epitaxial structure of an avalanche photodetector on an intrinsic InP substrate (1); Step 2: using a photolithography process to photolithographically pattern a P electrode on the top surface of the epitaxial structure, leaving an incident window (13), and sputtering a P electrode with a glue; then, using a lift-off process to prepare a P electrode (11); Step 3, using a photolithography process to photoetch a first-level step pattern on the epitaxial structure; using a wet etching process to etch the epitaxial structure portion of the first step from top to bottom until the intrinsic InGaAs absorption region stops, forming a first-level step structure (15); Step 4, using a photolithography process to photoetch a second-level step pattern on the epitaxial structure, wherein the radius of the second-level step pattern is larger than that of the first-level step structure; using a wet etching process, continuing to etch until the N-type InAlAs ohmic contact layer (2) stops, thereby preparing a second-level step structure (16); Step 5: Use photolithography to pattern the third step on the front side of the epitaxial layer; use wet etching to etch into the intrinsic InP substrate and stop, forming a third step structure; the depth of etching into the epitaxial substrate should be greater than 0.3 μm to form good electrical isolation; wherein, Phosphoric acid etching solution is used to etch the N-type InAlAs ohmic contact layer (2), and bromine water etching solution is used to etch the intrinsic InP substrate; Step 6: Using plasma enhanced chemical vapor deposition process, grow 100nm of SiO2 and 210nm thick SiN with a refractive index of 1.85 on the epitaxial structure. x Thin film, passivation layer (14), SiN x At the same time, the antireflection film used as the incident window (13) has a growth temperature between 200°C and 300°C; Step 7, using photolithography process, photolithography N electrode window (18) and P electrode window pattern on the epitaxial structure; using wet etching process, etching away SiO2 and SiN at the electrode window x , forming an N-electrode window and a P-electrode window; Step 8: Use photolithography to re-etch the N electrode window; sputter Au / Ge / Ni / Au with glue, and then peel off the N electrode (12); Step 9, using a photolithography process, photolithography the N electrode lead window and the P electrode lead window in the epitaxial structure; sputtering Ti / Au with glue, and then peeling off the N electrode lead (19) and the P electrode lead (20); Step 10: Rapid annealing of the alloy at 390° C. for 40 seconds to form a good ohmic contact between the semiconductor device and the metal. Step 11, thinning and polishing the back side of the epitaxial structure; Step 12: cleave the epitaxial wafer and separate it into independent devices.

7. The method for preparing a high-speed, low-dark-current three-step-structure avalanche photodetector according to claim 6, characterized in that: The etching solution used in step 3 and step 4 is phosphoric acid etching solution; the etching solution selected in step 7 is BOE etching solution.

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