Inverter pulse insulation test device

Abstract

The inverter pulse insulation test device comprises a pulse generation circuit and a surge voltage generation circuit. The pulse generation circuit outputs a voltage having an analog drive voltage waveform including intermittent pulses. The surge voltage generation circuit generates a surge voltage at a rising portion and a falling portion of each pulse of the drive voltage waveform to change the drive voltage waveform, and outputs a voltage having the changed drive voltage waveform. The surge voltage generation circuit includes a variable resistor and a variable inductor connected in series with each other, and a capacitance variable capacitor.

Description

Technical Field

[0001] The present invention relates to an inverter pulse insulation test device. Background Art

[0002] Patent document 1 discloses an insulation inspection device and an insulation inspection method for an inverter-driven motor. Patent document 2 discloses an inverter-driven rotating electrical machine (particularly an inverter-driven rotating electrical machine with a rated voltage of 700 Vrms or less), and a phase-to-phase insulation partial discharge inspection method and a phase-to-phase insulation partial discharge inspection device for the rotating electrical machine. Patent document 3 discloses a method for performing a discharge resistance test on the windings of a multi-channel variable frequency motor. Patent document 4 discloses a method for performing a discharge resistance test on the windings of an inverter-driven motor.

[0003] [Prior art literature]

[0004] [Patent Document]

[0005] Patent Document 1: International Publication No. 2014 / 083866

[0006] Patent Document 2: International Publication No. 2012 / 147163

[0007] Patent Document 3: Chinese Patent No. 106226663

[0008] Patent Document 4: China Utility Model No. 204439681 Summary of the invention

[0009] [Problems to be solved by the invention]

[0010] In recent years, from the perspective of energy saving, variable speed drive of electric motors using inverters has become popular. For example, in the automotive industry, from the perspective of global warming and environmental issues, reducing CO2 emissions has become a topic. Therefore, the conversion from the previous engine drive to inverter motor drive, that is, from gasoline vehicles and diesel vehicles to electric vehicles (Electric Vehicles, EV), hybrid vehicles (Hybrid Electric Vehicles, HEV), plug-in hybrid electric vehicles (Plug-in Hybrid Electric Vehicles, PHEV) and fuel cell vehicles (Fuel Cell Vehicles, FCV) is being promoted. Moreover, with the main purpose of increasing the output of the motor, the motor drive voltage is being promoted to a higher voltage (for example, 600V or more). This trend is not limited to the automotive industry, but also applies to other industries.

[0011] In the control of inverter-driven motors, pulse control methods such as pulse width modulation (PWM) control methods are widely used. In the pulse control method, voltage pulses are generated by high-speed switching of power devices. However, surge voltages are generated in the rising and falling parts of the voltage pulses due to the inductance of the wiring from the power device to the motor. If the surge voltage becomes too large, local discharges occur in the windings of the motor, and the insulation performance of the resin covering the windings deteriorates. If the thickness of the insulating coating of the windings is increased in order to suppress local discharges, the motor will be enlarged. In addition, the higher the carrier frequency of the pulse control, the higher the frequency of local discharges, and the earlier the insulation performance deteriorates. Therefore, it is ideal to correctly test and evaluate the degree of deterioration of insulating components such as the insulating coating of the windings caused by the surge voltage contained in the voltage pulses.

[0012] An object of the present disclosure is to provide an inverter pulse insulation test device that can accurately test and evaluate the degree of deterioration of an insulation component caused by a surge voltage included in a voltage pulse.

[0013] [Technical means to solve the problem]

[0014] One aspect of the present disclosure is an inverter pulse insulation test device. The inverter pulse insulation test device includes a pulse generating circuit and a surge voltage generating circuit. The pulse generating circuit has a first output terminal, and a voltage having a simulated driving voltage waveform including intermittent pulses is output from the first output terminal. The surge voltage generating circuit has an input terminal electrically connected to the first output terminal of the pulse generating circuit and a second output terminal connected to a motor as a test object. The surge voltage generating circuit generates a surge voltage in the rising part and the falling part of each pulse of the driving voltage waveform input from the input terminal to change the driving voltage waveform, and outputs a voltage having the changed driving voltage waveform from the second output terminal. The surge voltage generating circuit has a variable resistor and a variable inductor connected in series with each other, and a variable capacitor. One end of the series circuit of the variable resistor and the variable inductor constitutes the input end of the surge voltage generating circuit. The other end of the series circuit is connected to the second output end of the surge voltage generating circuit. One end of the variable capacitor is connected to a node between the other end of the series circuit and the second output end. The other end of the variable capacitor is connected to a constant potential line.

[0015] According to the above device, the degree of deterioration of the insulating member caused by the surge voltage included in the voltage pulse can be accurately tested and evaluated.

[0016] In the device, the pulse generating circuit can output a voltage having a two-level or three-level inverter driving waveform as a driving voltage waveform. The pulse generating circuit can have a first semiconductor switch, a second semiconductor switch, a bridge full-wave rectifier and a third semiconductor switch. One end of the first semiconductor switch is connected to the positive voltage terminal, and the other end of the first semiconductor switch is connected to the first output terminal. One end of the second semiconductor switch is connected to the negative voltage terminal, and the other end of the second semiconductor switch is connected to the first output terminal. The bridge full-wave rectifier has two input terminals and two output terminals, one of the two input terminals is connected to the reference potential line, and one of the two output terminals is connected to the first output terminal. One end of the third semiconductor switch is connected to the other input terminal of the bridge full-wave rectifier, and the other end of the third semiconductor switch is connected to the other output terminal of the bridge full-wave rectifier.

[0017] In the device, the pulse generating circuit may include: a plurality of semiconductor switches for forming a driving voltage waveform; and a first control unit for generating a plurality of light trigger signals for controlling the plurality of semiconductor switches respectively. Furthermore, the first control unit provides each of the plurality of light trigger signals to each of the plurality of semiconductor switches.

[0018] The device may also include a second control unit and an input operation unit. The second control unit controls the driving voltage waveform in the pulse generating circuit. The input operation unit receives an input operation related to the number of intermittent pulses, and provides information related to the number of intermittent pulses input by the input operation to the second control unit. Moreover, the second control unit may determine the number of intermittent pulses based on the information.

[0019] The device may also include a second control unit and an input operation unit. The second control unit controls the driving voltage waveform in the pulse generating circuit. The input operation unit receives an input operation related to the driving voltage waveform, and provides the information related to the driving voltage waveform input by the input operation to the second control unit. The second control unit may determine the driving voltage waveform based on the information. The information related to the driving voltage waveform may include at least one of the following information: information related to whether the intermittent pulses only contain positive polarity pulses, or only contain negative polarity pulses, or contain both positive polarity pulses and negative polarity pulses; information related to whether the intermittent pulses are continuously output before the end of the test, or are output suddenly within a predetermined period; information related to the amplitude of the intermittent pulses; information related to the frequency of the intermittent pulses; information related to the time width of each pulse constituting the intermittent pulses.

[0020] [Effects of the Invention]

[0021] According to the present disclosure, it is possible to provide an inverter pulse insulation test device that can accurately test and evaluate the degree of deterioration of the insulation coating of a winding caused by a surge voltage included in a voltage pulse. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram showing the structure of an inverter pulse insulation test device according to one embodiment.

[0023] Figure 2 This is a circuit diagram showing a configuration example of a pulse generating circuit.

[0024] Figure 3 : is a circuit diagram showing a configuration example of a surge voltage generating circuit.

[0025] Figure 4 : is a circuit diagram showing another configuration example of the surge voltage generating circuit.

[0026] Figure 5 This is a circuit diagram showing still another configuration example of the surge voltage generating circuit.

[0027] Figure 6 Parts (a), (b), and (c) of FIG. 1 are diagrams schematically showing a voltage pulse of positive polarity including a surge voltage output from a surge voltage generating circuit.

[0028] Figure 7 FIG. 1 is a diagram schematically showing an example of a driving voltage waveform including bipolarities of a surge voltage.

[0029] Figure 8 It is a diagram schematically showing an example of a driving voltage waveform including a surge voltage.

[0030] Fig. 9 It is a diagram schematically showing an example of a driving voltage waveform including a surge voltage.

[0031] Fig.10 It is a diagram schematically showing an example of a driving voltage waveform including a surge voltage.

[0032] Fig.11 It is a diagram schematically showing an example of a driving voltage waveform including a surge voltage.

[0033] Fig.12 It is a diagram schematically showing an example of a driving voltage waveform that does not include a surge voltage.

[0034] Fig.13 It is a diagram schematically showing an example of a driving voltage waveform that does not include a surge voltage.

[0035] Fig.14 It is a diagram schematically showing an example of a driving voltage waveform including a surge voltage.

[0036] Fig.15 Parts (a) to (e) of FIG. 1 are diagrams showing driving voltage waveforms including surge voltages actually measured in a test device.

[0037] Fig.16 Parts (a) to (e) of FIG. 1 are diagrams showing driving voltage waveforms actually measured in a test device.

[0038] Fig.17 This is a block diagram showing an example of the system configuration of a test apparatus according to one embodiment.

[0039] Fig.18 It is a diagram showing an example of a two-level PWM drive waveform.

[0040] Fig.19 It is a diagram showing an example of a three-level PWM drive waveform.

[0041] Fig. 20 Part (a) schematically shows a rectangular wave before a surge voltage is generated. Fig. 20 Part (b) schematically shows a rectangular wave after a surge voltage is generated. DETAILED DESCRIPTION

[0042] Hereinafter, a specific example of the inverter pulse insulation test device disclosed in the present invention will be described with reference to the drawings. In addition, the present invention is not limited to these examples, but is shown by the claims, and is intended to include all changes within the meaning and scope equivalent to the claims. In the following description, the same symbols are marked on the same parts in the description of the drawings, and repeated descriptions are omitted.

[0043] Figure 1 The present invention is a schematic diagram showing the structure of an inverter pulse insulation test device (hereinafter referred to as the test device) 1 according to an embodiment. The test device 1 is used, for example, to perform insulation evaluation of an inverter drive motor and windings, insulating coating resins, and insulating parts used therein. Alternatively, the test device 1 is used for insulation evaluation of electromagnetic wires, insulation evaluation of surface insulating coatings of electromagnetic wires, etc., insulation evaluation of electrical parts, etc., and life evaluation and Vt tests thereof. Figure 1 As shown, the test device 1 of the present embodiment includes a pulse generating circuit 10 and a surge voltage generating circuit 20 .

[0044] The pulse generating circuit 10 has an output terminal 10b (first output terminal), and outputs a voltage having a simulated driving voltage waveform including intermittent voltage pulses from the output terminal 10b. The driving voltage waveform includes, for example, a one-level, two-level, or three-level inverter driving waveform to simulate, for example, pulse width modulation (PWM) control.

[0045] Figure 2 : is a circuit diagram showing a configuration example of the pulse generating circuit 10 . Figure 2 The pulse generating circuit 10 shown has a positive polarity DC power supply V1, a negative polarity DC power supply V2, resistors Rp1 and Rp2, capacitors C1 and C2, and discharge resistors Rd1 and Rd2. Furthermore, the pulse generating circuit 10 has a plurality of (three in the example shown) semiconductor switches HVS1, HVS2, and HVS3 for forming a drive voltage waveform, and a bridge full-wave rectifier BR1.

[0046] The positive polarity DC power supply V1 and the negative polarity DC power supply V2 constitute the power supply unit of the pulse generating circuit 10. The positive polarity DC power supply V1 and the negative polarity DC power supply V2 are connected in series with each other. The node N3 between the positive polarity DC power supply V1 and the negative polarity DC power supply V2 is connected to the reference potential line GND and is defined as the reference potential (0V). The end of the positive polarity DC power supply V1 opposite to the reference potential is set as the positive high voltage terminal 11 (+HV). The end of the negative polarity DC power supply V2 opposite to the reference potential is set as the negative high voltage terminal 12 (-HV). In one example, the absolute value of the potential of the positive high voltage terminal 11 is equal to the absolute value of the potential of the negative high voltage terminal 12.

[0047] Capacitor C1 and capacitor C2 constitute the energy storage unit of the pulse generating circuit 10. Capacitor C1 and capacitor C2 are connected in series with each other. The node between capacitor C1 and capacitor C2 is connected to the reference potential line GND and is defined as the reference potential (0V). One end of capacitor C1 opposite to the reference potential is connected to node N1. Node N1 is connected to the positive high voltage terminal 11 via resistor Rp1. One end of capacitor C2 opposite to the reference potential is connected to node N2. Node N2 is connected to the negative high voltage terminal 12 via resistor Rp2. Capacitor C1 stores positive energy. Capacitor C2 stores negative energy. The smaller the inductive component of capacitor C1 and capacitor C2, the better.

[0048] The discharge resistor Rd1 and the discharge resistor Rd2 are connected in series with each other. The node between the discharge resistor Rd1 and the discharge resistor Rd2 is connected to the reference potential line GND and is defined as the reference potential (0V). One end of the discharge resistor Rd1 opposite to the reference potential is connected to the node N1. One end of the discharge resistor Rd2 opposite to the reference potential is connected to the node N2. In other words, the discharge resistor Rd1 is connected in parallel with the capacitor C1, and the discharge resistor Rd2 is connected in parallel with the capacitor C2.

[0049] The semiconductor switch HVS1, the semiconductor switch HVS2 and the semiconductor switch HVS3 constitute the semiconductor switch portion of the pulse generating circuit 10. The semiconductor switch HVS1, the semiconductor switch HVS2 and the semiconductor switch HVS3 are, for example, field effect transistors (FETs) including SiC-based semiconductors. The semiconductor switch HVS1 is the first semiconductor switch in this embodiment. One end of the semiconductor switch HVS1 is connected to the node N1 and is connected to the positive high voltage terminal 11 via the resistor Rp1. The resistor Rp1 is a charging protection resistor. The other end of the semiconductor switch HVS1 is connected to the output terminal 10b via the resistor Rs1 which is a non-inductive protection resistor. The resistor Rs1 protects the semiconductor switch HVS1 in such a way that the output current of the semiconductor switch HVS1 does not exceed the maximum rated current of the semiconductor switch HVS1. The semiconductor switch HVS1 outputs a voltage pulse of positive polarity.

[0050] The semiconductor switch HVS2 is the second semiconductor switch in this embodiment. One end of the semiconductor switch HVS2 is connected to the negative high voltage terminal 12 via a resistor Rp2. The resistor Rp2 is a charging protection resistor. The other end of the semiconductor switch HVS2 is connected to the output terminal 10b via a resistor Rs2 as a non-inductive protection resistor. The resistor Rs2 protects the semiconductor switch HVS2 in a manner that the output current of the semiconductor switch HVS2 does not exceed the maximum rated current of the semiconductor switch HVS2. The semiconductor switch HVS2 outputs a voltage pulse of negative polarity. The semiconductor switch HVS2 is controlled not to be turned on at the same time as the semiconductor switch HVS1.

[0051] The bridge full-wave rectifier BR1 has two input terminals and two output terminals. One of the two input terminals of the bridge full-wave rectifier BR1 is connected to the reference potential line GND and is connected to the node N3 between the positive polarity DC power supply V1 and the negative polarity DC power supply V2. One of the two output terminals of the bridge full-wave rectifier BR1 is connected to the output terminal 10b via the resistor Rs3 as a non-inductive protection resistor. The resistor Rs3 protects the semiconductor switch HVS3 in such a way that the output current of the semiconductor switch HVS3 does not exceed the maximum rated current of the semiconductor switch HVS3.

[0052] The resistors Rs1, Rs2, and Rs3 constitute a protection unit of the pulse generating circuit 10. Since the resistors Rs1, Rs2, and Rs3 are non-inductive resistors, the driving voltage waveform that does not include a surge voltage is output (see Fig.12 and Fig.13 ), the overshoot voltage generated in the voltage pulse can be suppressed.

[0053] The semiconductor switch HVS3 is a third semiconductor switch in this embodiment. One end of the semiconductor switch HVS3 is connected to the other input end of the bridge full-wave rectifier BR1. The other end of the semiconductor switch HVS3 is connected to the other output end of the bridge full-wave rectifier BR1. The semiconductor switch HVS3 advances the falling time of the positive polarity voltage pulse and the negative polarity voltage pulse, and restores these voltage pulses to the reference potential at a high speed.

[0054] Refer again Figure 1 . The surge voltage generating circuit 20 has: an input terminal 20a, which is electrically connected to the output terminal 10b of the pulse generating circuit 10; and an output terminal 20b (a second output terminal), which is connected to the output terminal 13 of the test device 1. The surge voltage generating circuit 20 is a waveform adjustment unit, and causes the rectangular wave input from the input terminal 20a, i.e., the driving voltage waveform, to resonate and vibrate through a resistor inductor capacitor (RLC) circuit. As a result, the surge voltage generating circuit 20 generates a surge voltage at the rising and falling parts of each voltage pulse of the driving voltage waveform to change the driving voltage waveform, and outputs a voltage having the changed driving voltage waveform from the output terminal 20b. In addition, the surge voltage generating circuit 20 can freely change the resonance condition by making the resistance value, inductance and capacitance value of the RLC circuit variable.

[0055] A current sensor 41 is provided in the wiring between the output terminal 20b of the surge voltage generating circuit 20 and the output terminal 13 of the test device 1. The current sensor 41 measures the magnitude of the current output from the output terminal 20b. The current sensor 41 has, for example, a current transformer type, a Hall element type, or a resistor type. A high voltage probe 42 for measuring the voltage waveform is connected to the node between the output terminal 20b of the surge voltage generating circuit 20 and the output terminal 13 of the test device 1. In order to accurately adjust the driving voltage waveform including the surge voltage, it is desirable that the high voltage probe 42 has high accuracy and high speed. As the high voltage probe 42, for example, a high voltage probe of model EP-50K (voltage division ratio 1 / 2000) manufactured by Nissin Pulse Electronics Co., Ltd. can be used. Alternatively, for example, a high voltage probe of model EP-100K (voltage division ratio 1 / 5000) manufactured by Nissin Pulse Electronics Co., Ltd. can be used. The current sensor 41 and the high voltage probe 42 constitute the measuring section of the test device 1. The output signals of the current sensor 41 and the high voltage probe 42 are provided to the oscilloscope 43 and displayed in real time.

[0056] The test object M is connected between the output terminal 13 of the test device 1 and the reference potential line GND. Figure 1 In FIG. 1 , the test object M is schematically shown by a capacitor symbol. The test object M is, for example, a coating resin included in a winding of a motor.

[0057] Figure 3 2 is a circuit diagram showing a surge voltage generating circuit 20A as a configuration example of the surge voltage generating circuit 20 . Figure 3 The surge voltage generating circuit 20A shown has a series circuit 21A and a variable capacitance capacitor section 22A. The series circuit 21A includes a variable resistor section 23A and a variable inductor section 24A connected in series with each other. One end of the series circuit 21A constitutes the input terminal 20a of the surge voltage generating circuit 20A. The other end of the series circuit 21A is connected to the output terminal 20b of the surge voltage generating circuit 20A. In the series circuit 21A, the order of the variable resistor section 23A and the variable inductor section 24A is unlimited. That is, the variable inductor section 24A can be connected between the variable resistor section 23A and the input terminal 20a, and the variable resistor section 23A can also be connected between the variable inductor section 24A and the input terminal 20a. One end of the variable capacitance capacitor section 22A and the other end of the series circuit 21A are connected to a node N4 between the output terminal 20b. The other end of the variable capacitance capacitor section 22A is connected to a constant potential line (e.g., a reference potential line GND).

[0058] In one example, the resistance value of the variable resistor 23A is controlled by a motor M1. Specifically, the motor M1 causes the slider 23b in contact with the resistor 23a of the variable resistor 23A to slide, thereby controlling the contact position of the slider 23b relative to the resistor 23a. The contact position of the slider 23b is detected by a sensor. The relationship between the contact position of the slider 23b and the resistance value of the variable resistor 23A is prepared in advance, and the contact position of the slider 23b is controlled based on the relationship and the detection result obtained by the sensor so as to achieve the desired resistance value. The motor M1 is controlled by a computer 52 (see FIG. 5 ) described later. Fig.17 Alternatively, the resistance value of the variable resistor 23A may also be adjusted manually.

[0059] Similarly, the inductance of the variable inductor unit 24A is controlled by the motor M2. Specifically, the contact position of the slider 23b with respect to the inductor 24a is controlled by sliding the slider 24b in contact with the inductor 24a of the variable inductor unit 24A through the motor M2. The contact position of the slider 24b is detected by the sensor. The relationship between the contact position of the slider 24b and the inductance of the variable inductor unit 24A is prepared in advance, and the contact position of the slider 24b is controlled based on the relationship and the detection result obtained by the sensor so as to achieve the desired inductance. The motor M2 is controlled by the computer 52 (see FIG. 5 ) described later. Fig.17 Alternatively, the inductance of the variable inductor unit 24A may be manually adjusted.

[0060] The variable capacitance capacitor unit 22A functions as a parallel resonant capacitor. The capacitance value of the variable capacitance capacitor unit 22A is controlled by the motor M3. The capacitance value of the variable capacitance capacitor unit 22A is detected by the sensor, and the capacitance value of the variable capacitance capacitor unit 22A is controlled to a desired value. The capacitance value of the variable capacitance capacitor unit 22A is determined by a computer 52 (see Fig.17 ) control. Alternatively, the capacitance value of the variable capacitance capacitor unit 22A may also be adjusted manually.

[0061] The structure of the variable inductor unit 24A is not limited to the contact moving method based on the slider 24b as described above. For example, the variable inductor unit 24A may have another method such as inserting a movable magnetic body or diamagnetic body into an air-core coil. In the method of inserting a movable magnetic body or diamagnetic body into an air-core coil, the inductance changes according to the insertion depth of the magnetic body or diamagnetic body into the air-core coil.

[0062] The minimum resistance value of the variable resistor section 23A is 0Ω, and the maximum resistance value of the variable resistor section 23A is, for example, in the range of 400Ω to 1kΩ. In the variable resistor section 23A, the resistance value can be adjusted steplessly within the range. The minimum inductance of the variable inductor section 24A is 0H, and the maximum inductance of the variable inductor section 24A is, for example, in the range of 200μH to 500μH. In the variable inductor section 24A, the resistance value can be adjusted steplessly within the range. The maximum capacitance value of the variable capacitor section 22A is, for example, in the range of 1nF to 10nF. In the case where the capacitance of the test body M is large, the variable capacitor section 22A can be omitted (in other words, the capacitance can be 0).

[0063] According to the surge voltage generating circuit 20A, the resistance value, inductance and capacitance value can be continuously varied, and the driving voltage waveform can be finely adjusted. In addition, according to the surge voltage generating circuit 20A, the resistance value, inductance and capacitance value can be automatically controlled.

[0064] Figure 4 2 is a circuit diagram showing a surge voltage generating circuit 20B as another configuration example of the surge voltage generating circuit 20 . Figure 4The surge voltage generating circuit 20B shown has a series circuit 21B and a variable capacitance capacitor section 22B. The series circuit 21B includes a variable resistor section 23B and a variable inductor section 24B connected in series with each other. One end of the series circuit 21B constitutes the input terminal 20a of the surge voltage generating circuit 20B. The other end of the series circuit 21B is connected to the output terminal 20b of the surge voltage generating circuit 20B. In the series circuit 21B, the order of the variable resistor section 23B and the variable inductor section 24B is unlimited. That is, the variable inductor section 24B may be connected between the variable resistor section 23B and the input terminal 20a, or the variable resistor section 23B may be connected between the variable inductor section 24B and the input terminal 20a. One end of the variable capacitance capacitor section 22B is connected to a node between the other end of the series circuit 21B and the output terminal 20b. The other end of the variable capacitance capacitor section 22B is connected to a constant potential line (e.g., a reference potential line GND).

[0065] The variable resistor section 23B includes N resistors R(1) to R(N) connected in series as non-inductive fixed resistors and N switches YR(1) to YR(N) connected in parallel to the N resistors R(1) to R(N). N is an integer greater than 2. The nth switch YR(n) (n is an integer greater than 1 and less than N) becomes conductive and bypasses the corresponding resistor R(n). The resistance value of the variable resistor section 23B is determined by the combination of switches YR(1) to YR(N) that become conductive. Switches YR(1) to YR(N) are, for example, electromagnetic relays.

[0066] The variable inductor unit 24B includes M inductors L(1) to L(M) and (M+1) switches YL(0) to YL(M). M is an integer greater than or equal to 2. The inductance of the inductors L(1) to L(M) is a fixed value. One end of the switch YL(0) is connected to the variable resistor unit 23B. The other end of the switch YL(0) is connected to the output terminal 20b. Each of the inductors L(1) to L(M) is connected in series with each of the switches YL(1) to YL(M). Furthermore, the M series circuits including each inductor L and each switch YL are connected in parallel with each other between the variable resistor unit 23B and the output terminal 20b. In the example shown in the figure, each of the inductors L(1) to L(M) is connected between each of the switches YL(1) to YL(M) and the variable resistor section 23B, or each of the switches YL(1) to YL(M) may be connected between each of the inductors L(1) to L(M) and the variable resistor section 23B. When the mth switch YL(m) (m is an integer greater than 1 and less than M) is turned on, the corresponding inductor L(m) becomes effective. The inductance of the variable inductor section 24B is determined by the combination of switches that are turned on among the switches YL(1) to YL(M). When the 0th switch YL(0) is turned on, the inductance of the variable inductor section 24B can be made 0. The switches YL(0) to YL(M) are, for example, electromagnetic relays.

[0067] The variable capacitance capacitor section 22B functions as a parallel resonant capacitor. The variable capacitance capacitor section 22B includes Q capacitors Cd(1) to Cd(Q) and Q switches YC(1) to YC(Q). Q is an integer greater than 2. The capacitance values ​​of capacitors Cd(1) to Cd(Q) are fixed values. Each of capacitors Cd(1) to Cd(Q) is connected in series with each of switches YC(1) to YC(Q). Furthermore, Q series circuits including each capacitor Cd and each switch YC are connected in parallel to each other between a node between the variable inductor section 24B and the output terminal 20b and the reference potential line GND. In the example shown in the figure, each of capacitor Cd(1) to capacitor Cd(Q) is connected between each of switch YC(1) to switch YC(Q) and the reference potential line GND, or each of switch YC(1) to switch YC(Q) is connected between each of capacitor Cd(1) to capacitor Cd(Q) and the reference potential line GND. When the qth switch YC(q) (q is an integer greater than 1 and less than Q) becomes conductive, the corresponding capacitor Cd(q) becomes effective. The capacitance value of the variable capacitor unit 22B is determined by the combination of switches that become conductive among switches YC(1) to switch YC(Q). Switches YC(1) to switch YC(Q) are, for example, electromagnetic relays.

[0068] Figure 520 is a circuit diagram showing a surge voltage generating circuit 20C as still another configuration example of the surge voltage generating circuit 20 . Figure 5 The surge voltage generating circuit 20C shown has a series circuit 21C and a variable capacitance capacitor section 22C. The series circuit 21C includes a variable resistor section 23C and a variable inductor section 24C connected in series with each other. One end of the series circuit 21C constitutes the input terminal 20a of the surge voltage generating circuit 20C. The other end of the series circuit 21C is connected to the output terminal 20b of the surge voltage generating circuit 20C. In the series circuit 21C, the order of the variable resistor section 23C and the variable inductor section 24C is unlimited. That is, the variable inductor section 24C may be connected between the variable resistor section 23C and the input terminal 20a, or the variable resistor section 23C may be connected between the variable inductor section 24C and the input terminal 20a. One end of the variable capacitance capacitor section 22C is connected to a node between the other end of the series circuit 21C and the output terminal 20b. The other end of the variable capacitance capacitor section 22C is connected to a constant potential line (e.g., a reference potential line GND).

[0069] The variable resistor unit 23C includes N resistors R(1) to R(N) connected in series with each other and N busbars TB(1) to TB(N) which are connected in parallel to the N resistors R(1) to R(N) and can be detached. The busbars TB(1) to TB(N) are made of copper, for example. The structure of the variable resistor unit 23C is the same as that of the variable resistor unit 23B, except that each of the switches YR(1) to YR(N) is replaced by each of the busbars TB(1) to TB(N). The corresponding resistor R(n) is bypassed by installing the nth busbar TB(n). The resistance value of the variable resistor unit 23C is determined by the combination of the installed busbars among the busbars TB(1) to TB(N).

[0070] The variable inductor unit 24C includes M inductors L(1) to L(M) and a detachable busbar TBL. The busbar TBL is made of copper, for example. The inductances of the inductors L(1) to L(M) are fixed values ​​and are different from each other. One end of the inductors L(1) to L(M) is connected to the variable resistor unit 23C. The other end of each of the inductors L(1) to L(M) is connected to each of the terminals AL(1) to AL(M) that can be connected to one end of the busbar TBL. The variable inductor unit 24C further includes a terminal AL(0) that can be connected to one end of the busbar TBL and a terminal ATB that can be connected to the other end of the busbar TBL. The terminal AL(0) is connected to the variable resistor unit 23C without passing through the inductor. The terminal ATB is connected to the output end 20b. In the example shown in the figure, each of the inductors L(1) to L(M) is arranged between the variable resistor unit 23C and the circuit components including the bus bar TBL and the terminals AL(1) to AL(M). Alternatively, the circuit components including the bus bar TBL and the terminals AL(1) to AL(M) may be arranged between each of the inductors L(1) to L(M) and the variable resistor unit 23C. When one end of the bus bar TBL is connected to the m-th terminal AL(m), the corresponding inductor L(m) becomes effective. The inductance of the inductor L(m) selected by the bus bar TBL becomes the inductance of the variable inductor unit 24C.

[0071] The variable capacitance capacitor section 22C functions as a parallel resonant capacitor. The variable capacitance capacitor section 22C includes Q capacitors Cd(1) to Cd(Q) and Q detachable busbars TBC(1) to TBC(Q). The capacitance values ​​of capacitors Cd(1) to Cd(Q) are fixed values. Each of capacitors Cd(1) to Cd(Q) can be connected in series with each of busbars TBC(1) to TBC(Q). Furthermore, Q series circuits including each capacitor Cd and each busbar TBC are connected in parallel with each other between the node between the variable inductor section 24C and the output terminal 20b and the reference potential line GND. In the example shown in the figure, each of capacitor Cd(1) to capacitor Cd(Q) is connected between each of busbar TBC(1) to busbar TBC(Q) and reference potential line GND, or each of busbar TBC(1) to busbar TBC(Q) is connected between each of capacitor Cd(1) to capacitor Cd(Q) and reference potential line GND. By setting the qth busbar TBC(q), the corresponding capacitor Cd(q) becomes effective. The capacitance value of the variable capacitance capacitor unit 22C is determined by the combination of the busbars set in busbar TBC(1) to busbar TBC(Q).

[0072] exist Figure 4 The surge voltage generating circuit 20B shown or Figure 5In the surge voltage generating circuit 20C shown, the resistance value of the variable resistor 23B or the variable resistor 23C, the inductance of the variable inductor 24B or the variable inductor 24C, and the capacitance value of the variable capacitor 22B or the variable capacitor 22C can be made variable in stages. The surge voltage generating circuit 20B or the surge voltage generating circuit 20C can be used when there is no need to make fine adjustments to the drive voltage waveform or when a specific drive voltage waveform is used for a test. Figure 3 Compared with the surge voltage generating circuit 20A shown, the surge voltage generating circuit 20B and the surge voltage generating circuit 20C have advantages of simple structure, easy setting and operation, and high practicality. In addition, according to the surge voltage generating circuit 20B, the resistance value, inductance and capacitance value can be automatically controlled.

[0073] The combination of the variable resistors 23A to 23C, the variable inductors 24A to 24C, and the variable capacitors 22A to 22C is not limited to the above example. For example, the variable resistor 23A, the variable inductor 24B, and the variable capacitor 22C may be combined, or other combinations may be used.

[0074] Figure 6 1 is a diagram schematically showing a voltage pulse of positive polarity including a surge voltage output from the surge voltage generating circuit 20 . Figure 6 Part (a) of FIG. 1 shows that the resistance value R of the variable resistor portion 23A (23B or 23C) is sufficiently smaller than the square root of the ratio (L / Cc) of the combined capacitance Cc of the capacitance variable capacitor portion 22A (22B or 22C) and the floating electrostatic capacitance of the test body M, and the inductance L of the variable inductor portion 24A (24B or 24C), that is,

[0075] [Formula 1]

[0076]

[0077] Voltage pulse waveform at . Figure 6 Part (b) indicates that the resistance value R is less than the square root of the ratio (L / Cc) and Figure 6 When the situation of part (a) is larger than that of part (b),

[0078] [Formula 2]

[0079]

[0080] Voltage pulse waveform at . Figure 6 Part (c) indicates that the resistance value R is less than the square root of the ratio (L / Cc) and Figure 6 (b) is larger than that of

[0081] [Formula 3]

[0082]

[0083] The voltage pulse waveform at Figure 6 Part (a) shows the voltage pulse P1 output from the pulse generating circuit 10 and the voltage pulse P2 including the surge voltage output from the surge voltage generating circuit 20 in a superimposed manner. The positive voltage pulse P1 is rectangular and is formed by turning on / off the semiconductor switch HVS1 once.

[0084] The amplitude of the voltage pulse P1, i.e., the peak voltage +Vp, can be freely adjusted by the set voltage of the positive polarity DC power supply V1. The time width tw1 of the voltage pulse P1 can be freely adjusted by the conduction time of the semiconductor switch HVS1. Similarly, the amplitude of the negative polarity voltage pulse, i.e., the peak voltage, can be freely adjusted by the set voltage of the negative polarity DC power supply V2. The time width of the negative polarity voltage pulse can be freely adjusted by the conduction time of the semiconductor switch HVS2. The peak value Vs and half width tw2 of the surge voltage contained in the voltage pulse P2 are determined by the LC resonant vibration based on the inductance L and the synthetic capacitance Cc. The vibration period T of the surge voltage is expressed by the following formula (4).

[0085] [Formula 4]

[0086]

[0087] like Figure 6 As shown, the smaller the resistance value R is, the larger the peak value Vs and the half width tw2 of the surge voltage are. In addition, the smaller the resistance value R is, the larger the number of oscillations of the surge voltage is.

[0088] As described above, by adjusting the resistance value R, the inductance L and the composite capacitance Cc, the peak value, half width and vibration frequency of the surge voltage can be freely set. In addition, by adjusting the set voltage of the positive polarity DC power supply V1 (or the negative polarity DC power supply V2) and the conduction time of the semiconductor switch HVS1 (or the semiconductor switch HVS2), the amplitude and time width of the voltage pulse (fundamental wave) output from the pulse generating circuit 10 can be freely set. Therefore, the test device 1 of this embodiment can completely simulate the actual surge voltage vibration waveform generated in the inverter drive motor.

[0089] Figure 7: is a diagram schematically showing an example of a driving voltage waveform including two polarities of a surge voltage. In the example, a first pulse group PG1 including a plurality of voltage pulses Pp having a positive polarity of a surge voltage and a second pulse group PG2 including a plurality of voltage pulses Pn having a negative polarity of a surge voltage are alternately output from a surge voltage generating circuit 20 with a time interval (dead time) Δt therebetween. In the example, the voltage pulses Pp of the positive polarity and the voltage pulses Pn of the negative polarity are output in a burst manner within a predetermined period, respectively. In the first pulse group PG1, the repetition period t1 of the voltage pulses Pp is constant. In the second pulse group PG2, the repetition period t2 of the voltage pulses Pn is constant.

[0090] Figure 8 2 is a diagram schematically showing an example of a driving voltage waveform including a surge voltage. In the example, a positive polarity voltage pulse Pp including a surge voltage is continuously output from the surge voltage generating circuit 20 until the end of the test. The repetition period t1 of the voltage pulse Pp is constant.

[0091] Fig. 9 1 is a diagram schematically showing an example of a driving voltage waveform including a surge voltage. In the example, a plurality of first pulse groups PG1 including a plurality of voltage pulses Pp having a positive polarity of a surge voltage are outputted from a surge voltage generating circuit 20 at intervals Δt from each other. In the example, the voltage pulses Pp of the positive polarity are outputted in a burst within a preset period. In the first pulse group PG1, the repetition period t1 of the voltage pulses Pp is constant.

[0092] Fig.10 2 is a diagram schematically showing an example of a driving voltage waveform including a surge voltage. In the example, a negative-polarity voltage pulse Pn including a surge voltage is continuously output from the surge voltage generating circuit 20 until the end of the test. The repetition period t2 of the voltage pulse Pn is constant.

[0093] Fig.11 2 is a diagram schematically showing an example of a driving voltage waveform including a surge voltage. In the example, a plurality of second pulse groups PG2 including a plurality of voltage pulses Pn having a negative polarity of the surge voltage are outputted from the surge voltage generating circuit 20 at intervals of Δt from each other. In the example, the negative polarity voltage pulses Pn are outputted in a burst within a preset period. In the second pulse group PG2, the repetition period t2 of the voltage pulses Pn is constant.

[0094] Fig.12: is a diagram schematically showing an example of a driving voltage waveform that does not include a surge voltage. In the example, a single voltage pulse Pp of positive polarity that does not include a surge voltage and a single voltage pulse Pn of negative polarity that does not include a surge voltage are alternately output from the surge voltage generating circuit 20 at intervals of Δt. This driving voltage waveform that does not include a surge voltage is achieved by short-circuiting the inductor in the surge voltage generating circuit 20 to form a non-inductive circuit. That is, in Figure 3 In the surge voltage generating circuit 20A shown in FIG. 1 , the slider 24b of the variable inductor unit 24A is moved to a position bypassing the inductor 24a. Figure 4 In the surge voltage generating circuit 20B shown in FIG. 1 , only the switch YL(0) among the switches YL(0) to YL(M) is turned on. Figure 5 In the surge voltage generating circuit 20C shown, one end of the bus bar TBL is connected to the terminal AL(0). The rise time and fall time of the voltage pulse Pp and the voltage pulse Pn are adjusted by the resistance value of the variable resistor 23A, the variable resistor 23B or the variable resistor 23C. The figure shows the steep rise and fall and the gentle rise and fall in a superimposed manner.

[0095] Fig.13 1 is a diagram schematically showing an example of a driving voltage waveform that does not include a surge voltage. In the example, a single voltage pulse Pp of positive polarity that does not include a surge voltage and a single voltage pulse Pn of negative polarity that does not include a surge voltage are not separated by a time interval (i.e., Fig.12 The driving voltage waveform without surge voltage is alternately output from the surge voltage generating circuit 20. Fig.12 The driving voltage waveform shown is similarly realized by short-circuiting the inductor in the surge voltage generating circuit 20 to form a non-inductive circuit. By setting the time width of the voltage pulse Pp to be equal to the time width of the voltage pulse Pn, and making the absolute value of the peak voltage +Vp of the voltage pulse Pp to be equal to the absolute value of the peak voltage -Vp of the voltage pulse Pn, a positive and negative symmetrical driving voltage waveform with a duty cycle of 50% is obtained. The rise time and fall time of the voltage pulse Pp and the voltage pulse Pn are adjusted by the resistance value of the variable resistor 23A, the variable resistor 23B or the variable resistor 23C. The figure shows the steep rise and fall and the gentle rise and fall in overlap.

[0096] Fig.12 and Fig.13 The driving voltage waveform not including the surge voltage shown can be used to compare the insulation and life of the test object M with the driving voltage waveform including the surge voltage (for example, see Fig.14 ) for comparison.

[0097] exist Figure 7 to Figure 13In the embodiment, the absolute value of the peak value Vs of the surge voltage is, for example, greater than 3 kVp and less than 20 kVp. In one embodiment, the absolute value of the peak value Vs of the surge voltage is set to 3 kVp, 6 kVp, 10 kVp and 20 kVp. The frequency of the voltage pulse Pp and the voltage pulse Pn (the inverse of the repetition period t1 and the repetition period t2) can be set in a range of, for example, 1 kHz to 100 kHz. The rise time and fall time of the voltage pulse Pp and the voltage pulse Pn can be set in a range of, for example, 20 ns to 100 ns.

[0098] Fig.15 and Fig.16 This is a diagram showing a driving voltage waveform actually measured in the test device 1 . Fig.15 Parts (a) to (e) of FIG. 1 show a single positive-polarity voltage pulse Pp including a surge voltage. Fig.16 Parts (a), (d), and (e) show a case where a positive voltage pulse Pp and a negative voltage pulse Pn are alternately output. Fig.16 Parts (b) and (c) of FIG. 1 show that a first pulse group PG1 including a plurality of positive voltage pulses Pp and a second pulse group PG2 including a plurality of negative voltage pulses Pn are alternately output with time intervals (see FIG. 1 ). Figure 7 ). Fig.16 Parts (a), (b), and (c) of FIG. 1 show driving voltage waveforms that do not include surge voltage. Fig.16 Parts (d) and (e) of FIG. 5 show driving voltage waveforms including surge voltages.

[0099] Fig.17 1 is a block diagram showing an example of the system configuration of the test device 1 according to the present embodiment. Fig.17 As shown, the test apparatus 1 includes, in addition to the above-described structure, a collection interface 51 , a computer 52 , a display unit 53 , a printer 54 , an input operation unit 55 , a low-voltage power supply 56 , a partial discharge measurement device 57 , and a constant temperature chamber 58 for accommodating the test object M.

[0100] The low voltage power supply 56 supplies power supply voltage to the semiconductor switches HVS1 to HVS3 and the control element. The low voltage power supply 56 constitutes a power supply unit of the pulse generating circuit 10 together with the positive polarity DC power supply V1 and the negative polarity DC power supply V2.

[0101] The collective interface 51 is electrically connected to the computer 52. The group including the collective interface 51 and the computer 52 also serves as the first control unit and the second control unit in this embodiment. The collective interface 51 is connected to the semiconductor switches HVS1 to HVS3 via optical fibers. The computer 52 provides each of the optical trigger signals LT1 to LT3 to each of the semiconductor switches HVS1 to HVS3 through the collective interface 51. The computer 52 controls the on / off time points of the semiconductor switches HVS1 to HVS3 through the optical trigger signals LT1 to LT3, thereby forming a driving voltage waveform. The time width of the positive polarity voltage pulse is equal to the time width of the optical trigger signal LT1 to the semiconductor switch HVS1. The time width of the negative polarity voltage pulse is equal to the time width of the optical trigger signal LT2 to the semiconductor switch HVS2.

[0102] The integrated interface 51 is electrically connected to the positive polarity DC power supply V1, the negative polarity DC power supply V2, the variable resistor unit 23A, the variable resistor unit 23B, or the variable resistor unit 23C, the variable inductor unit 24A, the variable inductor unit 24B, or the variable inductor unit 24C, the variable capacitor unit 22A, the variable capacitor unit 22B, or the variable capacitor unit 22C, the current sensor 41, the high voltage probe 42, the partial discharge measurement device 57, and the thermostatic chamber 58. The computer 52 outputs control signals to each of the positive polarity DC power supply V1, the negative polarity DC power supply V2, the variable resistor unit 23A, the variable resistor unit 23B, or the variable resistor unit 23C, the variable inductor unit 24A, the variable inductor unit 24B, or the variable inductor unit 24C, the variable capacitor unit 22A, the variable capacitor unit 22B, or the variable capacitor unit 22C, and the thermostatic chamber 550 through the integrated interface 51. The computer 52 controls the voltage values ​​of the positive polarity DC power supply V1 and the negative polarity DC power supply V2 through control signals. The computer 52 controls the resistance value of the variable resistor section 23A, the variable resistor section 23B, or the variable resistor section 23C through control signals. The computer 52 controls the inductance of the variable inductor section 24A, the variable inductor section 24B, or the variable inductor section 24C through control signals. The computer 52 controls the capacitance value of the variable capacitor section 22A, the variable capacitor section 22B, or the variable capacitor section 22C through control signals. The computer 52 controls the temperature of the thermostatic bath 58 through control signals, receives a signal indicating the temperature in the thermostatic bath 58, and collects and records temperature data.

[0103] The computer 52 can know the magnitude of the current output from the surge voltage generating circuit 20 through the signal from the current sensor 41. The computer 52 can know the magnitude of the voltage output from the surge voltage generating circuit 20 through the signal from the high voltage probe 42. Fig.15As shown, the output signal of the current sensor 41 and the output signal of the high voltage probe 42 can be divided into two, one of which is sent to the collective interface 51, and is used in the computer 52 for overcurrent protection, data collection and recording. In addition, the other signal can be sent to the oscilloscope 43, and the drive voltage waveform and current waveform output from the surge voltage generating circuit 20 are displayed in real time in the oscilloscope 43. In the case where the output signal from the current sensor 41 exceeds the value preset by the operator due to insulation damage or grounding of the test object M, the computer 52 quickly disconnects the semiconductor switches HVS1 to HVS3 in operation, and immediately disconnects the positive polarity DC power supply V1 and the negative polarity DC power supply V2. In addition, the computer 52 notifies the operator of the abnormality of the test object M through the display unit 53.

[0104] The computer 52 can know the magnitude of the partial discharge generated in the test body M through the signal from the partial discharge measuring device 57. The computer 52 determines whether the partial discharge has occurred, detects the partial discharge starting voltage, analyzes the intensity of the partial discharge, etc. based on the signal from the partial discharge measuring device 57. As the partial discharge measuring device 57, for example, a partial discharge detector (model NPD-1) manufactured by Nissin Pulse Electronics Co., Ltd. is used. Compared with the conventional partial discharge detector, the partial discharge detector can measure a wider frequency band, and even a partial discharge charge of several pC (picocoulomb) can be measured with good accuracy.

[0105] The display unit 53, the printer 54, and the input operation unit 55 are electrically connected to the computer 52. The computer 52 causes the display unit 53 to display the test results. The computer 52 causes the printer 54 to print the test results. The display unit 53 and the printer 54 are used for data processing of the test results, recording of the test results, and report preparation. The display unit 53 can also display the operating status of the test device 1.

[0106] The input operation unit 55 receives input of setting parameters and input of execution commands from the operator. The setting parameters received by the input operation unit 55 are displayed on the display unit 53. The input operation unit 55 may be a keyboard connected to the computer 52 or a touch panel provided on the display unit 53.

[0107] The setting parameters accepted by the input operation unit 55 may include the intermittent voltage pulses included in the driving voltage waveform. Figure 8 or Fig. 9 As shown, it only contains positive voltage pulses Pp, or as Fig.10 or Fig.11 As shown, it only contains negative voltage pulses Pn, or as shown Figure 7 , Fig.12 or Fig.13The setting parameters may include information about the intermittent voltage pulses included in the drive voltage waveform. Figure 8 or Fig.10 As shown, the output continues until the test is completed, or as Figure 7 , Fig. 9 or Fig.11 The setting parameters may include information related to the amplitude of the voltage pulse contained in the driving voltage waveform, i.e., the peak voltage +Vp and the peak voltage -Vp of the voltage pulse Pp and the voltage pulse Pn. The setting parameters may include information related to the frequency (1 / t1 or 1 / t2) of the intermittent voltage pulse Pp and the voltage pulse Pn contained in the driving voltage waveform. The setting parameters may include information related to the time width tw1 of the intermittent voltage pulse Pp and the voltage pulse Pn contained in the driving voltage waveform. The setting parameters may include at least one or all of the group consisting of the time interval Δt, the power supply voltage +HV of the positive polarity DC power supply V1, the power supply voltage -HV of the negative polarity DC power supply V2, the resistance value R of the variable resistor part 23A (23B or 23C), the inductance L of the variable inductor part 24A (24B or 24C), and the capacitance value C of the variable capacitor part 22A (22B or 22C). The input operation unit 55 supplies the setting parameters input by the input operation to the computer 52 .

[0108] In addition, the input operation unit 55 receives input operations related to the number of intermittent voltage pulses (number of repetitions) included in the drive voltage waveform output from the pulse generating circuit 10, that is, the number of voltage pulses Pp and voltage pulses Pn included in the first pulse group PG1 and the second pulse group PG2, respectively. The input operation unit 55 provides the computer 52 with information related to the number of intermittent voltage pulses input by the input operation.

[0109] The effects obtained by the test device 1 of the present embodiment described above will be described together with the conventional problems. Conventionally, a PWM control method has been widely used to control each phase of an electric motor. Fig.18 It is a diagram showing an example of a two-level PWM drive waveform. Fig.19 1 is a diagram showing an example of a three-level PWM drive waveform. In these diagrams, the vertical axis represents voltage and the horizontal axis represents time. The diagrams overlap and show a rectangular wave PWM output waveform B1 and an output waveform B2 after the PWM output waveform B1 passes through an LC filter. The output waveform B2 becomes a sine wave.

[0110] In the PWM control method, the PWM output waveform B1 is formed by high-speed switching of the semiconductor switch. However, in the rising and falling parts of the rectangular wave included in the PWM output waveform B1, a surge voltage is significantly generated due to the wiring inductance to the electric motor. Fig. 20 Part (a) schematically shows a rectangular wave before a surge voltage is generated. Fig. 20 Part (b) schematically shows a rectangular wave after a surge voltage is generated. The larger the peak value of the surge voltage intruding into the electric motor, the more partial discharge will be generated in the coating resin of the winding, and the insulation degradation of the electric motor and the winding will proceed.

[0111] The mechanism of insulation degradation caused by partial discharge caused by surge voltage is known, but the correlation between partial discharge inception voltage (PDIV) and discharge charge has not been quantitatively evaluated. There has also been no quantitative evaluation of partial discharge relative to a PWM output waveform that alternately repeats a pulse group containing multiple positive voltage pulses and a pulse group containing multiple negative voltage pulses. In addition, there has been no test equipment that can perform insulation evaluation, life evaluation based on repeated operation, and Vt accelerated degradation testing, including partial discharge, which is a precursor phenomenon of insulation damage in electric motors caused by surge voltage.

[0112] With regard to the above-mentioned problem, in the test device 1 of the present embodiment, the PWM output waveform can be simulated by the pulse generating circuit 10, and further, the surge voltage can be added to the simulated PWM output waveform by the surge voltage generating circuit 20. In addition, since the resistance value, inductance and capacitance value of the CLR resonance circuit of the surge voltage generating circuit 20 are variable, the peak value, half width and vibration number of the surge voltage can be freely set. Therefore, the surge voltage generated in the actual PWM control can be accurately simulated, and the insulation evaluation for partial discharge, the life evaluation based on repeated operation and the Vt accelerated degradation test can be accurately performed. Moreover, the correlation between PDIV and the discharge charge amount can be quantitatively evaluated, and the partial discharge with respect to the PWM output waveform in which the pulse group including a plurality of positive polarity voltage pulses and the pulse group including a plurality of negative polarity voltage pulses are alternately repeated can be quantitatively evaluated.

[0113] The structure of the test device 1 of this embodiment divides the operating functions into units, and each unit is equipped with a rich fault detection function, and the occurrence of a fault can be automatically notified to the operator through the display unit 53, etc. When repair is required, the entire unit that has a fault can be simply replaced, and even if the manufacturer of the test device 1 is not a person skilled in the art, the repair work can be quickly carried out.

[0114] As in the present embodiment, the pulse generating circuit 10 may include a semiconductor switch HVS1, a semiconductor switch HVS2, a bridge full-wave rectifier BR1, and a semiconductor switch HVS3. A circuit that advances the falling time of a positive voltage pulse and a negative voltage pulse and restores these voltage pulses to a reference potential at high speed is also called a grounding (GND) circuit in view of its function. Originally, in order to set the falling potential of a positive voltage pulse and a negative voltage pulse as a reference potential, a semiconductor switch corresponding to a positive voltage pulse and a semiconductor switch corresponding to a negative voltage pulse are required, totaling two semiconductor switches. However, in the present embodiment, a grounding circuit is formed by only one semiconductor switch HVS3 by using a bridge full-wave rectifier BR1. Thus, the circuit structure can be simplified. Moreover, the pulse generating circuit 10 can output a voltage having a two-level or three-level inverter drive waveform as a drive voltage waveform.

[0115] As in the present embodiment, the pulse generating circuit 10 may include a plurality of semiconductor switches HVS1 to HVS3 for forming a driving voltage waveform, and a collective interface 51 and a computer 52 for generating a plurality of light trigger signals LT1 to LT3 for controlling the plurality of semiconductor switches HVS1 to HVS3, respectively. Furthermore, the collective interface 51 may provide each of the plurality of light trigger signals LT1 to LT3 to each of the plurality of semiconductor switches HVS1 to HVS3. By providing each of the light trigger signals LT1 to LT3 to each of the semiconductor switches HVS1 to HVS3, the influence of noise may be reduced and malfunction may be prevented.

[0116] As in the present embodiment, the input operation unit 55 can receive input operations related to the number of voltage pulses Pp included in the first pulse group PG1 and / or the number of voltage pulses Pn included in the second pulse group PG2, and provide information related to the number of voltage pulses Pp and voltage pulses Pn input by the input operation to the computer 52. Moreover, the computer 52 can determine the number of voltage pulses Pp included in the first pulse group PG1 and / or the number of voltage pulses Pn included in the second pulse group PG2 based on the information. In the above case, the number of voltage pulses Pp included in the first pulse group PG1 and / or the number of voltage pulses Pn included in the second pulse group PG2 can be freely and easily set.

[0117] As in the present embodiment, the input operation unit 55 can receive input operations related to the driving voltage waveform, and provide information related to the driving voltage waveform input by the input operation to the computer 52, and the computer 52 can determine the driving voltage waveform based on the information. The information related to the driving voltage waveform may include at least one of the following information: information related to whether the intermittent pulses only include positive polarity pulses, only include negative polarity pulses, or include both positive polarity and negative polarity; information related to whether the intermittent pulses are continuously output before the end of the test, or are output suddenly within a predetermined period; information related to the amplitude of the intermittent pulses; information related to the frequency of the intermittent pulses; information related to the time width of each pulse constituting the intermittent pulses. In the above case, the driving voltage waveform can be arbitrarily constructed, so the test conditions can be freely set.

[0118] The inverter pulse insulation test device based on the present disclosure is not limited to the above-mentioned embodiment, and can be modified in various other ways. For example, in the above-mentioned embodiment, a variable non-inductive resistor is used in the variable resistor section of the surge voltage generating circuit, but the type of resistor used in the variable resistor section is not limited thereto, and for example, an electronically controlled equivalent variable resistor may also be used.

[0119] Description of Figure Numbers

[0120] 1: Inverter pulse insulation test device

[0121] 10: Pulse generating circuit

[0122] 10b: Output terminal (first output terminal)

[0123] 11, 12: High voltage terminals

[0124] 13: Output terminal

[0125] 20, 20A, 20B, 20C: Surge voltage generating circuit

[0126] 20a: Input terminal

[0127] 20b: Output terminal (second output terminal)

[0128] 21A, 21B, 21C: Series circuit

[0129] 22A, 22B, 22C: Capacitance variable capacitor section

[0130] 23A, 23B, 23C: Variable resistor

[0131] 23a: Resistor

[0132] 23b: Slider

[0133] 24A, 24B, 24C: variable inductor section

[0134] 24a: Inductor

[0135] 24b: Slider

[0136] 41: Current sensor

[0137] 42: High voltage probe

[0138] 43: Oscilloscope

[0139] 51: Collection Interface

[0140] 52: Computer

[0141] 53: Display unit

[0142] 54: Printing press

[0143] 55: Input operation unit

[0144] 56: Low voltage power supply

[0145] 57: Partial discharge tester

[0146] 58: Constant temperature bath

[0147] ATB, AL(0)~AL(M): Terminal

[0148] BR1: Bridge full-wave rectifier

[0149] C1, C2: capacitors

[0150] Cd(1)~Cd(Q): Capacitor

[0151] GND: Reference potential line

[0152] HVS1: semiconductor switch (first semiconductor switch)

[0153] HVS2: semiconductor switch (second semiconductor switch)

[0154] HVS3: semiconductor switch (third semiconductor switch)

[0155] L(1)~L(Q): Inductor

[0156] LT1~LT3: Light trigger signal

[0157] M: Test subject

[0158] M1, M2, M3: Motor

[0159] N1, N2, N3, N4: nodes

[0160] P1, P2: voltage pulse

[0161] PG1: First pulse group

[0162] PG2: Second pulse group

[0163] Pn, Pp: voltage pulse

[0164] R(1)~R(N): Resistance

[0165] Rd1, Rd2: discharge resistors

[0166] Rp1, Rp2, Rs1, Rs2, Rs3: resistance

[0167] TBL, TB(1)~TB(N), TBC(1)~TBC(Q): Bus

[0168] V1: Positive polarity DC power supply

[0169] V2: Negative polarity DC power supply

[0170] YC(1)~YC(Q), YL(0)~YL(M), YR(0)~YR(N): switch

Claims

1. An inverter pulse insulation test device, comprising: A pulse generating circuit having a first output terminal, from which a voltage having a simulated driving voltage waveform including intermittent pulses is output; as well as a surge voltage generating circuit having an input terminal electrically connected to the first output terminal of the pulse generating circuit and a second output terminal connected to the test object, generating a surge voltage at the rising part and the falling part of each pulse of the driving voltage waveform input from the input terminal to change the driving voltage waveform, and outputting a voltage having the changed driving voltage waveform from the second output terminal, The surge voltage generating circuit has: A variable resistor and a variable inductor connected in series with each other, and Capacitance variable capacitor, One end of the series circuit of the variable resistor and the variable inductor constitutes the input end of the surge voltage generating circuit. The other end of the series circuit is connected to the second output end of the surge voltage generating circuit, One end of the capacitance variable capacitor and a node between the other end of the series circuit and the second output end are connected, The other end of the variable capacitance capacitor is connected to a constant potential line.

2. The inverter pulse insulation test device according to claim 1, wherein: The pulse generating circuit outputs a two-level or three-level inverter driving waveform as the voltage of the driving voltage waveform, The pulse generating circuit has: A first semiconductor switch, one end of which is connected to the positive voltage terminal, and the other end of which is connected to the first output terminal; a second semiconductor switch, one end of which is connected to the negative voltage terminal, and the other end of which is connected to the first output terminal; A bridge full-wave rectifier having two input terminals and two output terminals, wherein one of the two input terminals is connected to a reference potential line, and one of the two output terminals is connected to the first output terminal; and A third semiconductor switch has one end connected to the other input end of the bridge full-wave rectifier, and the other end connected to the other output end of the bridge full-wave rectifier.

3. The inverter pulse insulation test device according to claim 1, wherein: The pulse generating circuit has: A plurality of semiconductor switches, used for forming the driving voltage waveform; and a first control unit, generating a plurality of light trigger signals for controlling the plurality of semiconductor switches respectively; The first control unit provides each of the plurality of light triggering signals to each of the plurality of semiconductor switches.

4. The inverter pulse insulation test device according to any one of claims 1 to 3, further comprising: A second control unit controls the driving voltage waveform in the pulse generating circuit; as well as an input operation unit that receives an input operation related to the number of the intermittent pulses and provides information related to the number of the intermittent pulses input by the input operation to the second control unit, The second control unit determines the number of the intermittent pulses according to the information.

5. The inverter pulse insulation test device according to any one of claims 1 to 3, further comprising: A second control unit controls the driving voltage waveform in the pulse generating circuit; as well as an input operation unit that receives an input operation related to the driving voltage waveform and provides information related to the driving voltage waveform input by the input operation to the second control unit, The second control unit determines the driving voltage waveform according to the information. The information related to the driving voltage waveform includes at least one of the following information: Information about whether the intermittent pulses include only pulses of positive polarity, only pulses of negative polarity, or both pulses of positive polarity and pulses of negative polarity; Information on whether the intermittent pulses are continuously output until the end of the test or are output in bursts within a predetermined period; information related to the amplitude of the intermittent pulses; information related to the frequency of the intermittent pulses; Information on the time width of each pulse constituting the intermittent pulse.

Images