Reverse recovery protection in switching voltage converters

Abstract

A voltage regulator control circuit includes a transistor input controller (404). The transistor input controller (404) forces the pendulum control signal into a state on its pendulum control output in response to changes in load conditions and forces the turn-on signal into a state on its first transistor control output. The first transistor (HS) has a first control input and first and second current terminals. A second transistor (LS) is coupled to the first transistor. The driver (406) has a pendulum control input, a driver input, and a driver output. The driver input is coupled to the first transistor control output. The driver output is coupled to the first control input. In response to a first state of the pendulum control signal and a first state of the on signal, the driver (406) provides a higher current to the first control input, and in response to a second state of the pendulum control signal and the first state of the on signal, the driver (406) provides a lower current to the first control input.

Description

Background Art

[0001] A direct current (DC)-DC voltage converter converts an input DC voltage (VIN) to an output DC voltage (VOUT). Depending on the type of voltage converter, VOUT may be smaller or larger than VIN. One type of DC-DC voltage converter is a switching converter. Various types of switching converters are available. In one example, a switching converter includes a first transistor (sometimes referred to as a high-side (HS) transistor), which is coupled to a second transistor (sometimes referred to as a low-side (LS) transistor), which is located between VIN and ground. The connection between the transistors is referred to as a switch node (SW). In response to the HS transistor being turned on, the SW voltage (Vsw) is pulled up to approximately VIN. In response to the LS transistor being turned on, the SW voltage (Vsw) is pulled down to approximately ground. As the control circuit mutually turns on and off the HS transistor and the LS transistor, a square wave voltage waveform is generated on SW. An inductor may be coupled to SW. In response to the HS transistor being turned on, the current through the inductor increases approximately linearly. In response to the LS transistor being turned on, the current through the inductor decreases approximately linearly. Summary of the invention

[0002] In one example, a voltage regulator control circuit includes a transistor input controller. The transistor input controller forces a slew control signal to enter a certain state on its slew control output in response to a change in load conditions, and forces a turn-on signal to enter a certain state on its first transistor control output. The first transistor has a first control input and a first current terminal and a second current terminal. The second transistor is coupled to the first transistor. A driver has a slew control input, a driver input, and a driver output. The driver input is coupled to the first transistor control output. The driver output is coupled to the first control input. In response to the first state of the slew control signal and the first state of the turn-on signal, the driver provides a higher current to the first control input, and in response to the second state of the slew control signal and the first state of the turn-on signal, the driver provides a lower current to the first control input. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 is a schematic diagram of a voltage converter in an example.

[0004] Figure 2 is a waveform of a control signal used to control a transistor in a voltage converter in one example.

[0005] Figure 3 0047] are additional waveforms of voltage and current in one example illustrating the operation of the voltage converter in response to changes in load conditions.

[0006] Figure 4 is a schematic diagram of a voltage converter with a multi-drive strength gate driver in another example.

[0007] Figure 5 is a schematic diagram of an example implementation of a multiple drive strength gate driver.

[0008] Figure 6 is a schematic diagram of a voltage converter with an active clamping circuit in another example.

[0009] Figure 7 is a schematic diagram of an example implementation of an active clamp circuit.

[0010] Figure 8 is a schematic diagram of a voltage converter having both a multi-drive strength gate driver and an active clamp circuit in one example.

[0011] Fig. 9 is a block diagram of a system in which any of the voltage converters described herein may be used. DETAILED DESCRIPTION

[0012] The same reference numbers or other reference designators are used in the drawings to indicate the same or similar (functionally and / or structural) features.

[0013] Figure 1 1 is a schematic diagram of a voltage converter 100 in an example. In this example, the voltage converter 100 includes a pulse width modulator (PWM) generator 102, a gate controller 104, drivers 106 and 108, an HS transistor, an LS transistor, an inductor L1, and an output capacitor C1. The HS transistor and the LS transistor are n-channel field effect transistors (NFETs) in this example, but may be other types of transistors in other examples. Diode D1 represents the parasitic body diode of the HS transistor. Diode D2 represents the body diode of the LS transistor. An input voltage VIN is provided to the drain of the HS transistor. The voltage across the capacitor C1 is an output voltage VOUT, which may be provided to a load 120.

[0014] The PWM generator 102 generates a PWM signal 103. The PWM generator 102 provides the PWM signal 103 to the gate controller 104. In one example, a logic high level of the PWM signal 103 indicates that the HS transistor is to be turned on, and a logic low level indicates that the LS transistor is to be turned on. The gate controller 104 receives the PWM signal 103 and generates gate control signals, namely HSON 105 for the HS transistor and LSON 107 for the LS transistor. The gate controller 104 may implement a small amount of idle time between turning one transistor off and before turning another transistor on.

[0015] Signals HSON 105 and LSON 107 are provided to their respective drivers 106 and 108, as shown. Drivers 106 and 108 generate voltages (HSG from driver 106 and LSG from driver 108) and currents of respective HS and LS transistors in logic levels sufficient to turn on and off HSON 105 and LSON 107. The source of the HS transistor is coupled to the drain of the LS transistor at a switch node SW. One terminal of inductor L1 is coupled to SW. The current through inductor L1 is labeled IL. Capacitor C1 is coupled between the other terminal of inductor L1 and ground.

[0016] Figure 2 105 and LSON 107 are example waveforms for signals HSON 105 and LSON 107. A high logic level of signal HSON causes driver 106 to turn on the HS transistor, and a logic low of HSON causes driver 106 to turn off the HS transistor. Similarly, a high logic level of signal LSON causes driver 106 to turn on the LS transistor, and a logic low of LSON causes driver 106 to turn off the LS transistor. Because both transistors are on at the same time, LSON is generally the logical opposite of HSON. The idle time between the falling edge of HSON before the subsequent rising edge of LSON and between the falling edge of LSON before the subsequent rising edge of HSON is small ( Figure 2 ) ensures that the two transistors are not turned on at the same time.

[0017] The voltage converter 100 uses a feedback signal (not shown) to generate a regulated output voltage VOUT for a range of load conditions. For example, the load 120 can have a normal operating mode (getting a higher current from the converter 100) and a sleep state (getting a lower current from the converter 100). Reference numerals 201 and 203 represent higher load conditions (e.g., normal operating conditions of the load 120). Reference numeral 202 represents a fast load reduction condition in which the load current changes very quickly from a relatively high level to a relatively low level. In this example, the switching cycle of the HS transistor and the LS transistor stops during the fast load reduction condition implemented during 202.

[0018] Figure 3Example waveforms including inductor current IL, switch node voltage Vsw, and PWM signal 103. In response to PWM 103 being at a logic high level (301), the HS transistor turns on, thereby pulsing Vsw to approximately VIN. With the HS transistor on, current (IL) flows through the HS transistor and flows to the inductor L1. When the HS transistor is on, the inductor current IL increases approximately linearly, as indicated by reference numeral 302. Conversely, when the HS transistor is off and the LS transistor is on (in response to the PWM signal 103 being a logic low (303)), Vsw is pulled down to approximately ground, and the inductor current IL decreases approximately linearly, as indicated by reference numeral 304.

[0019] For some applications, the downward slope of IL at 304 (when the HS transistor is turned off and the LS transistor is turned on) may not be large enough. For example, the load 120 may be a server computer (or a subcircuit of a server computer) powered by the voltage converter. In a data center that may have a large number of server computers, it may be useful to convert a given server computer to a low power mode as quickly as possible for the purpose of saving power. In order to convert the voltage converter 100 to a lower power state more quickly, the gate controller 104 may implement a third logic level 305. In this example, the third logic level 305 is between the logic high level 301 and the logic low level 303. The intermediate third logic level 305 indicates that both transistors HS and LS are disconnected. Thus, when the voltage converter 100 detects that the load 120 enters a low power mode (e.g., the external control detects the entry into the low power state and notifies the voltage converter 100), after turning on the LS transistor, the PWM generator 102 converts the PWM signal 103 to an intermediate level (305). The gate controller 104 responds to this particular logic level of the PWM signal 103 by turning both transistors off (the HS transistor is already off at this point, and the gate controller 106 ensures that the HS transistor does not turn back on).

[0020] When the LS transistor is turned off, the inductor current can no longer flow through the channel of the LS transistor. Instead, the body diode D2 of the LS transistor is turned on, and the current IL continues to flow through the body diode D2 to the inductor L1. Since the body diode is turned on, a forward voltage drop (Vd, Figure 1 ), the forward voltage drop causes Vsw to become negative (approximately -Vd). When the body diode D2 is turned on and the current IL flows through the body diode, charge accumulates in the body diode. This charge is called reverse recovery charge. Then, when the load 120 changes from a low load condition back to a higher load condition (such as Figure 2), the PWM generator 102 again generates a PWM signal to turn the HS transistor and the LS transistor on and off mutually.

[0021] However, with the reverse recovery charge still present on the body diode D2, when the HS transistor is first turned on (211) to start the higher load condition, the body diode D2 discharges its reverse recovery charge with a relatively large current, which generates a ringing voltage 310 on Vsw (the ringing voltage 310 is due to Figure 3 Although the ringing may be brief, the maximum voltage of the ringing Vsw voltage can exceed the safe operating value of the drain-source voltage (Vds) of the LS transistor. Therefore, the switch node ringing may damage the LS transistor.

[0022] The examples described herein are directed to protecting the LS transistor from potentially harmful switch node voltage ringing resulting from rapid discharge of the reverse recovery charge of the body diode of the LS transistor.

[0023] Figure 4 is a schematic diagram of a voltage converter 400 in an example. In this example, the voltage converter 400 reduces the turn-on speed of the HS transistor in the first switching cycle after the load changes from a lower load condition to a higher load condition. By reducing the turn-on speed of the HS transistor, the voltage (Vsw) on SW rises more gradually than when the turn-on speed of the transistor is higher. Therefore, the current generated by the discharge of the body diode D2 of the LS transistor rises more gradually, and SW thereby experiences a lower magnitude of voltage ringing.

[0024] The voltage converter 400 includes a HS transistor and a LS transistor, a PWM generator 102 , a gate controller 404 , a driver 108 , a multi-drive strength driver 404 for the HS transistor, a register 410 , an inductor L1 , and a capacitor C1 . Figure 4 The HS transistor and LS transistor shown in FIG. 4 are FETs, but may be implemented as other types of transistors (e.g., bipolar junction transistors). The term gate controller 404 is a general term that refers to a circuit that controls a signal applied to a control input of a transistor, whether the control input is a gate in the case of a FET or a base in the case of a bipolar junction transistor. In general, the gate controller 404 may also be referred to as a transistor input controller.

[0025] The components are connected in most cases in the same manner as described above. The gate controller 404 receives the PWM signal 103 from the PWM generator 102 and generates the HSON signal 105 and the LSON signal 107 as described above. The gate controller 404 also has an output on which the gate controller 404 generates a slew control signal 412. The gate controller 404 asserts the slew control signal 412 to a first logic state (e.g., logic high) to cause the multi-drive strength driver 406 to generate a first drive strength to turn on the HS transistor. The gate controller 404 de-asserts the slew control signal 412 to a second logic state (e.g., logic low) to cause the multi-drive strength driver 406 to generate a second drive strength to turn on the HS transistor. In one example, the first drive strength is less than the second drive strength. In order to turn on the HS transistor more slowly, the gate controller 404 asserts the slew control signal 412 to a first logic level. In order to turn on the HS transistor more quickly, the gate controller 404 de-asserts the slew control signal 412 to a second logic state. In one example, when the load transitions from a lower load condition to a higher load condition, the gate controller 404 asserts the slew control signal 412 to a first logic state only for the first switching cycle of the HS transistor. By turning on the HS transistor more slowly only for the first switching cycle, the body diode of the LS transistor is able to discharge its reverse recovery charge more slowly, thereby producing a lower magnitude ringing on SW than if the HS transistor were turned on more quickly. Then, for the next (and subsequent) switching cycle of the HS transistor, the gate controller 404 de-asserts the slew control signal 412 to cause the multi-drive strength driver 406 to turn on the HS transistor more quickly.

[0026] Register 410 is a programmable register (e.g., via a serial bus such as an inter-integrated circuit (I2C) bus) into which a value may be stored to enable or disable the slew rate control capability of voltage converter 400. For example, where it is desired for a given application that slew rate control is not required, a first value may be programmed into register 410 such that gate controller 404 is not able to assert slew control signal 412. However, where it is desired for a given application (e.g., a server computer in a data center as described above) that slew rate control may be used, a second value may be programmed into register 410 such that gate controller 404 is able to assert slew control signal 412 as described above.

[0027] exist Figure 4In the example of FIG. 4 , at least some of the components of the voltage converter 400 may be fabricated in the form of an integrated circuit (IC). For example, the PWM generator 102, the gate controller 404, the register 410, and the drivers 108 and 406 may be fabricated on one IC. The HS transistor and the LS transistor may be fabricated on the same IC, or may be provided separately (e.g., on a circuit board to which the IC containing the other components is mounted).

[0028] Figure 5 4 is a schematic diagram of an example implementation of a multi-drive strength driver 406. In this example, the multi-drive strength driver 406 includes a first current source I1 and a second current source I2. Switch SW1 is coupled between current source I1 and the gate of the HS transistor. Switch SW2 is coupled between current source I2 and the gate of the HS transistor. The slew control signal controls the on (closed) or off (OFF / open) state of switches SW1 and SW2. In one example, a logic high level of slew control signal 412 closes switch SW1 and opens switch SW2 through inverter 407. Current from any one of the current sources whose switches are closed is provided to the gate of the HS transistor to charge the gate and turn on the transistor. The on time of the HS transistor is at least partially a function of the magnitude of the gate current from the activated current source. The magnitude of the current generated by current source I1 can be less than the magnitude of the current generated by current source I2. A logic low level of slew control signal 412 opens switch SW1 and closes switch SW2, thereby providing a larger drive current to the gate of the HS transistor. In another example, a slower on-time of the HS transistor is achieved by closing one of switches SW1 or SW2, and a faster on-time is achieved by closing both switches.

[0029] Figure 6 Schematic diagram of a voltage converter 600 in an example. The voltage converter 600 includes a HS transistor and a LS transistor, a PWM generator 102, a gate controller 604, drivers 106 and 108, a register 610, an inductor L1, and a capacitor C1. The components are connected in most cases in the same manner as described above. The gate controller 604 receives the PWM signal 103 from the PWM generator 102 and generates the HSON signal 105 and the LSON signal 107 as described above. In this example, the voltage converter 600 includes an active clamp circuit 620, which is coupled to the LS transistor. The active clamp circuit 620 prevents the Vds of the LS transistor from exceeding a certain voltage (e.g., a voltage higher than which the LS transistor may be damaged). In addition, destructive voltages may be caused by ringing on SW, as described above. The specific voltage includes a design margin relative to the maximum possible safe Vds of the LS transistor.

[0030] When transitioning from a lower load condition to a higher load condition, for a first switching cycle, the active clamp circuit 620 is enabled by a clamp control signal 605 generated by the gate controller 604. In one example, the gate controller 604 asserts the clamp control signal 605 (e.g., to a logic high level) when the LS transistor is turned off. During the first switching cycle, when the HS transistor is turned on (and the LS transistor is turned off), switch node voltage ringing may occur that may damage the LS transistor. The body diode D2 of the LS transistor may discharge its reverse recovery charge, thereby causing ringing on the switch node and thereby causing ringing on the drain of the LS transistor. When activated, the active clamp circuit 620 reduces the magnitude of the ringing on the drain of the LS transistor.

[0031] exist Figure 6 In the example of FIG. 6 , at least some of the components of the voltage converter 600 can be manufactured in the form of an IC. For example, the PWM generator 102, the gate controller 604, the register 610, the active clamp circuit 620, and the drivers 106 and 108 can be manufactured on one IC. The HS transistor and the LS transistor can be manufactured on the same IC, or can be provided separately.

[0032] Figure 7 6 is a schematic diagram of an example implementation of an active clamp circuit 620. The active clamp circuit 620 includes a Zener diode Z1 (or other suitable diode), a resistor R1, a transistor M1, and a switch SW3. The cathode of the Zener diode Z1 is coupled to the switch node SW and the drain of the LS transistor. In this example, the transistor M1 is an NFET. The drain of the transistor M1 is also coupled to the switch node SW and the drain of the LS transistor. The anode of the Zener diode Z1 is coupled to the gate of the transistor M1. The resistor R1 is coupled between the anode of the Zener diode Z1 and ground. The switch SW3 is coupled across the resistor R1. The switch SW3 has a control input, which is controlled by the clamp control signal 605. In one example, asserting the clamp control signal 605 (e.g., logic high) opens the switch SW3, and deasserting the clamp control signal 605 (e.g., logic low) closes the switch SW3.

[0033] To implement the clamping capability of the active clamp circuit 620, the clamp control signal 605 is asserted, which causes the switch SW3 to be turned off. In this state, due to the ringing occurring on SW, in the event that Vsw becomes large enough (e.g., exceeds the reverse breakdown voltage of the Zener diode), the Zener diode Z1 will turn on, and current will flow through the Zener diode and resistor R1 to ground. As the current flows through resistor R1, a voltage is generated across resistor R1 and thereby reaches the gate of transistor M1. When the gate-source voltage (Vgs) of transistor M1 reaches the threshold voltage of transistor M1, transistor M1 turns on, thereby pulling the gate voltage on the LS transistor up toward Vsw. When the Vgs of the LS transistor reaches its threshold voltage, the LS transistor turns on. When the LS transistor turns on, the voltage at its drain is pulled down toward ground, thereby preventing the harmful Vds voltage from damaging the LS transistor.

[0034] When the clamping capability of active clamp circuit 620 is not needed, gate controller 604 deasserts clamp control signal 605. Deasserting clamp control signal 605 closes switch SW3. When resistor R1 is shorted by switch SW3, the gate voltage on transistor M1 is low enough to prevent transistor M1 from turning on.

[0035] Register 610 is a programmable register into which a value may be stored to enable or disable active clamp circuit 620. Some applications may not benefit from the clamping capability and may write a value to register 610 to cause gate controller 604 to always assert clamp control signal 605. However, other applications may benefit from the clamping capability and may write another value to register 610 to cause gate controller 604 to assert clamp control signal 605 for the first HS transistor switching cycle after transitioning from a lower load condition to a higher load condition, as described above.

[0036] Figure 88 is a schematic diagram of a voltage converter 800 that combines both the slew rate control capability and the active clamping capability described above. The voltage converter 800 includes an HS transistor and an LS transistor, a PWM generator 102, a gate controller 804, a multi-drive strength driver 406, a driver 108, a register 810, an inductor L1, and a capacitor C1. The components are connected in most cases in the same manner as described above. The gate controller 804 receives the PWM signal 103 from the PWM generator 102 and generates the HSON signal 105 and the LSON signal 107 as described above. In this example, the voltage converter 800 includes an active clamping circuit 620 and a multi-drive strength driver 406, which is coupled to the LS transistor. The gate controller 804 asserts the slew control signal 412 to the multi-drive strength driver 406 and asserts the clamping control signal 605 to the active clamping circuit 620. The multiple drive strengths 406 and active clamp circuit 620 function as described above. Register 810 is a programmable register into which values ​​may be stored to individually enable or disable the slew control capability and the clamp control capability.

[0037] exist Figure 8 In the example of FIG. 8 , at least some of the components of the voltage converter 800 can be manufactured in the form of an IC. For example, the PWM generator 102, the gate controller 804, the register 810, the active clamp circuit 620, the multi-drive strength driver 406, and the driver 108 can be manufactured on one IC. The HS transistor and the LS transistor can be manufactured on the same IC, or can be provided separately.

[0038] Fig. 9 is a block diagram of a system 900 in which any voltage converter described herein may be used. System 900 includes a central processing unit (CPU) 902, a network interface 904, a memory device 906, and a voltage converter 910. Voltage converter 910 provides power to CPU 902, network interface 904, and memory device 906. Voltage converter 910 may be implemented as any voltage converter described herein.

[0039] In this specification, the term "coupled" may encompass a connection, transmission, or signal path that achieves a functional relationship consistent with this specification. For example, if device A generates a signal for controlling device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C without the intermediate component C changing the functional relationship between device A and device B, so that device B is controlled by device A through the control signal generated by device A.

[0040] Also, in this description, the statement “based on” means “based, at least in part, on.” Thus, if X is based on Y, then X may be a function of Y and any number of other factors.

[0041] A device that is "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) by a manufacturer at the time of manufacture to perform a function and / or may be configured (or reconfigured) by a user after manufacture to perform a function and / or other additional or alternative functions. Configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of hardware components and interconnection of the device, or a combination thereof.

[0042] As used herein, the terms "terminal", "node", "interconnect", "pin", "pad" and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to an interconnect between device elements, circuit elements, integrated circuits, devices or other electronic or semiconductor components, or a terminal thereof.

[0043] Circuits or devices described herein as including certain components may be conversely adapted to be coupled to components used to form the described circuit systems or devices. For example, a device described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may conversely include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure during or after manufacture, e.g., by an end user and / or a third party.

[0044] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may be used instead with little or no changes to the remaining circuitry. For example, field effect transistors ("FETs") such as n-channel FETs (NFETs) or p-channel FETs (PFETs), bipolar junction transistors (BJTs—e.g., NPN transistors or PNP transistors), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used in place of the devices disclosed herein, or these may be used in combination with the devices described herein. The transistors may be depletion mode devices, drain extension devices, enhancement mode devices, native transistors, or other types of device structure transistors. Furthermore, the devices may be implemented in / on silicon substrates (Si), silicon carbide substrates (SiC), gallium nitride substrates (GaN), or gallium arsenide substrates (GaAs).

[0045] The control input of a transistor and its current terminals may be referenced in the claims. In the context of a FET, the control input is the gate, and the current terminals are the drain and source. In the context of a BJT, the control input is the base, and the current terminals are the collector and emitter.

[0046] Reference herein to a FET being "on" means that the conduction channel of the FET exists and drain current can flow through the FET. Reference herein to a FET being "off" means that the conduction channel of the FET does not exist and drain current does not flow through the FET. However, an "off" FET can have current flowing through the body diode of the transistor.

[0047] The circuits described herein are reconfigurable to include additional or different components to provide functionality that is at least partially similar to the functionality available before component replacement. Unless otherwise specified, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide a certain amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may instead be a plurality of resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be a plurality of resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor.

[0048] Reference to a signal being "asserted" refers to the signal being forced into a particular logic state, and a signal being "deasserted" refers to the signal being forced into another logic state.

[0049] Although certain elements of the described examples are included in the integrated circuit and other elements are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features shown as being external to the integrated circuit may be included in the integrated circuit, and / or some features shown as being internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / on a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0050] The use of the phrase "ground" in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification. In this specification, unless otherwise specified, "about", "approximately" or "substantially" preceding a parameter means within + / -10% of the parameter.

[0051] Modifications may be made to the described examples, and other examples are possible, within the scope of the claims.

Claims

1. A voltage regulator control circuit, comprising: a transistor input controller having a pulse width modulation (PWM) input, a first transistor control output, a second transistor control output, and a slew control output, the transistor input controller being configured to force a slew control signal to a certain state at the slew control output in response to a change in load conditions and to force a make signal to a certain state at the first transistor control output; a first transistor having a first control input and a first current terminal and a second current terminal; a second transistor having a second control input and a third current terminal and a fourth current terminal, the third current terminal being coupled to the second current terminal; as well as a driver having a slew control input, a driver input, and a driver output, the slew control input being coupled to the slew control output, the driver input being coupled to the first transistor control output, the driver output being coupled to the first control input, and the driver being configured to: providing a first current at the driver output in response to a first state of the switch-on signal and a first state of the slew control signal; and A second current is provided at the driver output in response to the first state of the turn-on signal and a second state of the slew control signal, wherein the second current is greater than the first current.

2. The voltage regulator control circuit of claim 1 , wherein the transistor input controller is configured to force the slew control signal at the slew control output to enter the first state of the slew control signal in response to a decrease in the load condition.

3. The voltage regulator control circuit of claim 1 , wherein the transistor input controller is configured to force the slew control signal into the second state of the slew control signal prior to a switching cycle of the first transistor, the switching cycle immediately followed by a next switching cycle of the first transistor.

4. The voltage regulator control circuit of claim 1, further comprising a clamp circuit coupled to the second transistor, the clamp circuit configured to prevent a voltage between the third current terminal and the fourth current terminal from exceeding a specific voltage.

5. The voltage regulator control circuit according to claim 4, wherein: The clamp circuit has a clamp control input; The transistor input controller has a clamp control output coupled to the clamp control input; the transistor input controller being configured to force a clamp control signal at the clamp control output into a first state in response to the change in the load condition; and The clamp circuit is configured to prevent the voltage between the third current terminal and the fourth current terminal from exceeding the specific voltage in response to the first state of the clamp control signal.

6. The voltage regulator control circuit of claim 4, wherein the clamping circuit comprises: a diode coupled to the third current terminal; a resistor coupled between the diode and the second control input; as well as a third transistor having a third control input coupled to the diode and the resistor, and having a fifth current terminal and a sixth current terminal coupled to the third current terminal and the sixth current terminal coupled to the second control input.

7. The voltage regulator control circuit of claim 1 , further comprising: a diode coupled to the third current terminal; a resistor coupled between the diode and the second control input; as well as a third transistor having a third control input coupled to the diode and the resistor, and having a fifth current terminal and a sixth current terminal coupled to the third current terminal and the sixth current terminal coupled to the second control input.

8. The voltage regulator control circuit of claim 7, further comprising a switch coupled across the resistor, the switch having a switch control input coupled to the transistor input controller.

9. A voltage regulator control circuit, comprising: a transistor input controller having a pulse width modulation (PWM) input, a first transistor control output, a second transistor control output, and a clamp control output, the transistor input controller being configured to force a clamp control signal at the clamp control output to a first state in response to a change in a load condition; a first transistor having a first control input coupled to the first transistor control output and a first current terminal and a second current terminal; a second transistor having a second control input and a third current terminal and a fourth current terminal, the third current terminal being coupled to the second current terminal and the second control input being coupled to the second transistor control output; as well as a clamp circuit coupled to the second transistor, the clamp circuit having a clamp control input coupled to the clamp control output, the clamp circuit being configured to prevent a voltage between the third current terminal and the fourth current terminal from exceeding a specific voltage in response to the first state of the clamp control signal.

10. The voltage regulator control circuit of claim 9, wherein the clamp circuit comprises: a diode coupled to the third current terminal; a resistor coupled between the diode and the second control input; as well as a third transistor having a third control input coupled to the diode and the resistor, and having a fifth current terminal and a sixth current terminal coupled to the third current terminal and the sixth current terminal coupled to the second control input.

11. The voltage regulator control circuit of claim 10, further comprising a switch coupled across the resistor, the switch having a switch control input, the switch control input being the clamp control input. 12 . The voltage regulator control circuit of claim 11 , wherein the switch is configured to open in response to the first state of the clamp control signal.

13. The voltage regulator control circuit of claim 9, wherein the transistor input controller is configured to force the clamp control signal to enter the second state prior to a next switching cycle of the first transistor, the next switching cycle immediately following a switching cycle in which the clamp control signal of the first transistor is in the first state.

14. The voltage regulator control circuit of claim 9, wherein the transistor input controller has a slew control output and is configured to activate a slew control signal at the slew control output in response to the change in the load condition, and the control circuit comprises: A driver is coupled between the first transistor control output and the first control input, the driver having a first drive strength capability and a second drive strength capability, the driver having a slew control input coupled to the slew control output, the driver being configured to activate the first drive strength capability or the second drive strength capability in response to a logic state of the slew control signal.

15. A voltage regulator control circuit, comprising: a transistor input controller having a pulse width modulation (PWM) input, a first transistor control output, a second transistor control output, a clamp control output, and a slew control output, the transistor input controller being configured to assert a clamp control signal at the clamp control output and assert a slew control signal at the slew control output in response to a change in a load condition; a first transistor having a first control input coupled to the first transistor control output and a first current terminal and a second current terminal; a second transistor having a second control input and a third current terminal and a fourth current terminal, the third current terminal being coupled to the second current terminal and the second control input being coupled to the second transistor control output; a driver coupled between the first transistor control output and the first control input, the driver having a first drive strength capability and a second drive strength capability, the driver having a slew control input coupled to the slew control output, the driver configured to selectively assert the first drive strength capability or the second drive strength capability in response to a logic state of the slew control signal; as well as a clamp circuit coupled to the second transistor, the clamp circuit having a clamp control input coupled to the clamp control output, the clamp circuit being configured to prevent a voltage between the third current terminal and the fourth current terminal from exceeding a specific voltage in response to activation of the clamp control signal.

16. The voltage regulator control circuit of claim 15, wherein the first drive strength capability is configured to provide a lesser drive strength to the first transistor than the second drive strength capability, and the driver is configured to select the first drive strength capability in response to the assertion of the slew control signal.

17. The voltage regulator control circuit of claim 15, wherein in response to a change from a higher load condition to a lower load condition, the transistor input controller is configured to assert the slew control signal at the slew control output and assert the clamp control signal on the clamp control output.

18. The voltage regulator control circuit of claim 15, wherein in response to a change from the lower load condition to the higher load condition, the transistor input controller is configured to de-assert the slew control signal at the slew control output and de-assert the clamp control signal at the clamp control output.

19. The voltage regulator control circuit of claim 15, wherein the transistor input controller is configured to deassert the slew control signal and the clamp control signal prior to a switching cycle of the first transistor, the switching cycle being immediately followed by a switching cycle in which the slew control signal and the clamp control signal of the first transistor are activated.

20. The voltage regulator control circuit of claim 15, wherein the clamp circuit comprises: a Zener diode coupled to the third current terminal; a resistor coupled between the Zener diode and the second control input; as well as a third transistor having a third control input coupled to the Zener diode and the resistor, and having a fifth current terminal and a sixth current terminal coupled to the third current terminal and the sixth current terminal coupled to the second control input.

Images