Undervoltage detection circuit and electronic product

Abstract

The invention provides an under-voltage detection circuit and an electronic product, and the circuit comprises a starting module which is connected with a power voltage, and is used for generating an initial state signal at a power-on initial stage; the reference generation module is used for generating a reference signal; the reference establishment judgment module is used for judging whether the reference signal is established or not and outputting an effective reference establishment signal after the reference signal is established; the under-voltage detection module is used for detecting the power supply voltage and outputting an under-voltage detection signal; and the logic module shields the undervoltage detection signal before the establishment of the reference signal is completed, and outputs the undervoltage detection signal after the establishment of the reference signal is completed. According to the invention, the structure is simple, and a reference establishment signal with relatively high stability can be generated only by consuming relatively low current; according to the undervoltage detection circuit, glitch signals generated by the undervoltage detection module when the voltage is low in the power-on process can be filtered out, and mistaken overturning of the undervoltage detection circuit caused by abnormal fluctuation of the power supply voltage can be effectively shielded.

Description

Technical Field

[0001] The invention relates to the field of power supplies, and in particular to an undervoltage detection circuit and an electronic product. Background Art

[0002] With the continuous development of science and technology, the application of electronic devices is becoming more and more extensive; and the performance of the power supply used for power supply and its impact on the circuit composed of electronic devices are also attracting more and more attention. Among them, undervoltage detection is the most common type of power supply voltage detection. The power supply voltage value is detected, and by comparison, it is judged whether the power supply voltage is lower than the preset value, so as to obtain information on whether there is undervoltage.

[0003] Generally, undervoltage detection is implemented through a comparator. The power supply voltage or its sampled signal is compared with the reference signal, and the comparison result is the undervoltage detection signal. During the power-on process, the undervoltage detection may be falsely triggered when the power supply voltage is small; in addition, it may also be falsely triggered when the power supply voltage fluctuates. When the subsequent circuit receives the undervoltage detection signal, it will make corresponding adjustments. Once falsely triggered, the subsequent circuit will inevitably make corresponding adjustments, which will affect the normal operation of the circuit.

[0004] Therefore, how to avoid false triggering of undervoltage detection and improve detection accuracy has become one of the problems that technical personnel in this field need to solve urgently.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present invention and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the present invention. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an undervoltage detection circuit and an electronic product, so as to solve the problem of poor undervoltage detection accuracy in the prior art.

[0007] To achieve the above-mentioned object and other related objects, the present invention provides an undervoltage detection circuit, which at least includes:

[0008] Startup module, benchmark generation module, benchmark establishment judgment module, undervoltage detection module and logic module;

[0009] The startup module is connected to the power supply voltage and is used to generate an initial state signal in the initial stage of power-on;

[0010] The reference generation module is connected to the output end of the start-up module and the power supply voltage, and is used to generate a reference signal;

[0011] The reference establishment judgment module is connected to the output ends of the start-up module and the reference generation module, and is also connected to the power supply voltage to judge whether the reference signal has been established, and output a valid reference establishment signal after the establishment is completed;

[0012] The undervoltage detection module is connected to the power supply voltage, detects the power supply voltage and outputs an undervoltage detection signal;

[0013] The logic module is connected to the output ends of the reference establishment judgment module and the undervoltage detection module, shields the undervoltage detection signal before the reference signal is established, and outputs the undervoltage detection signal after the reference signal is established.

[0014] Optionally, the reference generation module includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first triode, a second triode, a first resistor, a second resistor and a third resistor;

[0015] The sources of the first PMOS tube and the second PMOS tube are connected to the power supply voltage; the gate and drain of the first PMOS tube are connected to the collector of the first transistor; the emitter of the first transistor is grounded via the first resistor; the gate of the second PMOS tube is connected to the gate of the first PMOS tube, and the drain is connected to the collector of the second transistor; the emitter of the second transistor is connected to the connection node of the first transistor and the first resistor via the second resistor;

[0016] The source of the third PMOS tube is connected to the power supply voltage, the gate is connected to the drain of the second PMOS tube, and the drain is grounded via the third resistor; the bases of the first transistor and the second transistor are connected to the drain of the third PMOS tube.

[0017] Optionally, the startup circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth resistor;

[0018] The sources of the first NMOS tube and the second NMOS tube are grounded, and the gates are connected together; the drain of the first NMOS tube is connected to the gate of the third PMOS tube; the drain and gate of the second NMOS tube are connected and connected to the power supply voltage via the fourth resistor; the source of the third NMOS tube is grounded, the gate is connected to the drain of the third PMOS tube, and the drain is connected to the drain of the second NMOS tube; the drain of the second NMOS tube outputs the initial state signal.

[0019] Optionally, the reference establishment judgment module includes an initial state setting unit, a detection unit and a latch unit;

[0020] The initial state setting unit receives the initial state signal and provides an initial state for the latch unit based on the initial state signal;

[0021] The detection unit is connected to the reference generation module and is used to determine whether the reference signal has been established;

[0022] The latch unit is connected to the output end of the initial state setting unit and the detection unit to latch the detection result.

[0023] More optionally, the initial state setting unit provides a valid reset signal to the reset terminal of the latch unit when the initial state signal is valid.

[0024] More optionally, the initial state setting unit includes a fourth PMOS tube and a fifth resistor; the source of the fourth PMOS tube is connected to the power supply voltage, the gate receives the initial state signal, and the drain is grounded via the fifth resistor; the drain of the fourth PMOS tube serves as the output end of the initial state setting unit.

[0025] More optionally, the detection unit provides a valid set signal to the set terminal of the latch unit after establishing the reference signal.

[0026] More optionally, the detection unit includes a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth resistor and a seventh resistor;

[0027] The sources of the fifth PMOS tube and the sixth PMOS tube are connected to the power supply voltage, and the gates are connected to the bias voltage provided by the reference generation module; the drain of the fifth PMOS tube is connected to the drain of the fourth NMOS tube; the gate of the fourth NMOS tube is connected to the gate of the fifth NMOS tube, and the source is grounded; the drain of the sixth PMOS tube is connected to the source of the seventh PMOS tube; the gate and drain of the seventh PMOS tube are connected, and connected to the gate and drain of the fifth NMOS tube; the source of the fifth NMOS tube is grounded via the sixth resistor; one end of the seventh resistor is connected to the power supply voltage, and the other end is connected to the drain of the fifth PMOS tube and serves as the output end of the detection unit.

[0028] More optionally, the latch unit includes a first inverter, a second inverter, a third inverter, a first NOR gate and a second NOR gate;

[0029] The input end of the first inverter is connected to the output end of the initial state setting unit, and the output end is connected to the first input end of the first NOR gate; the input end of the second inverter is connected to the output end of the detection unit, and the output end is connected to the first input end of the second NOR gate; the second input end of the first NOR gate is connected to the output end of the second NOR gate, and the second input end of the second NOR gate is connected to the output end of the first NOR gate; the input end of the third inverter is connected to the output end of the second NOR gate, and the output end serves as the output end of the latch unit.

[0030] Optionally, the logic module is an AND logic unit.

[0031] To achieve the above-mentioned purpose and other related purposes, the present invention also provides an electronic product, which at least includes: a power supply generating circuit and the above-mentioned undervoltage detection circuit; the undervoltage detection circuit is connected to the power supply generating circuit to perform undervoltage detection on the power supply voltage output by the power supply generating circuit.

[0032] As described above, the undervoltage detection circuit and electronic product of the present invention have the following beneficial effects:

[0033] 1. The undervoltage detection circuit of the present invention has a simple structure. The reference establishment judgment module is combined with the start-up module, and only a small current is consumed to generate a reference establishment signal with strong stability.

[0034] 2. The undervoltage detection circuit of the present invention can not only filter out the glitch signal generated by the undervoltage detection module when the voltage is low during the power-on process, but also effectively shield the erroneous flipping of the undervoltage detection circuit caused by abnormal fluctuation of the power supply voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 Shown is a schematic block diagram of an undervoltage detection circuit of the present invention.

[0036] Figure 2 It is a schematic diagram showing the specific structure of the undervoltage detection circuit of the present invention.

[0037] Figure 3 Shown is a schematic diagram of waveforms of key nodes of the undervoltage detection circuit of the present invention.

[0038] Component number description

[0039] 1 Undervoltage detection circuit

[0040] 11 Startup Module

[0041] 12 Benchmark Generation Module

[0042] 13 Benchmark establishment judgment module

[0043] 131 Initial setting unit

[0044] 132 Detection Unit

[0045] 133 Latch Unit

[0046] 14 Undervoltage detection module

[0047] 15 Logic Module DETAILED DESCRIPTION

[0048] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0049] See also Figure 1 to Figure 3 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0050] like Figure 1 As shown, the present invention provides an undervoltage detection circuit 1, and the undervoltage detection circuit 1 includes:

[0051] A start-up module 11 , a reference generation module 12 , a reference establishment determination module 13 , an undervoltage detection module 14 and a logic module 15 .

[0052] like Figure 1 As shown, the reference generation module 12 is connected to the output end of the start-up module 11 and the power supply voltage VDD to generate a reference signal VREF.

[0053] Specifically, Figure 2As shown, in this embodiment, the reference generation module 12 includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first transistor Q1, a second transistor Q2, a first resistor R1, a second resistor R2 and a third resistor R3. The sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are connected to the power supply voltage VDD; the gate and the drain of the first PMOS transistor MP1 are connected to the collector of the first transistor Q1; the emitter of the first transistor Q1 is grounded via the first resistor R1; the gate of the second PMOS transistor MP2 is connected to the gate of the first PMOS transistor MP1, and the drain is connected to the collector of the second transistor Q2; the emitter of the second transistor Q2 is connected to the connection node of the first transistor Q1 and the first resistor R1 via the second resistor R2; in this example, the first transistor Q1 and the second transistor Q2 are NPN transistors. The source of the third PMOS transistor MP3 is connected to the power supply voltage VDD, the gate is connected to the drain of the second PMOS transistor MP2, and the drain is grounded via the third resistor R3; the drain of the third PMOS transistor MP3 outputs the reference signal VREF and is connected to the bases of the first transistor Q1 and the second transistor Q2.

[0054] More specifically, in this embodiment, the reference signal satisfies: VREF=VBE+VT*(lnN / R2)*(R1+R2), where V BE is the voltage difference between the base and emitter of the second transistor Q2, V T is the thermal voltage, and N is the proportionality coefficient between the first transistor Q1 and the second transistor Q2.

[0055] It should be noted that, in actual use, any circuit structure that can generate a reference signal is applicable to the present invention, and the value of the reference signal can be set as required, which will not be described in detail here.

[0056] like Figure 1 As shown, the startup module 11 is connected to the power supply voltage VDD and is used to generate an initial state signal CTR_P in the initial stage of power-on.

[0057] Specifically, Figure 2As shown, in this embodiment, the startup circuit 11 includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3 and a fourth resistor R4. The sources of the first NMOS transistor MN1 and the second NMOS transistor MN2 are grounded, and the gates are connected together; the drain of the first NMOS transistor MN1 is connected to the gate of the third PMOS transistor MP3; the drain and gate of the second NMOS transistor MN2 are connected and connected to the power supply voltage VDD via the fourth resistor R4; the source of the third NMOS transistor MN3 is grounded, the gate is connected to the drain of the third PMOS transistor MP3, and the drain is connected to the drain of the second NMOS transistor MN2; the drain of the second NMOS transistor MN2 outputs the initial state signal CTR_P.

[0058] More specifically, as the power supply voltage VDD rises, the initial state signal CTR_P gradually rises to a high level, the second NMOS tube MN2 is turned on, and the current flowing through the second NMOS tube MN2 is proportionally mirrored to the drain of the first NMOS tube MN1 via the current mirror structure formed by the second NMOS tube MN2 and the first NMOS tube MN1, thereby pulling down the gate voltage of the third PMOS tube MP3, so that the reference generation module 12 is separated from the degenerate point and the startup is completed. When the reference signal VREF is established to a certain extent, the third NMOS tube MN3 is turned on, pulling down the drain voltage of the second NMOS tube MN2, the initial state signal CTR_P is at a low level, the current flowing through the second NMOS tube MN2 is 0, the startup module 11 fails (saving energy consumption), and has no effect on the subsequent circuit.

[0059] It should be noted that the structure of the start module 11 can be set according to the specific structure of the reference generation module 12, and any circuit structure that can provide the initial state signal CTR_P (start signal) is applicable to the present invention and is not limited to this embodiment.

[0060] like Figure 1 As shown, the reference establishment judgment module 13 is connected to the output ends of the startup module 11 and the reference generation module 12, and is also connected to the power supply voltage VDD to judge whether the reference signal VREF is established, and output a valid reference establishment signal BG_OK after the establishment is completed.

[0061] Specifically, Figure 2As shown, in this embodiment, the reference establishment judgment module 13 includes an initial state setting unit 131, a detection unit 132 and a latch unit 133. The initial state setting unit 131 receives the initial state signal CTR_P, and provides an initial state for the latch unit 133 based on the initial state signal CTR_P; the detection unit 132 is connected to the reference generation module 12, and is used to determine whether the reference signal VREF has been established; the latch unit 133 is connected to the output ends of the initial state setting unit 131 and the detection unit 132, and latches the detection result to prevent the spike of the power supply voltage VDD from affecting the stability of the detection result.

[0062] Specifically, in this embodiment, the initial state setting unit 131 provides a valid reset signal to the reset terminal of the latch unit 133 when the initial state signal CTR_P is valid. Figure 2 As shown, as an example, the initial state setting unit 131 includes a fourth PMOS tube MP4 and a fifth resistor R5; the source of the fourth PMOS tube MP4 is connected to the power supply voltage VDD, the gate receives the initial state signal CTR_P, and the drain is grounded via the fifth resistor R5; the drain of the fourth PMOS tube serves as the output end of the initial state setting unit 131.

[0063] More specifically, when the initial state signal CTR_P is at a low level, the fourth PMOS tube MP4 is turned on, and the drain (node ​​A) voltage of the fourth PMOS tube MP4 follows the power supply voltage VDD. When the initial state signal CTR_P is at a high level, the fourth PMOS tube MP4 is turned off, and the drain (node ​​A) voltage of the fourth PMOS tube MP4 is pulled down. As the power supply voltage VDD increases from low, the initial state signal CTR_P gradually increases following VDD. The initial state signal CTR_P is the gate drive voltage of the fourth PMOS tube, so the fourth PMOS tube MP4 is in a closed state at the beginning, and point A is pulled down to the ground through the fifth resistor R5; when the reference generation module 12 completes the startup, the initial state signal CTR_P is pulled low, and the fourth PMOS tube MP4 is in a conducting state at this time, and the potential of point A follows the power supply voltage VDD, so the voltage at point A is a signal from low to high level during the power-on process of the power supply voltage VDD, and this signal serves as the initial state of the latch unit 133.

[0064] Specifically, in this embodiment, the detection unit 132 provides a valid set signal to the set terminal of the latch unit 133 after establishing the reference signal VREF. Figure 2As shown, as an example, the detection unit 132 includes a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth resistor R6 and a seventh resistor R7. The sources of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are connected to the power supply voltage VDD, and the gates are connected to the bias voltage provided by the reference generation module 12 (in this example, connected to the gates of the first PMOS transistor MP1 and the second PMOS transistor MP1); the drain of the fifth PMOS transistor MP5 is connected to the drain of the fourth NMOS transistor MN4; the gate of the fourth NMOS transistor MN4 is connected to the gate of the fifth NMOS transistor MN5, and the source is grounded; the drain of the sixth PMOS transistor MP6 is connected to the source of the seventh PMOS transistor MP6; the gate and drain of the seventh PMOS transistor MP6 are connected, and are connected to the gate and drain of the fifth NMOS transistor MN5; the source of the fifth NMOS transistor MN5 is grounded via the sixth resistor R6; one end of the seventh resistor R7 is connected to the power supply voltage VDD, and the other end is connected to the drain of the fifth PMOS transistor MP5 and serves as the output end of the detection unit 132.

[0065] More specifically, before the reference signal VREF is established, as the power supply voltage VDD increases, the currents of the first transistor Q1 and the second transistor Q2 start to increase from 0, and the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 mirror the current in the reference generation module 12. However, since the power supply voltage VDD is relatively low in the initial stage of power-on, the seventh PMOS transistor MP7 (diode structure) and the sixth resistor R6 cause the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 to be in a cut-off state, and the level of the output signal BG_OK_PRE of the detection unit 132 is determined by the seventh resistor R7. At this time, the output signal BG_OK_PRE of the detection unit 132 follows the power supply voltage VDD. When the reference signal VREF is established, the fifth PMOS transistor MP5, the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 pull up the gates of the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 to be turned on, and the output signal BG_OK_PRE of the detection unit 132 is pulled low by the fourth NMOS transistor MN4.

[0066] Specifically, in this embodiment, the latch unit 133 includes a first inverter not1, a second inverter not2, a third inverter not3, a first NOR gate nor1 and a second NOR gate nor2. The input end of the first inverter not1 is connected to the output end of the initial state setting unit 131, and the output end is connected to the first input end of the first NOR gate nor1; the input end of the second inverter not2 is connected to the output end of the detection unit 132, and the output end is connected to the first input end of the second NOR gate nor2; the second input end of the first NOR gate nor1 is connected to the output end of the second NOR gate nor2, and the second input end of the second NOR gate nor2 is connected to the output end of the first NOR gate nor1; the input end of the third inverter not3 is connected to the output end of the second NOR gate nor2, and the output end serves as the output end of the latch unit 133.

[0067] Specifically, the latch unit 133 is used to latch the detection result. When the power supply voltage VDD has a spike, the output signal BG_OK of the latch unit 133 is maintained (maintained at a low level before the reference signal is established, and maintained at a high level after the reference signal is established), which does not affect the output result of the undervoltage detection circuit.

[0068] It should be noted that any circuit structure capable of determining whether a reference signal is established is applicable to the reference establishment determination module 13 of the present invention, and is not limited to this embodiment.

[0069] like Figure 1 As shown, the undervoltage detection module 14 is connected to the power supply voltage VDD, detects the power supply voltage VDD and outputs an undervoltage detection signal.

[0070] Specifically, any circuit structure capable of implementing undervoltage detection is applicable to the undervoltage detection module 14 of the present invention. As an example, the undervoltage detection module 14 includes a comparator (not shown in the figure), which will not be described in detail here.

[0071] like Figure 1 As shown, the logic module 15 is connected to the output ends of the reference establishment judgment module 13 and the undervoltage detection module 14, shields the undervoltage detection signal UVLO_PRE before the reference signal is established, and outputs the undervoltage detection signal UVLO_PRE after the reference signal is established (the output signal of the logic module 15 is UVLO).

[0072] Specifically, before the reference signal VREF is established (during the power-on process of the power supply voltage VDD), the output signal UVLO_PRE of the undervoltage detection module 14 cannot be output, and at this time, the burr or misdetection of the undervoltage detection module will not affect the final output UVLO. After the reference signal VREF is established, the reference establishment judgment module 13 maintains a stable output (high level) and does not change the state of the output signal UVLO of the undervoltage detection circuit 1. The output signal UVLO of the undervoltage detection circuit 1 is determined by the undervoltage detection signal UVLO_PRE output by the undervoltage detection module 14.

[0073] Specifically, in this embodiment, the logic module 15 is implemented by an AND logic unit. Before the reference signal is established, the reference establishment signal BG_OK is invalid (low level); after the reference signal is established, the reference establishment signal BG_OK is valid (high level). When no undervoltage is detected, the undervoltage detection signal UVLO_PRE and the output signal UVLO of the undervoltage detection circuit 1 are invalid (high level); when undervoltage is detected, the undervoltage detection signal UVLO_PRE and the output signal UVLO of the undervoltage detection circuit 1 are valid (low level).

[0074] like Figure 3 As shown, the initial state signal CTR_P provides an initial state for the reference generation module 12 during the power-on process of the power supply voltage VDD, so that the reference generation module 12 can escape from the degeneracy point and be established normally. The reference establishment judgment module 13 mirrors the reference current generated by the reference generation module 12. Before the reference signal is established, the reference establishment signal BG_OK maintains a low level, shielding the undervoltage detection signal UVLO_PRE, thereby filtering out the burr signal generated by the undervoltage detection module at a lower voltage during the power-on process, avoiding the output signal UVLO of the undervoltage detection circuit 1 from being falsely triggered. The output signal UVLO of the undervoltage detection circuit 1 is a low level. When the reference signal is established to a certain extent, the reference establishment signal BG_OK will flip from a low level to a high level, and will be latched through the latch unit 133 when a spike occurs in the power supply voltage VDD. The reference establishment signal BG_OK is maintained at a high level. At this time, the output signal UVLO of the undervoltage detection circuit 1 follows the change of the undervoltage detection signal UVLO_PRE; when the power supply voltage VDD is maintained above the undervoltage point, the undervoltage detection signal UVLO_PRE outputs a high level. After passing through the logic AND gate, the output signal UVLO of the undervoltage detection circuit 1 outputs a high level, and the subsequent circuit works normally; when the power supply voltage VDD continues to decrease, the undervoltage detection signal UVLO_PRE is triggered to become a low level. After passing through the logic AND gate, the output signal UVLO of the undervoltage detection circuit 1 jumps to a low level, which can be used to shut down the subsequent circuit.

[0075] The present invention also provides an electronic product, which at least includes: a power generation circuit and the undervoltage detection circuit 1; the undervoltage detection circuit 1 is connected to the power generation circuit to perform undervoltage detection on the power voltage output by the power generation circuit. The undervoltage detection circuit 1 of the present invention can be used in any occasion requiring undervoltage detection, and will not be described in detail here.

[0076] In summary, the present invention provides an undervoltage detection circuit and an electronic product, comprising: a startup module, a reference generation module, a reference establishment judgment module, an undervoltage detection module and a logic module; the startup module is connected to the power supply voltage, and is used to generate an initial state signal in the initial stage of power-on; the reference generation module is connected to the output end of the startup module and the power supply voltage, and is used to generate a reference signal; the reference establishment judgment module is connected to the output end of the startup module and the reference generation module, and is also connected to the power supply voltage, to judge whether the reference signal has been established, and output a valid reference establishment signal after the establishment is completed; the undervoltage detection module is connected to the power supply voltage, detects the power supply voltage and outputs an undervoltage detection signal; the logic module is connected to the output end of the reference establishment judgment module and the undervoltage detection module, shields the undervoltage detection signal before the reference signal is established, and outputs the undervoltage detection signal after the reference signal is established. The undervoltage detection circuit of the present invention has a simple structure, and the reference establishment judgment module is combined with the start-up module, and only a small current is consumed to generate a reference establishment signal with strong stability; the undervoltage detection circuit of the present invention can not only filter out the burr signal generated by the undervoltage detection module at a low voltage during the power-on process, but also effectively shield the erroneous flipping of the undervoltage detection circuit caused by abnormal fluctuations in the power supply voltage. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0077] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. An undervoltage detection circuit, characterized in that: The undervoltage detection circuit at least comprises: Startup module, benchmark generation module, benchmark establishment judgment module, undervoltage detection module and logic module; The startup module is connected to the power supply voltage and is used to generate an initial state signal in the initial stage of power-on; The reference generation module is connected to the output end of the start-up module and the power supply voltage, and is used to generate a reference signal; The reference establishment judgment module is connected to the output ends of the start-up module and the reference generation module, and is also connected to the power supply voltage to judge whether the reference signal has been established, and output a valid reference establishment signal after the establishment is completed; The undervoltage detection module is connected to the power supply voltage, detects the power supply voltage and outputs an undervoltage detection signal; The logic module is connected to the output ends of the reference establishment judgment module and the undervoltage detection module, shields the undervoltage detection signal before the reference signal is established, and outputs the undervoltage detection signal after the reference signal is established.

2. The undervoltage detection circuit according to claim 1, characterized in that: The reference generation module includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first triode, a second triode, a first resistor, a second resistor and a third resistor; The sources of the first PMOS tube and the second PMOS tube are connected to the power supply voltage; the gate and drain of the first PMOS tube are connected to the collector of the first transistor; the emitter of the first transistor is grounded via the first resistor; the gate of the second PMOS tube is connected to the gate of the first PMOS tube, and the drain is connected to the collector of the second transistor; the emitter of the second transistor is connected to the connection node of the first transistor and the first resistor via the second resistor; The source of the third PMOS tube is connected to the power supply voltage, the gate is connected to the drain of the second PMOS tube, and the drain is grounded via the third resistor; the bases of the first transistor and the second transistor are connected to the drain of the third PMOS tube.

3. The undervoltage detection circuit according to claim 2, characterized in that: The startup circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth resistor; The sources of the first NMOS tube and the second NMOS tube are grounded, and the gates are connected together; the drain of the first NMOS tube is connected to the gate of the third PMOS tube; the drain and gate of the second NMOS tube are connected and connected to the power supply voltage via the fourth resistor; the source of the third NMOS tube is grounded, the gate is connected to the drain of the third PMOS tube, and the drain is connected to the drain of the second NMOS tube; the drain of the second NMOS tube outputs the initial state signal.

4. The undervoltage detection circuit according to claim 1, characterized in that: The reference establishment judgment module includes an initial state setting unit, a detection unit and a latch unit; The initial state setting unit receives the initial state signal and provides an initial state for the latch unit based on the initial state signal; The detection unit is connected to the reference generation module and is used to determine whether the reference signal has been established; The latch unit is connected to the output end of the initial state setting unit and the detection unit to latch the detection result.

5. The undervoltage detection circuit according to claim 4, characterized in that: The initial state setting unit provides a valid reset signal to the reset terminal of the latch unit when the initial state signal is valid.

6. The undervoltage detection circuit according to claim 4 or 5, characterized in that: The initial state setting unit includes a fourth PMOS tube and a fifth resistor; the source of the fourth PMOS tube is connected to the power supply voltage, the gate receives the initial state signal, and the drain is grounded via the fifth resistor; the drain of the fourth PMOS tube serves as the output end of the initial state setting unit.

7. The undervoltage detection circuit according to claim 4, characterized in that: The detection unit provides a valid setting signal to the setting terminal of the latch unit after establishing the reference signal.

8. The undervoltage detection circuit according to claim 4 or 7, characterized in that: The detection unit includes a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth resistor and a seventh resistor; The sources of the fifth PMOS tube and the sixth PMOS tube are connected to the power supply voltage, and the gates are connected to the bias voltage provided by the reference generation module; the drain of the fifth PMOS tube is connected to the drain of the fourth NMOS tube; the gate of the fourth NMOS tube is connected to the gate of the fifth NMOS tube, and the source is grounded; the drain of the sixth PMOS tube is connected to the source of the seventh PMOS tube; the gate and drain of the seventh PMOS tube are connected, and connected to the gate and drain of the fifth NMOS tube; the source of the fifth NMOS tube is grounded via the sixth resistor; one end of the seventh resistor is connected to the power supply voltage, and the other end is connected to the drain of the fifth PMOS tube and serves as the output end of the detection unit.

9. The undervoltage detection circuit according to claim 4, characterized in that: The latch unit includes a first inverter, a second inverter, a third inverter, a first NOR gate and a second NOR gate; The input end of the first inverter is connected to the output end of the initial state setting unit, and the output end is connected to the first input end of the first NOR gate; the input end of the second inverter is connected to the output end of the detection unit, and the output end is connected to the first input end of the second NOR gate; the second input end of the first NOR gate is connected to the output end of the second NOR gate, and the second input end of the second NOR gate is connected to the output end of the first NOR gate; the input end of the third inverter is connected to the output end of the second NOR gate, and the output end serves as the output end of the latch unit.

10. The undervoltage detection circuit according to claim 1, characterized in that: The logic module is an AND logic unit.

11. An electronic product, characterized in that: The electronic product at least comprises: a power generation circuit and an undervoltage detection circuit as described in any one of claims 1 to 10; the undervoltage detection circuit is connected to the power generation circuit and performs undervoltage detection on the power supply voltage output by the power generation circuit.

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