Noise test information generation method and device, noise evaluation method and device, medium and product

Abstract

The invention discloses a noise test information generation and noise evaluation method and device, a medium and a product, and relates to the technical field of servers, and the method comprises the steps: carrying out the noise test of test circuit boards corresponding to different circuit board parameter groups, obtaining a noise value, and carrying out the noise evaluation based on the circuit board parameter groups, corresponding noise influence objects, noise source regions and noise values, and generating total noise test information. When the noise influence of the circuit board is evaluated, the noise value of the to-be-evaluated circuit board can be determined in the total noise test information based on the circuit board parameter group, the noise influence object and the noise source area of the to-be-evaluated circuit board, and then the noise evaluation information is generated according to the noise value and the maximum noise threshold evaluation. And indicating whether to adjust the to-be-evaluated circuit board. Thus, under the condition that adjustment is determined, the total noise test information can be used as reference to adjust the circuit board instead of using fixed circuit board parameters to design the circuit, and the problem of waste of hardware resources can be reduced.

Description

Technical Field

[0001] The present application relates to the field of server technology, and in particular to noise test information generation and noise assessment methods, devices, media and products. Background Art

[0002] In the field of server technology, a server includes a printed circuit board (PCB). The power supply on the PCB will produce rapid voltage and current changes during the switching process, thereby interfering with other components on the PCB, which is power supply noise.

[0003] Currently, in order to reduce the impact of noise on other components on the PCB, the arrangement of devices on the PCB is generally designed according to common design rules. In this way, different PCBs use the same design rules, which will lead to a waste of hardware resources. Summary of the invention

[0004] The present application provides a noise test information generation and noise evaluation method, device, electronic device, storage medium, and program product to at least solve the problem of hardware resource waste in the related art.

[0005] The present application provides a method for generating noise test information, comprising: Acquire at least one noise-affected object and at least one noise source area; Combining any one of the at least one noise-affecting object and any one of the at least one noise source area in pairs, respectively, to obtain at least one noise factor combination; According to the noise-affecting objects and noise source areas in each noise factor combination and the circuit board parameters matching the noise factor combination in the pre-built circuit board parameter pool, a plurality of circuit board parameter groups corresponding to each noise factor combination are generated; Performing noise tests on the test circuit boards corresponding to each circuit board parameter group to obtain noise values ​​corresponding to each circuit board parameter group; According to each noise factor combination, a plurality of circuit board parameter groups corresponding to each noise factor combination, and a noise value corresponding to each circuit board parameter group, total noise test information is generated to evaluate whether the noise of the circuit board is within a preset noise range.

[0006] The present application also provides a noise test information generating device, comprising: A first acquisition module, used to acquire at least one noise-affected object and at least one noise source area; a combining module, used to respectively combine any one of the at least one noise-affecting object and any one of the at least one noise source area in pairs to obtain at least one noise factor combination; A first generating module is used to generate a plurality of circuit board parameter groups corresponding to each noise factor combination according to the noise impact object and the noise source area in each noise factor combination and the circuit board parameters matching the noise factor combination in the pre-built circuit board parameter pool; A test module, used to perform noise tests on the test circuit boards corresponding to each circuit board parameter group, respectively, to obtain noise values ​​corresponding to each circuit board parameter group; The first generating module is also used to generate total noise test information according to each noise factor combination, multiple circuit board parameter groups corresponding to each noise factor combination, and the noise value corresponding to each circuit board parameter group, so as to evaluate whether the noise of the circuit board is within a preset noise range.

[0007] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any one of the above-mentioned noise test information generation methods when executing the computer program.

[0008] The present application also provides a computer-readable storage medium, in which a computer program is stored, wherein when the computer program is executed by a processor, the steps of any one of the above-mentioned noise test information generating methods are implemented.

[0009] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned noise test information generation methods when executed by a processor.

[0010] Through this application, since a larger circuit board parameter threshold is generally given in the general design rules, technicians design circuits based on the larger circuit board parameter threshold, resulting in frequent waste of hardware resources. However, this application can indicate whether the circuit board meets the noise regulations corresponding to the circuit board based on the actual total noise test information, thereby guiding technicians to make adjustments, so that the circuit board design of each project can meet the personalized regulations of the project, that is, the circuit board can be laid out using more accurate circuit board parameters, rather than using the specified circuit board parameter threshold for design, which can reduce the problem of hardware resource waste.

[0011] The present application provides a noise assessment method, comprising: Obtaining a circuit board parameter group, a noise influencing object, a noise source area, and a maximum noise threshold corresponding to the circuit board to be evaluated; According to the circuit board parameter group, the noise influencing object, and the noise source area, the noise value corresponding to the circuit board to be evaluated is determined in the pre-acquired total noise test information, wherein the total noise test information is generated according to the above-mentioned noise test information generation method; Determine a noise test result based on a noise value corresponding to the circuit board to be evaluated and a maximum noise threshold; After performing an operation corresponding to the noise test result according to the noise test result, noise evaluation information of the circuit board to be evaluated is generated, wherein the noise evaluation information is used to indicate whether to adjust the circuit board to be evaluated.

[0012] The present application also provides a noise assessment device, comprising: A second acquisition module is used to acquire a circuit board parameter group, a noise impact object, a noise source area, and a maximum noise threshold corresponding to the circuit board to be evaluated; A determination module is used to determine the noise value corresponding to the circuit board to be evaluated in the pre-acquired total noise test information according to the circuit board parameter group, the noise influencing object, and the noise source area, wherein the total noise test information is generated according to the above-mentioned noise test information generation method; determine the noise test result according to the noise value corresponding to the circuit board to be evaluated and the maximum noise threshold; The second generating module is used to generate noise evaluation information of the circuit board to be evaluated after executing an operation corresponding to the noise test result according to the noise test result, wherein the noise evaluation information is used to indicate whether to adjust the circuit board to be evaluated.

[0013] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any one of the above-mentioned noise assessment methods when executing the computer program.

[0014] The present application also provides a computer-readable storage medium, in which a computer program is stored, wherein when the computer program is executed by a processor, the steps of any one of the above-mentioned noise assessment methods are implemented.

[0015] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned noise assessment methods when executed by a processor.

[0016] Through the present application, in the process of evaluating a circuit board, the circuit board parameter group, noise influencing object, noise source area, and maximum noise threshold of the current circuit board (i.e., the circuit board to be evaluated) can be first obtained. Furthermore, based on the circuit board parameter group, noise influencing object, and noise source area, the noise value corresponding to the circuit board to be evaluated can be determined in the pre-acquired total noise test information. In this way, there is no need to perform real-time noise testing, which can improve the evaluation efficiency. In addition, according to the noise value corresponding to the circuit board to be evaluated and the maximum noise threshold corresponding to the circuit board to be evaluated, the noise test result can be determined, and then the noise evaluation information is generated according to the noise test result, indicating whether the technician adjusts the evaluation circuit board, so that the circuit board parameters can be accurately adjusted, rather than directly using larger circuit board parameters to design the circuit board, which can reduce the occurrence of hardware resource waste. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 A schematic diagram of the architecture of a noise testing system provided in an embodiment of the present application; Figure 2 A flowchart of a noise test information generating method provided in an embodiment of the present application; Figure 3 A schematic diagram of the positional relationship between a noise hole and a routing line provided in an embodiment of the present application; Figure 4 A schematic diagram of the positional relationship between a power plane and a routing provided in an embodiment of the present application; Figure 5 A schematic cross-sectional diagram of noise interference provided in an embodiment of the present application; Figure 6 A schematic diagram of the distance relationship between different noise source areas of a wiring and a power supply provided in an embodiment of the present application; Figure 7 A schematic diagram of the distance relationship between different noise source areas of another wiring and power supply provided in an embodiment of the present application; Figure 8 A flowchart of a noise assessment method provided in an embodiment of the present application; Fig. 9 A circuit diagram of a power supply provided in an embodiment of the present application; Fig.10 A schematic diagram of a circuit board layout of a power supply provided in an embodiment of the present application; Fig.11 A schematic diagram of the structure of a noise test information generating device provided in an embodiment of the present application; Fig.12 A schematic diagram of the structure of a noise assessment device provided in an embodiment of the present application; Fig.13 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0020] It should be noted that, in the description of this application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in this application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0021] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0022] The embodiments of the present application can be implemented by a noise testing system, such as Figure 1 As shown, the noise test system may include a target device, a noise meter, a power supply, and a circuit board. The target device may be a computer device, such as a desktop computer or a laptop computer. The noise meter may be a frequency domain noise meter and a time domain noise meter. Both the power supply and the circuit board may be printed circuit boards (PCBs). The power supply is used to generate noise to test the noise impact of the power supply on the test circuit board. The noise meter is used to measure the noise on the test circuit board. The circuit board may be a test circuit board, a verification circuit board, and a circuit board to be evaluated. The power supply may be a separate power supply circuit board electrically connected to the circuit board, or the power supply may be located on the circuit board.

[0023] The embodiment of the present application provides a noise test generation method, which can be executed by the above-mentioned target device, such as Figure 2 As shown, the method may specifically include the following steps: Step S201: Acquire at least one noise-affected object and at least one noise source area.

[0024] Among them, the objects affected by noise can be traces, signal holes, etc. on the circuit board. Traces can also be called signal traces, which are paths for transmitting data or control signals. Signal holes can be vias used to transfer current or signals from one layer of the circuit board to another layer.

[0025] The noise source region may be a field-effect transistor (FET) region (also referred to as a field-effect transistor node), a phase region (also referred to as a phase node), an inductor region, etc. in a power supply. The field-effect transistor region may be a region including a field-effect transistor. The phase region may be a region where the phase of a signal changes. The inductor region may be a region where an inductor is located.

[0026] Specifically, the technician can input the noise impact object and the noise source area to be tested on the target device, and the target device can obtain at least one noise impact object and at least one noise source area.

[0027] Step S202: Combining any one of the at least one noise influencing object and any one of the at least one noise source area in pairs, respectively, to obtain at least one noise factor combination.

[0028] Specifically, the target device can combine the noise-affecting objects and the noise source areas in pairs to obtain at least one noise factor combination. For example, the noise-affecting objects include routing, and the noise source areas include field effect transistor areas and phase areas. After the pairwise combination, the obtained noise factor combination can include [routing, field effect transistor area] and [routing, phase area].

[0029] Step S203, generating a plurality of circuit board parameter groups corresponding to each noise factor combination according to the noise impact object and the noise source area in each noise factor combination and the circuit board parameters matching the noise factor combination in the pre-built circuit board parameter pool.

[0030] Among them, the circuit board parameter pool may include one or more elements in the circuit board parameter pool, including the spacing between noise holes (Noisy VR vias) and traces, the number of ground layers (GND) between the power plane (Power Plane) and the traces, the spacing between the power plane and the traces, the number of ground layers between the power plane and the traces, the spacing between the noise holes and the traces, the inductance, the spacing between the noise holes and the signal holes, etc. The noise hole is a via on the power supply that produces noise on the circuit board. The power plane is an important component in the printed circuit board, mainly used to provide a stable power supply and a low-impedance path to ensure that each component in the circuit can obtain the required operating voltage. The power plane is usually a large area of ​​copper layer that covers the entire or part of the PCB layer.

[0031] For example, Figure 3 The positional relationship between the noise hole and the trace is shown, where the trace can be between two ground layers and the noise hole can pass through the two ground layers. Figure 4 The positional relationship between the power plane and the trace is shown. The trace can be between the power plane and the ground layer. Figure 5 As shown, the power supply transmits current to the load through the power plane and the noise hole (the current transmission path can be referred to Figure 5 Indicated by the arrow in the figure), during the current transmission process, the noise generated will also affect the traces on the test circuit board through the power plane and noise holes. Figure 5 D1, D2, and D3 may be the corresponding spacings between the noise hole and the three traces.

[0032] Step 1: According to the target noise influencing object and the target noise source area included in the target noise factor combination, at least one circuit board parameter matching both the target noise influencing object and the target noise source area is selected from a circuit board parameter pool.

[0033] The target noise factor combination is any one of the multiple noise factor combinations.

[0034] Specifically, when the target noise impact object is determined to be a routing line and the target noise source area is a field effect transistor area, the target device can select one or more elements of the spacing between the noise hole and the routing line, and the number of ground layers between the power plane and the routing line as circuit board parameters that match both the target noise impact object and the target noise source area. When the target noise impact object is determined to be a routing line and the target noise source area is a phase area, one or more elements of the spacing between the power plane and the routing line, the number of ground layers between the power plane and the routing line, and the spacing between the noise hole and the routing line are selected as circuit board parameters that match both the target noise impact object and the target noise source area. When the target noise impact object is determined to be a routing line or a signal hole and the target noise source area is an inductance area, the inductance is selected as a circuit board parameter that matches both the target noise impact object and the target noise source area. When the target noise impact object is determined to be a signal hole and the target noise source area is a field effect transistor area or a phase area, the spacing between the noise hole and the signal hole is selected as a circuit board parameter that matches both the target noise impact object and the target noise source area.

[0035] Since different noise factor combinations correspond to different types of circuit board parameters, the corresponding circuit board parameters can be selected from the circuit board parameter pool and the corresponding circuit board parameter group can be generated based on the noise factor combination. This can avoid the resource waste problem caused by using all circuit board parameters for each group of circuit board parameters, and ensure the comprehensiveness of the test (that is, the noise values ​​extracted from different sub-noise test information can be combined later) and accuracy.

[0036] Step 2: According to each circuit board parameter, a parameter value generation rule corresponding to each circuit board parameter is obtained.

[0037] The parameter value generation rules include the initial parameter value, the step size, and the number of parameter values.

[0038] Specifically, the target device may store a first correspondence between circuit board parameters and parameter value generation rules. In this way, after the target device determines the circuit board parameters that match both the target noise impact object and the target noise source area, for each circuit board parameter, the target device may determine the parameter value generation rule corresponding to the circuit board parameter based on the circuit board parameter and the first correspondence.

[0039] Step three: generating a plurality of circuit board parameter groups corresponding to target noise factor combinations according to parameter value generation rules corresponding to each circuit board parameter and preset permutation and combination rules.

[0040] Specifically, taking the target circuit board parameters (any circuit board parameters that match both the target noise affecting object and the target noise source area) as an example, the target device can use the initial parameter value included in the parameter value generation rule corresponding to the target circuit board parameters as the starting value, and use the step size as the adjustment value to adjust the starting value multiple times to obtain a number of parameter values ​​equal to the number of parameter values ​​included in the parameter value generation rule corresponding to the target circuit board parameters (the difference between adjacent parameter values ​​is the step size included in the parameter value generation rule corresponding to the target circuit board parameters).

[0041] Step S204, performing noise tests on the test circuit boards corresponding to each circuit board parameter group, respectively, to obtain noise values ​​corresponding to each circuit board parameter group.

[0042] Specifically, the technician can design a test circuit board corresponding to each circuit board parameter group and connect it to the above-mentioned noise test system, that is, the circuit board in the noise test system is a test circuit board. In this way, the technician can input the control instruction in the target device. After the target device obtains the control instruction, it can perform a noise test on the test circuit board according to the preset test process to obtain the noise value corresponding to the circuit board parameter group. Accordingly, the target device can complete the noise test process according to the following specific steps: Step 1: adjusting the state of a power supply connected to a target test circuit board to perform a noise test on the target test circuit board.

[0043] The target test circuit board is a test circuit board corresponding to the second circuit board parameter group, and the second circuit board parameter group is any one circuit board parameter group among a plurality of circuit board parameter groups corresponding to each noise factor combination.

[0044] Step 2: Send a test instruction to a noise measuring instrument connected to the target test circuit board to instruct the noise measuring instrument to monitor and feed back target noise test information of the target test circuit board.

[0045] Step three, analyzing the target noise test information to obtain a target noise value corresponding to the second circuit board parameter group.

[0046] Specifically, taking the target test circuit board as an example, the target device can adjust the state of the power supply connected to the target test circuit board, for example, turn on the power supply so that it can output current to the target test circuit board. In addition, the target device can send a test instruction to the noise measuring instrument. After receiving the test instruction, the noise measuring instrument can start to measure the noise affecting object in the target test circuit board to detect the target noise test information of the target test circuit board and feed it back to the target device. The target device can analyze the target noise test information to determine the noise value.

[0047] For example, Figure 6 and Figure 7 The circuit board layout of the power supply is shown in Figure 1. Figure 6 and Figure 7 In the power supply shown, the noise source area includes the field effect transistor area ( Figure 6 FET nodes in the phase region ( Figure 6 In addition, the circuit board of the power supply may also include multiple nodes such as input inductor, power input node, capacitor, resistor, boot network (Boot Net), phase network (Phase Net), grounding, output inductor, power output, etc. When the target noise influencing object is the trace and the target noise source area is the field effect transistor area, the distance from the trace on the target test circuit board to the field effect transistor area is less than the distance from the trace on the target test circuit board to the phase area, such as Figure 6 As shown, S1 is the distance from the trace on the target test circuit board to the field effect transistor area (black bold frame), and S2 is the distance from the trace on the target test circuit board to the phase area. Since both the field effect transistor area and the phase area of ​​the power supply will have noise effects on the traces, therefore, when the target noise source area is the field effect transistor area, the above-mentioned trace arrangement method can reduce the noise effect of the phase area on the traces, thereby making the determined target noise value more accurate. For example, S2 can be greater than 30mil (an imperial unit, 1mil equals one thousandth of an inch).

[0048] On the contrary, under the same circuit board structure, when the target noise influencing object is the trace and the target noise source area is the phase area, the distance from the trace on the target test circuit board to the field effect transistor area is greater than the distance from the trace on the target test circuit board to the phase area, such as Figure 7 As shown, S3 is the area from the trace to the field effect transistor on the target test circuit board ( Figure 7 The distance from the field effect transistor node in the target test circuit board to the phase region ( Figure 7 The distance from the phase node in the circuit is a bold black box). Since both the field effect transistor region and the phase region of the power supply will have noise impact on the routing, when the target noise source region is the phase region, the above routing arrangement can reduce the noise impact of the field effect transistor region on the routing, thereby making the determined target noise value more accurate. For example, S3 can be greater than 30mil.

[0049] Step S205, generating total noise test information according to each noise factor combination, the multiple circuit board parameter groups corresponding to each noise factor combination, and the noise value corresponding to each circuit board parameter group, to evaluate whether the noise of the circuit board is within a preset noise range.

[0050] The total noise test information may be composed of one or more data tables.

[0051] Step 1: generating sub-noise test information corresponding to the target noise factor combination according to each circuit board parameter group in a plurality of circuit board parameter groups corresponding to the target noise factor combination and the corresponding noise value.

[0052] The sub-noise test information may be in the form of a table.

[0053] Step 2: Generate total noise test information based on the sub-noise test information corresponding to each noise factor combination.

[0054] Specifically, for the target noise factor combination, the target device can use a circuit board parameter group and the noise value corresponding to the circuit board parameter group as a noise test data, so that the target device can generate a noise test data corresponding to each of the multiple circuit board parameter groups corresponding to the target noise factor combination according to each of the multiple circuit board parameter groups corresponding to the target noise factor combination and the corresponding noise value. These noise test data constitute sub-noise test information corresponding to the target noise factor combination.

[0055] Based on the above method, the target device can determine the sub-noise test information corresponding to each noise factor combination for each noise factor combination. Furthermore, the target device can generate the total noise test information in the following two ways: Method 1: The sub-noise test information corresponding to all noise factor combinations are jointly determined as the total noise test information.

[0056] Method 2 Step 1: when it is determined that there are multiple noise factor combinations to be processed including a target noise influencing object, generate parent noise test information corresponding to the target noise influencing object according to the child noise test information corresponding to each noise factor combination to be processed.

[0057] The parent noise test information may be in the form of a table.

[0058] Step 1 may specifically include: Step a: In the current processing round, a noise value corresponding to the current processing round is extracted from each noise test information corresponding to each noise factor combination to be processed, and the noise value combination corresponding to the current processing round is obtained. After the last processing round is completed, multiple noise value combinations are obtained.

[0059] Step b: calculating a total noise value corresponding to the target noise value combination according to all noise values ​​included in the target noise value combination.

[0060] The target noise value combination is any one of the multiple noise value combinations.

[0061] Step c: generating parent noise test information corresponding to the target noise impact object according to each noise value combination and the total noise value corresponding to each noise value combination.

[0062] Specifically, the target device may first determine whether there are multiple noise factor combinations to be processed including the target noise influencing object in the above-mentioned noise factor combinations. If so, the noise values ​​in the sub-noise test information corresponding to each noise factor combination to be processed may be subjected to permutation and combination operations between combinations to generate multiple noise value combinations. Then, for each noise value combination, the target device may calculate the total noise value corresponding to each noise value combination according to the following formula (1).

[0063] Wherein, step b can adopt the following expression: Formula (1) Where T is the total noise value corresponding to the target noise value combination, A i is the noise value extracted from the i-th noise factor combination to be processed, n is the number of noise factor combinations to be processed, and i is an integer less than or equal to n and greater than 0.

[0064] Example 1: When the noise-affected object is the trace, and the noise source area includes the field effect transistor area and the phase area, the above formula (1) can be transformed into: Formula (2) in, is a noise value in the sub-noise test information corresponding to [track, field effect transistor area], It is a noise value in the sub-noise test information corresponding to [trace, phase region].

[0065] Example 2: When the noise-affected object is the trace, and the noise source area includes the field effect transistor area, the phase area, and the inductor area, the above formula (1) can be transformed into: Formula (3) in, is a noise value in the sub-noise test information corresponding to [track, field effect transistor area], is a noise value in the sub-noise test information corresponding to [Trace, Phase Region], It is a noise value in the sub-noise test information corresponding to [track, inductance area].

[0066] Step 2: The sub-noise test information corresponding to all noise factor combinations and the parent noise test information corresponding to all noise impact objects are jointly determined as the total noise test information.

[0067] In some optional implementations, in order to improve the accuracy of the total noise test information, a verification operation may be performed first to determine whether the total noise test information is accurate, and an update operation may be performed if the total noise test information is determined to be inaccurate. The specific steps may be as follows: Step 1: Obtain a first circuit board parameter group, a first noise impact object, and a first noise source area corresponding to the verification circuit board.

[0068] Step 2: Determine a first noise value corresponding to the verification circuit board in the total noise test information according to the first circuit board parameter group, the first noise influencing object, and the first noise source area.

[0069] Step three: perform a noise test on the verification circuit board to obtain a second noise value.

[0070] Step 4: Determine whether to update the total noise test information according to the first noise value and the second noise value.

[0071] Step 5: When it is determined to update the total noise test information, the noise compensation circuit board parameters corresponding to the first noise impact object are added to the circuit board parameter pool to update the total noise test information after re-performing the noise test.

[0072] When the first noise-affected object is a trace, the noise compensation circuit board parameter is the dielectric thickness between the ground layer and the power plane, or when the first noise-affected object is a signal hole, the noise compensation circuit board parameter is the spacing between the power plane and the signal hole. For example, the dielectric thickness can be found in Figure 5 H shown in .

[0073] Specifically, the target device can first design a verification circuit board, and the technician can input the circuit board parameters, the first noise impact object, and the first noise source area of ​​the verification circuit board into the target device. In this way, the target device can obtain the first circuit board parameter group, the first noise impact object, and the first noise source area corresponding to the verification circuit board. Then, the target device can determine the first sub-noise test information that matches both the first noise impact object and the first noise source area in the total test information, and then, according to each circuit board parameter value included in the first circuit board parameter group, the first noise value corresponding to the first circuit board parameter group can be found in the first sub-noise test information. The target device tests the verification circuit board in a manner similar to step S204 to obtain the actual second noise value. Finally, the target device can compare whether the absolute value of the difference between the first noise value and the second noise value is less than a preset threshold value. If yes, it can be determined that there is no need to update the total noise test information (that is, the verification is passed), and if not, it can be determined that the total noise test information is updated (that is, the verification is not passed). In the case of determining to update, the target device can add the noise supplementary circuit board parameters to the circuit board parameter pool. Subsequently, a new set of total noise test information can be obtained again according to the test method of step S201 to step S205.

[0074] Technicians can design multiple verification circuit boards for different tests and update the total noise test information multiple times to obtain more accurate and comprehensive total noise test information, which can make subsequent evaluations more reasonable and accurate. In addition, since the noise compensation circuit board parameters are factors that have a smaller impact on noise, if they are added to the circuit board parameter pool as a factor for testing at the beginning, it will lead to a large amount of testing and occupy more resources. Therefore, this solution chooses to use a verification circuit board for verification. Only when the verification fails, will it be retested. If the verification passes, there is no need to update the total noise test information, thereby ensuring accuracy while reducing the amount of testing.

[0075] In some optional implementations, for any noise-affected object, the target device can count the percentage of verifications that pass and the percentage of verifications that fail after executing multiple verification operations corresponding to the noise-affected object, and for each verification operation, the absolute value of the difference between the measurement result of the noise meter and the result obtained through the total noise test information can be recorded. Furthermore, the target device can calculate the total verification value based on the percentage of verifications that pass and the percentage of verifications that fail, and the absolute value of the difference corresponding to each verification operation, and when the total verification value is greater than a preset verification threshold, the noise compensation circuit board parameters corresponding to the noise-affected object can be added to the circuit board parameter pool, or, when the total verification value is less than or equal to the preset verification threshold, it can be determined that the total noise test information is not updated.

[0076] Among them, the total verification value is calculated according to the proportion of verification passed and the proportion of verification failed, as well as the difference corresponding to each verification operation, and the following expression can be used: Formula (4) in, is the total verification value, is the first weight value, which is used to indicate the importance of passing the verification to the total verification value. is the second weight value, which is used to indicate the importance of verification failure to the total verification value. is the third weight value, which is used to indicate the importance of the absolute value of the difference to the total verification value. is the ratio of those that passed the verification. is the ratio of unsuccessful verification, q is the number of verification operations, e z is the absolute value of the difference corresponding to the zth verification operation.

[0077] In this way, with the advantages of the above verification process, whether to update the total noise test information is further evaluated through the total verification value of multiple tests, which can improve the accuracy of the total noise test information and further improve the accuracy of the subsequent evaluation results of the circuit board.

[0078] The noise test information generation method provided by the embodiment of the present application is that the noise affecting object is the component affected by the noise on the circuit board, and the noise source area is the area on the power supply that generates noise. Then, by combining the noise affecting object and the noise source area, a noise factor combination can be obtained. According to the noise affecting object and the noise source area in the noise factor combination, and the circuit board parameter pool, a plurality of circuit board parameter groups can be generated. In this way, after performing a noise test on the test circuit board corresponding to each circuit board parameter value, a noise value can be obtained. Finally, according to the noise factor combination, the circuit board parameter group corresponding to the noise factor combination, and the noise value corresponding to the circuit board parameter group, the total noise test information can be obtained. In this way, by pre-testing the circuit boards corresponding to different circuit board parameter groups, the noise impact under different designs can be obtained.

[0079] In common design rules, a relatively large circuit board parameter threshold is generally given, and technicians design circuit boards based on this. However, designing circuits with relatively large circuit board parameter thresholds often leads to the problem of wasting hardware resources. However, in this application, it is possible to indicate whether a circuit board meets the noise regulations corresponding to the circuit board based on the actual total noise test information, thereby guiding technicians to make adjustments, so that the circuit board design of each project can meet the personalized regulations of the project, that is, the circuit board can be laid out using relatively accurate circuit board parameters, rather than using the specified circuit board parameter threshold for design, which can reduce the problem of wasting hardware resources.

[0080] In addition, when technicians need to evaluate a circuit board later, they can directly use the total noise test information to evaluate whether the noise of the circuit board meets the regulations (that is, whether the noise of the circuit board is within the preset noise range) and give corresponding instructions. During the evaluation process, there is no need to perform real-time noise testing, but the corresponding noise value can be directly found from the total noise test information, which can improve the evaluation efficiency.

[0081] The embodiment of the present application provides a noise evaluation method, which can be executed by the above-mentioned target device, such as Figure 8 As shown, the method may specifically include the following steps: Step S801, obtaining a circuit board parameter group, a noise influencing object, a noise source area, and a maximum noise threshold corresponding to the circuit board to be evaluated.

[0082] Step S802: According to the circuit board parameter group, the noise influencing object, and the noise source area, a noise value corresponding to the circuit board to be evaluated is determined in the pre-acquired total noise test information.

[0083] The total noise test information is generated according to step S201 to step S205, or can be updated after the verification operation is performed.

[0084] Specifically, when there is one noise influencing object and one noise source area, the target device can determine, in the total noise test information, second sub-noise test information that matches both the noise influencing object and the noise source area corresponding to the circuit board to be evaluated, based on the noise influencing object and the noise source area corresponding to the circuit board to be evaluated. Furthermore, based on the circuit board parameter group corresponding to the circuit board to be evaluated, the target device can determine in the second sub-noise test information a noise value that matches the circuit board parameter group corresponding to the circuit board to be evaluated, that is, determine the noise value corresponding to the circuit board to be evaluated.

[0085] Alternatively, when the noise influencing objects include multiple or the noise source areas include multiple, the target device can arrange and combine the noise influencing objects and the noise source areas to obtain multiple noise influencing factor combinations corresponding to the circuit board to be evaluated. For each noise influencing factor combination, the target device can find the third sub-noise test information that matches the noise influencing objects and the noise source areas included in the noise influencing factor combination in the total noise test information, and the first parent noise test information that matches the noise influencing objects included in the noise influencing factor combination, according to the noise influencing objects and the noise source areas included in the noise influencing factor combination, and then, according to the circuit board parameter group corresponding to the circuit board to be evaluated, find the noise value that matches all circuit board parameters in the circuit board parameter group corresponding to the circuit board to be evaluated in the third sub-noise test information. In this way, for each noise influencing factor combination, the target device can find the noise value corresponding to the noise influencing factor combination in the total noise test information, and then, the target device can combine the noise values ​​corresponding to each noise influencing factor combination into a noise value combination, and find the total noise value that matches each noise value in the noise value combination in the first parent noise test information, that is, determine the noise value corresponding to the circuit board to be evaluated.

[0086] The specific processing from step S801 to step S802 may refer to the above-mentioned processing procedure of searching for the first noise value, which will not be described in detail here.

[0087] Step S803: determining a noise test result according to the noise value corresponding to the circuit board to be evaluated and the maximum noise threshold.

[0088] Specifically, the target device may determine whether the noise value corresponding to the circuit board to be evaluated is less than or equal to the maximum noise threshold, and if so, the noise test result may be determined to be passed, and if not, the noise test result may be determined to be failed.

[0089] Step S804: after performing an operation corresponding to the noise test result according to the noise test result, noise evaluation information of the circuit board to be evaluated is generated.

[0090] The noise evaluation information is used to indicate whether to adjust the circuit board to be evaluated.

[0091] Specifically, the target device may determine whether to adjust the circuit board to be evaluated according to the noise test result, and directly output the noise test result if it is determined that no adjustment is required, or output the noise test result and give adjustment advice if it is determined that adjustment is required. Accordingly, the target device may perform the following specific steps: Step 1: When the noise test result is failed, at least one circuit board parameter group whose noise value is less than or equal to the maximum noise threshold is selected from the total noise test information according to the maximum noise threshold, the noise impact object and the noise source area.

[0092] Step 2: Determine at least one recommended circuit board parameter group based on each circuit board parameter group whose noise value is less than or equal to the maximum noise threshold and the circuit board parameter group corresponding to the circuit board to be evaluated.

[0093] Step 3: Generate noise evaluation information based on the noise test results and each recommended circuit board parameter group.

[0094] Step 4: When the noise test result is passed, the noise test result is directly determined as noise evaluation information.

[0095] Specifically, when the target device determines that the noise test result is passed, it can directly determine the noise test result as noise evaluation information, so that the technician can know that the current circuit board to be evaluated meets the noise regulations. Alternatively, when the noise test result is determined to be failed, the target device determines the circuit board parameter group (hereinafter referred to as the candidate circuit board parameter group) whose noise value is less than or equal to the maximum noise threshold in the second sub-noise test information.

[0096] The target device can calculate the difference value between the circuit board parameter group corresponding to the circuit board to be evaluated and each candidate circuit board parameter group, and then the target device can determine whether there is a candidate circuit board parameter group whose difference value between the circuit board parameter group corresponding to the circuit board to be evaluated is less than a preset threshold. If so, the target device can use the candidate circuit board parameter group whose difference value is less than the preset threshold as the recommended circuit board parameter group. If not, the target device can select the candidate circuit board parameter group with the smallest difference value as the recommended circuit board parameter group.

[0097] The above process of calculating the difference value may adopt the calculation formula of the Euclidean distance, for example, the following formula (5) or formula (6) may be adopted: Formula (5) Where V is the difference value, k is the number of circuit board parameters in the circuit board parameter group corresponding to the circuit board to be evaluated (the same as the number of circuit board parameters in the candidate circuit board parameter group), is the i-th circuit board parameter in the candidate circuit board parameter group, is the i-th circuit board parameter in the circuit board parameter group corresponding to the circuit board to be evaluated.

[0098] Formula (6) Where V is the difference value, k is the number of circuit board parameters in the circuit board parameter group corresponding to the circuit board to be evaluated, is the i-th circuit board parameter in the candidate circuit board parameter group, is the i-th circuit board parameter in the circuit board parameter group corresponding to the circuit board to be evaluated, is the weight value corresponding to the i-th circuit board parameter.

[0099] In this way, by selecting the recommended circuit board parameter group with a smaller difference value, the technician can ensure that the noise value is within the specified range when adjusting the circuit, and can also improve the convenience of reducing the adjustment of the circuit board. In addition, by further introducing the weight value corresponding to the circuit board parameter, the recommended circuit board parameters can be selected more flexibly. For the circuit board parameters with a smaller weight value, the probability of needing adjustment can be reduced, and for the circuit board parameters with a larger weight value, the probability of needing adjustment can be increased. In this way, the process of adjusting the circuit board can be focused on a small number of circuit board parameters, improving the adjustment efficiency and ease of operation.

[0100] In some optional implementations, the target device may also directly determine all circuit board parameter groups with noise values ​​less than or equal to the maximum noise threshold as recommended circuit board parameter groups. In this way, a wider range of choices can be provided, allowing technicians to adjust the design of the circuit board to be evaluated based on this.

[0101] The noise evaluation method provided by the embodiment of the present application can first obtain the circuit board parameter group, noise influencing object, noise source area, and maximum noise threshold of the current circuit board (i.e., the circuit board to be evaluated) in the process of evaluating the circuit board. Furthermore, based on the circuit board parameter group, noise influencing object, and noise source area, the noise value corresponding to the circuit board to be evaluated can be determined in the pre-acquired total noise test information. In this way, there is no need to perform real-time noise testing, which can improve the evaluation efficiency. In addition, according to the noise value corresponding to the circuit board to be evaluated and the maximum noise threshold corresponding to the circuit board to be evaluated, the noise test result can be determined, and then the noise evaluation information is generated according to the noise test result, indicating whether the technician adjusts the evaluation circuit board, so that the circuit board parameters can be accurately adjusted, rather than directly using larger circuit board parameters to design the circuit board, which can reduce the occurrence of hardware resource waste.

[0102] The following describes in detail the process of the noise test information generation method by taking the case where the noise-affected object is a routing line and the noise source region includes a field effect transistor region and a phase region as an example.

[0103] The circuit diagram of the power supply can be as follows Fig. 9 As shown, the power supply includes an input inductor, an input capacitor, multiple grounding points, a power pulse width adjustment controller, an upper field effect transistor, a lower field effect transistor, an output inductor, a transformer inductor (the two sides of the transformer inductor are transformer node 1 and transformer node 2 respectively), an output capacitor, a phase node, a low-voltage load, a return point and other nodes. Among them, transformer node 1 is connected to the output inductor, transformer node 2 is connected to the next phase, the high voltage is still high voltage after passing through the input inductor, and a low voltage is output after passing through the transformer inductor, and the low voltage can be output to the low-voltage load. The circuit board layout diagram of the power supply can be as follows Fig.10 As shown, multiple nodes include field effect transistor nodes, phase nodes, input inductors, power input nodes, capacitors, resistors, startup networks, phase networks, grounding, output inductors, transformer nodes 1, transformer nodes 2, power output, etc. Among them, the bold black frame indicates the noise source area.

[0104] Step 1: Based on the routing, field effect transistor area and phase area, two noise factor combinations can be determined, namely [routing, field effect transistor area] and [routing, phase area].

[0105] Step 2, based on the determined [routing, field effect transistor area] and [routing, phase area], the circuit board parameters corresponding to the [routing, field effect transistor area] can be determined to include the spacing between the noise hole and the routing, and the number of ground layers between the power plane and the routing, and the circuit board parameters corresponding to the [routing, phase area] include the spacing between the power plane and the routing, and the number of ground layers between the power plane and the routing.

[0106] Step 3, generate circuit board parameter groups as shown in Table 1 and Table 2. Table 1 includes multiple circuit board parameter groups corresponding to [routing, field effect transistor area], and Table 2 includes multiple circuit board parameter groups corresponding to [routing, phase area]. One row of data in the table corresponds to one circuit board parameter group.

[0107] Table 1

[0108] Table 2

[0109] Step 4: Perform noise tests on the test circuit boards corresponding to each circuit board parameter group in Table 1 and Table 2 to obtain noise values ​​corresponding to each circuit board parameter group.

[0110] Step 5, generate a noise test table corresponding to [routing, field effect transistor area], refer to Table 3, and a noise test table corresponding to [routing, phase area] (that is, sub-noise test information corresponding to the combination of noise factors), refer to Table 4.

[0111] Table 3

[0112] Table 4

[0113] Step 6: Arrange and combine the noise values ​​in the third column of Table 3 and the noise values ​​in the third column of Table 4 to obtain Table 5. Each row in Table 5 is a noise value combination.

[0114] Table 5

[0115] Step 7: Calculate the total noise value corresponding to each noise value according to the above formula (2).

[0116] Table 6

[0117] The above Tables 3, 4 and 6 together constitute the overall noise test information.

[0118] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method.

[0119] The embodiment of the present application also provides a noise test information generating device, such as Fig.11 As shown, including: A first acquisition module 1110 is used to acquire at least one noise-affected object and at least one noise source area; A combining module 1120 is used to respectively combine any noise-affected object of the at least one noise-affected object with any noise source area of ​​the at least one noise source area in pairs to obtain at least one noise factor combination; A first generating module 1130 is used to generate a plurality of circuit board parameter groups corresponding to each noise factor combination according to the noise affecting object and the noise source area in each noise factor combination and the circuit board parameters matching the noise factor combination in the pre-built circuit board parameter pool; A testing module 1140 is used to perform noise tests on the test circuit boards corresponding to each circuit board parameter group to obtain noise values ​​corresponding to each circuit board parameter group; The first generating module 1130 is also used to generate total noise test information according to each noise factor combination, multiple circuit board parameter groups corresponding to each noise factor combination, and the noise value corresponding to each circuit board parameter group, so as to evaluate whether the noise of the circuit board is within a preset noise range.

[0120] In some optional implementations, the first generating module 1130 is specifically configured to: According to the target noise influencing object and the target noise source area included in the target noise factor combination, at least one circuit board parameter matching both the target noise influencing object and the target noise source area is selected from the circuit board parameter pool, wherein the target noise factor combination is any one of the multiple noise factor combinations; According to each circuit board parameter, a parameter value generation rule corresponding to each circuit board parameter is obtained; According to the parameter value generation rule corresponding to each circuit board parameter and the preset arrangement and combination rule, a plurality of circuit board parameter groups corresponding to the target noise factor combination are generated.

[0121] In some optional implementations, the noise test information generating device may further include a verification module 1150: Acquire a first circuit board parameter group, a first noise impact object, and a first noise source area corresponding to the verification circuit board; Determine a first noise value corresponding to the verification circuit board in the total noise test information according to the first circuit board parameter group, the first noise influencing object, and the first noise source area; Performing a noise test on the verification circuit board to obtain a second noise value; Determining whether to update the total noise test information according to the first noise value and the second noise value; When it is determined to update the total noise test information, the noise compensation circuit board parameter corresponding to the first noise influencing object is added to the circuit board parameter pool to update the total noise test information after re-performing the noise test.

[0122] In some optional implementations, the testing module 1140: Adjusting the state of a power supply connected to a target test circuit board to perform a noise test on the target test circuit board, wherein the target test circuit board is a test circuit board corresponding to a second circuit board parameter group, and the second circuit board parameter group is any one circuit board parameter group of a plurality of circuit board parameter groups corresponding to each noise factor combination; and, sending a test instruction to a noise measuring instrument connected to a target test circuit board to instruct the noise measuring instrument to monitor and feed back target noise test information of the target test circuit board; The target noise test information is analyzed to obtain a target noise value corresponding to the second circuit board parameter group.

[0123] In some optional implementations, the first generating module 1130 is specifically configured to: Generate sub-noise test information corresponding to the target noise factor combination according to each circuit board parameter group in the plurality of circuit board parameter groups corresponding to the target noise factor combination and the noise value of each circuit board parameter group in the plurality of circuit board parameter groups corresponding to the target noise factor combination; The total noise test information is generated according to the sub-noise test information corresponding to each noise factor combination.

[0124] In some optional implementations, the first generating module 1130 is specifically configured to: The sub-noise test information corresponding to all noise factor combinations are collectively determined as the total noise test information.

[0125] In some optional implementations, generating total noise test information according to sub-noise test information corresponding to each noise factor combination includes: When it is determined that there are a plurality of noise factor combinations to be processed including the target noise influencing object, generating parent noise test information corresponding to the target noise influencing object according to the child noise test information corresponding to each noise factor combination to be processed; The sub-noise test information corresponding to all noise factor combinations and the parent noise test information corresponding to all noise-affecting objects are jointly determined as the total noise test information.

[0126] In some optional implementations, the first generating module 1130 is specifically configured to: In the current processing round, a noise value corresponding to the current processing round is respectively extracted from the sub-noise test information corresponding to each noise factor combination to be processed, and the noise values ​​corresponding to the current processing round are combined to obtain a noise value combination corresponding to the current processing round; After completing the last processing round, multiple noise value combinations are obtained; Calculating a total noise value corresponding to the target noise value combination according to all noise values ​​included in the target noise value combination, wherein the target noise value combination is any one of the multiple noise value combinations; According to each noise value combination and the total noise value corresponding to each noise value combination, parent noise test information corresponding to the target noise affecting object is generated.

[0127] In some optional implementations, according to all noise values ​​included in the target noise value combination, a total noise value corresponding to the target noise value combination is calculated using the following expression:

[0128] Where T is the total noise value corresponding to the target noise value combination, A i is the noise value extracted from the i-th noise factor combination to be processed, n is the number of noise factor combinations to be processed, and i is an integer less than or equal to n and greater than 0.

[0129] For the description of the features in the embodiment corresponding to the noise test information generating device, reference may be made to the relevant description of the embodiment corresponding to the noise test information generating method, which will not be described in detail here.

[0130] The embodiment of the present application also provides a noise evaluation device, such as Fig.12 As shown, including: The second acquisition module 1210 is used to acquire a circuit board parameter group, a noise impact object, a noise source area, and a maximum noise threshold corresponding to the circuit board to be evaluated; The determination module 1220 is used to determine the noise value corresponding to the circuit board to be evaluated in the pre-acquired total noise test information according to the circuit board parameter group, the noise influencing object, and the noise source area, wherein the total noise test information is generated according to the above-mentioned noise test information generation method; determine the noise test result according to the noise value corresponding to the circuit board to be evaluated and the maximum noise threshold; The second generating module 1230 is used to generate noise evaluation information of the circuit board to be evaluated after performing an operation corresponding to the noise test result according to the noise test result, wherein the noise evaluation information is used to indicate whether to adjust the circuit board to be evaluated.

[0131] In some optional implementations, the second generating module 1230 is specifically configured to: When the noise test result is failed, at least one circuit board parameter group having a noise value less than or equal to the maximum noise threshold is selected from the total noise test information according to the maximum noise threshold, the noise impact object and the noise source area; Determine at least one recommended circuit board parameter group based on each circuit board parameter group having a noise value less than or equal to the maximum noise threshold and the circuit board parameter group corresponding to the circuit board to be evaluated; Generate noise assessment information based on the noise test results, along with each recommended board parameter set.

[0132] In some optional implementations, the second generating module 1230 is specifically configured to: When the noise test result is passed, the noise test result is directly determined as the noise evaluation information.

[0133] For the description of the features in the embodiment corresponding to the noise assessment device, reference may be made to the relevant description of the embodiment corresponding to the noise assessment method, which will not be described in detail here.

[0134] The embodiment of the present application also provides an electronic device, such as Fig.13 As shown, it includes a memory 10 and a processor 20, the memory 10 stores a computer program, and the processor 20 is configured to run the computer program to execute the steps in any one of the above-mentioned noise test information generation method embodiments or noise evaluation method embodiments.

[0135] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any one of the above-mentioned noise test information generation method embodiments or noise evaluation method embodiments when run.

[0136] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0137] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above-mentioned noise test information generating method embodiments or noise evaluation method embodiments are implemented.

[0138] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, the non-volatile computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, implementing the steps in any of the above-mentioned noise test information generation method embodiments or noise evaluation method embodiments.

[0139] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0140] The above is a detailed introduction to a noise test information generation and noise assessment method, device, electronic device, storage medium, and program product provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A method for generating noise test information, characterized in that: include: Acquire at least one noise-affected object and at least one noise source area; Combining any one of the at least one noise-affected object and any one of the at least one noise source area in pairs to obtain at least one noise factor combination; Generate multiple circuit board parameter groups corresponding to each noise factor combination according to the noise impact object and the noise source area in each noise factor combination and the circuit board parameters matching the noise factor combination in the pre-built circuit board parameter pool; Performing noise tests on the test circuit boards corresponding to each of the circuit board parameter groups to obtain noise values ​​corresponding to each of the circuit board parameter groups; According to each of the noise factor combinations, the multiple circuit board parameter groups corresponding to each of the noise factor combinations, and the noise value corresponding to each of the circuit board parameter groups, total noise test information is generated to evaluate whether the noise of the circuit board is within a preset noise range.

2. The noise test information generating method according to claim 1, characterized in that: The method comprises generating a plurality of circuit board parameter groups corresponding to each noise factor combination according to the noise affecting object and the noise source area in each noise factor combination and the circuit board parameters matching the noise factor combination in the pre-built circuit board parameter pool, including: According to the target noise influencing object and the target noise source area included in the target noise factor combination, at least one circuit board parameter matching both the target noise influencing object and the target noise source area is selected from the circuit board parameter pool, wherein the target noise factor combination is any one of the multiple noise factor combinations; According to each circuit board parameter, obtaining a parameter value generation rule corresponding to each circuit board parameter; According to the parameter value generation rule corresponding to each of the circuit board parameters and the preset arrangement and combination rule, a plurality of circuit board parameter groups corresponding to the target noise factor combination are generated.

3. The noise test information generating method according to claim 1 or 2, characterized in that: After generating the total noise test information according to each of the noise factor combinations, the multiple circuit board parameter groups corresponding to each of the noise factor combinations, and the noise value corresponding to each of the circuit board parameter groups, the method further includes: Acquire a first circuit board parameter group, a first noise impact object, and a first noise source area corresponding to the verification circuit board; Determining a first noise value corresponding to the verification circuit board in the total noise test information according to the first circuit board parameter group, the first noise impact object, and the first noise source area; Performing a noise test on the verification circuit board to obtain a second noise value; Determining whether to update the total noise test information according to the first noise value and the second noise value; When it is determined to update the total noise test information, the noise compensation circuit board parameter corresponding to the first noise influencing object is added to the circuit board parameter pool to update the total noise test information after re-performing the noise test.

4. The noise test information generating method according to claim 1 or 2, characterized in that: The performing noise tests on the test circuit boards corresponding to each circuit board parameter group to obtain the noise values ​​corresponding to each circuit board parameter group includes: Adjusting the state of a power supply connected to a target test circuit board to perform a noise test on the target test circuit board, wherein the target test circuit board is a test circuit board corresponding to a second circuit board parameter group, and the second circuit board parameter group is any one of a plurality of circuit board parameter groups corresponding to each of the noise factor combinations; and, sending a test instruction to a noise measuring instrument connected to the target test circuit board to instruct the noise measuring instrument to monitor and feed back target noise test information of the target test circuit board; The target noise test information is analyzed to obtain a target noise value corresponding to the second circuit board parameter group.

5. The noise test information generating method according to claim 2, characterized in that: The generating of total noise test information according to each of the noise factor combinations, a plurality of circuit board parameter groups corresponding to each of the noise factor combinations, and a noise value corresponding to each of the circuit board parameter groups comprises: Generate sub-noise test information corresponding to the target noise factor combination according to each circuit board parameter group in a plurality of circuit board parameter groups corresponding to the target noise factor combination and a noise value of each circuit board parameter group in a plurality of circuit board parameter groups corresponding to the target noise factor combination; The total noise test information is generated according to the sub-noise test information corresponding to each of the noise factor combinations.

6. The noise test information generating method according to claim 5, characterized in that: The generating the total noise test information according to the sub-noise test information corresponding to each of the noise factor combinations comprises: The sub-noise test information corresponding to all the noise factor combinations are collectively determined as the total noise test information.

7. The noise test information generating method according to claim 5, characterized in that: The generating the total noise test information according to the sub-noise test information corresponding to each of the noise factor combinations comprises: When it is determined that there are a plurality of noise factor combinations to be processed including the target noise influencing object, generating parent noise test information corresponding to the target noise influencing object according to the sub-noise test information corresponding to each of the noise factor combinations to be processed; The sub-noise test information corresponding to all the noise factor combinations and the parent noise test information corresponding to all the noise influencing objects are jointly determined as the total noise test information.

8. The noise test information generating method according to claim 7, characterized in that: When it is determined that there are multiple noise factor combinations to be processed including the target noise influencing object, generating parent noise test information corresponding to the target noise influencing object according to the sub-noise test information corresponding to each of the noise factor combinations to be processed, comprises: In the current processing round, a noise value corresponding to the current processing round is respectively extracted from the sub-noise test information corresponding to each of the noise factor combinations to be processed, and the noise values ​​corresponding to the current processing round are combined to obtain a noise value combination corresponding to the current processing round; After completing the last processing round, a plurality of noise value combinations are obtained; Calculating a total noise value corresponding to a target noise value combination according to all noise values ​​included in the target noise value combination, wherein the target noise value combination is any one of the multiple noise value combinations; According to each of the noise value combinations and the total noise value corresponding to each of the noise value combinations, parent noise test information corresponding to the target noise influencing object is generated.

9. The noise test information generating method according to claim 8, characterized in that: According to all the noise values ​​included in the target noise value combination, the total noise value corresponding to the target noise value combination is calculated using the following expression: Wherein, T is the total noise value corresponding to the target noise value combination, A i is the noise value extracted from the i-th noise factor combination to be processed, n is the number of the noise factor combinations to be processed, and i is an integer less than or equal to n and greater than 0.

10. A noise assessment method, characterized in that: include: Obtaining a circuit board parameter group, a noise influencing object, a noise source area, and a maximum noise threshold corresponding to the circuit board to be evaluated; According to the circuit board parameter group, the noise influencing object, and the noise source area, a noise value corresponding to the circuit board to be evaluated is determined in the pre-acquired total noise test information, wherein the total noise test information is generated according to the noise test information generating method according to any one of claims 1 to 9; Determining a noise test result according to the noise value corresponding to the circuit board to be evaluated and the maximum noise threshold; After performing an operation corresponding to the noise test result according to the noise test result, noise evaluation information of the circuit board to be evaluated is generated, wherein the noise evaluation information is used to indicate whether to adjust the circuit board to be evaluated.

11. The noise assessment method according to claim 10, characterized in that: After performing an operation corresponding to the noise test result according to the noise test result, generating noise evaluation information of the circuit board to be evaluated includes: When the noise test result is failed, selecting at least one circuit board parameter group having a noise value less than or equal to the maximum noise threshold from the total noise test information according to the maximum noise threshold, the noise influencing object and the noise source area; Determine at least one recommended circuit board parameter group according to each circuit board parameter group having a noise value less than or equal to the maximum noise threshold and a circuit board parameter group corresponding to the circuit board to be evaluated; The noise evaluation information is generated according to the noise test result and each of the recommended circuit board parameter groups.

12. The noise assessment method according to claim 11, characterized in that: The method further comprises: When the noise test result is passed, the noise test result is directly determined as the noise evaluation information.

13. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the noise test information generating method according to any one of claims 1 to 10 when executing the computer program, or to implement the steps of the noise evaluation method according to claim 11 or 12.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the noise test information generating method according to any one of claims 1 to 10, or implements the steps of the noise evaluation method according to claim 11 or 12.

15. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the computer program implements the steps of the noise test information generating method according to any one of claims 1 to 10, or implements the steps of the noise evaluation method according to claim 11 or 12.

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