Test equipment, parallel test method for multiple anti-counterfeiting chips and readable storage medium

Abstract

The invention relates to the technical field of chip testing, and discloses testing equipment, a parallel testing method for multiple anti-counterfeiting chips and a readable storage medium. The test equipment comprises a chip carrier, a switching circuit and a main control module, the chip carrier comprises a plurality of test positions, and the test positions are used for placing anti-counterfeiting chips to be tested; the switching circuit comprises a plurality of switching branches and a decoder; the decoder is used for controlling connection and disconnection of the switching branch; the switching branches are in one-to-one correspondence with the test positions, and connection and disconnection of the switching branches are used for switching the to-be-tested anti-counterfeiting chips in the corresponding test positions to be connected with the SWI output end of the main control module or an external power supply; and the main control module is used for outputting a control instruction to the decoder to control the switch-on and switch-off of the switching branch according to the number of the test positions for placing the to-be-tested anti-counterfeiting chips and the test duration of each test item of the to-be-tested anti-counterfeiting chips, so as to carry out parallel test on the to-be-tested anti-counterfeiting chips placed in the plurality of test positions. According to the invention, the testing efficiency of batch anti-counterfeiting chips can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of anti-counterfeiting chip testing, for example, to a testing device, a parallel testing method for multiple anti-counterfeiting chips, and a readable storage medium. Background Art

[0002] Currently, anti-counterfeiting chips that use asymmetric algorithms, including non-volatile memory (NVM) and SWI (Single-Wire Interface) communication interfaces, are widely used in anti-counterfeiting verification due to their high security and reliability. To ensure the reliability of anti-counterfeiting chips, various functions of the chips must be tested after production.

[0003] In the related art, the test master usually sends SWI test instructions to the anti-counterfeiting chip in sequence, and tests each test item in sequence. The test master needs to wait for the anti-counterfeiting chip to complete the test of one test item before it can send the SWI test instruction of the next test item to the anti-counterfeiting chip.

[0004] During the implementation of the embodiments of the present disclosure, it was found that at least the following problems exist in the related art:

[0005] In related technologies, due to limitations in the SWI communication interface of security chips, the test host can only test one security chip at a time. Furthermore, when controlling the security chip to execute a test item that takes a long time, the test host will remain in a waiting state. This results in a long test time for batches of security chips, resulting in low test efficiency. Therefore, improving the test efficiency of batches of security chips has become a pressing technical issue.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to ordinary technicians in this field. Summary of the Invention

[0007] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical elements or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0008] The embodiments of the present disclosure provide a testing device, a parallel testing method for multiple anti-counterfeiting chips, and a readable storage medium, which can improve the testing efficiency of batch anti-counterfeiting chips.

[0009] In some embodiments, the testing equipment includes: a chip carrier, a switching circuit and a main control module; the chip carrier includes multiple test positions, and the test positions are used to place the anti-counterfeiting chip to be tested; the switching circuit includes multiple switching branches and a decoder; the decoder is connected to the main control module and each switching branch, and is used to control the conduction and disconnection of the switching branch; the switching branch corresponds one-to-one to the test position, and the conduction and disconnection of the switching branch are used to switch the anti-counterfeiting chip to be tested in the corresponding test position to the SWI output end of the main control module or to an external power supply; the main control module is used to output control instructions to the decoder to control the conduction and disconnection of the switching branch according to the number of test positions where the anti-counterfeiting chip to be tested is placed and the test time of each test item of the anti-counterfeiting chip to be tested, so as to perform parallel testing on the anti-counterfeiting chips to be tested placed in multiple test positions.

[0010] Optionally, the output end of the switching branch is connected to the input end of the corresponding test bit; the first input end of the switching branch is connected to the SWI output end of the main control module, the second input end is connected to the output end of the decoder, and the third input end is connected to the external power supply; the decoder is connected to the GPIO output end of the main control module.

[0011] Optionally, the switching branch includes: a PMOS tube, a first resistor and a second resistor; the source of the PMOS tube is connected to the SWI output end of the main control module as the first input end of the switching branch; the gate of the PMOS tube is connected to the output end of the decoder as the second input end of the switching branch; the drain of the PMOS tube is connected to the input end of the corresponding test bit as the output end of the switching branch; one end of the first resistor is connected to the external power supply as the third input end of the switching branch, and the other end is connected to the drain of the PMOS tube; one end of the second resistor is connected to the source of the PMOS tube, and the other end is connected to the gate of the PMOS tube.

[0012] In some embodiments, a parallel testing method for multiple anti-counterfeiting chips is applied to a testing device such as the above-mentioned one, and the parallel testing method includes: determining the number of test positions where the anti-counterfeiting chips to be tested are placed and the test duration of each test item of the anti-counterfeiting chip to be tested; dividing the chip testing process into multiple test stages with the same number of test positions according to the number of test positions where the anti-counterfeiting chips to be tested are placed, and each test stage at least traverses and tests all the test positions where the anti-counterfeiting chips to be tested are placed; determining a first test item and a second test item according to the test duration of each test item, wherein the test duration of the first test item is greater than the test duration of each second test item; in each test stage, selecting one of the multiple test positions where the anti-counterfeiting chip to be tested is placed as the first test position, and the remaining test positions as the second test positions; the first test position executes the first test item, and the multiple second test positions respectively execute their corresponding second test items; wherein the first test position in each test stage is different.

[0013] Optionally, the maximum test duration of each test phase is the test duration of the first test item; in each test phase, the first test bit is first controlled to start executing the first test item, and while the first test bit is executing the first test item, multiple second test bits are alternately controlled to start executing corresponding second test items.

[0014] Optionally, the first test bit is first controlled to start executing the first test item, and during the process of the first test bit executing the first test item, multiple second chip test bits are alternately controlled to start executing corresponding second test items, including: controlling the switching branch corresponding to the first test bit to be turned on, so that the first test bit is connected to the SWI output end of the main control module, and receives the test instruction of the first test item output by the SWI output end; after the first test bit completes receiving the test instruction of the first test item, controlling the switching branch corresponding to the first test bit to be disconnected, so that the first test bit is connected to the external power supply; alternately controlling the switching branches corresponding to multiple second test bits to be turned on, so that the multiple second test bits are alternately connected to the SWI output end of the main control module, and receive the test instructions of the corresponding second test item output by the SWI output end.

[0015] Optionally, when the sum of the test durations of the plurality of second test items is less than the test duration of the first test item, one second test bit will execute the plurality of second test items in one test phase.

[0016] Optionally, the parallel testing method further includes: after each test phase, obtaining first test result data of the anti-counterfeiting chip to be tested in each test position; determining abnormal anti-counterfeiting chips among multiple anti-counterfeiting chips to be tested based on the first test result data; and isolating the test position where the abnormal anti-counterfeiting chip is placed.

[0017] Optionally, the parallel testing method further includes: obtaining second test result data of the anti-counterfeiting chip to be tested in each test position after all test stages are completed; and generating a test report for each anti-counterfeiting chip to be tested according to the second test result data.

[0018] In some embodiments, a computer-readable storage medium stores program instructions, and when the program instructions are executed, they are used to execute the above-mentioned parallel testing method for multiple anti-counterfeiting chips.

[0019] The test device, parallel testing method for multiple anti-counterfeiting chips, and readable storage medium provided by the embodiments of the present disclosure can achieve the following technical effects:

[0020] In the disclosed embodiment, the test equipment includes a chip carrier, a switching circuit, and a main control module. The chip carrier includes multiple test positions. The switching branch includes multiple switching branches and a decoder. The decoder is connected to the main control module and each switching branch to control the switching branch's conduction and disconnection. The switching branches correspond one-to-one with the test positions. The conduction and disconnection of the switching branches are used to switch the anti-counterfeiting chip under test in the corresponding test position to the SWI output terminal of the main control module or to an external power supply. This allows the main control module to send control instructions to the decoder according to a certain strategy when testing batch anti-counterfeiting chips, based on the number of test positions where the anti-counterfeiting chips to be tested are placed and the test duration of each test item of the anti-counterfeiting chips to be tested, to control the conduction and disconnection of the switching branch corresponding to each test position where the anti-counterfeiting chip to be tested is placed, and to connect to the SWI output end of the main control module or to an external power supply, so that multiple anti-counterfeiting chips to be tested can receive test instructions for different test items during the test process, and when the anti-counterfeiting chip to be tested receives the test instruction for a certain test item, other anti-counterfeiting chips to be tested are powered by the external power supply and will not affect the test items they are executing. In this way, parallel testing of multiple anti-counterfeiting chips to be tested is achieved, so that within the time it takes to test one anti-counterfeiting chip in the related art, the embodiment of the present disclosure can complete the testing of multiple anti-counterfeiting chips. Therefore, the embodiment of the present disclosure can improve the testing efficiency of batch anti-counterfeiting chips.

[0021] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily described by corresponding drawings. These exemplary descriptions and drawings do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements. The drawings do not constitute a scale limitation. In addition,

[0023] Figure 1 is a schematic diagram of a test device provided by an embodiment of the present disclosure;

[0024] Figure 2 is a schematic diagram of another testing device provided by an embodiment of the present disclosure;

[0025] Figure 3 is a schematic diagram of a parallel testing method for multiple anti-counterfeiting chips provided by an embodiment of the present disclosure;

[0026] Figure 4 This is a timing diagram of a plurality of test bits executing various test items in different test phases provided by an embodiment of the present disclosure;

[0027] Figure 5 is another timing diagram of multiple test bits executing various test items in different test phases provided by an embodiment of the present disclosure;

[0028] Figure 6 is another timing diagram of multiple test bits executing various test items in different test phases provided by an embodiment of the present disclosure;

[0029] Figure 7 This is a schematic diagram of a main control module provided by an embodiment of the present disclosure.

[0030] Description of reference numerals:

[0031] 10. Test equipment;

[0032] 100, chip carrier; 110, test position;

[0033] 200, switching circuit; 210, switching branch; Q1, PMOS transistor; R1, first resistor; R2, second resistor; 220, decoder;

[0034] 300. Main control module. DETAILED DESCRIPTION

[0035] In order to be able to understand the features and technical content of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The accompanying drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the sake of convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0036] In the description and claims of the embodiments of the present disclosure, as well as in the accompanying drawings, the terms "first," "second," and the like are used to distinguish similar items and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate to describe the embodiments of the present disclosure herein. In addition, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions.

[0037] Unless otherwise stated, the term "plurality" of a feature means two or more.

[0038] In the embodiment of the present disclosure, the character " / " feature indicates that the preceding and following objects are in an "or" relationship. For example, the A / B feature indicates: A or B.

[0039] The term "and / or" describes an association between objects and indicates that three relationships can exist. For example, "A and / or B" indicates three relationships: A or B, or A and B.

[0040] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0041] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other.

[0042] like Figure 1 As shown, the test device 10 provided by the embodiment of the present disclosure includes: a chip carrier 100, a switching circuit 200 and a main control module 300. The chip carrier 100 includes a plurality of test positions 110, and the test positions 110 are used to place the anti-counterfeiting chip to be tested. The switching circuit 200 includes a plurality of switching branches 210 and a decoder 220. The decoder 220 is connected to the main control module 300 and each switching branch 210, and is used to control the conduction and disconnection of the switching branch 210. The switching branch 210 corresponds one-to-one to the test position 110, and the conduction and disconnection of the switching branch 210 are used to switch the anti-counterfeiting chip to be tested in the corresponding test position 110 to be connected to the SWI output terminal of the main control module 300 or to an external power supply. The main control module 300 is used to output control instructions to the decoder 220 to control the conduction and shutdown of the switching branch 210 according to the number of test positions 110 where the anti-counterfeiting chips to be tested are placed and the test duration of each test item of the anti-counterfeiting chip to be tested, so as to perform parallel testing on the anti-counterfeiting chips to be tested placed in multiple test positions 110.

[0043] In the embodiment of the present disclosure, when testing a batch of anti-counterfeiting chips, multiple anti-counterfeiting chips to be tested can be placed simultaneously in multiple test positions 110 in the chip carrier 100, so that each anti-counterfeiting chip to be tested is connected to the switching branch 210. The main control module 300 can send control instructions to the decoder 220 according to a certain strategy based on the number of test positions 110 where the anti-counterfeiting chips to be tested are placed and the test duration of each test item of the anti-counterfeiting chips to be tested, to control the conduction and disconnection of the switching branch 210 corresponding to each test position 110 where the anti-counterfeiting chip to be tested is placed, and connect to the SWI output end of the main control module 300 or to an external power supply, so that multiple anti-counterfeiting chips to be tested can receive test instructions for different test items during the testing process. When the anti-counterfeiting chip to be tested receives the test instruction of a certain test item, the other anti-counterfeiting chips to be tested are powered by the external power supply, which does not affect the test items being executed. In this way, multiple anti-counterfeiting chips to be tested can be tested in parallel, so that in the time it takes to test one anti-counterfeiting chip in the related art, the embodiment of the present disclosure can complete the testing of multiple anti-counterfeiting chips. Therefore, the embodiment of the present disclosure can improve the testing efficiency of batch anti-counterfeiting chips.

[0044] like Figure 1As shown, in some embodiments, the output of the switching branch 210 is connected to the input of the corresponding test bit 110; the first input of the switching branch 210 is connected to the SWI output of the main control module 300, the second input is connected to the output of the decoder 220, and the third input is connected to an external power supply. The decoder 220 is connected to the GPIO output of the main control module 300.

[0045] Specifically, according to Figure 1 It can be seen that the main control module 300 and each test position 110 include a ground terminal ( Figure 1 These ground terminals all need to be connected to the ground wire.

[0046] Specifically, by connecting the decoder 220 to the GPIO output of the main control module 300, connecting the first input of the switch branch 210 to the SWI output of the main control module 300, connecting the second input of the switch branch 210 to the output of the decoder 220, and connecting the output of the switch branch 210 to the input of the test position 110. When testing batches of anti-counterfeiting chips, after placing multiple anti-counterfeiting chips to be tested in the test position 110, the main control module 300 can send control instructions to the decoder 220 via the GPIO output, so that the decoder 220 can send control signals to the switch branch 210 corresponding to each test position 110 to control the conduction and shutdown of the switch branch 210. When the switch branch 210 is turned on, the main control module 300 can output test instructions to the test position 110 corresponding to the switch branch 210 via the SWI output, thereby testing the anti-counterfeiting chips to be tested placed in the test position 110.

[0047] Specifically, by connecting the third input terminal of the switching branch 210 to the external power supply ( Figure 1 When the switch branch 210 is disconnected, the anti-counterfeiting chip to be tested placed in the test position 110 can be powered by an external power supply and continue to execute the received test instructions and test the corresponding test items. In this way, when the main control module 300 sends test instructions to other test positions 110 containing anti-counterfeiting chips to be tested through other switch branches 210, the test items of the anti-counterfeiting chip to be tested in the current test position 110 can also be executed.

[0048] like Figure 2As shown, in some embodiments, the switching branch 210 includes: a PMOS transistor Q1, a first resistor R1, and a second resistor R2. The source of the PMOS transistor Q1 serves as the first input terminal of the switching branch 210 and is connected to the SWI output terminal of the main control module 300; the gate of the PMOS transistor Q1 serves as the second input terminal of the switching branch 210 and is connected to the output terminal of the decoder 220; and the drain of the PMOS transistor Q1 serves as the output terminal of the switching branch 210 and is connected to the input terminal of the corresponding test bit 110. One end of the first resistor R1 serves as the third input terminal of the switching branch 210 and is connected to the external power supply, and the other end is connected to the drain of the PMOS transistor Q1. One end of the second resistor R2 is connected to the source of the PMOS transistor Q1, and the other end is connected to the gate of the PMOS transistor Q1.

[0049] Specifically, a PMOS transistor Q1 is provided in the switching branch 210, and the source of the PMOS transistor Q1 is connected to the SWI output of the main control module 300 as the first input of the switching branch 210, the gate is connected to the output of the decoder 220 as the second input of the switching branch 210, and the drain is connected to the input of the corresponding test bit 110 as the output of the switching branch 210. When the decoder 220 sends a high-level or low-level control signal to the gate of the PMOS transistor Q1, the PMOS transistor Q1 can be controlled to be turned on or off, thereby controlling whether the test bit 110 currently connected to the switching branch 210 is connected to the SWI output of the main control module 300.

[0050] Specifically, a pull-up resistor is formed by providing a first resistor R1 in the switching branch 210, connecting one end of the first resistor R1 to an external power source as the third input terminal of the switching branch 210, and connecting the other end to the drain of the PMOS transistor Q1. In this way, when the PMOS transistor Q1 is turned off, the external power source can provide power to the anti-counterfeiting chip to be tested in the test position 110 corresponding to the current switching branch 210.

[0051] Specifically, by setting a second resistor R2 in the switching branch 210, and connecting one end of the second resistor R2 to the source of the PMOS tube Q1 and the other end to the gate of the PMOS tube Q1, current limiting protection can be formed for the PMOS tube Q1, thereby reducing the risk of damage to the PMOS tube Q1.

[0052] In combination with the above-mentioned test equipment, the embodiment of the present disclosure provides a parallel testing method for multiple anti-counterfeiting chips. The parallel testing method is applied to the above-mentioned test equipment. The execution subject of the parallel testing method is the main control module in the test equipment, such as Figure 3 As shown, the parallel testing method includes:

[0053] S301: The main control module determines the number of test locations where the anti-counterfeiting chip to be tested is placed and the test duration of each test item of the anti-counterfeiting chip to be tested.

[0054] It should be noted that within a batch, the number and content of test items to be performed on each anti-counterfeiting chip to be tested are the same.

[0055] Specifically, the main control module can confirm which test positions in the chip carrier have the anti-counterfeiting chips to be tested placed therein by sending signals to the test positions, thereby determining the number of test positions where the anti-counterfeiting chips to be tested are placed.

[0056] Specifically, each batch of security chips tested may have different test items than other batches due to their different types. Furthermore, the duration of each test item is crucial for controlling the timing of the execution of each test item by the multiple security chips placed in the test slots to enable parallel testing of multiple security chips. Therefore, in addition to determining the number of test slots where the security chips to be tested will be placed, the main control module also needs to determine the duration of each test item for the security chips to be tested.

[0057] S302, the main control module divides the chip testing process into multiple test phases equal to the number of test bits placed therein, and each test phase at least traverses and tests all the test bits placed therein.

[0058] Specifically, by dividing the chip testing process into a plurality of testing phases having the same number as the testing positions, it can be ensured that the anti-counterfeiting chip to be tested on each testing position can go through a complete testing process.

[0059] Specifically, by traversing and testing all test positions where the anti-counterfeiting chips to be tested are placed in each test phase, it is possible to avoid the situation where some test positions are omitted or the corresponding test items are not executed, ensuring that each anti-counterfeiting chip to be tested in a test phase executes at least one test item.

[0060] S303: The main control module determines a first test item and a second test item according to the test duration of each test item, wherein the test duration of the first test item is greater than the test duration of each second test item.

[0061] Specifically, based on the test duration of each test item, the test item with the longest test duration among the multiple test items is determined as the first test item, and the test item with the shorter test duration among the multiple test items is determined as the second test item. In each test phase, the anti-counterfeiting chip under test in one test position can be selected to execute the first test item. While the chip is executing the first test item, the anti-counterfeiting chips under test in other test positions are controlled to execute the corresponding second test item. In this way, within each test phase, multiple anti-counterfeiting chips under test can execute at least one test item in parallel.

[0062] S304, in each test phase, the main control module selects one of the multiple test positions where the anti-counterfeiting chip to be tested is placed as the first test position, and the remaining test positions as the second test positions; the first test position executes the first test item, and the multiple second test positions respectively execute their corresponding second test items; wherein, the first test position in each test phase is different.

[0063] Specifically, within each test phase, one test bit from the multiple tests is selected as the first test bit (the first test bit is different in each test phase), and the remaining test bits are selected as second test bits. After the test phase begins, the first test item is executed by the first test bit, and the multiple second test bits respectively execute their corresponding second test items. This approach ensures that the chip in each test bit can execute all test items.

[0064] Optionally, the maximum test duration of each test phase is the test duration of the first test item; in each test phase, the first test bit is first controlled to start executing the first test item, and while the first test bit is executing the first test item, multiple second test bits are alternately controlled to start executing corresponding second test items.

[0065] Specifically, the longest test duration of each test phase is the test duration of the first test item, and the duration of alternately executing the corresponding second test items by the plurality of second test bits is close to or equal to the test duration of the first test item.

[0066] Specifically, within each test phase, the first test bit is controlled to begin executing the first test item. While the first test bit is executing the first test item, multiple second test bits are alternately controlled to begin executing corresponding second test items. This allows for parallel control of the security chips under test in multiple test bits to execute different test items within each test phase.

[0067] Optionally, the first test bit is first controlled to start executing the first test item, and during the process of the first test bit executing the first test item, multiple second chip test bits are alternately controlled to start executing corresponding second test items, including: controlling the switching branch corresponding to the first test bit to be turned on, so that the first test bit is connected to the SWI output end of the main control module, and receives the test instruction of the first test item output by the SWI output end; after the first test bit completes receiving the test instruction of the first test item, controlling the switching branch corresponding to the first test bit to be disconnected, so that the first test bit is connected to the external power supply; alternately controlling the switching branches corresponding to multiple second test bits to be turned on, so that the multiple second test bits are alternately connected to the SWI output end of the main control module, and receive the test instructions of the corresponding second test item output by the SWI output end.

[0068] Specifically, in each test phase, the first test bit is controlled to execute the first test item, and the second test bit is controlled to execute the corresponding second test item. This is achieved by controlling the conduction and disconnection of the switching branch corresponding to the test bit, so that the test bit is connected to the SWI output end of the main control module or to the external power supply.

[0069] Optionally, when the sum of the test durations of the plurality of second test items is less than the test duration of the first test item, one second test bit will execute the plurality of second test items in one test phase.

[0070] Specifically, if the sum of the test durations of multiple second test items is less than the test duration of the first test item, this indicates that the duration for the first test bit to execute the first test item is sufficient for one second test bit to alternately execute multiple second test items. Therefore, in this case, multiple different second test items need to be assigned to one second test bit item within a test phase.

[0071] For example, the above solution is described by taking the following example: the number of test positions where the anti-counterfeiting chip to be tested is placed is 3, the number of test items is 3, and the sum of the test durations of test item 2 and test item 3 is not less than the test duration of test item 1:

[0072] Specifically, in the above case, the chip test process will be divided into three test phases, and the timing of executing the test items in each test phase is as follows: Figure 4 As shown. Figure 4It can be seen that since test item 1 takes the longest test time, test item 1 is selected as the first test item, and test items 2 and 3 are selected as the second test items. In test phase 1, test bit 1 is the first test bit, and test item 1 is executed first. Test bits 2 and 3 are the second test bits. During the process of test bit 1 executing test item 1, test bit 2 receives the test instruction of test item 2 for execution, and then test bit 3 receives the test instruction of test item 3 for execution. In test phase 2, test bit 2 is the first test bit, and test item 1 is executed first. Test bit 1 and 3 are the second test bits. During the process of test bit 2 executing test item 1, test bit 1 receives the test instruction of test item 3 for execution, and then test bit 3 receives the test instruction of test item 2 for execution. In test phase 3, test bit 3 is the first test bit, and test item 1 is executed first. Test bit 1 and test bit 2 are second test bits. When test bit 3 executes test item 1, test bit 1 receives the test instruction of test item 2 for execution, and then test bit 2 receives the test instruction of test item 3 for execution.

[0073] For example, the above solution is described by taking the following example: the number of test positions where the anti-counterfeiting chip to be tested is placed is 3, the number of test items is 5, and the sum of the test durations of test item 2 and test item 5 is less than the test duration of test item 1.

[0074] Specifically, in the above case, the chip test process will be divided into three test phases, and the timing of executing the test items in each test phase is as follows: Figure 5 As shown. Figure 5 It can be seen that since test item 1 has the longest test time, test item 1 is selected as the first test item, and test items 2 to 5 are selected as the second test items. In test phase 1, test bit 1 is the first test bit, and test item 1 is executed first. Test bits 2 and 3 are the second test bits. During the process of test bit 1 executing test item 1, test bit 2 alternately receives the test instructions of test items 2 and 3 for execution, and then test bit 3 receives the test instructions of test items 4 and 5 for execution. In test phase 2, test bit 2 is the first test bit, and test item 1 is executed first. Test bit 1 and 3 are the second test bits. During the process of test bit 2 executing test item 1, test bit 1 receives the test instructions of test items 4 and 5 for execution, and then test bit 3 receives the test instructions of test items 2 and 3 for execution. In test phase 3, test bit 3 is the first test bit, and test item 1 is executed first. Test bit 1 and test bit 2 are the second test bits. When test bit 3 executes test item 1, test bit 1 receives the test instructions of test item 2 and test item 3 for execution. Then, test bit 2 receives the test instructions of test item 4 and test item 5 for execution.

[0075] Combined with the specific anti-counterfeiting chip test items of asymmetric algorithm test (EEC test) and NVM non-volatile memory test (this test includes 16 customer page NVM tests), taking the number of test bits placed on the anti-counterfeiting chip to be tested as 3 as an example, the above parallel test process is specifically explained.

[0076] It should be noted that the asymmetric algorithm uses the ECC P256 curve, with a test signature time of 440ms. The entire test process only needs to be performed once. The NVM non-volatile memory is FLASH memory, and the test time for each client page is 30ms. The communication time of the SWI communication interface is 100us, and the communication time for each client page test is 20ms. The communication time for each ECC test is 320ms (including 280ms data throughput time and 40ms instruction transmission time).

[0077] Specifically, since there are three test positions where the anti-counterfeiting chip to be tested is placed, the test process is divided into three test phases. And according to the test duration of the asymmetric algorithm test and the NVM non-volatile memory test, specific test items are allocated to each test position in each test phase. The specific details are as follows: Figure 6 shown.

[0078] according to Figure 6 It can be seen that in test phase 1, test bit 1 is the first test bit, the ECC test is performed, test bits 2 and test bits 3 are the second test bits, and the total test execution time is equal to the 1st to 8th customer page NVM tests of the ECC test. In test phase 2, test bit 2 is the first test bit, the ECC test is performed, test bits 1 and test bits 3 are the second test bits, and the total test execution time of test bit 1 is equal to the 1st to 8th customer page NVM tests of the ECC test, and the total test execution time of test bit 3 is equal to the 9th to 16th customer page NVM tests of the ECC test. In test phase 3, test bit 3 is the first test bit, the ECC test is performed, test bits 1 and test bits 2 are the second test bits, and the total test execution time is equal to the 9th to 16th customer page NVM tests of the ECC test.

[0079] Specifically, in test phase 1, the specific control logic is as follows:

[0080] First, the main control module sends a control command to the decoder via the GPIO output. This command causes the decoder to control the switch connected to test position 1, connect the main control module's SWI output, and output an EEC test command to the security chip under test in test position 1. This test command takes 160ms to output. This test command initiates the ECC test of the security chip under test in test position 1.

[0081] Second, while the anti-counterfeiting chip in test position 1 undergoes a 440ms ECC test, the main control module disconnects the SWI output from test position 1 and instead supplies power to test position 1 from an external power source connected to the third input of the switching branch. Simultaneously, the switching branch connecting the main control module to test position 2 connects the main control module's SWI output to test position 2, and the main control module sends the first client page NVM test instruction to the anti-counterfeiting chip in test position 2. This instruction takes 20ms to output. This test instruction initiates the first client page NVM test operation for anti-counterfeiting chip 2.

[0082] Third, while the first customer page NVM test of security chip 2 (under test) takes 30ms, the main control module disconnects the SWI output from test position 2 and instead supplies power to test position 2 from an external power source connected to the third input of the switching branch. Simultaneously, the switching branch of test position 3 is turned on, connecting the main control module's SWI output to test position 3 and sending the first customer page NVM test instruction to the security chip under test in test position 3. This test instruction takes 20ms to output. This test instruction initiates the first customer page NVM test operation for the security chip under test in test position 3.

[0083] Fourth, when the anti-counterfeiting chip to be tested in test position 3 is in the first customer page NVM test which takes 30ms, the main control module disconnects the SWI output terminal from test position 3, and instead powers test position 3 with an external power supply connected to the third input terminal of the switching branch. At this point, the first customer page NVM test of the anti-counterfeiting chip to be tested in test position 2 is nearly completed. The main control module reopens the switching branch to test position 2, and after the estimated test is completed, it sends an acquisition instruction to test position 2 to obtain the test result data of the first customer page NVM test. If the test passes, the second customer page NVM test instruction continues to be sent. The above operations take a total of 40ms, and after completion, test position 2 switches to a state powered by the switching branch. At this point, the first customer page NVM test of test position 3 has been completed, and the main control module turns on the switching branch of test position 3.

[0084] Fifth, repeat the logic of steps 2 through 4 above, alternating between test positions 2 and 3 to perform the NVM test for the second value of nine client pages. While test position 1 completes the 440ms ECC test, test positions 2 and 3 perform NVM tests in parallel. This achieves the effect of parallel testing of the security chips under test in all three test positions.

[0085] Specifically, by further performing control of test phases 2 and 3 according to the control logic in test phase 1, the anti-counterfeiting chips to be tested in the three test positions can complete the entire test in parallel.

[0086] In the embodiment of the present disclosure, when testing a batch of anti-counterfeiting chips, the main control module can divide the chip testing process into multiple test phases with the same number of test bits according to the number of test bits where the anti-counterfeiting chips to be tested are placed. The first test item and the second test item can be determined according to the test duration of each test item. In each test phase, one of the multiple test bits where the anti-counterfeiting chip to be tested is placed can be selected as the first test bit, and the remaining test bits can be used as the second test bits. The first test bit then executes the first test item, and the multiple second test bits respectively execute their corresponding second test items. In this way, parallel testing of multiple anti-counterfeiting chips to be tested is achieved, so that the embodiment of the present disclosure can complete the testing of multiple anti-counterfeiting chips within the time it takes to test one anti-counterfeiting chip in the related art. Therefore, the embodiment of the present disclosure can improve the testing efficiency of batch anti-counterfeiting chips.

[0087] In some embodiments, the parallel testing method further includes: after each test phase, obtaining first test result data of the anti-counterfeiting chip to be tested in each test position; determining abnormal anti-counterfeiting chips among multiple anti-counterfeiting chips to be tested based on the first test result data; and isolating the test position where the abnormal anti-counterfeiting chip is placed.

[0088] Specifically, if an anti-counterfeiting chip exhibits an anomaly, testing it is of no use. Therefore, when testing multiple anti-counterfeiting chips in parallel, after each test phase, the first test result data for each chip in each test position is obtained to determine whether any of the multiple chips exhibit an anomaly. If an anomaly is present, the test position containing the anomaly is immediately isolated.

[0089] Optionally, after isolating the test position where the abnormal anti-counterfeiting chip is placed, the parallel testing method also includes: determining the number of non-abnormal anti-counterfeiting chips among the multiple anti-counterfeiting chips to be tested; re-dividing the test stages, and the first test position and the second test position in each test stage according to the number of non-abnormal anti-counterfeiting chips; and continuing to perform parallel testing on the non-abnormal anti-counterfeiting chips among the multiple anti-counterfeiting chips to be tested according to the re-divided test stages, and the first test position and the second test position in each test stage.

[0090] It is understandable that after the test position where the abnormal anti-counterfeiting chip is placed is isolated, if subsequent testing is still performed according to the previously divided test phases, first test position, and second test position, meaningless control of the switching branch will occur. Therefore, in this case, the number of non-abnormal anti-counterfeiting chips in the multiple anti-counterfeiting chips to be tested will be counted, and then the test phases and the first and second test positions within each test phase will be re-divided according to the number of non-abnormal anti-counterfeiting chips. Then, according to the re-divided test phases and the first and second test positions within each test phase, the non-abnormal anti-counterfeiting chips in the multiple anti-counterfeiting chips to be tested will continue to be tested in parallel.

[0091] Optionally, after isolating the test position where the abnormal anti-counterfeiting chip is placed, the parallel testing method also includes: introducing new anti-counterfeiting chips to be tested with the same number as the abnormal anti-counterfeiting chips, and continuing to perform parallel testing on the new anti-counterfeiting chips to be tested and the non-abnormal anti-counterfeiting chips among the multiple anti-counterfeiting chips to be tested; wherein, after the non-abnormal anti-counterfeiting chip completes all test items, the new anti-counterfeiting chip to be tested is tested for the test items completed by the abnormal anti-counterfeiting chip.

[0092] It's understandable that after the test position where the abnormal security chip is placed is isolated, if subsequent testing is still performed according to the previously divided test phases, first test position, and second test position, meaningless control of the switching branch will occur. Therefore, in this case, new security chips to be tested are introduced with the same number of abnormal security chips as the isolated abnormal security chips, replacing them.

[0093] It should be noted that the newly introduced anti-counterfeiting chip to be tested does not undergo the test items that were performed before the abnormal anti-counterfeiting chip was determined to be abnormal. Therefore, after the non-abnormal anti-counterfeiting chip completes all test items, the new anti-counterfeiting chip to be tested will be tested for the test items that the abnormal anti-counterfeiting chip completed.

[0094] In this embodiment, after each test phase is completed, the first test result data of each security chip to be tested is obtained. Based on the first test result data, it is determined whether there is an abnormal security chip among the multiple security chips to be tested. If there is, the test position where the abnormal security chip is placed is isolated. In this way, meaningless testing of abnormal security chips can be avoided.

[0095] In some embodiments, the parallel testing method further includes: obtaining second test result data of the anti-counterfeiting chip to be tested in each test position after all test stages are completed; and generating a test report for each anti-counterfeiting chip to be tested based on the second test result data.

[0096] In this embodiment, after all test phases are completed, the second test result data of each security chip to be tested is obtained and a test report for each security chip to be tested is determined. This allows the user to intuitively understand the performance of the security chip to be tested in each test position in different test items.

[0097] Combine Figure 7 As shown, the main control module 300 includes: a processor (processor) 701 and a memory (memory) 702. Optionally, the main control module may also include a communication interface (communication interface) 703 and a bus 704. The processor 701, communication interface 703, and memory 702 can communicate with each other via the bus 704. The communication interface 703 can be used for information transmission. The processor 701 can call the logic instructions in the memory 702 to execute the parallel testing method for multiple anti-counterfeiting chips of the above embodiment.

[0098] In addition, the logic instructions in the memory 702 can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0099] Memory 702, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as the program instructions / modules corresponding to the methods in the embodiments of the present disclosure. Processor 701 executes the program instructions / modules stored in memory 702 to perform functional applications and data processing, thereby implementing the parallel testing method for multiple anti-counterfeiting chips in the above-mentioned embodiments.

[0100] The memory 702 may include a program storage area and a data storage area. The program storage area may store an operating system and at least one application required for a function; the data storage area may store data generated based on the use of the terminal device. Furthermore, the memory 702 may include high-speed random access memory and non-volatile memory.

[0101] An embodiment of the present disclosure provides a computer-readable storage medium storing program instructions, wherein the program instructions are used to execute the above-mentioned parallel testing method for multiple anti-counterfeiting chips when running.

[0102] The technical solutions of the embodiments of the present disclosure may be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiments of the present disclosure. The aforementioned storage medium may be a non-transitory storage medium, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, among other media capable of storing program code.

[0103] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible variations. Unless explicitly required, individual components and functions are optional, and the order of operations may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to also include plural forms. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of one or more associated listings. In addition, when used in this application, the term "comprise" and its variations "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups of these. In the absence of further restrictions, an element defined by the sentence "comprising a..." does not exclude the presence of other identical elements in the process, method or device that includes the element. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments can be referenced to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can be found in the description of the method part.

[0104] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. The technicians will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0105] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units can be merely a logical functional division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, and can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected to implement this embodiment according to actual needs. In addition, the functional units in the embodiments of the present disclosure may be integrated into a processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0106] The flowcharts and block diagrams in the accompanying drawings show the possible implementation architectures, functions and operations of the systems, methods and computer program products according to the embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment or part of the code, and the module, program segment or part of the code contains one or more executable instructions for implementing the specified logical functions. In some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, or they can sometimes be executed in the opposite order, which can depend on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in an order different from that disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, or they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action, or may be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A testing device, characterized in that: include: Chip carrier, switching circuit and main control module; The chip carrier includes a plurality of test positions, and the test positions are used to place the anti-counterfeiting chip to be tested; The switching circuit includes a plurality of switching branches and a decoder; The decoder is connected to the main control module and each switching branch to control the on and off of the switching branch; the switching branch corresponds to the test position one by one, and the on and off of the switching branch is used to switch the anti-counterfeiting chip to be tested in the corresponding test position to be connected to the SWI output terminal of the main control module or to an external power supply; The main control module is used to output control instructions to the decoder to control the on and off of the switching branch according to the number of test positions where the anti-counterfeiting chips to be tested are placed and the test duration of each test item of the anti-counterfeiting chip to be tested, so as to perform parallel testing on the anti-counterfeiting chips to be tested placed in multiple test positions.

2. The test device according to claim 1, characterized in that The output end of the switching branch is connected to the input end of the corresponding test bit; the first input end of the switching branch is connected to the SWI output end of the main control module, the second input end is connected to the output end of the decoder, and the third input end is connected to the external power supply; The decoder is connected to the GPIO output terminal of the main control module.

3. The testing device according to claim 1, characterized in that The switching branch includes: a PMOS tube, a first resistor and a second resistor; The source of the PMOS tube is connected to the SWI output of the main control module as the first input of the switching branch; the gate of the PMOS tube is connected to the output of the decoder as the second input of the switching branch; the drain of the PMOS tube is connected to the input of the corresponding test bit as the output of the switching branch; One end of the first resistor is connected to the external power supply as the third input end of the switching branch, and the other end is connected to the drain of the PMOS tube; One end of the second resistor is connected to the source of the PMOS tube, and the other end is connected to the gate of the PMOS tube.

4. A parallel testing method for multiple anti-counterfeiting chips, applied to the testing device as described in any one of claims 1 to 3, characterized in that: Parallel testing methods include: Determine the number of test positions where the anti-counterfeiting chip to be tested is placed and the test duration of each test item of the anti-counterfeiting chip to be tested; According to the number of test positions where the anti-counterfeiting chips to be tested are placed, the chip testing process is divided into a plurality of test phases equal to the number of test positions, and each test phase at least traverses and tests all the test positions where the anti-counterfeiting chips to be tested are placed; Determine a first test item and a second test item according to the test duration of each test item, wherein the test duration of the first test item is greater than the test duration of each second test item; In each test phase, one of the multiple test positions where the anti-counterfeiting chip to be tested is placed is selected as the first test position, and the remaining test positions are selected as the second test positions; the first test position executes the first test item, and the multiple second test positions respectively execute their corresponding second test items; wherein the first test position in each test phase is different.

5. The parallel testing method according to claim 4, characterized in that: The maximum test duration of each test phase is the test duration of the first test item; In each test phase, the first test bit is first controlled to start executing the first test item. During the process of the first test bit executing the first test item, a plurality of second test bits are alternately controlled to start executing the corresponding second test items.

6. The parallel testing method according to claim 5, characterized in that: Firstly, the first test bit is controlled to start executing the first test item, and in the process of executing the first test item at the first test bit, a plurality of second chip test bits are alternately controlled to start executing the corresponding second test items, including: Controlling the switch branch corresponding to the first test bit to be turned on, so that the first test bit is connected to the SWI output terminal of the main control module, and receiving the test instruction of the first test item output by the SWI output terminal; After the first test position receives the test instruction of the first test item, the switch branch corresponding to the first test position is controlled to be disconnected, so that the first test position is connected to the external power supply; The switching branches corresponding to the plurality of second test bits are alternately controlled to be turned on, so that the plurality of second test bits are alternately connected to the SWI output terminal of the main control module, and the test instructions of the corresponding second test items outputted by the SWI output terminal are received.

7. The parallel testing method according to claim 5, characterized in that: When the sum of the test durations of the plurality of second test items is less than the test duration of the first test item, a second test position will execute the plurality of second test items in one test phase.

8. The parallel testing method according to any one of claims 4 to 7, characterized in that: Also includes: After each test phase is completed, first test result data of the anti-counterfeiting chip to be tested in each test position is obtained; Determining an abnormal anti-counterfeit chip among the plurality of anti-counterfeit chips to be tested according to the first test result data; The test location where the abnormal anti-counterfeit chip is placed is isolated.

9. The parallel testing method according to any one of claims 4 to 7, characterized in that: Also includes: After all the test phases are completed, the second test result data of the anti-counterfeiting chip to be tested in each test position is obtained; A test report for each anti-counterfeiting chip to be tested is generated according to the second test result data.

10. A computer-readable storage medium storing program instructions, characterized in that: When the program instructions are executed, they are used to execute the parallel testing method for multiple anti-counterfeiting chips as claimed in any one of claims 4 to 9.

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