Digital quantity input channel line fault monitoring circuit based on capacitor charging time

Abstract

The invention discloses a digital quantity input channel line fault monitoring circuit based on capacitor charging time, relates to a digital quantity input channel line fault detection device, and aims to solve the problems that an existing digital quantity input channel line fault monitoring circuit is relatively complex and large in size. The capacitor charging circuit is used for accessing an input channel line of a digital quantity input module and outputting a sampling monitoring signal; the voltage division circuit is used for carrying out voltage division on the sampling monitoring signal output by the capacitor charging circuit and outputting a level signal; and obtaining the state of the input channel line of the digital quantity input module according to the duration of the low level of the level signal. The circuit has the advantages that the circuit is simple in overall structure, small in size and low in cost, and when the circuit is applied, the purpose of line fault monitoring is achieved according to different line states and different low-level duration time of a level detection port in a single detection period.

Description

Technical Field

[0001] The invention relates to a digital quantity input channel line fault detection device. Background Art

[0002] As one of the most commonly used control systems in the field of industrial control, digital input modules are mainly used to receive external switch signal inputs and convert them into internally processable digital signals. Therefore, digital input modules usually have the need for line fault monitoring. The commonly used digital input channel line fault monitoring circuits are relatively complex, costly, and large in size, which restricts the development of digital input modules. Summary of the invention

[0003] The purpose of the present invention is to solve the problem that the existing digital quantity input channel line fault monitoring circuit is relatively complex and has a large circuit volume, and proposes a digital quantity input channel line fault monitoring circuit based on capacitor charging time.

[0004] The digital quantity input channel line fault monitoring circuit based on capacitor charging time of the present invention comprises a capacitor charging circuit and a voltage dividing circuit;

[0005] The capacitor charging circuit is used to access the input channel line of the digital input module and output a sampling monitoring signal;

[0006] The voltage divider circuit is used to divide the sampling monitoring signal output by the capacitor charging circuit and output a level signal; the state of the input channel line of the digital input module is obtained according to the duration of the level signal being at a low level; wherein, when the duration of the level signal output by the voltage divider circuit being at a low level is 0, the input channel line of the digital input module is in an open circuit state; when the duration of the level signal output by the voltage divider circuit being at a low level is greater than 0 and is less than the maximum value of the low level time in a normal state, the input channel line of the digital input module is in a normal state; when the duration of the level signal output by the voltage divider circuit being at a low level is greater than the minimum value of the low level time in a short circuit state and is less than the maximum value of the low level time in the short circuit state, the input channel line of the digital input module is in a short circuit state; when the duration of the level signal output by the voltage divider circuit being at a low level is greater than the minimum value of the low level time in an alarm state and is less than the maximum value of the low level time in an alarm state, the input channel line of the digital input module is in an alarm state.

[0007] Further, the capacitor charging circuit includes resistors R1 to R4, transistors Q1, Q2 and capacitor C1;

[0008] The base of the transistor Q1 is a first control signal input terminal;

[0009] The collector of transistor Q1 is connected to one end of resistor R3; the other end of resistor R3 is simultaneously connected to one end of resistor R2, one end of capacitor C1, one end of resistor R2 and one end of resistor R4; and one end of capacitor C1 is used as the output end of the sampling monitoring signal; the other end of resistor R2 is connected to one end of resistor R1, and the other end of resistor R2 is used to access the negative end of the input channel line of the digital input module; the positive end of the input channel line of the digital input module is connected to the output end of the +8V power supply; the other end of resistor R1 is grounded;

[0010] The emitter of transistor Q1 is connected to the other end of capacitor C1 and the collector of transistor Q2 at the same time;

[0011] The base of the transistor Q2 is the second control signal input terminal;

[0012] The emitter of the transistor Q2 is connected to the other end of the resistor R4 and is grounded.

[0013] Furthermore, it also includes an MCU controller;

[0014] The IO port operation1 of the MCU controller is used to be connected to the first control signal input terminal of the capacitor charging circuit;

[0015] The IO port operation2 of the MCU controller is used to be connected to the second control signal input terminal of the capacitor charging circuit.

[0016] Further, the voltage divider circuit includes resistors R5 to R11, a first comparator U1A, a second comparator U2A and a transistor Q3;

[0017] One end of the resistor R5 is connected to the output end of the +8V power supply; the other end of the resistor R5 is simultaneously connected to one end of the resistor R6 and the same-direction input end of the first comparator U1A;

[0018] The inverting input terminal of the first comparator U1A is used to input a sampling monitoring signal;

[0019] The other end of the resistor R6 is connected to one end of the resistor R7 and the same-direction input end of the second comparator U2A; the other end of the resistor R7 is grounded;

[0020] The reverse input terminal of the second comparator U2A is used to input the sampling monitoring signal; the positive power supply terminal of the second comparator U2A is connected to the output terminal of the +12V power supply; the negative power supply terminal of the second comparator U2A is grounded;

[0021] The output end of the first comparator U1A is simultaneously connected to the output end of the second comparator U2A, one end of the resistor R8 and one end of the resistor R9; the other end of the resistor R8 is connected to the output end of the power supply VCC; the other end of the resistor R9 is connected to the base of the transistor Q3; the collector of the transistor Q3 is connected to the output end of the power supply VCC; the emitter of the transistor Q3 is simultaneously connected to one end of the resistor R10 and one end of the resistor R11; the other end of the resistor R10 is grounded; the other end of the resistor R11 is the level signal output end.

[0022] Further, it also includes a level monitoring circuit;

[0023] The level monitoring circuit is used to receive the level signal output by the voltage divider circuit, determine the time when the level signal is at a low level, and obtain the state of the input channel line of the digital input module according to the duration of the level signal being at a low level.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] The present invention firstly utilizes a capacitor charging circuit to access an input channel line of a digital quantity input module to output a sampling monitoring signal, and then performs voltage division control on the sampling monitoring signal output by the capacitor charging circuit through a voltage division circuit to output a level signal, and finally determines the time when the level signal is at a low level according to the level monitoring circuit; and obtains the state of the input channel line of the digital quantity input module according to the time when the level signal is at a low level; the overall circuit structure is simple, the volume is small, and the cost is low. When the present invention is applied, according to different line states, the low level duration of the level detection port in a single detection cycle is different, so as to achieve the purpose of monitoring the input channel line fault of the digital quantity input module. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a principle block diagram of a digital quantity input channel line fault monitoring circuit based on capacitor charging time described in the first specific implementation mode;

[0027] Figure 2 is a circuit diagram of a capacitor charging circuit in a second specific implementation mode;

[0028] Figure 3 It is a circuit diagram of the voltage divider circuit in the fourth specific implementation mode. DETAILED DESCRIPTION

[0029] Specific implementation method 1. Combination Figure 1 To illustrate this embodiment, the digital quantity input channel line fault monitoring circuit based on capacitor charging time described in this embodiment includes a capacitor charging circuit 2 and a voltage divider circuit 3;

[0030] The capacitor charging circuit 2 is used to access the input channel line of the digital input module 1 and output a sampling monitoring signal;

[0031] The voltage divider circuit 3 is used to divide the sampling monitoring signal output by the capacitor charging circuit 2 and output a level signal; the state of the input channel line of the digital input module 1 is obtained according to the duration of the level signal being at a low level; wherein, when the duration of the level signal output by the voltage divider circuit 3 being at a low level is 0, the input channel line of the digital input module 1 is in an open circuit state; when the duration of the level signal output by the voltage divider circuit 3 being at a low level is greater than 0 and is less than the maximum value of the low level time in the normal state, the input channel line of the digital input module 1 is in a normal state; when the duration of the level signal output by the voltage divider circuit 3 being at a low level is greater than the minimum value of the low level time in the short-circuit state and is less than the maximum value of the low level time in the short-circuit state, the input channel line of the digital input module 1 is in a short-circuit state; when the duration of the level signal output by the voltage divider circuit 3 being at a low level is greater than the minimum value of the low level time in the alarm state and is less than the maximum value of the low level time in the alarm state, the input channel line of the digital input module 1 is in an alarm state.

[0032] In this embodiment, firstly, the capacitor charging circuit 2 is used to access the input channel line of the digital input module 1 to output a sampling monitoring signal. Secondly, the sampling monitoring signal output by the capacitor charging circuit 2 is controlled by the voltage divider circuit 3 to output a level signal. The state of the input channel line of the digital input module 1 is obtained according to the time when the level signal is at a low level; the maximum value of the low level time in the normal state, the minimum value of the low level time in the short circuit state, the minimum value of the low level time in the alarm state, and the maximum value of the low level time in the alarm state can all be confirmed through the product specification of the digital input module 1, and can also be obtained through multiple sampling tests; the maximum value of the low level time in the normal state, the minimum value of the low level time in the short circuit state, the minimum value of the low level time in the alarm state, and the maximum value of the low level time in the alarm state are all related to the configuration parameters of the digital input module 1.

[0033] Specific implementation method 2: Combination Figure 2 This embodiment is described. This embodiment further limits the digital input channel line fault monitoring circuit based on capacitor charging time described in the specific embodiment 1. In this embodiment, the capacitor charging circuit 2 includes resistors R1 to R4, transistors Q1, Q2 and capacitor C1;

[0034] The base of the transistor Q1 is a first control signal input terminal;

[0035] The collector of transistor Q1 is connected to one end of resistor R3; the other end of resistor R3 is simultaneously connected to one end of resistor R2, one end of capacitor C1, one end of resistor R2 and one end of resistor R4; and one end of capacitor C1 is used as the output end of the sampling monitoring signal; the other end of resistor R2 is connected to one end of resistor R1, and the other end of resistor R2 is used to access the negative end of the input channel line of digital quantity input module 1; the positive end of the input channel line of digital quantity input module 1 is connected to the output end of +8V power supply; the other end of resistor R1 is grounded;

[0036] The emitter of transistor Q1 is connected to the other end of capacitor C1 and the collector of transistor Q2 at the same time;

[0037] The base of the transistor Q2 is the second control signal input terminal;

[0038] The emitter of the transistor Q2 is connected to the other end of the resistor R4 and is grounded.

[0039] In this embodiment, the resistance value of resistor R1 is 2.2kΩ, the resistance value of resistor R2 is 100kΩ, the resistance value of resistor R3 is 200Ω, the resistance value of resistor R4 is 2.2MΩ, the capacitance value of capacitor C1 is 0.1uF, transistor Q1 is an NPN transistor, and transistor Q2 is an NPN transistor.

[0040] In this embodiment, the first control signal input terminal of the capacitor charging circuit 2 is controlled to be low level, and the second control signal input terminal of the capacitor charging circuit 2 is high level; the capacitor C1 enters the charging stage; the first control signal input terminal of the capacitor charging circuit 2 is controlled to be high level, and the second control signal input terminal of the capacitor charging circuit 2 is high level; the capacitor C1 enters the discharging stage;

[0041] During the discharge phase of capacitor C1, resistors R2, R3, R1 and the parts connected to the external interfaces DIN1+ and DIN1- form a voltage divider circuit. Resistor R1 also acts as a current limiter to prevent the current connected to the parts of the external detection interfaces DIN1+ and DIN1- from being too low, which would affect the detection effect. Capacitor C1 is connected to both ends of resistor R3, whose resistance is much lower than that of resistor R2, and the divided voltage is almost 0, achieving the purpose of rapid discharge;

[0042] Each acquisition cycle is divided into two parts: the capacitor C1 discharge stage and the capacitor C1 charging stage. During the capacitor C1 discharge stage, operation1 and operation2 are high level. Resistors R2 and R3 are connected in series and in parallel with resistor R1, and then divided with the external detection interface resistor. At this time, the voltage across capacitor C1 is approximately 0V.

[0043] In the charging stage, the control interface operation1 is low level, and operation2 is high level. Resistors R2, R84, R1, and the parts connected to the external interfaces DIN1+ and DIN1- form a voltage divider circuit. Resistors R1 also play a current limiting role to prevent the current of the parts connected to the external detection interfaces DIN1+ and DIN1- from being too low, which affects the detection effect. Capacitor C1 is connected to both ends of resistor R4, and the resistance of resistor R4 is much greater than that of resistor R2. At this time, capacitor C1 is charged. The state of the external interface line is different, the charging speed of capacitor C1 is different, and the final state after charging is also different. According to the low level duration of the output level signal of the voltage divider circuit, the charging change of capacitor C1 is reflected, and then the input channel line state of the digital input module 1 is judged.

[0044] During the charging phase of capacitor C1, resistors R2 and R4 are connected in series and then connected in parallel with resistor R1, and then voltage is divided with the external detection interface resistor. At this time, the state of the input channel line of the digital input module 1 can be determined by measuring the final charging voltage across capacitor C1;

[0045] When the final charging voltage across the capacitor C1 is the first threshold voltage, the input channel circuit of the digital input module 1 is in a normal state, and the first threshold voltage is 3.06V; when the final charging voltage across the capacitor C1 is the second threshold voltage, the input channel circuit of the digital input module 1 is in an alarm state, and the second threshold voltage is 4.55V; when the final charging voltage across the capacitor C1 is the third threshold voltage, the input channel circuit of the digital input module 1 is in a short circuit state; the third threshold voltage is 7.65V; when the final charging voltage across the capacitor C1 is 0V, the digital input The input channel line of the input module 1 is in an open circuit state; compared with obtaining the state of the input channel line of the digital input module 1 based on the time when the level signal is at a low level, the capacitor charging circuit described in this embodiment determines the state of the input channel line of the digital input module 1 through the final charging voltage across the capacitor C1; and the final charging voltage across the capacitor C1 can be directly measured by a voltmeter; the first threshold voltage, the second threshold voltage and the third threshold voltage are related to the resistance value of the resistor R1, the resistance value of the resistor R2, the resistance value of the resistor R3, the resistance value of the resistor R4 and the capacitance value of the capacitor C1.

[0046] In each charging cycle of capacitor C1, when the input channel line of the digital input module 1 is in a normal state, before the voltage across capacitor C1 rises to 0.192V, the level signal output by the voltage divider circuit is a high level, and after the voltage across capacitor C1 is greater than 0.192V, the level signal output by the voltage divider circuit is a low level; when the input channel line of the digital input module 1 is in an alarm state, before the voltage across capacitor C1 rises to 0.192V, the level signal output by the voltage divider circuit is a high level, before the voltage across capacitor C1 is greater than 0.192V and less than 4.024V, the level signal output by the voltage divider circuit is a low level, and after the voltage across capacitor C1 is greater than 4.024V, The level signal output by the voltage divider circuit is a high level; when the input channel line of the digital input module 1 is in a short-circuit state, before the voltage across the capacitor C1 rises to 0.192V, the level signal output by the voltage divider circuit is a high level, and before the voltage across the capacitor C1 is greater than 0.192V and less than 4.024V, the level signal output by the voltage divider circuit is a low level, and the low level duration is less than the alarm state. After the voltage across the capacitor C1 is greater than 4.024V, the level signal output by the voltage divider circuit is a high level; when the input channel line of the digital input module 1 is in an open-circuit state, the voltage across the capacitor C1 is always less than 0.192V, and the level signal output by the voltage divider circuit is always a high level.

[0047] Specific implementation method three: This implementation method further limits the digital input channel line fault monitoring circuit based on capacitor charging time described in specific implementation method two. In this implementation method, it also includes an MCU controller;

[0048] The IO port operation1 of the MCU controller is used to connect to the first control signal input terminal of the capacitor charging circuit 2;

[0049] The IO port operation2 of the MCU controller is used to be connected to the second control signal input terminal of the capacitor charging circuit 2.

[0050] In this embodiment, the first control signal and the second control signal are provided by the MCU controller; the first control signal is provided by the IO port operation1 of the MCU controller, and the first control signal switches between a low level and a high level; the second control signal is always in a high level state. The model of the MCU controller is: STM32F103C8T6.

[0051] Specific implementation method 4. Combination Figure 3This embodiment is described. This embodiment further limits the digital input channel line fault monitoring circuit based on capacitor charging time described in the specific embodiment 1. In this embodiment, the voltage divider circuit 3 includes resistors R5 to R11, a first comparator U1A, a second comparator U2A and a transistor Q3;

[0052] One end of the resistor R5 is connected to the output end of the +8V power supply; the other end of the resistor R5 is simultaneously connected to one end of the resistor R6 and the same-direction input end of the first comparator U1A;

[0053] The inverting input terminal of the first comparator U1A is used to input a sampling monitoring signal;

[0054] The other end of the resistor R6 is connected to one end of the resistor R7 and the same-direction input end of the second comparator U2A; the other end of the resistor R7 is grounded;

[0055] The reverse input terminal of the second comparator U2A is used to input the sampling monitoring signal; the positive power supply terminal of the second comparator U2A is connected to the output terminal of the +12V power supply; the negative power supply terminal of the second comparator U2A is grounded;

[0056] The output end of the first comparator U1A is simultaneously connected to the output end of the second comparator U2A, one end of the resistor R8 and one end of the resistor R9; the other end of the resistor R8 is connected to the output end of the power supply VCC; the other end of the resistor R9 is connected to the base of the transistor Q3; the collector of the transistor Q3 is connected to the output end of the power supply VCC; the emitter of the transistor Q3 is simultaneously connected to one end of the resistor R10 and one end of the resistor R11; the other end of the resistor R10 is grounded; the other end of the resistor R11 is the level signal output end.

[0057] In this embodiment, the resistor R5 is a 24.9kΩ resistor, the resistor R6 is a 24kΩ resistor, the resistor R7 is a 1.2kΩ resistor, the resistor R8 is a 15kΩ resistor, the resistor R9 is a 4.7kΩ resistor, the resistor R10 is a 4.7kΩ resistor, and the resistor R11 is a 470Ω resistor; the transistor Q3 is a PNP transistor; the resistor R5, the resistor R6 and the resistor R7 form a voltage divider circuit, which is connected to the first comparator U1A and the second comparator U1B, the voltage divider voltage of the positive input terminal of the first comparator U1A is 4.024V, and the voltage divider voltage of the positive input terminal of the second comparator U1B is 0.192V. When the voltage across the capacitor C1 is greater than 0.192V and less than 4.024V, the first comparator U1A and the second comparator U1B jointly output a high level, and the voltage divider circuit 3 outputs a low level signal, and in other cases, the voltage divider circuit 3 outputs a high level signal.

[0058] Specific implementation method 5: This implementation method further limits the digital input channel line fault monitoring circuit based on capacitor charging time described in specific implementation method 1. In this implementation method, it also includes a level monitoring circuit 4;

[0059] The level monitoring circuit 4 is used to receive the level signal output by the voltage divider circuit 3, determine the time when the level signal is at a low level, and obtain the state of the input channel line of the digital input module 1 according to the duration of the level signal being at a low level.

[0060] In this embodiment, the level monitoring circuit 4 determines whether the level signal is a high level or a low level, and draws a plane rectangular coordinate system with time as the horizontal coordinate and the high or low level of the level signal as the vertical coordinate; by accumulating the low level in different time periods in each cycle, the duration of the level signal being a low level is obtained; and then the input channel line point state of the digital input module 1 is determined according to the duration of the low level.

[0061] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A digital input channel line fault monitoring circuit based on capacitor charging time, characterized in that: It comprises a capacitor charging circuit (2) and a voltage dividing circuit (3); A capacitor charging circuit (2) is used to connect to the input channel line of the digital quantity input module (1) and output a sampling monitoring signal; The voltage divider circuit (3) is used to divide the sampling monitoring signal output by the capacitor charging circuit (2) and output a level signal; the state of the input channel line of the digital quantity input module (1) is obtained according to the duration of the level signal being at a low level; wherein, when the duration of the level signal output by the voltage divider circuit (3) being at a low level is 0, the input channel line of the digital quantity input module (1) is in an open circuit state; when the duration of the level signal output by the voltage divider circuit (3) being at a low level is greater than 0 and less than the maximum value of the low level time in the normal state, the input channel line of the digital quantity input module (1) is in a normal state; when the duration of the level signal output by the voltage divider circuit (3) being at a low level is greater than the minimum value of the low level time in the short circuit state and less than the maximum value of the low level time in the short circuit state, the input channel line of the digital quantity input module (1) is in a short circuit state; when the duration of the level signal output by the voltage divider circuit (3) being at a low level is greater than the minimum value of the low level time in the alarm state and less than the maximum value of the low level time in the alarm state, the input channel line of the digital quantity input module (1) is in an alarm state.

2. The digital input channel line fault monitoring circuit based on capacitor charging time according to claim 1, characterized in that: The capacitor charging circuit (2) comprises resistors R1 to R4, a transistor Q1, a transistor Q2 and a capacitor C1; The base of the transistor Q1 is a first control signal input terminal; The collector of the transistor Q1 is connected to one end of the resistor R3; the other end of the resistor R3 is simultaneously connected to one end of the resistor R2, one end of the capacitor C1, one end of the resistor R2 and one end of the resistor R4; and one end of the capacitor C1 is used as the output end of the sampling monitoring signal; the other end of the resistor R2 is connected to one end of the resistor R1, and the other end of the resistor R2 is used to connect to the negative end of the input channel line of the digital input module (1); the positive end of the input channel line of the digital input module (1) is connected to the output end of the +8V power supply; the other end of the resistor R1 is grounded; The emitter of transistor Q1 is connected to the other end of capacitor C1 and the collector of transistor Q2 at the same time; The base of the transistor Q2 is the second control signal input terminal; The emitter of the transistor Q2 is connected to the other end of the resistor R4 and is grounded.

3. The digital input channel line fault monitoring circuit based on capacitor charging time according to claim 2, characterized in that: Also includes MCU controller; The IO port operation1 of the MCU controller is used to be connected to the first control signal input terminal of the capacitor charging circuit (2); The IO port operation2 of the MCU controller is used to be connected to the second control signal input end of the capacitor charging circuit (2).

4. The digital input channel line fault monitoring circuit based on capacitor charging time according to claim 1, characterized in that: The voltage divider circuit (3) comprises resistors R5 to R11, a first comparator U1A, a second comparator U2A and a transistor Q3; One end of the resistor R5 is connected to the output end of the +8V power supply; the other end of the resistor R5 is simultaneously connected to one end of the resistor R6 and the same-direction input end of the first comparator U1A; The inverting input terminal of the first comparator U1A is used to input a sampling monitoring signal; The other end of the resistor R6 is connected to one end of the resistor R7 and the same-direction input end of the second comparator U2A; the other end of the resistor R7 is grounded; The reverse input terminal of the second comparator U2A is used to input the sampling monitoring signal; the positive power supply terminal of the second comparator U2A is connected to the output terminal of the +12V power supply; the negative power supply terminal of the second comparator U2A is grounded; The output end of the first comparator U1A is simultaneously connected to the output end of the second comparator U2A, one end of the resistor R8 and one end of the resistor R9; the other end of the resistor R8 is connected to the output end of the power supply VCC; the other end of the resistor R9 is connected to the base of the transistor Q3; the collector of the transistor Q3 is connected to the output end of the power supply VCC; the emitter of the transistor Q3 is simultaneously connected to one end of the resistor R10 and one end of the resistor R11; the other end of the resistor R10 is grounded; the other end of the resistor R11 is the level signal output end.

5. The digital input channel line fault monitoring circuit based on capacitor charging time according to claim 1, characterized in that: Also includes a level monitoring circuit (4); A level monitoring circuit (4) is used to receive the level signal output by the voltage divider circuit (3) and determine the time when the level signal is at a low level; The state of the input channel line of the digital quantity input module (1) is obtained according to the duration of the low level of the level signal.

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