Multi-clock domain reset data processing method and system

Abstract

The invention relates to the technical field of multi-clock domain reset data processing, and discloses a multi-clock domain reset data processing method and system, and the method comprises the steps: setting a data buffer region at each clock domain input interface for data interaction, and enabling a data receiving clock domain to buffer a data package transmitted by a data transmitting clock domain, the data cache region at least can store one data packet with the maximum length type; and determining to clear or output data stored in the data cache region of the data receiving clock domain based on the reset signal moments generated by the data sending clock domain and the data receiving clock domain and the transmission state of the data packet. According to the embodiment of the invention, during multi-clock domain resetting, a reasonable decision can be made according to the data transmission state, so that the data can be correctly processed under different conditions, the data transmission of the system under the multi-clock domain environment is more reliable, the probability of data errors and system faults caused by clock domain differences is reduced, and the reliability of the system is improved. And the stability of the system in a multi-clock domain environment is ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of cross-clock domain reset data processing, and in particular to a multi-clock domain reset data processing method and system. Background Art

[0002] Cross-clock design is widely used in required fields and scenarios, which can ensure the correctness and reliability of data transmission and processing between different clock domains and improve the performance and stability of the system. For example, in complex integrated circuits, different modules are often required to run at different clock frequencies. For example, the CPU core, graphics processing unit, memory controller, etc. in the processor chip may use different clocks, so that the design can be optimized according to the performance requirements and power consumption requirements of each module; in the network switch of the communication system, the data of different ports may come from different devices with different clock frequencies, and cross-clock processing is required to correctly forward the data; different control tasks in the embedded system may need to be executed at different clock frequencies. For example, tasks such as motor control and temperature control may require different sampling cycles and control frequencies. In the design of smart network cards based on FPGA hardware platforms, there will be different clock domains. When different clock domains need to communicate with each other, signal transmission across clock domains will be involved. In this case, there are mainly two directions, one is the synchronization between cross-clock domain signals, which is the synchronization relationship between the control bus and the data bus. The other is the reset relationship between signals across clock domains, which is the abnormal handling of signal transmission.

[0003] In a multi-clock domain system, when data is transmitted between different clock domains, in addition to the synchronization problem of the reset signal, the consistency of the data itself is also difficult to ensure. The clock frequency and phase differences between different clock domains may cause data loss, duplication or errors during transmission. Especially in high-speed data transmission and complex system architecture, this data consistency problem is more prominent, so it is necessary to solve the problem of multiple clock domains resetting at different times and abnormal data packet transmission. Summary of the invention

[0004] In view of this, the present invention provides a multi-clock domain reset data processing method and system, which can solve the problem of abnormal transmission of data packets when resetting multiple clock domains.

[0005] In a first aspect, the present invention provides a multi-clock domain reset data processing method, the method comprising:

[0006] A data buffer is set at each clock domain input interface for data interaction, wherein the data buffer is used for caching data packets sent by the data receiving clock domain from the data sending clock domain, and the data buffer can store at least one data packet of the maximum length type;

[0007] Based on the reset signal timing generated by the data sending clock domain and the data receiving clock domain and the transmission status of the data packet, it is determined whether the data stored in the data buffer area of ​​the data receiving clock domain is cleared or outputted.

[0008] The multi-clock domain reset data processing method provided by the embodiment of the present invention determines the data clearing or outputting of the data stored in the data buffer area of ​​the data receiving clock domain based on the reset signal moment generated by the data sending clock domain and the data receiving clock domain and the transmission status of the data packet, thereby realizing the precise control of the transmission data. Under the action of the reset signal, reasonable decisions can be made according to the specific data transmission status to ensure that the data can be correctly processed under different circumstances, making the data transmission of the system in a multi-clock domain environment more reliable, and reducing the probability of data errors and system failures caused by clock domain differences. At the same time, by detecting the packet header and / or packet tail of the transmission data, the reasonable management and control of the data buffer area also improves the stability and maintainability of the system. When a problem occurs, it can be easier to locate and solve the failure of the data transmission link, reducing the difficulty and cost of system maintenance.

[0009] In an optional embodiment, at the moment of the reset signal generated by the data sending clock domain and / or the data receiving clock domain, if no data packet is being transmitted across the clock module, the reset signal generated by the data sending clock domain and the data receiving clock domain does not affect the integrity of the data packet, and the data in the data buffer area of ​​the data receiving clock domain is output normally.

[0010] In the embodiment of the present invention, when no data packet is being transmitted across the clock module, the reset signal does not affect the integrity of the data packet. During the reset operation, the transmission data corresponding to the corresponding clock domain will be cleared and the control signal will be initialized. After the reset operation is completed, the data signals from other clock domains will be received and transmitted again, and corresponding judgments will be made. The subsequent packet header and packet tail judgment is for the integrity detection of the data packet. During the reset period, the corresponding clock domain data transmission is interrupted, and data cannot be transmitted at this time. It is necessary to wait until the reset operation is completed before starting to judge and transmit data.

[0011] In an optional implementation, the determining of clearing or outputting data stored in a data buffer area of ​​a data receiving clock domain based on the reset signal timing generated by a data sending clock domain and a data receiving clock domain and the transmission status of a data packet includes:

[0012] At the moment of the reset signal generated by the data sending clock domain and / or the data receiving clock domain, if a data packet is being transmitted across the clock module, the integrity of the data packet transmission during the reset signal generated by the data sending clock domain and / or the data receiving clock domain is determined by detecting the packet header and / or packet tail of the newly transmitted data after the reset signal ends, and based on the integrity of the data packet transmission, the data stored in the data buffer area of ​​the data receiving clock domain is cleared or output.

[0013] In the embodiment of the present invention, when a data packet is being transmitted across the clock module, the integrity of the data packet transmission during the reset signal process can be accurately determined by detecting the packet header and / or packet tail of the newly transmitted data after the reset signal ends. This enables the system to effectively monitor the transmission status of the data packet in a complex multi-clock domain environment to avoid incomplete or erroneous data caused by the interference of the reset signal. In this way, it is possible to promptly discover whether the data packet is truncated or damaged during the transmission process. If the data packet is detected to be incomplete, corresponding measures can be taken, such as clearing part of the data or requesting retransmission, to ensure the integrity of the data.

[0014] In an optional embodiment, at the moment of the reset signal generated by the data receiving clock domain, if a data packet is being transmitted across the clock module and part of the data in the data packet has been transmitted to the data cache area of ​​the data receiving clock domain, the data stored in the data cache area is cleared; after monitoring that the reset of the data receiving clock domain is completed, the input interface is checked to see if there is a packet header indication signal in the newly input data packet, and if so, the data packet is received and cached in the data cache area, otherwise it is directly discarded.

[0015] In the embodiment of the present invention, when the data receiving clock domain generates a reset signal and a data packet is being transmitted, some of the existing data in the data buffer area is cleared, which can prevent confusion caused by the mixing of new and old data. This ensures that after the reset, the system starts to receive new data from a clear state, avoiding data inconsistency problems caused by the interweaving of some residual old data and new data. By clearing the existing data and receiving the data packet according to the new packet header indication signal after the reset, a clear starting point is established for data processing. This makes the subsequent data processing process more orderly, and each module can operate based on a unified data source, improving the overall data consistency of the system.

[0016] In an optional embodiment, at the moment of the reset signal generated by the data sending clock domain, if a data packet is being transmitted across the clock module and part of the data in the data packet has been transmitted to the data buffer area of ​​the data receiving clock domain, and the remaining data still exists in the data sending clock domain, then the remaining data in the data sending clock domain is cleared; a packet header is detected on the incoming data at the input interface of the data receiving clock domain, and the data packet is written to the data buffer area after a packet header indication signal is detected, and the data is output when a packet tail indication signal of the data packet is detected; if after the data packet is written to the data buffer area after the packet header indication signal is detected, the packet tail indication signal is not detected in the subsequent data input but the packet header indication signal is detected again, the previously cached data is cleared and a new data packet is written, until the packet tail indication signal of the data packet is detected and the data is output.

[0017] In the embodiment of the present invention, when the data transmission clock domain generates a reset signal and there is a partial transmission of a data packet, the remaining data in the data transmission clock domain is cleared, which can prevent incomplete data from continuing to be transmitted and possibly introducing errors. At the same time, strict packet header and packet tail detection is performed on the incoming data in the data receiving clock domain to ensure that only complete data packets are written into the buffer area and output, thereby greatly improving the accuracy of the data. The writing and output of data are controlled by clear packet header and packet tail indication signals, ensuring that the transmission of data between different clock domains is orderly and accurate, and there will be no chaotic writing or erroneous output of data, providing a reliable data source for subsequent data processing; timely clearing of the remaining data in the data transmission clock domain and reasonable processing of data packets in the data receiving clock domain can avoid conflicts between different data packets and improve the stability of the system.

[0018] In an optional implementation, when a reset signal is generated simultaneously in the data transmission clock domain and the data reception clock domain and a data packet is being transmitted, the data in the data buffer area of ​​the data reception clock domain and the remaining data in the transmission clock domain are cleared;

[0019] After monitoring that the reset of the data receiving clock domain has ended, the input interface detects whether there is a packet header indication signal in the newly input data packet; if so, the data packet is received and cached in the data cache area; if not, it is directly discarded; if after the packet header indication signal is detected and the data packet is written to the data cache area, the packet tail indication signal is not detected in the subsequent data input but the packet header indication signal is detected again, the previously cached data is cleared and a new data packet is written, until the packet tail indication signal of the data packet is detected and the data is output.

[0020] In the embodiment of the present invention, when the data transmission clock domain and the data reception clock domain generate a reset signal at the same time and a data packet is being transmitted, all the relevant data in the two clock domains are cleared, thereby avoiding incomplete or possibly erroneous data from remaining in the system. This ensures that the system starts from a clean state after reset, laying a foundation for the accurate transmission and processing of subsequent data. By detecting the packet header indication signal of the new input data packet after the reset, the data packet is received and cached only when the packet header indication signal exists, and detecting the packet tail indication signal in the subsequent data input, it is ensured that only complete data packets are processed and output. This strict detection mechanism greatly improves the accuracy of data transmission, reduces system failures and erroneous results caused by incomplete or erroneous data, and clears all relevant data during reset, effectively preventing conflicts and confusion between different data packets, ensuring that the system can process data in an orderly manner at any time, and improving the stability of the system.

[0021] In a second aspect, the present invention provides a multi-clock domain reset data processing system, comprising:

[0022] A data buffer setting module, used to set a data buffer at each clock domain input interface for data interaction, used for caching data packets sent by the data receiving clock domain from the data sending clock domain, wherein the data buffer can store at least one data packet of the maximum length type;

[0023] The data detection module is used to determine whether to clear or output the data stored in the data buffer area of ​​the data receiving clock domain based on the reset signal time generated by the data sending clock domain and the data receiving clock domain and the transmission status of the data packet.

[0024] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the multi-clock domain reset data processing method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0025] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the multi-clock domain reset data processing method of the first aspect or any corresponding embodiment thereof.

[0026] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions for causing a computer to execute the multi-clock domain reset data processing method of the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0028] Figure 1 A scenario-based schematic diagram for the design of a smart network card based on an FPGA hardware platform;

[0029] Figure 2 It is a schematic diagram of data transmission in multiple clock domains through cross-clock domain modules;

[0030] Figure 3 A schematic diagram of a flow chart of a multi-clock domain reset data processing method according to an embodiment of the present invention;

[0031] Figure 4 is a schematic diagram of a situation in which no data packet is being transmitted across clock modules at the time of a reset signal generated in a data transmission clock domain and / or a data reception clock domain according to an embodiment of the present invention;

[0032] Figure 5 is a schematic diagram of a data packet being transmitted at the time of a reset signal generated in a data receiving clock domain according to an embodiment of the present invention;

[0033] Figure 6 is a schematic diagram of a data packet being transmitted at the moment of a reset signal generated in a data transmission clock domain according to an embodiment of the present invention;

[0034] Figure 7 is a schematic diagram of a data packet being transmitted at the moment when a reset signal is generated simultaneously in a data transmission clock domain and a data reception clock domain according to an embodiment of the present invention;

[0035] Figure 8 A structural block diagram of a multi-clock domain reset data processing system according to an embodiment of the present invention;

[0036] Fig. 9 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0038] There are many solutions for processing multiple clock domains in the existing technology, but there are few designs for smart network cards with DPU (Data Processing Unit). DPU is a dedicated processor in data center scenarios, providing a computing engine for high-bandwidth, low-latency, and data-intensive computing scenarios. This is mainly because there are not many companies that can independently develop smart network cards, and even fewer of them can be commercialized, so there is less related technology research and development.

[0039] In the design of smart network cards based on FPGA hardware platforms, there will be different clock domains. They need to communicate with each other, which will involve signal transmission across clock domains. In this case, there are mainly two directions: one is the synchronization between signals across clock domains, which is the synchronization relationship between the control bus and the data bus. The other is the reset relationship between signals across clock domains, which is the abnormal handling of signal transmission.

[0040] In a design scenario, if Figure 1 The figure shows the DPU smart NIC architecture and its clock domain division. The smart NIC is mainly composed of FPGA+Soc, and peripherals such as DDR are added. Host is the host, and the smart NIC is connected to it through the PCIE slot. In the smart NIC, there are three clock domains, namely Host clock domain, Soc clock domain, and DDR clock domain. Among them, the clock and reset of the Host clock domain are mainly the clock and reset output of the PCIE linked to the Host; the clock and reset of the Soc clock domain are mainly the clock and reset output of the PCIE linked to the Soc; the clock and reset of the DDR clock domain are the clock and reset output of the DDR IP core; the Host clock domain and the Soc clock domain communicate with each other; the Soc clock domain communicates with the DDR clock domain.

[0041] The following is a brief introduction to the data flow between the three clock domains. Figure 1 , the clock direction has two main paths:

[0042] 1. Host--pcie--virtio_blk--virtio_net_blk--pcie--Soc--pcie--virtio_net_blk--ovs--sfp. Specifically, the virtio_blk controller is connected to the Host through the pcie controller, etc. The Host initiates the backend disk read and write operation, which is forwarded by virtio_blk, transparently transmitted in the FPGA, and sent to the Soc outside the FPGA through the virito_net_blk module. The Soc mainly disassembles, merges, maintains the order and forwards the storage package. Then, the TCP protocol is used and the virito_net_blk module forwards it to the optical port through OVS, and the optical fiber is used to connect to the remote switch and disk to realize the read and write operation of the block storage.

[0043] 2. Host--pcie--virtio_net--ovs--ddr--ovs--sfp, specifically means that the Host initiates network packet transmission, which will be forwarded by virtio_net, split or parsed by OVS, and query the corresponding flow table in DDR according to the matching situation, and finally transmitted through the optical port.

[0044] Data flows bidirectionally between these three clock domains, and the interface parts are unified. The following table shows the interface information between cross-clock domains.

[0045]

[0046] The above are signals connected across clock domains, divided into two directions: input and output.

[0047] like Figure 2 As shown in the figure, there is an intermediate transition cross-clock module between the cross-clock domains, connecting the two clock domains a and b. The clock and reset of the b clock domain are driven by clock_b and reset_b, and the output signal bus is valid_b, sop_b, etc. in the table. There is a back pressure signal of ready_b, and the signal output to the cross-clock module is controlled by the back pressure signal. When ready_b is pulled low, the corresponding signal bus cannot be output at this time, that is, valid_b, data_b, etc. maintain the current value. Wait until ready_b is pulled high, and then start data transmission.

[0048] The clock and reset of the a clock domain are driven by clock_a and reset_a. The input signal bus is valid_a, sop_a, etc. in the table. It outputs a ready_a backpressure signal to the cross-clock module, and the received signal bus is controlled by the backpressure signal. When the a clock domain cannot process the data signal at some point in time and does not need to receive the data signal from the cross-clock module, ready_a is actively pulled low. At this time, the signal bus corresponding to the cross-clock module cannot be output, that is, valid_a, data_a, etc. maintain the current value. When the a clock domain processing signal space is released, ready_a is actively pulled high, and the cross-clock module starts to transmit data at this time.

[0049] The cross-clock module is a transition module. This module carries two sets of signals from different clock domains, and its clock drivers are clock_a and clock_b. The two clocks have different frequencies and phase differences. In this module, not only do we need to bridge the signals from two different clock domains, but we also need to do some exception processing. Because the reset signals of reset_a and reset_b are different and unrelated, there is a situation where a single reset occurs in the middle of data transmission, which is a reset exception. At this time, we need to do some evasive processing, otherwise it is very easy to cause incomplete data packet transmission, resulting in abnormal signal processing in the subsequent a clock domain, causing a chain reaction and causing the entire system to crash.

[0050] The method for processing the transmission of signals across clocks generally adopts an asynchronous clock FIFO as a bridge, or adopts several levels of storage to perform multi-clock cycle pipeline processing. The embodiment of the present invention mainly adopts the asynchronous FIFO mode. With this method, the design is relatively simple, because the corresponding FIFO instantiation is directly in the IP library, and the back pressure processing is also relatively convenient, and there is no need to spend a lot of time to develop and debug this part of the code by yourself.

[0051] According to an embodiment of the present invention, an embodiment of a multi-clock domain reset data processing method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0052] In this embodiment, a multi-clock domain reset data processing method is provided. Figure 3 is a flowchart of a method for processing multi-clock domain reset data according to an embodiment of the present invention. Figure 3 As shown, the process includes the following steps:

[0053] S101, setting a data buffer at each clock domain input interface for data exchange for the data receiving clock domain to buffer data packets sent by the data sending clock domain, and the data buffer can store at least one data packet of a maximum length type.

[0054] For example, the b clock domain is used as the data sending domain and the a clock domain is used as the data receiving domain. A larger cache FIFO is added at the input interface of the a clock domain. This cache space can store a data packet of a maximum length type. Reasonable settings are made according to the actual application scenario, and no specific restrictions are made here.

[0055] The embodiment of the present invention sets a data buffer at the input interface of different clock domains, which can effectively alleviate the problem of unstable data transmission caused by clock domain differences. The data buffer can store data packets sent by the data sending clock domain, avoiding the loss or error of data that may occur at the moment of switching between different clock domains. In particular, when the data buffer area can store at least one data packet of the maximum length type, it can cope with various possible data packet size situations and provide reliable cache space for data transmission.

[0056] S102, based on the reset signal timings generated by the data sending clock domain and the data receiving clock domain and the transmission status of the data packet, determine whether to clear or output the data stored in the data buffer area of ​​the data receiving clock domain.

[0057] In practical applications, a reset signal needs to be generated, for example, when the system is started or reset, when a data packet is transmitted incorrectly, when the clock domain switch is unstable, or when system resources are tight or when an upgrade or configuration change occurs. Specifically:

[0058] 1. In actual applications, when the system is just started or a global reset is required due to some faults, the reset signal is triggered. At this time, the data receiving clock domain needs to determine whether the data in the data buffer should be cleared. If there may be residual uncertain data in the buffer before the system starts, or the data in the buffer may have lost its validity after the fault reset, it is necessary to clear these data to ensure that the system starts running from a clean state.

[0059] 2. In a multi-clock domain system, clock domain switching may occur sometimes. If an unstable state occurs during the switching process, the data in the data buffer may be in an uncertain state. At this time, if a reset signal is generated, it can be determined whether to clear the data in the buffer according to the reset signal time and the transmission status of the data packet. If the transmission of the data packet has been interrupted or is in a chaotic state, clearing the data can prepare for data transmission after the system stabilizes again.

[0060] 3. When the system resources (such as memory, processing power, etc.) become tight, the data cache needs to be effectively managed. If the data in the data cache has not been processed for a long time, or there is higher priority data that requires cache space, then you can combine the reset signal time and the transmission status of the data packet to decide whether to clear part or all of the cache data.

[0061] 4. When the system is upgraded or the configuration is changed, it may affect the transmission and processing of data. In this case, the reset signal may be triggered to ensure that the system can operate correctly under the new configuration. The data receiving clock domain needs to determine the processing method of the buffer data based on the reset signal timing and the transmission status of the data packet. If the new configuration is incompatible with the data in the current buffer, or the data transmission process needs to be reinitialized, the data in the buffer may be cleared.

[0062] In actual applications, data in different clock domains may be in different transmission states when reset occurs, such as Figure 4 As shown, at the moment of the reset signal generated by the data sending clock domain and / or the data receiving clock domain, if no data packet is being transmitted across the clock module, the reset signal generated by the data sending clock domain and the data receiving clock domain does not affect the integrity of the data packet, and the data in the data buffer area of ​​the data receiving clock domain is output normally.

[0063] In the embodiment of the present invention, when no data packet is being transmitted across the clock module, the reset signal does not affect the integrity of the data packet. During the reset operation, the transmission data corresponding to the corresponding clock domain will be cleared and the control signal will be initialized. After the reset operation is completed, the data signals from other clock domains will be received and transmitted again, and corresponding judgments will be made. The subsequent packet header and packet tail judgment is for the integrity detection of the data packet. During the reset period, the corresponding clock domain data transmission is interrupted, and data cannot be transmitted at this time. It is necessary to wait until the reset operation is completed before starting to judge and transmit data.

[0064] In an embodiment of the present invention, at the moment when a reset signal is generated in the data sending clock domain and / or the data receiving clock domain, if a data packet is being transmitted across the clock module, the packet header and / or the packet tail of the newly transmitted data after the reset signal ends are detected to determine the completeness of the data packet transmission during the reset signal generated by the data sending clock domain and / or the data receiving clock domain, and based on the completeness of the data packet transmission, determine whether to clear or output the data stored in the data buffer area of ​​the data receiving clock domain.

[0065] In the embodiment of the present invention, when a data packet is being transmitted across the clock module, the integrity of the data packet transmission during the reset signal process can be accurately determined by detecting the packet header and / or packet tail of the newly transmitted data after the reset signal ends. This enables the system to effectively monitor the transmission status of the data packet in a complex multi-clock domain environment, avoiding incomplete or erroneous data caused by the interference of the reset signal. In this way, it is possible to promptly detect whether the data packet is truncated or damaged during the transmission process. Specifically, it includes the following situations:

[0066] 1. At the moment of the reset signal generated by the data receiving clock domain, if a data packet is being transmitted across the clock module and part of the data in the data packet has been transmitted to the data buffer area of ​​the data receiving clock domain, the data stored in the data buffer area is cleared; after monitoring the reset of the data receiving clock domain, the input interface is checked for a packet header indication signal in the newly input data packet. If so, the data packet is received and cached in the data buffer area. If not, it is directly discarded. For example, Figure 5 As shown in the figure, when reset_a of clock domain a is pulled high to reset, data packet pkt_a is being transmitted. At this time, d0, d1, and d2 in the data packet have been transmitted to clock domain a, while data from d3 to dn are still in the middle of transmission and in clock domain b. In this case, when clock domain a is reset, data from d0, d1, and d2 in the data packet will be cleared, and ready will be actively pulled low. Affected by this, the remaining data packet from d3 to dn is blocked in the middle and stays at the input interface of clock domain a. When reset_a of clock domain a is pulled low and reset is completed, ready will be actively pulled high, and the remaining data packet pkt_a from d3 to dn will continue to be transmitted to clock domain a. At this time, a serious problem will arise, that is, the data packet newly received by clock domain a is not a complete packet, and the part corresponding to the packet header sop is missing. In the subsequent processing, due to the incomplete packet and the lack of the packet header sop indication signal, it will be impossible to analyze, and the logic of clock domain a will be abnormal.

[0067] In order to solve this problem, the embodiment of the present invention adds a sop packet exception detection logic in the a clock domain, the purpose of which is to discard the newly received data packet d3 to dn after the reset is completed, so that it is discarded at the a clock domain interface and no longer transmitted to the subsequent module. The specific implementation method is that at the a clock domain input interface, when it is detected that reset_a is reset, the sop packet header indication signal of the newly input data packet is detected. If it is found that the first incoming data does not carry a valid sop packet header indication signal, the data corresponding to the current clock cycle is directly discarded, and it is not until a new valid sop packet header indication signal is detected that the data is retained and allowed to continue to be transmitted. In this way, the d3 to dn parts of the data packet pkt_a will all be discarded at the a clock domain input interface, ensuring that the subsequent output is normal.

[0068] In the embodiment of the present invention, when the data receiving clock domain generates a reset signal and a data packet is being transmitted, some of the existing data in the data buffer area is cleared, which can prevent confusion caused by the mixing of new and old data. This can ensure that after the reset, the system starts to receive new data from a clear state, avoiding data inconsistency problems caused by the interweaving of some residual old data and new data. By clearing the existing data and receiving the data packet according to the new packet header indication signal after the reset, a clear starting point is established for data processing. This makes the subsequent data processing process more orderly, and each module can operate based on a unified data source, improving the overall data consistency of the system.

[0069] 2. At the moment of the reset signal generated by the data sending clock domain, if a data packet is being transmitted across the clock module and part of the data in the data packet has been transmitted to the data buffer area of ​​the data receiving clock domain, and the remaining data still exists in the data sending clock domain, the remaining data in the data sending clock domain is cleared; the input interface of the data receiving clock domain performs packet header detection on the incoming data, and when the packet header indication signal is detected, the data packet is written to the data buffer area, and the data is output when the packet tail indication signal of the data packet is detected; if the packet is written to the data buffer area after the packet header indication signal is detected, and the packet tail indication signal is not detected in the subsequent data input but the packet header indication signal is detected again, the previously cached data is cleared and a new data packet is written, until the packet tail indication signal of the data packet is detected and the data is output.

[0070] For example, Figure 6 As shown in the figure, when the reset_b of the b clock domain is pulled high to reset, a data packet pkt_a is being transmitted. At this time, d0, d1, and d2 in the data packet have been transmitted to the a clock domain, and the data from d3 to dn-2 is in the middle of transmission, but the data from dn-1 and dn is still in the b clock domain. In this case, since the a clock domain is still running normally, the data from d0 to dn-2 of the data packet pkt_a can be normally transmitted to the a clock domain, but since the b clock domain is being reset, the remaining dn-1 and dn of the data packet pkt_a are cleared at this time, which will cause the pkt_a received by the a clock domain to be an incomplete packet, lacking the data at the end of the packet. In the subsequent processing, due to the incomplete packet and the lack of the eop indication signal at the end of the packet, it will be impossible to analyze, and the logic of the a clock domain will be abnormal.

[0071] In order to solve this problem, the embodiment of the present invention adds an eop packet abnormality detection logic in the a clock domain, the purpose of which is to discard the residual packets that lack the eop packet tail indication signal, that is, the data from d0 to dn-2 of the data packet pkt_a, so that it is discarded at the a clock domain interface and no longer transmitted to the subsequent module. The specific implementation method is that at the a clock domain input interface, when the sop packet header indication signal of the data packet pkt_a is detected, the pkt_a data packet content is written to the FIFO, but the output end of the FIFO does not allow it to read the data. Only when the eop packet tail indication signal of the data packet pkt_a is detected, the data in the FIFO is completely read out and transmitted to the subsequent module. If the eop packet tail indication signal of pkt_a is not detected, it is kept waiting. After the b clock domain is reset, the remaining parts dn-1 and dn of the data packet pkt_a are cleared, and the corresponding eop cannot be transmitted to the a clock domain. At this time, the cache FIFO of the a clock domain is not output, that is, it is not allowed to be transmitted to the subsequent module unless a complete packet is received. If a data packet pkt_b is transmitted at this time, the first data signal corresponds to the sop packet header indication signal, indicating that the previous data packet pkt_a has lost the packet tail eop, which can be regarded as a residual packet and is discarded. At this time, all the data from d0 to dn-2 of pkt_a previously cached in the FIFO are cleared; after clearing, the new pkt_b data is written to the FIFO, and finally the eop packet tail indication signal of pkt_b is detected, then all the data of pkt_b in the FIFO is read out and transmitted to the subsequent modules. The above processing can well handle the reset moment, the lack of the eop packet tail indication signal, discard the residual packet, ensure the complete transmission of the subsequent module data packet, and improve the stability of the system.

[0072] In the embodiment of the present invention, when the data transmission clock domain generates a reset signal and there is a partial transmission of a data packet, the remaining data in the data transmission clock domain is cleared, which can prevent incomplete data from continuing to be transmitted and possibly introducing errors. At the same time, strict packet header and packet tail detection is performed on the incoming data in the data receiving clock domain to ensure that only complete data packets are written into the buffer area and output, thereby greatly improving the accuracy of the data. The writing and output of data are controlled by clear packet header and packet tail indication signals, ensuring that the transmission of data between different clock domains is orderly and accurate, and there will be no chaotic writing or erroneous output of data, providing a reliable data source for subsequent data processing; timely clearing the remaining data in the data transmission clock domain and reasonably processing the data packet in the data receiving clock domain can avoid conflicts between different data packets. If such processing is not performed, multiple incomplete data packets may be mixed, resulting in the system being unable to process data normally or even malfunctioning. This method ensures that each data packet is processed independently and completely, improving the stability of the system.

[0073] 3. When a reset signal is generated in the data sending clock domain and the data receiving clock domain at the same time and a data packet is being transmitted, the data in the data buffer of the data receiving clock domain and the remaining data in the sending clock domain are cleared; after monitoring that the reset of the data receiving clock domain is completed, the input interface is used to detect whether there is a packet header indication signal in the newly input data packet. If so, the data packet is received and cached in the data buffer; otherwise, it is directly discarded; if the packet header indication signal is detected and the data packet is written to the data buffer, and the packet tail indication signal is not detected in the subsequent data input but the packet header indication signal is detected again, the previously cached data is cleared and a new data packet is written until the packet tail indication signal of the data packet is detected and the data is output.

[0074] For example, Figure 7 As shown, if the a and b clock domains are reset at the same time, there is a data packet being transmitted, that is, the reset causes the data packet pkt_a to lack both the header and the tail, and only the middle part of the data is transmitted to the a clock domain after the reset. In this case, the above sop and eop detection mechanism is also used to handle it. Specifically, after monitoring the reset of the a clock domain, the input interface detects whether there is a sop header indication signal in the newly input data packet. If so, the data packet is received and cached in the FIFO, otherwise it is directly discarded; if the sop header indication signal is detected and the data packet is written to the sop header indication signal, the eop indication signal is not detected in the subsequent data input but the sop indication signal is detected again, the previously cached data d0-d3 is cleared, and a new data packet is written, until the eop indication signal of the data packet is detected, the data is output from the FIFO, to ensure the complete transmission of the subsequent module data packet and improve the stability of the system.

[0075] In the embodiment of the present invention, when the data transmission clock domain and the data reception clock domain generate a reset signal at the same time and a data packet is being transmitted, all the relevant data in the two clock domains are cleared, thereby avoiding incomplete or possibly erroneous data from remaining in the system. This ensures that the system starts from a clean state after reset, laying a foundation for the accurate transmission and processing of subsequent data, and by detecting the header indication signal of the new input data packet after the reset, receiving the data packet and caching it only when the header indication signal exists, and detecting the tail indication signal in the subsequent data input, it is ensured that only complete data packets are processed and output. This strict detection mechanism greatly improves the accuracy of data transmission, reduces system failures and erroneous results caused by incomplete or erroneous data, and clears all relevant data during reset, effectively preventing conflicts and confusion between different data packets. If such processing is not performed, multiple incomplete data packets may be intertwined in the system, resulting in the system being unable to process data normally or even crashing. This method ensures that the system can process data in an orderly manner at any time, thereby improving the stability of the system.

[0076] The multi-clock domain reset data processing method provided by the embodiment of the present invention is a method for multi-clock domain reset applied to an intelligent network card, and analyzes in detail the influence of the reset signal on data transmission across clock domains and the corresponding processing method, thereby improving the stability of multi-clock domain data transmission and the robustness of the system when the system is reset, and having good scalability and portability. Based on the transmission of data between two clock domains, it can be extended to the mutual interaction between multiple clock domains. Under the action of the reset signal, reasonable decisions can be made according to the specific transmission state to ensure that data can be correctly processed under different circumstances, so that the data transmission of the system in a multi-clock domain environment is more reliable, and the probability of data errors and system failures caused by clock domain differences is reduced. At the same time, by detecting the packet header and / or packet tail of the transmission data, the reasonable management and control of the data buffer area also improves the stability and maintainability of the system. When a problem occurs, it is easier to locate and solve the failure of the data transmission link, reducing the difficulty and cost of system maintenance.

[0077] In this embodiment, a multi-clock domain reset data processing system is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the system described in the following embodiments is preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0078] This embodiment provides a multi-clock domain reset data processing system, such as Figure 8 As shown, including:

[0079] A data buffer setting module 801 is used to set a data buffer at each clock domain input interface for data interaction, which is used for caching data packets sent by the data receiving clock domain and the data buffer can store at least one data packet of the maximum length type;

[0080] The data detection module 802 is used to determine whether to clear or output the data stored in the data buffer area of ​​the data receiving clock domain based on the reset signal time generated by the data sending clock domain and the data receiving clock domain and the transmission status of the data packet.

[0081] In some optional embodiments, when the data detection module 802 generates a reset signal in the data sending clock domain and / or the data receiving clock domain, if no data packet is being transmitted across the clock module, the reset signal generated by the data sending clock domain and the data receiving clock domain does not affect the integrity of the data packet, and the data in the data buffer area of ​​the data receiving clock domain is output normally.

[0082] In some optional embodiments, at the moment of the reset signal generated by the data sending clock domain and / or the data receiving clock domain, if a data packet is being transmitted across the clock module, the integrity of the data packet transmission during the reset signal generated by the data sending clock domain and / or the data receiving clock domain is determined by detecting the packet header and / or packet tail of the newly transmitted data after the reset signal ends, and based on the integrity of the data packet transmission, it is determined whether the data stored in the data buffer area of ​​the data receiving clock domain is cleared or output.

[0083] In some optional implementations, at the time of the reset signal generated by the data receiving clock domain, if a data packet is being transmitted in the cross-clock module and part of the data in the data packet has been transmitted to the data buffer area of ​​the data receiving clock domain, the data stored in the data buffer area is cleared;

[0084] After monitoring that the reset of the data receiving clock domain is completed, the input interface detects whether there is a packet header indication signal in the newly input data packet. If yes, the data packet is received and buffered in the data buffer area. Otherwise, it is directly discarded.

[0085] In some optional embodiments, at the moment of the reset signal generated by the data sending clock domain, if a data packet is being transmitted across the clock module and part of the data in the data packet has been transmitted to the data buffer area of ​​the data receiving clock domain, and the remaining data still exists in the data sending clock domain, then the remaining data in the data sending clock domain is cleared; a packet header is detected on the incoming data at the input interface of the data receiving clock domain, and the data packet is written to the data buffer area after a packet header indication signal is detected, and the data is output when a packet tail indication signal of the data packet is detected; if the data packet is written to the data buffer area after a packet header indication signal is detected, and the packet tail indication signal is not detected in the subsequent data input but the packet header indication signal is detected again, the previously cached data is cleared and a new data packet is written, and the data is output until the packet tail indication signal of the data packet is detected.

[0086] In some optional embodiments, when a reset signal is generated simultaneously in the data sending clock domain and the data receiving clock domain and a data packet is being transmitted, the data located in the data buffer area of ​​the data receiving clock domain and the remaining data in the sending clock domain are cleared; after monitoring that the reset of the data receiving clock domain is completed, the input interface is detected to see whether there is a packet header indication signal in the newly input data packet; if so, the data packet is received and cached in the data buffer area; if not, it is directly discarded; if after the packet header indication signal is detected and the data packet is written to the data buffer area, if the packet tail indication signal is not detected in the subsequent data input but the packet header indication signal is detected again, the previously cached data is cleared and a new data packet is written, until the packet tail indication signal of the data packet is detected and the data is output.

[0087] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0088] The multi-clock domain reset data processing system in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0089] The embodiment of the present invention also provides a computer device having the above Figure 8 The multi-clock domain reset data processing system shown.

[0090] See also Fig. 9 , Fig. 9 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Fig. 9As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Fig. 9 A processor 10 is taken as an example.

[0091] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0092] The memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiment.

[0093] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0094] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0095] The computer device further comprises a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0096] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor central control system or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor or hardware, the method shown in the above embodiment is implemented.

[0097] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0098] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A multi-clock domain reset data processing method, characterized in that: include: A data buffer is set at each clock domain input interface for data interaction, the data buffer is used for the data receiving clock domain to cache data packets sent by the data sending clock domain, and the data buffer area can store at least one data packet of the maximum length type; Based on the reset signal timing generated by the data sending clock domain and the data receiving clock domain and the transmission status of the data packet, it is determined whether the data stored in the data buffer area of ​​the data receiving clock domain is cleared or outputted.

2. The method according to claim 1, characterized in that The method of determining to clear or output data stored in a data buffer area of ​​the data receiving clock domain based on the reset signal time generated by the data sending clock domain and the data receiving clock domain and the transmission status of the data packet comprises: At the moment of the reset signal generated by the data sending clock domain and / or the data receiving clock domain, if no data packet is being transmitted across the clock module, the reset signal generated by the data sending clock domain and the data receiving clock domain does not affect the integrity of the data packet, and the data in the data buffer area of ​​the data receiving clock domain is output normally.

3. The method according to claim 1, characterized in that The method of determining to clear or output data stored in a data buffer area of ​​the data receiving clock domain based on the reset signal time generated by the data sending clock domain and the data receiving clock domain and the transmission status of the data packet comprises: At the moment of the reset signal generated by the data sending clock domain and / or the data receiving clock domain, if a data packet is being transmitted across the clock module, the integrity of the data packet transmission during the reset signal generated by the data sending clock domain and / or the data receiving clock domain is determined by detecting the packet header and / or packet tail of the newly transmitted data after the reset signal ends, and based on the integrity of the data packet transmission, the data stored in the data buffer area of ​​the data receiving clock domain is cleared or output.

4. The method according to claim 3, characterized in that At the moment of the reset signal generated by the data receiving clock domain, if a data packet is being transmitted in the cross-clock module and part of the data in the data packet has been transmitted to the data buffer area of ​​the data receiving clock domain, the data stored in the data buffer area is cleared; After monitoring that the reset of the data receiving clock domain is completed, the input interface detects whether there is a packet header indication signal in the newly input data packet. If yes, the data packet is received and buffered in the data buffer area. Otherwise, it is directly discarded.

5. The method according to claim 3, characterized in that: At the moment of the reset signal generated by the data transmission clock domain, if a data packet is being transmitted in the cross-clock module and part of the data in the data packet has been transmitted to the data buffer area of ​​the data receiving clock domain, and the remaining part of the data still exists in the data transmission clock domain, the remaining part of the data in the data transmission clock domain is cleared; Performing packet header detection on the incoming data at the input interface of the data receiving clock domain, writing the data packet into the data buffer area after detecting the packet header indication signal, and outputting the data after detecting the packet tail indication signal of the data packet; If a packet is written into a data buffer after a packet header indication signal is detected, and a packet tail indication signal is not detected in subsequent data input but a packet header indication signal is detected again, the previously cached data is cleared and a new packet is written until the packet tail indication signal of the packet is detected and the data is output.

6. The method according to claim 3, characterized in that When a reset signal is generated in the data transmission clock domain and the data reception clock domain at the same time and a data packet is being transmitted, the data in the data buffer area of ​​the data reception clock domain and the remaining data in the transmission clock domain are cleared; After monitoring that the reset of the data receiving clock domain is completed, detecting whether there is a packet header indication signal in the newly input data packet at the input interface; If yes, the data packet is received and cached in the data buffer; if no, it is discarded directly; If a packet is written into a data buffer after a packet header indication signal is detected, and a packet tail indication signal is not detected in subsequent data input but a packet header indication signal is detected again, the previously cached data is cleared and a new packet is written until the packet tail indication signal of the packet is detected and the data is output.

7. A multi-clock domain reset data processing system, characterized in that: include: A data buffer setting module, used to set a data buffer at each clock domain input interface for data interaction, used for caching data packets sent by the data receiving clock domain from the data sending clock domain, wherein the data buffer can store at least one data packet of the maximum length type; The data detection module is used to determine whether to clear or output the data stored in the data buffer area of ​​the data receiving clock domain based on the reset signal time generated by the data sending clock domain and the data receiving clock domain and the transmission status of the data packet.

8. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the multi-clock domain reset data processing method according to any one of claims 1 to 6 by executing the computer instructions.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the multi-clock domain reset data processing method according to any one of claims 1 to 6.

10. A computer program product, characterized in that The method comprises computer instructions, wherein the computer instructions are used to enable a computer to execute the multi-clock domain reset data processing method according to any one of claims 1 to 6.

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