Storage device based on flash memory and method for managing prefetched data thereof

Abstract

A storage device is disclosed. The storage device includes: a memory device; a buffer memory configured to store a portion of data among the data stored in the memory device; and a memory controller configured to determine prefetch logical addresses expected to be sequentially received after a sequential logical address is received from a host, read prefetch data corresponding to the prefetch logical addresses from the memory device to store the prefetch data in the buffer memory in a prefetch group, and in response to receiving a logical address discontinuous from the logical address from the host, releasing the prefetch group from the buffer memory.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0141871 filed on October 23, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Background Art

[0003] Example embodiments relate generally to a semiconductor memory device, and more particularly, to a flash memory-based memory device and / or a pre-fetch data management method thereof.

[0004] Semiconductor memory can be mainly classified as volatile memory or non-volatile memory. Volatile memory (e.g., dynamic random access memory (DRAM) and / or static random access memory (SRAM)) has a fast read and / or write speed, but when the power is turned off, the data stored in the volatile memory disappears. In contrast, non-volatile memory can retain data even when the power is turned off. Therefore, non-volatile memory can be used to store content that must be saved regardless of whether power is supplied or not.

[0005] Representative examples of nonvolatile memories include flash memories. Flash memories are widely used as storage media for audio and / or video data in information devices such as computers and / or smart phones. Recently, high-capacity, high-speed input / output and / or low-power technologies for flash memories are being actively studied to be installed in mobile devices such as smart phones.

[0006] Flash memory may have the following disadvantages: slow writing and erasing speeds compared to reading speeds, limited number of uses, and no possibility of rewriting. Therefore, flash memory-based storage devices are designed to increase speed by pre-fetching frequently used data into a buffer memory. However, if the pre-fetched data in the buffer memory is not managed, the speed increase may be affected. Summary of the invention

[0007] Various example embodiments provide a storage device that efficiently manages a prefetch cache by grouping prefetched data in a prefetch cache of a buffer memory and by releasing all prefetched data in groups at once.

[0008] According to some example embodiments, a storage device includes: a memory device; a buffer memory configured to store a portion of data stored in the memory device; and a memory controller configured to determine a prefetch logical address expected to be received sequentially after receiving a sequential logical address from a host, read prefetch data corresponding to the prefetch logical address from the memory device to store the prefetch data in the buffer memory according to a prefetch group, and release the prefetch group from the buffer memory in response to receiving a logical address that is discontinuous with the logical address from the host.

[0009] Alternatively or additionally, according to various example embodiments, a prefetch management method for a storage device includes: performing a first prefetch operation in response to receiving a first sequential workload from a host; increasing the speed of the first prefetch operation based on the first sequential workload; monitoring whether a prefetch hit occurs in a first prefetch group data stored in a buffer memory through the first prefetch operation; releasing the prefetch data in which the prefetch hit occurs in the first prefetch group data through a single prefetch abort; and releasing the first prefetch group data through a large number of prefetch aborts in response to receiving a second workload that is discontinuous with the first sequential workload from the host.

[0010] Alternatively or additionally, according to various example embodiments, a storage device includes: a memory device; a buffer memory, the buffer memory including a prefetch cache, the prefetch cache being configured to store prefetch data corresponding to a workload received from a host; and a memory controller configured to read data corresponding to a sequential workload from the memory device and store the data in the prefetch cache in response to receiving the sequential workload from the host. The memory controller is configured to perform a first prefetch operation corresponding to a first workload in response to receiving a first sequential workload from the host, increase the speed of the first prefetch operation based on the size of the prefetch cache, and release all prefetch data prefetched from the prefetch cache by the first prefetch operation through a bulk prefetch abort in response to receiving a second workload that is discontinuous with the first workload from the host. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other objects and features will become apparent by describing embodiments thereof in detail with reference to the accompanying drawings.

[0012] Figure 1 is a block diagram illustrating a user equipment according to various example embodiments.

[0013] Figure 2 It is shown Figure 1 Block diagrams of some example embodiments of memory devices are shown in FIG.

[0014] Figure 3 It is shown Figure 2 Circuit diagrams of some exemplary embodiments of a memory block BLK1 of a memory cell array shown in FIG.

[0015] Figure 4 is shown by the first string selection line from Figure 3 FIG. 1 is a circuit diagram of a selected cell string among the cell strings of the memory block BLK1 .

[0016] Figure 5 It is shown Figure 1 Block diagrams of some example embodiments of a memory controller.

[0017] Figure 6 It is shown by Figure 5 A diagram of some example embodiments of a workload received by a host interface from a host.

[0018] Figure 7 It is shown that the storage Figure 5 A diagram of prefetch data in a prefetch cache.

[0019] Figure 8 It is shown by Figure 5 A diagram of some example embodiments of addresses prefetched by a prefetch manager over time.

[0020] Fig. 9 It is shown by Figure 5 The prefetch manager in Figure 8 Figure 2 shows some example embodiments of operations performed in the first and second phases.

[0021] Fig.10 It shows confirmation Figure 8 A diagram of a method for improving the prefetch speed of a segment.

[0022] Fig.11 It is shown Figure 5 Flowchart of the prefetch operation of the memory controller.

[0023] Fig.12 is to show that the link is included in Figure 7 FIG. 1 is a diagram of a method of prefetching data in a first prefetch group.

[0024] Fig.13 It is shown by Figure 5 A diagram of some example embodiments of addresses prefetched by a prefetch manager over time.

[0025] Fig.14 is a block diagram illustrating an example in which a storage device according to some example embodiments is implemented using a solid state drive (SSD). DETAILED DESCRIPTION

[0026] Hereinafter, various exemplary embodiments will be described in detail and clearly so that a person having ordinary skill in the art can easily realize the inventive concept.

[0027] Figure 1 is a block diagram illustrating a user equipment according to some example embodiments. Figure 1 , the user device 100 may include a storage device 1000 and a host 1500. The storage device 1000 and the host 1500 may be connected through a host interface 1201. The host interface 1201 may be or may include (or be included in) a standard interface, such as one or more of ATA, SATA, PATA, USB, SCSI, ESDI, IEEE 1394, IDE, and / or a card interface, etc.

[0028] According to some example embodiments, the storage device 1000 may be a storage device based on a nonvolatile memory or may include a storage device based on a nonvolatile memory (or be included in a storage device based on a nonvolatile memory). For example, the storage device 1000 may include a memory device 1100, a memory controller 1200, and a buffer memory 1300. The memory device 1100 may be or include a nonvolatile memory, such as a flash memory or a phase change memory (PRAM). When the memory device 1100 is or includes a flash memory, the storage device 1000 may be or include a flash memory storage device based on a flash memory. For example, the storage device 1000 may be or include an SSD, a UFS, and / or a memory card, etc. The buffer memory 1300 may include a volatile memory (e.g., a DRAM and / or an SRAM).

[0029] According to some example embodiments, the memory device 1100 may be connected to the memory controller 1200 through the memory interface 1202. The memory device 110 may include a memory cell array and / or a peripheral circuit. The peripheral circuit may include all analog and / or digital circuits required or used to store and / or read data in the memory cell array.

[0030] According to some example embodiments, the peripheral circuit may receive external power from the memory controller 1200 and may generate various levels of internal power. The peripheral circuit may receive commands, addresses, and data from the memory controller 1200 and may store data in the memory cell array according to control signals. Additionally or alternatively, the peripheral circuit may read data stored in the memory cell array and provide the data to the memory controller 1200.

[0031] According to some example embodiments, the memory cell array may include a plurality of memory blocks. Each memory block may have a vertical three-dimensional structure; however, example embodiments are not limited thereto. Each memory block may include a plurality of memory cells. Multi-bit data may be stored in each memory cell. For example, the memory device 1100 may be or may include a TLC flash memory capable of storing 3-bit data in one memory cell; however, example embodiments are not limited thereto.

[0032] According to some example embodiments, the memory cell array may be located next to or above the peripheral circuit, for example, due to the design arrangement structure. In addition, the structure in which the memory cell array is located above the peripheral circuit may also be referred to as a COP (Cell on Periphery) structure. The memory cell array may be manufactured as a chip separated from the peripheral circuit. The upper chip including the memory cell array and the lower chip including the peripheral circuit may also be connected to each other using a bonding method. This structure may be referred to as a C2C (chip to chip) structure. However, example embodiments are not limited thereto.

[0033] According to some example embodiments, the memory controller 1200 may be connected between the memory device 1100 and the host 1500. Additionally or alternatively, the memory controller 1200 may be connected between the buffer memory 1300 and the host 1500. The memory controller 1200 may control a read and / or write operation of the memory device 1100 and / or the buffer memory 1300 in response to a request from the host 1500. The memory controller 1200 may receive host data from the host 1500 and may provide the host data to the memory device 1100 and / or the buffer memory 1300.

[0034] According to some example embodiments, the memory controller 1200 may include a control unit and a working memory. The control unit may control the overall operation of the memory controller 1200. For example, the control unit may control a flash translation layer (FTL) to perform an address mapping operation. The control unit may be or may include a commercially available and / or customized microprocessor.

[0035] According to some example embodiments, the working memory may be a cache memory (e.g., SRAM and / or DRAM). The working memory may be used as a buffer memory for temporarily storing data. Additionally or alternatively, the working memory may be or may include a drive memory of the memory controller 1200. The working memory may drive a flash translation layer (FTL).

[0036] According to some example embodiments, the FTL may be or may include firmware and / or a program for efficiently managing the memory device 1100. The memory device 1100 may not support a rewrite function different from a hard disk drive. Therefore, the memory device 1100 may perform the following process while updating the data written to the page. In some examples, the memory device 1100 may copy all valid data in the first memory block to which the written page belongs to an empty second memory block. In some examples, the memory device 1100 may erase the first memory block and make it an empty memory block. The memory device 1100 may perform a large number of page copy operations (e.g., page read operations and / or page write operations) and erase operations while undergoing this process.

[0037] According to some example embodiments, an FTL may be used between the host 1500 and the memory device 1100 to reduce the number of page copy and erase operations. The FTL may perform address mapping functions, garbage collection functions, and wear leveling functions, etc. When a rewrite request is received from the host 1500, the address mapping function may write the corresponding data to another empty page instead of rewriting the original page, thereby reducing additional page copy and block erase operations. For this purpose, an address mapping table with a specified size must be maintained in the working memory and the buffer memory 1300. Through this, the FTL may manage the operation of mapping the logical address received from the host 1500 to the physical address in the memory device 1100.

[0038] According to some example embodiments, the memory controller 1200 may include a prefetch manager 1230. The prefetch manager 1230 may store (or prefetch) prefetch data corresponding to the host workload among the data stored in the memory device 1100 in the buffer memory 1300 based on the host workload received from the host 1500. When the host workload is sequential, the prefetch manager 1230 may connect the prefetch data through a link, and may manage the link as prefetch group data. When a host workload that is discontinuous with a previous sequential host workload (e.g., not in the order of the previous sequential host workload) is received, the prefetch manager 1230 may release (and / or delete) the prefetch group data from the buffer memory 1300 at one time. Therefore, the buffer memory 1300 may quickly secure a blank space for prefetching, and the performance of the storage device 1000 may be improved.

[0039] According to some example embodiments, the buffer memory 1300 may be connected to the memory controller 1200 through the buffer interface 1203. For example, the buffer memory 1300 may be used to store (or temporarily store) data to be stored in or read from the memory device 1100. Additionally or alternatively, a cache area capable of storing cache data may be allocated to the buffer memory 1300. The buffer memory 1300 may be implemented with DRAM and / or SRAM, etc. The buffer memory 1300 may be included in the memory device 1100 or the memory controller 1200.

[0040] According to some example embodiments, the host 1500 may include a processor and a host memory. The processor and the host memory may be connected via an address / data bus. The host 1500 may be or include (or be included in) a personal digital assistant (PDA), a computer, a digital audio player, a digital camera, and / or a mobile phone, etc. The host memory may be or include or be included in one or more forms of non-volatile or volatile memory in a cache, ROM, PROM, EPROM, EEPROM, flash, SRAM, DRAM, etc.

[0041] According to some example embodiments, the host memory may drive a plurality of software and / or firmware. For example, the host memory may drive one or more of an operating system (OS), an application, a file system, a memory manager, an I / O driver, and the like.

[0042] Figure 2 It is shown Figure 1 Block diagrams of various example embodiments of memory devices are shown in FIG. Figure 1 The storage device 1000 may be a flash memory storage device based on a flash memory. For example, the storage device 1000 may be implemented as or include one or more of an SSD, a UFS, and / or a memory card, etc.

[0043] refer to Figure 1 and Figure 2 , the memory device 1100 may include a memory cell array 1110 and a peripheral circuit 1115. The peripheral circuit 1115 may include an address decoder 1120, a page buffer circuit 1130, an input / output circuit 1140, a word line voltage generator 1150, and a control logic 1160.

[0044] According to some example embodiments, the memory cell array 1110 may include a plurality of memory blocks BLK1 to BLKn. Each memory block may be composed of a plurality of pages (e.g., the same number of pages or a different number of pages). Each page may include a plurality of memory cells. Each memory cell or at least some of the memory cells may store multi-bit data (e.g., two or more bits); example embodiments are not limited thereto. Each memory block may correspond to an erase unit, and each page may correspond to a read and / or write unit.

[0045] According to some example embodiments, the memory cell array 1110 may be formed in a direction perpendicular to the substrate; however, the example embodiments are not limited thereto. The gate electrode layer and the insulating layer may be alternately deposited on the substrate. Each memory block (e.g., BLK1) may be connected to one or more string selection lines SSL, a plurality of word lines WL1 to WLm, and one or more ground selection lines GSL. WLk is the selected word line sWL, and the remaining word lines (WL1 to WLk-1, WLk+1 to WLm) are unselected word lines uWL. Here, m may be equal to or greater than or less than n.

[0046] According to some example embodiments, the address decoder 1120 may be connected to the memory cell array 1110 through the selection lines SSL and GSL and the word lines WL1 to WLm. The address decoder 1120 may select a word line during a program or read operation. The address decoder 1120 may receive a word line voltage VWL from a word line voltage generator 1150 and provide a program voltage or a read voltage to the selected word line.

[0047] According to some example embodiments, the page buffer circuit 1130 may be connected to the memory cell array 1110 through the bit lines BL1 to BLz. Here, z may be the same as or different from m or n. The page buffer circuit 1130 may store (e.g., temporarily store) data to be stored in the memory cell array 1110 and / or data read from the memory cell array 1110. The page buffer circuit 1130 may include page buffers PB1 to PBz connected to corresponding bit lines. Each page buffer may include a plurality of latches to store or read multi-bit data.

[0048] According to some example embodiments, the input / output circuit 1140 may be internally connected to the page buffer circuit 1130 through data lines, and may be externally connected to a memory controller (refer to FIG. 10A ) through input / output lines IO1 to ION. Figure 1 , 1200). The input / output circuit 1140 may receive program data from the memory controller 1200 during a program operation. In some example embodiments, the input / output circuit 1140 may provide data read from the memory cell array 1110 to the memory controller 1200 during a read operation.

[0049] According to some example embodiments, the word line voltage generator 1150 may receive internal power from the control logic 1160 and may generate a word line voltage VWL required to read or write data. The word line voltage VWL may be provided to a selected word line (sWL) and / or an unselected word line (uWL) through the address decoder 1120.

[0050] According to some example embodiments, the word line voltage generator 1150 may include a program voltage generator 1151 and a pass voltage generator 1152. The program voltage generator 1151 may generate a program voltage Vpgm to be provided to a selected word line sWL during a program operation. The pass voltage generator 1152 may generate a pass voltage Vpass to be provided to the selected word line sWL and unselected word lines uWL.

[0051] According to some example embodiments, the word line voltage generator 1150 may include a read voltage generator 1153 and a read pass voltage generator 1154. The read voltage generator 1153 may generate a selection read voltage Vrd provided to a selection word line sWL during a read operation. The read pass voltage generator 1154 may generate a read pass voltage Vrdps provided to an unselected word line uWL. The read pass voltage Vrdps may be a voltage having a magnitude sufficient to turn on a memory cell connected to an unselected word line uWL during a read operation.

[0052] According to some example embodiments, the control logic 1160 may control operations of the memory device 1100, such as reading, writing, and erasing, using a command CMD, an address ADDR, and a control signal CTRL provided from the memory controller 1200. The address ADDR may include a block selection address for selecting a memory block, a row address for selecting a page, and a column address for selecting a memory cell.

[0053] Figure 3 It is shown Figure 2 1 is a circuit diagram of some example embodiments of a memory block BLK1 of a memory cell array shown in FIG. Figure 3 In the memory block BLK1, a plurality of cell strings STR11 to STR8z may be formed between the bit lines BL1 to BLz and the common source line CSL. Each cell string includes a string selection transistor SST, a plurality of memory cells MC1 to MCm, and a ground selection transistor GST.

[0054] According to some example embodiments, the string selection transistor SST may be connected to the string selection lines SSL1 to SSL8. The ground selection transistor GST may be connected to the ground selection lines GSL1 to GSL8. The string selection transistor SST may be connected to the bit lines BL1 to BLz, and the ground selection transistor GST may be connected to the common source line CSL. Although eight ground selection lines GSL1 to GSL8 are shown, example embodiments are not limited thereto.

[0055] According to some example embodiments, first to m-th word lines WL1 to WLm may be connected to the plurality of memory cells MC1 to MCm in a row direction. First to z-th bit lines BL1 to BLz may be connected to the plurality of memory cells MC1 to MCm in a column direction.

[0056] According to some example embodiments, the first word line WL1 may be placed above the first to eighth ground selection lines GSL1 to GSL8. The first memory cell MC1 placed at the same height from the substrate may be connected to the first word line WL1. In a similar manner, the second to m-th memory cells MC2 to MCm placed at the same height from the substrate may be connected to the second to m-th word lines WL2 to WLm, respectively.

[0057] Figure 4 The first string selection line SSL1 is shown from Figure 3 1. A circuit diagram of a cell string selected from a cell string of a memory block BLK1 shown in . A one-to-one cell string STR11 to a pair of z cell strings STR1z may be selected by a first string selection line SSL1. The one-to-one cell string STR11 to a pair of z cell strings STR1z may be connected to a first bit line BL1 to a z-th bit line BLz, respectively. A first page buffer PB1 to a z-th page buffer PBz may be connected to a first bit line BL1 to a z-th bit line BLz, respectively.

[0058] According to some example embodiments, a one-to-one cell string STR11 may be connected to a first bit line BL1 and a common source line CSL. The one-to-one cell string STR11 may include a string selection transistor SST selected by a first string selection line SSL1, first to m-th memory cells MC1 to MCm connected to first to m-th word lines WL1 to WLm, and a ground selection transistor GST selected by a first ground selection line GSL1. A one-to-two cell string STR12 may be connected to a second bit line BL2 and a common source line CSL. A one-to-z cell string STR1z may be connected to a z-th bit line BLz and a common source line CSL.

[0059] According to some example embodiments, the first word line WL1 and the m-th word line WLm may be edge word lines (edge ​​WL). The second word line WL2 and the (m-1)-th word line WLm-1 may be edge-adjacent word lines. The k-th word line WLk may be the selected word line sWL. The (k-1)-th word line WLK-1 and the (k+1)-th word line WLk+1 may be adjacent word lines adjacent to the selected word line. When the k-th word line WLk is the selected word line sWL, the remaining word lines WL1 to WLK-1 and WLk+1 to WLm may be unselected word lines uWL.

[0060] According to some example embodiments, the first memory cell MC1 and the m-th memory cell MCm may be edge memory cells. The second memory cell MC2 and the (m-1)-th memory cell MCm-1 may be edge adjacent memory cells. The k-th memory cell MCk may be the selected memory cell sMC. The (k-1)-th memory cell MCk-1 and the (k+1)-th memory cell MCk+1 may be memory cells (adjacent MCs) adjacent to the selected memory cell. When the k-th memory cell MCk is the selected memory cell sMC, the remaining memory cells MC1 to MCk-1 and MCk+1 to MCm may be unselected memory cells uMC.

[0061] According to some example embodiments, a group of memory cells selected by one string selection line and connected to one word line may be one page. For example, memory cells selected by the first string selection line SSL1 and connected to the k-th word line WLk may be one page. For example, eight pages may be configured on the k-th word line WLk; however, example embodiments are not limited to eight pages. Among the eight pages, the page connected to the first string selection line SSL1 is a selected page, and the pages connected to the second to eighth string selection lines SSL2 to SSL8 are unselected pages.

[0062] Figure 5 It is shown Figure 1 Block diagrams of some example embodiments of a memory controller. Figure 5 , the memory controller 1200 may include a host interface 1201 , a memory interface 1202 , a buffer interface 1203 , a control unit 1210 , a working memory 1220 , and a pre-fetch manager 1230 .

[0063] Although not in Figure 51 , but the memory controller 1200 may further include various other components. For example, the memory controller 1200 may further include one or more of the following: an ECC circuit that generates an error correction code (ECC) to correct a failed bit or an error bit of data received from the memory device 1100, or a command generation module that generates a command (CMD) for controlling a memory operation according to a request received from the host 1500.

[0064] According to some example embodiments, the host interface 1201 may provide an interface between the host 1500 and the memory controller 1200. The standard interface includes various interface methods, such as one or more of Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI) and PCI Express (PCI-E), IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card, MultiMediaCard (MMC) card, Embedded MultiMediaCard (eMMC) card, Universal Flash Storage (UFS), and / or Compact Flash (CF) card, etc.

[0065] According to some example embodiments, the memory interface 1202 may provide an interface between the memory device 1100 and the memory controller 1200. For example, write and / or read data may be sent to and / or received from the memory device 1100 through the memory interface 1202. The memory interface 1202 may provide commands and addresses to the memory device 1100. Additionally or alternatively, the memory interface 1202 may provide data read from the memory device 1100 to the memory controller 1200.

[0066] According to some example embodiments, the buffer interface 1203 may provide an interface between the buffer memory 1300 and the memory controller 1200. For example, data temporarily stored in the buffer memory 1300 may be transmitted to and received from the buffer memory 1300 through the buffer interface 1203. The buffer interface 1203 may provide pre-fetched data received from the memory device 1100 to the buffer memory 1300.

[0067] According to some example embodiments, the control unit 1210 may include a central processing unit or a microprocessor, and may control overall operations of the memory controller 1200. The control unit 1210 may drive firmware loaded in the working memory 1220 to control the memory controller 1200.

[0068] According to some example embodiments, the working memory 1220 may be implemented with various memories (e.g., at least one of a cache memory, a DRAM, an SRAM, a PRAM, and a flash memory). The working memory 1220 may drive the flash translation layer 1221 under the control of the control unit 1210. The flash translation layer 1221 may perform an address mapping operation page by page or block by block. The flash translation layer 1221 may convert a logical address received from the host 1500 into a physical address in the memory device 1100.

[0069] According to some example embodiments, the prefetch manager 1230 may monitor a workload received through the host interface 1201. For example, the prefetch manager 1230 may perform a prefetch operation when a sequential workload is received through the host interface 1201. The prefetch manager 1230 may prefetch data corresponding to sequential logical addresses from the memory device 1100 to the buffer memory 1300.

[0070] According to some example embodiments, the prefetch manager 1230 may set a prefetch cache 1310 in the buffer memory 1300. When a sequential workload is received through the host interface 1201, the prefetch manager 1230 may determine the size of the prefetch cache 1310 by considering the size of the buffer memory 1300. The prefetch manager 1230 may perform a prefetch operation based on the size of the prefetch cache 1310.

[0071] According to some example embodiments, prefetch manager 1230 may set a group for consecutive prefetch data. Prefetch manager 1230 may connect consecutive prefetch data through a link. Prefetch manager 1230 may release prefetch data connected by a link or set as a group at once. Therefore, storage device 1000 may quickly secure an empty space in prefetch cache 1310, and may improve the performance of storage device 1000.

[0072] Figure 6 It is shown by Figure 5 A diagram of some example embodiments of a workload received by a host interface from a host. Figure 7 It is shown that the storage Figure 5 Figure 1.1 shows the prefetch data in the prefetch cache. Figures 5 to 7 , the host interface 1201 can receive workloads 10 and 20 from the host 1500.

[0073] According to some example embodiments, the host interface 1201 may receive (e.g., serially and / or in parallel) a first workload 10 corresponding to a first logical address (LBA11, LBA12, LBA13, ...) from the host 1500. The prefetch manager 1230 may detect whether the first workload 10 is sequential. When the first workload 10 is sequential, the prefetch manager 1230 may perform a first prefetch operation. As an example, the prefetch manager 1230 may detect the sequentiality of the first workload 10 by comparing a specified number of logical addresses (e.g., three addresses).

[0074] According to some example embodiments, the prefetch manager 1230 may set a first workload 10 corresponding to sequential first logical addresses (LBA11, LBA12, LBA13, ...) to a first prefetch group 1311. The prefetch manager 1230 may prefetch first prefetch group data corresponding to the first prefetch group 1311 from the memory device 1100 to the buffer memory 1300. The prefetch manager 1230 may establish a link to each of the first prefetch group data.

[0075] According to some example embodiments, the host interface 1201 may receive (e.g., serially and / or in parallel) from the host 1500 a second workload 20 corresponding to a second logical address (LBA21, LBA22, LBA23, ...) that is discontinuous with a sequential first logical address (LBA11, LBA12, LBA13, ...). When receiving the first workload 10 and the discontinuous or non-continuous second workload 20, the prefetch manager 1230 may release the first prefetch group data corresponding to the first prefetch group 1311 at once. The prefetch manager 1230 may delete the first prefetch group data from the prefetch cache 1310. Therefore, the prefetch cache 1310 may quickly secure an empty space for prefetching.

[0076] According to some example embodiments, the prefetch manager 1230 may detect whether the second workload 20 is sequential or continuous. When the second workload 20 is sequential, the prefetch manager 1230 may perform a second prefetch operation. The prefetch manager 1230 may set the second workload 20 corresponding to the second logical address (LBA21, LBA22, LBA23, ...) to the second prefetch group 1312. The prefetch manager 1230 may prefetch the second prefetch group data corresponding to the second prefetch group 1312 from the memory device 1100 to the buffer memory 1300. The prefetch manager 1230 may establish links to each other to the second prefetch group data.

[0077] Figure 8 It is shown by Figure 5 A diagram of some example embodiments of addresses prefetched by a prefetch manager over time. Fig. 9 It is shown by Figure 5 The prefetch manager in Figure 8 Figure 1 shows some example embodiments of operations performed in the first and second phases of FIG. Figures 5 to 9 , the prefetch manager 1230 may prefetch data of the memory device 1100 into the buffer memory 1300 or release data prefetched in the buffer memory 1300 according to the first stage ST1 , the second stage ST2 , the third stage ST3 , and the fourth stage ST4 .

[0078] According to some example embodiments, in the first stage ST1, the prefetch manager 1230 may detect a first workload 10 corresponding to a first logical address 11 (e.g., LBA11, LBA12, LBA13, ...). The prefetch manager 1230 may determine whether the first logical address 11 corresponding to the first workload 10 is sequential (or continuous) at the first time point t1.

[0079] According to some example embodiments, the prefetch manager 1230 may determine the sequentiality or contiguity of the first workload 10 based on a specified number of logical addresses. As an example, the prefetch manager 1230 may detect whether the eleventh logical address LBA11, the twelfth logical address LBA12, and the thirteenth logical address LBA13 are sequential. When the eleventh logical address LBA11, the twelfth logical address LBA12, and the thirteenth logical address LBA13 are sequential, the prefetch manager 1230 may determine that the first workload 10 is sequential.

[0080] According to some example embodiments, at a first time point t1, when it is detected that the first workload 10 is sequential, the prefetch manager 1230 may set a first prefetch group 1311. The prefetch manager 1230 may determine a logical address 12 to be prefetched (hereinafter referred to as a first prefetch logical address) based on the first logical address 11. The prefetch manager 1230 may prefetch (or store) the first prefetch group data corresponding to the first prefetch logical address 12 from the memory device 1100 to the buffer memory 1300. As an example, the prefetch manager 1230 may prefetch (or store) data corresponding to the first prefetch logical address 12 (e.g., LBA14, LBA15, LBA16, LBA17, LBA18, LBA19, ...) expected to be received after the thirteenth logical address LBA13 from the memory device 1100 to the buffer memory 1300.

[0081] According to some example embodiments, between the first time point t1 and the second time point t2, the prefetch speed of the first prefetch group data corresponding to the first prefetch logical address I2 may be increased. For example, between the first time point t1 and the second time point t2, the prefetch data corresponding to the fourteenth logical address LBA14, the fifteenth logical address LBA15, the sixteenth logical address LBA16, the seventeenth logical address LBA17, and the eighteenth logical address LBA18 may be prefetched at an increased speed.

[0082] According to some example embodiments, between the first time point t1 and the second time point t2, the prefetch manager 1230 may predict the first logical address 11 (e.g., the fourteenth logical address LBA14, the fifteenth logical address LBA15, the sixteenth logical address LBA16, the seventeenth logical address LBA17, and the eighteenth logical address LBA18) to be received in the future, and determine a first prefetch logical address 12 corresponding to the first logical address 11. As an example, the first prefetch logical address 12 may be substantially the same as the first logical address 11.

[0083] According to some example embodiments, a physical address corresponding to the first prefetch logical address 12 may be sent to the memory device 1100 before receiving the first logical address 11 from the host 1500. The first prefetch group data received based on the first prefetch logical address 12 may be stored in the prefetch cache 1310 before receiving the first logical address 11 from the host 1500.

[0084] According to some example embodiments, between the first time point t1 and the second time point t2, the prefetch manager 1230 may monitor the prefetch hit rate. For example, a prefetch hit may mean that the prefetched data is used by the host 1500. When a prefetch hit occurs, the prefetch manager 1230 may release the prefetched data one by one on the basis of the logical address (hereinafter referred to as a single prefetch abort). As an example, between the first time point t1 and the second time point t2, the prefetch data corresponding to the fourteenth logical address LBA14 and the fifteenth logical address LBA15 may be released by a single prefetch abort.

[0085] According to some example embodiments, in the second stage ST2, the first prefetch group data may be prefetched from the memory device 1100 at the same speed as the speed of receiving the first logical address 11. The prefetch manager 1230 may set the size of the prefetch cache 1310 at the first time point t1. The second time point t2 at which the reception speed of the first logical address 11 and the prefetch speed of the first prefetch group data are the same may be determined according to the size of the prefetch cache 1310.

[0086] According to some example embodiments, between the second time point t2 and the third time point t3, the prefetch manager 1230 may monitor whether the first prefetch group data is in prefetch hit. The prefetch data in the prefetch hit (e.g., data for which the first logical address 11 is actually received from the host 1500 and executed in the host 1500) may be released by aborting a single prefetch from the buffer memory 1300. As an example, between the second time point t2 and the third time point t3, the prefetch data corresponding to the sixteenth logical address LBA16 and the seventeenth logical address LBA17 may be released by a single prefetch abort.

[0087] According to some example embodiments, at the third time point t3, when the second workload 20 that is discontinuous with the first logical address I1 is detected, the prefetch manager 1230 may release all first prefetch group data corresponding to the first prefetch group 131I pre-fetched based on the first prefetch logical address I2 from the buffer memory 1300 (hereinafter referred to as a large amount of prefetch abort). For example, at the third time point t3, the prefetch manager 1230 may delete all remaining first prefetch group data from the prefetch cache 1310. As an example, the prefetch manager 1230 may release the data prefetched after the eighteenth logical address LBA18 through a large amount of prefetch abort. Therefore, the prefetch cache 1310 may quickly secure a blank space for prefetching.

[0088] According to some example embodiments, in the third stage ST3, the prefetch manager 1230 may detect a second workload 20 corresponding to a second logical address 21 (e.g., LBA21, LBA22, LBA23, ...). The prefetch manager 1230 may determine whether the second logical address 21 corresponding to the second workload 20 is sequential at a fourth time point t4. The prefetch manager 1230 may determine the sequentiality of the second workload 20 based on a specified number of logical addresses (e.g., a twenty-first logical address LBA21, a twenty-second logical address LBA22, and a twenty-third logical address LBA23).

[0089] According to some example embodiments, at a fourth time point t4, when it is detected that the second workload 20 is sequential, the prefetch manager 1230 may set a second prefetch group 1312. The prefetch manager 1230 may determine a second prefetch logical address 22 corresponding to the second logical address 21. The prefetch manager 1230 may prefetch (or store) the second prefetch group data corresponding to the second prefetch logical address 22 from the memory device 1100 to the buffer memory 1300.

[0090] According to some example embodiments, between the fourth time point t4 and the fifth time point t5, the prefetch speed of the second prefetch group data corresponding to the second prefetch logical address 22 may be increased. The prefetch manager 1230 may predict the second logical address 21 to be received in the future, and determine the second prefetch logical address 22 corresponding to the second logical address 21. As an example, the second prefetch logical address 22 may be substantially the same as the second logical address 21.

[0091] According to some example embodiments, between the fourth time point t4 and the fifth time point t5, the prefetch manager 1230 may monitor the prefetch hit rate. For example, a prefetch hit may mean that the prefetch data is used by the host 1500. When a prefetch hit occurs, the prefetch manager 1230 may release the prefetch hit data on a logical address basis through a single prefetch abort.

[0092] According to some example embodiments, in the fourth stage ST4, the second prefetch group data may be prefetched from the memory device 1100 at the same speed as the speed of receiving the second logical address 21. The prefetch manager 1230 may set the size of the prefetch cache 1310 at the fourth time point t4. A fifth time point t5 at which the reception speed of the second logical address 21 and the prefetch speed of the second prefetch group data are equal may be determined according to the size of the prefetch cache 1310.

[0093] According to some example embodiments, between the fifth time point t5 and the sixth time point t6, the prefetch manager 1230 may monitor whether the second prefetch group data is in prefetch hit. The prefetch data in the prefetch hit (e.g., data actually receiving the first logical address 11 from the host 1500 and executed in the host 1500) may be released from the buffer memory 1300 by a single prefetch abort.

[0094] According to some example embodiments, after the sixth time point t6, the second prefetch group data may continue to be prefetched or released by a large number of prefetch aborts. For example, when maintaining the continuity or contiguity of the second logical address 21, the prefetch manager 1230 may continue to prefetch the second prefetch group data. When another workload that has no continuity with the second logical address 21 is received from the host 1500, the prefetch manager 1230 may release the second prefetch group data by a large number of prefetch aborts.

[0095] Fig.10 It shows confirmation Figure 8 A diagram of the method for improving the prefetch speed of the segments in . Figures 5 to 10, at the first time point t1 of the first stage ST1, the prefetch manager 1230 may detect the sequentiality of the first logical address 11 of the first workload 10. When the first logical address 11 continues to be sequentially received, the prefetch manager 1230 may predict the first expected logical address 11a. Between the first time point t1 and the second time point t2, the prefetch manager 1230 may store the first prefetch group data received based on the first prefetch logical address 12 corresponding to the first expected logical address 11a in the prefetch cache 1310 before receiving the first logical address 11 from the host 1500.

[0096] According to some example embodiments, at a second time point t2 of the second stage ST2, the first prefetch group data corresponding to the first prefetch logical address 12 may be prefetched at the same speed as the reception speed of the first logical address 11 from the memory device 1100. The second time point t2 at which the reception speed of the first logical address 11 and the prefetch speed of the first prefetch group data are the same may be determined according to the size of the prefetch cache 1310.

[0097] Fig.11 It is shown Figure 5 Flowchart of the prefetch operation of the memory controller. Figures 5 to 11 , the memory controller 1200 can effectively manage the prefetch cache 1310 based on the sequential workload of the host 1500.

[0098] According to some example embodiments, in operation S110, the memory controller 1200 may detect a first sequential workload of the host 1500, and then perform a first prefetch operation. For example, in the first stage ST1, the prefetch manager 1230 may detect a first workload 10 corresponding to a first logical address 11 (e.g., LBA11, LBA12, LBA13, ...). The prefetch manager 1230 may determine whether the first logical address 11 corresponding to the first workload 10 is sequential at a first time point t1. When it is detected that the first logical address 11 is sequential, the prefetch manager 1230 may determine a first prefetch logical address 12 to be prefetched based on the first logical address 11. The prefetch manager 1230 may prefetch (or store) a first prefetch group data corresponding to the first prefetch logical address 12 from the memory device 1100 to the buffer memory 1300.

[0099] According to some example embodiments, in operation S120, the memory controller 1200 may increase the speed of the first prefetch operation based on the first sequential workload. For example, between the first time point t1 and the second time point t2, the prefetch speed of the first prefetch group data may be increased. The memory controller 1200 may continuously prefetch (or store) the first prefetch group data corresponding to the first prefetch logical address 12 from the memory device 1100 to the buffer memory 1300.

[0100] According to some example embodiments, between the first time point t1 and the second time point t2, the prefetch manager 1230 may predict the first prefetch logical address 12. Before receiving the first logical address 11 from the host 1500, the prefetch manager 1230 may prefetch the first prefetch group data based on the predicted first prefetch logical address 12. Before receiving the first logical address 111 from the host 1500, the first prefetch group data may be stored in the prefetch cache 1310.

[0101] According to some example embodiments, in operation S130, the memory controller 1200 may monitor a prefetch hit rate. For example, in the second stage ST2, the first prefetch group data may be prefetched from the memory device 1100 at the same speed as the speed of receiving the first logical address 11. The prefetch manager 1230 may set the size of the prefetch cache 1310 at the first time point t1. The second time point t2 at which the reception speed of the first logical address 11 and the prefetch speed of the first prefetch group data are the same may be determined according to the size of the prefetch cache 1310.

[0102] According to some example embodiments, in operation S140, when a prefetch hit occurs, the memory controller 1200 may perform a single prefetch abort. For example, between the first time point t1 and the third time point t3, the prefetch manager 1230 may monitor a prefetch hit rate. A prefetch hit may mean that prefetch data is used by the host 1500. When a prefetch hit occurs, the prefetch manager 1230 may release the prefetch hit data based on the logical address through a single prefetch abort. Therefore, the prefetch manager 1230 may maintain a prefetch operation based on the first prefetch logical address 12.

[0103] As an example, between the first time point t1 and the second time point t2, the prefetch data corresponding to the fourteenth logical address LBA14 and the fifteenth logical address LBA15 can be released by a single prefetch abort. Between the second time point t2 and the third time point t3, the prefetch data corresponding to the sixteenth logical address LBA16 and the seventeenth logical address LBA17 can be released by a single prefetch abort.

[0104] According to some example embodiments, in operation S150, when a second workload from the host 1500 is detected, the memory controller 1200 may perform a large number of prefetch aborts. For example, at the third time point t3, when a second workload 20 that is discontinuous with the first logical address I1 is detected, the prefetch manager 1230 may release all first prefetch group data corresponding to the first prefetch group 131I pre-fetched based on the first prefetch logical address I2 in the buffer memory 1300 through a large number of prefetch aborts. That is, at the third time point t3, the prefetch manager 1230 may delete all remaining first prefetch group data from the prefetch cache 1310. Therefore, the prefetch cache 1310 may quickly secure an empty space for prefetching.

[0105] According to some example embodiments, in operation S160, when the second workload is sequential, the memory controller 1200 may perform a second prefetch operation. For example, in the third stage ST3, the prefetch manager 1230 may detect a second workload 20 corresponding to a second logical address 21 (e.g., LBA21, LBA22, LBA23, ...). The prefetch manager 1230 may determine whether the second logical address 21 corresponding to the second workload 20 is sequential at a fourth time point t4. When it is detected that the second logical address 21 is sequential, the prefetch manager 1230 may determine a second prefetch logical address 22 to be prefetched based on the second logical address 21. The prefetch manager 1230 may prefetch (or store) the second prefetch group data corresponding to the second prefetch logical address 22 from the memory device 1100 to the buffer memory 1300.

[0106] According to some example embodiments, in operation S170, the memory controller 1200 may increase the speed of the second prefetch operation based on the second workload. For example, between the fourth time point t4 and the fifth time point t5, the prefetch speed of the second prefetch group data may be increased. The memory controller 1200 may continuously prefetch (or store) the second prefetch group data corresponding to the second prefetch logical address 22 from the memory device 1100 to the buffer memory 1300.

[0107] According to some example embodiments, between the fourth time point t4 and the fifth time point t5, the prefetch manager 1230 may predict the second prefetch logical address 22. Before receiving the second logical address 21 from the host 1500, the prefetch manager 1230 may prefetch the second prefetch group data based on the predicted second prefetch logical address 22. Before receiving the second logical address 21 from the host 1500, the second prefetch group data may be stored in the prefetch cache 1310.

[0108] According to some example embodiments, in the fourth stage ST4, the second prefetch group data may be prefetched from the memory device 1100 at the same speed as the speed of receiving the second logical address 21. The prefetch manager 1230 may set the size of the prefetch cache 1310 at the fourth time point t4. A fifth time point t5 at which the reception speed of the second logical address 21 and the prefetch speed of the second prefetch group data are equal may be determined according to the size of the prefetch cache 1310.

[0109] Fig.12 is to show that the link is included in Figure 7 FIG. 1 is a diagram of a method for prefetching data in a first prefetch group. Fig.12 , the pre-fetch data included in the first pre-fetch group 1311 may include a previous tag and a next tag.

[0110] According to some example embodiments, the first prefetch data PFD1 corresponding to the eleventh logical address LBA11 may include the first user data D11, the first previous tag P1, and the first next tag N1. Since there is no prefetch data before the first prefetch data PFD1, the first previous tag P1 may be empty. The second prefetch data PFD2 corresponding to the twelfth logical address LBA12 may include the second user data D12, the second previous tag P2, and the second next tag N2. The second previous tag P2 may be the same as the first next tag N1. The third prefetch data PFD3 corresponding to the thirteenth logical address LBA13 may include the third user data D13, the third previous tag P3, and the third next tag N3. The third previous tag P3 may be the same as the second next tag N2.

[0111] As described above, the prefetch manager 1230 can add tags to the prefetch data to form a link between the first prefetch group data. The first next tag N1 and the second previous tag P2 can form a first link L1. The second next tag N2 and the third previous tag P3 can form a second link L2. The third next tag N3 and the fourth previous tag can form a third link L3.

[0112] Fig.13 It is shown by Figure 5 FIGURES 10 and 11 are diagrams of various example embodiments of addresses prefetched by a prefetch manager over time. Figure 5 and Fig.13 , the prefetch manager 1230 may prefetch data of the memory device 1100 to the buffer memory 1300 or release the prefetched data from the buffer memory 1300 according to the first stage ST1, the second stage ST2, the middle stage M_ST, the third stage ST3, and the fourth stage ST4. The operation of the prefetch manager 1230 in the first stage ST1, the second stage ST2, the third stage ST3, or the fourth stage ST4 may be the same as Figure 8Therefore, descriptions of operations of the prefetch manager 1230 in the first stage ST1 , the second stage ST2 , the third stage ST3 , or the fourth stage ST4 are omitted.

[0113] According to some example embodiments, between the third time point t3 and the fourth time point t4, the memory controller 1200 may receive the non-contiguous logical address 31 from the host 1500. Therefore, at the third time point t3, the prefetch manager 1230 may release the first prefetch group data corresponding to the first prefetch logical address I2 from the buffer memory 1300 through a mass prefetch abort. When the non-contiguous logical address 31 is received, the prefetch manager 1230 may not perform a prefetch operation.

[0114] According to some example embodiments, when the second logical address 21 is received between the fourth time point t4 and the fifth time point t5, the prefetch manager 1230 may determine whether the second logical address 21 is sequential. When the second logical address 21 is sequential, the prefetch manager 1230 may determine a second prefetch logical address 22 corresponding to the second logical address 21. The prefetch manager 1230 may newly prefetch the second prefetch group data corresponding to the second prefetch logical address 22 at the fifth time point t5.

[0115] Fig.14 is a block diagram illustrating an example in which a storage device according to some example embodiments of the present disclosure is implemented using a solid state drive (SSD). Fig.14 , the SSD 4000 may include a plurality of flash memories 4101 to 4104 and an SSD controller 4200 .

[0116] According to some example embodiments, the first flash memory 4101 and the second flash memory 4102 may be connected to the SSD controller 4200 through the first channel CH1. The third flash memory 4103 and the fourth flash memory 4104 may be connected to the SSD controller 4200 through the second channel CH2. The number of channels connected to the SSD controller 4200 may be more than two. The number of flash memories connected to one channel may be more than two.

[0117] According to some example embodiments, the SSD controller 4200 may include a host interface 4201, a flash interface 4202, a buffer interface 4203, a control unit 4210, and a working memory 4220. The working memory 4220 may drive a flash translation layer (FTL) 4221 and a prefetch manager 4222.

[0118] According to some example embodiments, the SSD controller 4200 may be connected to the host 1500 through a host interface 4201. The SSD controller 4200 may write data to a flash memory or read data from the flash memory according to a request of the host 1500.

[0119] According to some example embodiments, the SSD controller 4200 may be connected to the plurality of flash memories 4101 to 4104 through a flash interface 4202, and connected to the buffer memory 1300 through a buffer interface 4203. The flash interface 4202 may provide data temporarily stored in the buffer memory 1300 to the flash memories through corresponding channels CH1 and CH2. The flash interface 4202 may transfer data read from the flash memories 4101 to 4104 to the buffer memory 1300.

[0120] According to some example embodiments, the control unit 4210 may analyze and process a signal input from the host 1500. The control unit 4210 may control the host 1500 or the flash memories 4101 to 4104 through the host interface 4201 or the flash memory interface 4202. The control unit 4210 may control operations of the flash memories 4101 to 4104 according to firmware for driving the SSD 4000.

[0121] According to some exemplary embodiments, the working memory 4220 may drive the FTL 4221 under the control of the control unit 4210. The FTL 4221 may be loaded into the working memory 4220 from the flash memories 4101 to 4104 during a boot operation of the SSD 4000. The FTL 4221 may perform an address mapping operation, a garbage collection operation, a metadata management operation, etc., depending on the function implemented by the firmware.

[0122] According to some example embodiments, the working memory 4220 may drive the prefetch manager 4222 under the control of the control unit 4210. When a workload corresponding to a sequential logical address is received from the host 1500, the prefetch manager 4222 may determine an expected prefetch logical address when the sequential logical addresses are continuously received. The prefetch manager 4222 may group data corresponding to the prefetch logical address and prefetch them from the flash memories 4101 to 4104 to the buffer memory 1300 as prefetch group data. When a workload that is not continuous with the prefetch logical address is received, the prefetch manager 4222 may release the prefetch group data from the buffer memory 1300 at the same time (e.g., a large number of prefetch aborts). The prefetch manager 4222 may have Figures 5 to 13 The prefetch manager 1230 may have the same or similar functions and features as described in .

[0123] According to some example embodiments, the SSD controller 4200 may manage metadata or cache data to be stored in the flash memories 4101 to 4104. When a sudden power failure occurs, the SSD controller 4200 may back up metadata or cache data stored in the working memory 4220 or the buffer memory 1300 to the flash memories 4101 to 4104.

[0124] According to various example embodiments, performance of a storage device may be improved by efficiently or more efficiently managing a prefetch cache of a buffer memory.

[0125] Any of the elements and / or functional blocks disclosed above may include or be implemented in a processing circuit, such as hardware including a logic circuit; a hardware / software combination, such as a processor that executes software; or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. The processing circuit may include an electrical component such as at least one of a transistor, a resistor, a capacitor, etc. The processing circuit may include an electronic component such as a logic gate, which includes at least one of an AND gate, an OR gate, a NAND gate, a NOT gate, etc.

[0126] Although various example embodiments have been described with reference to embodiments thereof, it will be apparent to those of ordinary skill in the art that various changes and modifications may be made thereto without departing from the spirit and scope set forth in the appended claims. Furthermore, the example embodiments are not necessarily mutually exclusive of one another. For example, some example embodiments may include one or more features described with reference to one or more of the accompanying drawings, and may also include one or more other features described with reference to one or more of the other accompanying drawings.

Claims

1. A storage device, comprising: Memory devices; a buffer memory configured to store part of the data stored in the memory device; as well as A memory controller is configured to determine prefetch logical addresses that are expected to be received sequentially after receiving sequential logical addresses from a host, read prefetch data corresponding to the prefetch logical addresses from the memory device, store the prefetch data in the buffer memory according to prefetch groups, and release the prefetch groups from the buffer memory in response to receiving a logical address from the host that is not consecutive to the logical address.

2. The storage device according to claim 1, wherein: The memory controller is configured to: In response to receiving a first logical address from the host, comparing a specified portion of the first logical address, determining whether the first logical addresses are sequential based on the comparing, and In response to the first logical addresses being sequential, a prefetch cache is set in the buffer memory.

3. The storage device according to claim 2, wherein: The memory controller is configured to: determining an expected first prefetch logical address in response to receiving the first logical address in a continuing sequence, and Before receiving the first prefetch logical address from the host, first prefetch group data corresponding to the first prefetch logical address is stored in the prefetch cache based on a size of the prefetch cache. 4 . The memory device of claim 3 , wherein the memory controller is configured to release prefetch hit data in the first prefetch group data through a single prefetch abort. 5 . The storage device of claim 3 , wherein the memory controller is configured to release the first prefetch group data by a bulk prefetch abort in response to receiving a second logical address from the host that is discontinuous with the first logical address.

6. The storage device according to claim 5, wherein: The memory controller is configured to: determining whether the second logical address is sequential, In response to continuing to sequentially receive the second logical addresses and in response to the second logical addresses being sequential, determining an expected second prefetch logical address, and Before receiving the second prefetch logical address from the host, second prefetch group data corresponding to the second prefetch logical address is stored in the prefetch cache.

7. The storage device of claim 3, wherein the memory controller is configured to store the first prefetch group data in the prefetch cache at a first speed, and to receive the first logical address at the first speed after a time determined based on the size of the prefetch cache.

8. The storage device according to claim 3, wherein The first pre-fetched group of data includes first pre-fetched data and second pre-fetched data, The first pre-fetched data includes first user data, a first previous tag and a first next tag, The second pre-fetched data includes second user data, a second previous tag, and a second next tag, and The memory controller is configured to match the first next tag and the second previous tag to connect the first prefetch data and the second prefetch data into one group.

9. A pre-fetch management method for a storage device, the method comprising: performing a first prefetch operation in response to receiving a first sequential workload from a host; increasing a speed of the first prefetch operation based on the first sequential workload; monitoring whether a prefetch hit occurs in the first prefetch group data stored in the buffer memory through the first prefetch operation; releasing the prefetch data in which the prefetch hit occurs in the first prefetch group data by a single prefetch abort; as well as In response to receiving a second workload from the host that is discontinuous with the first sequential workload, the first prefetch set data is released via a bulk prefetch abort.

10. The method according to claim 9, wherein: The performing the first prefetch operation includes prefetching the first prefetch group data corresponding to the first sequential workload from a memory device to the buffer memory.

11. The method according to claim 9, wherein: The increasing the speed of the first prefetch operation includes storing the first prefetch group data corresponding to the first sequential workload in the buffer memory at an increased speed prior to receiving the first sequential workload.

12. The method according to claim 9, further comprising: A time to increase the speed of the first prefetch operation is determined based on a size of the buffer memory.

13. The method according to claim 9, wherein the monitoring whether the prefetch hit occurs comprises: After a time determined based on the size of the buffer memory, storing the first prefetch group data in the buffer memory at a first rate; as well as The first sequential workload is received at the first speed.

14. The method according to claim 9, further comprising: In response to the second workload being sequential, performing a second prefetch operation corresponding to the second workload; as well as A speed of the second prefetch operation is increased based on the second workload.

15. The method according to claim 14, further comprising: After a time determined based on the size of the buffer memory, a speed of the second prefetch operation is maintained at a speed that is the same as a reception speed of the second workload.

16. A storage device comprising: Memory devices; a buffer memory including a prefetch cache configured to store prefetch data corresponding to a workload received from a host; as well as a memory controller configured to read data corresponding to a sequential workload from the memory device and store the data in the prefetch cache in response to receiving the sequential workload from the host, Wherein, the memory controller is configured as: performing a first prefetch operation corresponding to the first workload in response to receiving a first sequential workload from the host; increasing the speed of the first prefetch operation based on the size of the prefetch cache; and In response to receiving a second workload discontinuous from the first workload from the host, all prefetch data prefetched by the first prefetch operation is released from the prefetch cache via a bulk prefetch abort.

17. The storage device according to claim 16, wherein: The memory controller is configured to detect whether the first workload is sequential by comparing a specified portion of logical addresses included in the first workload in response to receiving the first workload.

18. The storage device of claim 16, wherein the memory controller is configured to set the prefetch cache having a specified size within the buffer memory in response to the first workload being detected as sequential.

19. The storage device according to claim 18, wherein: The memory controller is configured to maintain a speed of the first prefetch operation at a same speed as a reception of the first workload after a time determined based on a size of the prefetch cache. 20 . The memory device of claim 16 , wherein the memory controller is configured to release prefetch hit data in a first prefetch group data stored in the prefetch cache by the first prefetch operation through a single prefetch abort.

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