Recording memory addresses associated with erroneous usage-based interference data

Abstract

Devices and techniques are described for recording memory addresses associated with erroneous usage-based interference data. In an example aspect, a memory device can detect errors associated with usage-based disturbing data at a local bank level. This detection enables the memory device to record a row address associated with the erroneous use-based interference data. To avoid increasing the complexity and / or size of the memory device, some embodiments of the memory device can perform the address recording at the multi-bank level with assistance of an engine, such as a test engine. The memory device stores the record address in at least one mode register to communicate the error to a memory controller. Through the record address, the memory controller can initiate a repair program to correct the erroneous use-based disturbing data.

Description

[0001] CROSS REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Patent Application Serial No. 63 / 592,761, filed on October 24, 2023, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The present application relates to memory devices, and in particular, to recording memory addresses associated with erroneous usage-based interference data. Background Art

[0004] Computers, smartphones, and other electronic devices rely on processors and memory. The processor executes code based on data to run applications and provide features to users. The processor obtains the code and data from the memory. The memory in an electronic device may include volatile memory, such as random access memory (RAM), and non-volatile memory, such as flash memory. Like the power of the processor, the power of the memory may affect the performance of the electronic device. This performance impact may increase as faster processors that execute code are developed and as applications operate on larger and larger data sets requiring larger and larger memory. Summary of the invention

[0005] On the one hand, the present application provides an apparatus comprising: a memory device comprising: at least one memory bank comprising multiple rows of memory cells, each of the multiple rows being configured to store data associated with usage-based interference in a subset of the memory cells; an engine configured to access the multiple rows of the at least one memory bank; and a circuit system coupled to the engine and the at least one memory bank, the circuit system being configured to: detect the occurrence of an error associated with the stored data within a row of the multiple rows; and record the address of the row based on the row being accessed by the engine and based on detecting the occurrence of the error.

[0006] On the other hand, the present application provides a method performed by a memory device, the method comprising: storing data associated with usage-based interference in a subset of memory cells in a row; using an engine to access the row; detecting the occurrence of an error associated with the data stored in the row at a local memory level of the memory device; and recording the address of the row at a multi-memory level of the memory device based on the row being accessed by the engine and based on detecting the occurrence of the error.

[0007] On the other hand, the present application provides an apparatus comprising: a memory device comprising: at least one memory body comprising multiple rows of memory cells, each of the multiple rows being configured to store data associated with usage-based interference in a subset of the memory cells; an engine configured to access the multiple rows of the at least one memory body; and a circuit system comprising: at least one first circuit coupled to the at least one memory body and implemented at a local memory body level, the at least one first circuit being configured to report detection of an occurrence of an error associated with the data stored in a row of the multiple rows based on the engine accessing the row; and a second circuit coupled to the engine and the at least one first circuit, the second circuit being implemented at a multi-memory body level and configured to latch the address of the row accessed by the engine based on the reported detection provided by the at least one first circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] An apparatus and technique for recording memory addresses associated with erroneous usage-based interference data is described with reference to the following figures. The same numbers are used throughout the drawings to refer to similar features and components.

[0009] Figure 1 An example device is described in which aspects of recording memory addresses associated with erroneous usage-based interference data may be implemented;

[0010] Figure 2 An example computing system is described that can implement aspects of recording memory addresses associated with erroneous usage-based interference data;

[0011] Figure 3 describing instance data stored in a row of a memory array;

[0012] Figure 4 An example memory device is described in which aspects of recording memory addresses associated with erroneous usage-based interference data may be implemented;

[0013] Figure 5 illustrating an example arrangement of usage-based disturbed data repair circuitry on a die;

[0014] Figure 6 An example of usage-based disturber data repair circuitry coupled to a mode register for implementing aspects of recording memory addresses associated with erroneous usage-based disturber data is described;

[0015] Figure 7 An example implementation of a usage-based disturbing data repair circuitry that directly records memory addresses associated with erroneous usage-based disturbing data is described;

[0016] Figure 8 An example implementation of a usage-based disturbing data repair circuitry that indirectly records memory addresses associated with erroneous usage-based disturbing data is described;

[0017] Fig. 9 A first example implementation of a detection circuit for indirectly recording a memory address associated with erroneous usage-based interference data is described;

[0018] Fig.10 A second example implementation of a detection circuit for indirectly recording a memory address associated with erroneous usage-based interference data is described;

[0019] Fig.11 A third example implementation of a detection circuit for indirectly recording a memory address associated with erroneous usage-based interference data is described; and

[0020] Fig.12 An example method is described in which a memory device performs aspects of recording memory addresses associated with erroneous usage-based interference data. DETAILED DESCRIPTION

[0021] Overview

[0022] Processors and memory work together to provide features to users of computers and other electronic devices. As processors and memory operate faster together in a complementary manner, electronic devices can provide enhanced features, such as high-resolution graphics and artificial intelligence (AI) analysis. Some applications (such as financial services, medical devices, and advanced driver assistance systems (ADAS) applications) also require more reliable memory. These applications use more and more reliable memory to limit errors in financial transactions, medical decisions, and object recognition. However, in some implementations, more reliable memory sacrifices bit density, power efficiency, and simplicity.

[0023] In order to meet the demand for physically smaller memories, memory devices can be designed with higher chip densities. However, increasing chip density increases electromagnetic coupling (e.g., capacitive coupling) between adjacent or proximate rows of memory cells, at least in part due to the reduced distance between these rows. Due to this undesirable coupling, the activation (or charging) of a first row of memory cells sometimes negatively affects nearby second row of memory cells. In particular, the activation of the first row may produce interference or crosstalk, which causes the second row to experience voltage fluctuations. In some examples, this voltage fluctuation may cause the state (or value) of the memory cell in the second row to be incorrectly determined by the sense amplifier. Consider an example in which the state of the memory cell in the second row is "1". In this example, the voltage fluctuation may cause the sense amplifier to incorrectly determine the state of the memory cell as "0" instead of "1". If not curbed, this interference may cause memory errors or data loss within the memory device.

[0024] In some cases, a particular row of memory cells is repeatedly activated, either unintentionally or intentionally (sometimes maliciously). For example, consider that the memory cells in row R are subjected to repeated activation, which causes one or more memory cells in nearby rows (e.g., within row R+1, row R+2, row R-1, and / or row R-2) to change state. This effect is called usage-based disturbance. The occurrence of usage-based disturbance can cause the contents within the affected memory row to be corrupted or changed.

[0025] Some memory devices utilize circuits that can detect usage-based disturbances and mitigate their effects. To monitor usage-based disturbances, a memory device may store an activation count within each row of a memory array. The activation count tracks the number of times the corresponding memory row is accessed or activated. If the activation count meets or exceeds a threshold, then a near row that includes one or more neighboring rows may face an increased risk of data corruption due to repeated activation of the accessed row and the effects of usage-based disturbances. To manage this risk for affected rows, a memory device may refresh the near row.

[0026] However, if the activation count fails or is erroneous, the effectiveness of this protection feature will be compromised. For example, the activation count may be corrupted when read or written during an array counter update procedure. On the other hand, the memory cell storing the activation count cannot retain the stored value of the activation count.

[0027] The memory device may perform a repair process that replaces an erroneous activation count in a permanent (or "hard") manner or in a temporary (or "soft") manner. However, the repair process is initiated by a host device (or storage controller). In some embodiments, the host device may not be able to directly detect an erroneous activation count. For example, if the memory cell storing the activation count cannot be written to or read from, then the host device cannot evaluate whether the activation count is erroneous. Therefore, when an activation count is erroneous, the host device cannot initiate a repair process.

[0028] To address this and other issues related to usage-based interference, this document describes techniques for recording memory addresses associated with erroneous usage-based interference data. In an example aspect, a memory device stores usage-based interference data in a subset of memory cells of multiple rows of a memory array. The memory device can detect errors associated with usage-based interference data at a local memory bank level. This detection enables the memory device to record addresses associated with erroneous usage-based interference data. To avoid increasing the complexity and / or size of the memory device, some embodiments of the memory device can perform address recording at a multi-memory bank level with the assistance of an engine, such as a test engine. The memory device stores the recorded address in at least one mode register to communicate the error to a memory controller. By recording the address, the memory controller can initiate a repair procedure to correct the erroneous usage-based interference data.

[0029] Instance operating environment

[0030] Figure 1 An example operating environment including an apparatus 102 is generally illustrated at 100, which may implement aspects of recording memory addresses associated with erroneous usage-based interference data. The apparatus 102 may include various types of electronic devices, including an Internet of Things (IoT) device 102-1, a tablet device 102-2, a smartphone 102-3, a laptop computer 102-4, a passenger car 102-5, a server computer 102-6, and a server cluster 102-7, which may be part of a cloud computing infrastructure, a data center, or a portion thereof, such as a printed circuit board (PCB). Other examples of the apparatus 102 include a wearable device (such as a smart watch or smart glasses), an entertainment device (such as a set-top box, a video dongle, a smart TV, a gaming device), a desktop computer, a motherboard, a blade server, a consumer appliance, a vehicle, a drone, an industrial device, a security device, a sensor, or an electronic component thereof. Each type of apparatus may include one or more components to provide computing functionality or features.

[0031] In an example embodiment, the apparatus 102 may include at least one host device 104, at least one interconnect 106, and at least one memory device 108. The host device 104 may include at least one processor 110, at least one cache 112, and a memory controller 114. The memory device 108 (which may also be implemented with a memory module) may include, for example, a dynamic random access memory (DRAM) die or module (e.g., a low power double data rate synchronous DRAM (LPDDR SDRAM)). The DRAM die or module may include a three-dimensional (3D) stacked DRAM device, which may be a high bandwidth memory (HBM) device or a hybrid memory cube (HMC) device. The memory device 108 may operate as a main memory of the apparatus 102. Although not illustrated, the apparatus 102 may also include a storage memory. The storage memory may include, for example, a storage class memory device (e.g., a flash memory, a hard disk drive, a solid state drive, a phase change memory (PCM), or a 3D XPoint TM of memory).

[0032] Processor 110 is operatively coupled to cache 112, which is operatively coupled to memory controller 114. Processor 110 is also directly or indirectly coupled to memory controller 114. Host device 104 may include other components to form, for example, a system on a chip (SoC). Processor 110 may include a general purpose processor, a central processing unit, a graphics processing unit (GPU), a neural network engine or accelerator, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) integrated circuit (IC), or a communication processor (e.g., a modem or baseband processor).

[0033] In operation, the memory controller 114 may provide a high-level or logical interface between the processor 110 and at least one memory, such as an external memory. The memory controller 114 may be implemented with any of a variety of suitable memory controllers, such as a double data rate (DDR) memory controller that can process requests for data stored on the memory device 108. Although not shown, the host device 104 may include a physical interface (PHY) that transmits data between the memory controller 114 and the memory device 108 through the interconnect 106. For example, the physical interface may be an interface compatible with the DDR PHY interface (DFI) group interface protocol. For example, the memory controller 114 may receive memory requests from the processor 110 and provide the memory requests to the external memory with appropriate formatting, timing, and reordering. The memory controller 114 may also forward responses to memory requests received from the external memory to the processor 110.

[0034] Host device 104 is operatively coupled to memory device 108 via interconnect 106. In some examples, memory device 108 is connected to host device 104 via interconnect 106 with an intermediate buffer or cache. Memory device 108 may be operatively coupled to storage memory (not shown). Host device 104 may also be coupled directly or indirectly to memory device 108 and storage memory via interconnect 106. Interconnect 106 and other interconnects ( Figure 1 The interconnect 106 may transmit data between two or more components of the apparatus 102 (not illustrated). Examples of the interconnect 106 include a bus (e.g., a unidirectional or bidirectional bus), a switching fabric, or one or more wires that carry voltage or current signals. The interconnect 106 may propagate one or more communications 116 between the host device 104 and the memory device 108. For example, the host device 104 may transmit a memory request to the memory device 108 via the interconnect 106. In addition, the memory device 108 may transmit a corresponding memory response to the host device 104 via the interconnect 106.

[0035] The illustrated components of the apparatus 102 represent an example architecture having a hierarchical memory system. The hierarchical memory system may include memory at different levels, with each level having memory with different speeds or capacities. As illustrated, the cache 112 logically couples the processor 110 to the memory device 108. In the illustrated implementation, the cache 112 is at a higher level than the memory device 108. The storage memory, in turn, may be at a lower level than the main memory (e.g., the memory device 108). The memory at the lower level has a reduced speed but increased capacity relative to the memory at the higher level.

[0036] Device 102 may be implemented in various ways with more, fewer, or different components. For example, host device 104 may include multiple caches (e.g., including multiple levels of caches) or no cache. In other embodiments, host device 104 may omit processor 110 or memory controller 114. Memory (e.g., memory device 108) may have an "internal" or "local" cache. As another example, device 102 may include a cache between interconnect 106 and memory device 108. Computer engineers may also include any of the illustrated components in a distributed or shared memory system.

[0037] Computer engineers can implement host device 104 and various memories in a variety of ways. In some cases, host device 104 and memory device 108 can be placed on or physically supported by a printed circuit board (such as a rigid or flexible motherboard). Host device 104 and memory device 108 can also be integrated together on an integrated circuit or fabricated on separate integrated circuits and packaged together. Memory device 108 can also be coupled to multiple host devices 104 via one or more interconnects 106 and can respond to memory requests from two or more host devices 104. Each host device 104 can include a corresponding memory controller 114, or multiple host devices 104 can share a memory controller 114. This document refers to Figure 1 An example computing system architecture is described having at least one host device 104 coupled to a memory device 108 .

[0038] Two or more memory components (e.g., modules, dies, banks, or groups of banks) may share an electrical path or coupling of the interconnect 106. The interconnect 106 may include at least one command and address bus (CA bus) and at least one data bus (DQ bus). The command and address bus may transmit addresses and commands from the memory controller 114 of the host device 104 to the memory device 108, which may eliminate the propagation of data. The data bus may propagate data between the memory controller 114 and the memory device 108. The memory device 108 may also be implemented as any suitable memory, including, but not limited to, DRAM, SDRAM, three-dimensional (3D) stacked DRAM, DDR memory, or LPDDR memory (e.g., LPDDR DRAM or LPDDR SDRAM).

[0039] Memory device 108 may form at least part of a main memory of apparatus 102. However, memory device 108 may form at least part of a cache, storage memory, or system-on-chip of apparatus 102. Memory device 108 includes at least one instance of usage-based disturb circuitry 120 (UBD circuitry 120) and at least one instance of usage-based disturb data repair circuitry 122 (UBD data repair circuitry 122).

[0040] The usage-based interference circuitry 120 mitigates usage-based interference of one or more memory banks associated with the memory device 108. The usage-based interference circuitry 120 may be implemented using software, firmware, hardware, fixed circuit circuitry, or a combination thereof. The usage-based interference circuitry 120 may also include at least one counter circuit for detecting conditions associated with usage-based interference, at least one queue for managing refresh operations to mitigate usage-based interference, and / or at least one error correction code (ECC) circuit for detecting and / or correcting bit errors associated with usage-based interference.

[0041] One aspect of usage-based interference mitigation involves tracking how often a row has been activated or accessed since the last refresh. Specifically, the usage-based interference circuitry 120 uses a counter circuit to perform an array counter update procedure to update an activation count associated with an activated row. During the array counter update procedure, the usage-based interference circuitry 120 reads the activation count stored within the activated row, increments the activation count, and writes the updated activation count to the activated row. By maintaining the activation count, the usage-based interference circuitry 120 can determine when to perform a refresh operation to reduce the risk of usage-based interference. For example, when the activation count meets or exceeds a threshold, the usage-based interference circuitry 120 can perform a mitigation procedure that refreshes one or more rows near the activated row to mitigate usage-based interference.

[0042] In general, techniques for recording memory addresses associated with erroneous usage-based disturbing data may be performed at least in part by usage-based disturbing data repair circuitry 122. More specifically, these techniques may be implemented using at least one detection circuit 124 and at least one address recording circuit 126. Address recording may be performed at a local bank level 128 or at a multi-bank level 130, as further described below.

[0043] The detection circuit 124 detects the occurrence (or absence) of errors associated with data referenced by the usage-based interference circuit system 120 to mitigate usage-based interference. This data is referred to as usage-based interference data. In general, the memory device 108 may perform various error detection tests to determine whether the usage-based interference data (or the memory cell storing the usage-based interference data) has errors. Example error detection tests include parity bit checking, error correction code checking, checksum checking, cyclic redundancy checking, another type of error detection procedure, or some combination thereof. In some implementations, the detection circuit 124 performs error detection tests and thus directly detects errors. In other implementations, the usage-based interference circuit system 120 performs error detection tests as part of an array counter update procedure. In this case, the detection circuit 124 stores information about any errors detected by the usage-based interference circuit system 120. The detection circuit 124 communicates the occurrence of the detected error to the address recording circuit 126.

[0044] At the multi-bank stage 130, the address recording circuit 126 records (or captures) addresses associated with erroneous usage-based interference data based on the occurrence of the detected error indicated by the detection circuit 124. The address recording circuit 126 may further provide the recorded address to other components of the memory device 108 so that the occurrence of the error and the recorded address may be communicated to the host device 104.

[0045] In an example embodiment, the detection circuits 124 are implemented at a local memory bank level 128. This means that each detection circuit 124 detects the occurrence of an error within a corresponding memory bank of the memory device 108. In contrast to the detection circuits 124, the address recording circuits 126 are implemented at a multi-memory bank level 130. This means that one instance of an address recording circuit 126 can serve two or more memory banks of the memory device 108. At the multi-memory bank level 130, the address recording circuits 126 can easily communicate information about the detected errors in a manner that enables the host device 104 to initiate a repair procedure. Figure 5 The local bank level 128 implementation of the detection circuit 124 and the multi-bank level 130 implementation of the address recording circuit 126 are further described.

[0046] The usage-based disturb data repair circuit system 122 enables information about the occurrence of errors and the addresses associated with the errors to be communicated to or accessed by the host device 104 (e.g., the memory controller 114). With this information, the host device 104 can initiate a repair procedure to correct the erroneous data within the memory device 108. One type of repair procedure is a hard post-package repair (hPPR) procedure. For a hard post-package repair procedure, the memory controller 114 may request the memory device 108 to permanently repair the entire combined row, including the erroneous data for usage-based disturb mitigation. However, with this repair procedure, the viability of the existing data stored in the memory row is uncertain. In addition, the permanent, non-volatile nature of the hard post-package repair requires blowing fuses. The procedure is relatively lengthy and can typically only be performed during power-on and initialization or in the case of a full memory reset, rather than in real time when the memory device 108 is operating normally and performing memory operations of the host device 104.

[0047] Soft Post Package Repair (sPPR) is a significantly faster temporary repair procedure than hard Post Package Repair. Furthermore, although the soft Post Package Repair procedure produces a volatile repair, the soft Post Package Repair procedure can be executed in real time in response to the detection of a fault. However, if the memory row is being repaired, then the computing system is responsible for handling the data transfer (e.g., a full page of data) from the memory row corresponding to the error activation count to the spare counter and memory row combination. This data transfer consumes a considerable amount of time while occupying the data bus. Figure 2 Other components of memory device 108 are further described.

[0048] Figure 2An example computing system 200 is illustrated in which aspects of recording memory addresses associated with erroneous usage-based interference data may be implemented. In some implementations, the computing system 200 includes at least one memory device 108, at least one interconnect 106, and at least one processor 202. The memory device 108 may include at least one memory array 204, at least one interface 206, and control circuitry 208 (or peripheral circuitry) operatively coupled to or associated with the memory array 204. The memory array 204 may include an array of memory cells, including, but not limited to, memory cells of DRAM, SDRAM, three-dimensional (3D) stacked DRAM, DDR memory, LPDDR SDRAM, and the like. The memory array 204 and the control circuitry 208 may be components on a single semiconductor die or separate semiconductor dies. The memory array 204 or the control circuitry 208 may also be distributed across multiple dies. Such control circuitry 208 may manage traffic on a bus separate from the interconnect 106.

[0049] The control circuitry 208 may include various components that the memory device 108 may use to perform various operations. These operations may include communicating with other devices, managing memory performance, performing refresh operations (such as self-refresh operations or auto-refresh operations), and performing memory read or write operations. In the depicted configuration, the control circuitry 208 includes usage-based disturbed data repair circuitry 122, at least one array control circuit 210, at least one instance of clock circuitry 212, and at least one mode register 214. The control circuitry 208 may also optionally include at least one engine 216.

[0050] Array control circuitry 210 may include circuitry that provides command decoding, address decoding, input / output functions, amplification circuitry, power supply management, power control modes, and other functions. Clock circuitry 212 may synchronize various memory components with one or more external clock signals, including command and address clocks or data clocks, provided through interconnect 106. Clock circuitry 212 may also use internal clock signals to synchronize memory components and may provide timer functionality.

[0051] In general, the control circuitry 208 stores the addresses recorded by the usage-based disturb data repair circuitry 122 in a manner accessible by the memory controller 114. With this information, the memory controller 114 can initiate an appropriate repair procedure. In an example embodiment, the mode register 214 facilitates control by and / or communication with the memory controller 114 (or one of the processors 202). Using the mode register 214, the memory device 108 can communicate information to the memory controller 114. Such communication can result in a command to enter or exit a repair mode or to provide a memory row address as a target for a repair procedure. To facilitate this communication, the mode register 214 may include one or more registers having at least one bit related to usage-based disturb repair functionality.

[0052] When implemented and enabled, the engine 216 can access each row of the memory array 204 in a controlled manner. The manner in which the engine 216 accesses the rows of the memory array 204 can be based on an automatic mode or a manual mode. Generally speaking, given sufficient time, the engine 216 accesses all rows of the memory array 204. In some embodiments, the engine 216 accesses the rows of the memory array 204 in a periodic or cyclic manner. The order in which the engine 216 accesses the rows can be a predetermined order, a rule-based order, or a randomized order. In some embodiments, the engine 216 is implemented as a test engine that can detect and / or correct errors in at least a subset of the data stored in the row. Example engines include an error checking and cleaning engine (ECS engine), an add-based engine, or a refresh engine.

[0053] The memory device 108 also includes usage-based interference circuitry 120. In some aspects, the usage-based interference circuitry 120 may be considered part of the control circuitry 208. For example, the usage-based interference circuitry 120 may represent another portion of the control circuitry 208. The usage-based interference circuitry 120 may be coupled to a set of memory cells within the memory array 204 that store usage-based interference data 218 (UBD data 218). The usage-based interference data 218 may include information such as activation counts that represent the number of times one or more rows within the memory array 204 have been activated (or accessed) by the memory device 108. In an example embodiment, each row of the memory array 204 includes a subset of memory cells that store usage-based interference data 218 associated with the row, such as information about the number of times the row has been activated (or accessed). Figure 3 Further description.

[0054] The interface 206 may couple the control circuitry 208 or the memory array 204 directly or indirectly to the interconnect 106. In some implementations, the usage-based interference circuitry 120, the usage-based interference data repair circuitry 122, the array control circuitry 210, the clock circuitry 212, the mode register 214, and the engine 216 may be parts of a single component, such as the control circuitry 208. In other implementations, one or more of the usage-based interference circuitry 120, the usage-based interference data repair circuitry 122, the array control circuitry 210, the clock circuitry 212, the mode register 214, or the engine 216 may be implemented as separate components that may be provided on a single semiconductor die or disposed across multiple semiconductor dies. These components may be coupled to the interconnect 106 individually or jointly via the interface 206.

[0055] Interconnect 106 may use one or more of a variety of interconnects that can communicatively couple various components together and enable commands, addresses, or other information and data to be transferred between two or more components (e.g., between memory device 108 and processor 202). Figure 2 1 and 2 , the interconnect 106 is illustrated with a single line, but the interconnect 106 may include at least one bus, at least one switching configuration, one or more wires or traces carrying voltage or current signals, at least one switch, one or more buffers, etc. Furthermore, the interconnect 106 may be separated into at least a command and address bus and a data bus.

[0056] In some aspects, the memory device 108 may be relative to ( Figure 1 The memory device 108 may be a "separate" component of any of the host device 104 or the processor 202 (or any of the host device 104 or the processor 202). The separate components may include a printed circuit board, a memory card, a memory stick, and a memory module (e.g., a single in-line memory module (SIMM) or a dual in-line memory module (DIMM)). Thus, the separate physical components may be located together within the same housing of an electronic device or may be distributed across a server rack, a data center, etc. Alternatively, the memory device 108 may be integrated with other physical components including the host device 104 or the processor 202 by being combined on a printed circuit board or in a single package or system on a chip.

[0057] like Figure 21, processor 202 may include a computer processor 202-1, a baseband processor 202-2, and an application processor 202-3 coupled to a memory device 108 via an interconnect 106. Processor 202 may include or form part of a central processing unit, a graphics processing unit, a system on a chip, an application specific integrated circuit, or a field programmable gate array. In some cases, a single processor may include multiple processing resources, each dedicated to a different function (e.g., modem management, applications, graphics, central processing). In some implementations, baseband processor 202-2 may include or be coupled to a modem ( Figure 2 Modem or baseband processor 202-2 may be implemented via, for example, cellular, Near field or another technology or protocol for wireless communication to wirelessly couple to the network.

[0058] In some implementations, processors 202 may be directly connected to memory device 108 (e.g., through interconnect 106). In other implementations, one or more of processors 202 may be indirectly connected to memory device 108 (e.g., through a network connection or through one or more other devices). Figure 3 Memory array 204 is further described.

[0059] Figure 3 2 illustrates example data stored in a row of memory array 204. Memory array 204 includes a plurality of rows 302 of memory cells. For example, Figure 3 2 includes rows 302-1, 302-2, ... 302-R, where R represents a positive integer. Each row 302 is associated with an address 304 (e.g., a row address, a memory row address, or a memory address). For example, the first row 302-1 has a first address 304-1, the second row 302-2 has a second address 304-2, and the Rth row 302-R has an Rth address 304-R.

[0060] Each of the rows 302 may store normal data 306 within a first subset of memory cells associated with the row 302. The normal data 306 represents data read from or written to the memory device 108 during normal memory operations (e.g., during normal read or write operations). For example, the normal data 306 may include data transmitted by the memory controller 114 and written to the memory array 204 for one or more rows 302.

[0061] In addition to the normal data 306, each of the rows 302 may store usage-based interference data 218 within a second subset of memory cells associated with the row 302. The usage-based interference data 218 includes information that enables the usage-based interference circuitry 120 to mitigate usage-based interference. In an example implementation, the usage-based interference data 218 includes an activation count 308.

[0062] In this example, the first row 302-1 stores first normal data 306-1 within a first subset of memory cells of the first row 302-1 and stores first usage-based interference data 218-1 within a second subset of memory cells of the first row 302-1. The first usage-based interference data 218-1 includes a first activation count 308-1, which indicates the number of times the first row 302-1 has been activated since the last refresh. As another example, the second row 302-2 stores second normal data 306-2 within a first subset of memory cells within the second row 302-2 and stores second usage-based interference data 218-2 within a second subset of memory cells within the second row 302-2. The second usage-based interference data 218-2 includes a second activation count 308-2, which indicates the number of times the second row 302-2 has been activated since the last refresh. Additionally, the Rth row 302-R stores Rth normal data 306-R in a first subset of memory cells within the Rth row 302-R and stores Rth usage-based interference data 218-R in a second subset of memory cells within the Rth row 302-R. The Rth usage-based interference data 218-R includes an Rth activation count 308-R that represents the number of times the Rth row 302-R has been activated since the last refresh.

[0063] The usage-based interference data 218 also includes information or is formatted (e.g., encoded) in a manner that supports error detection. In this example, the usage-based interference data 218 includes parity bits 310 to enable the use of parity to detect activation counts 308 that are in error. For example, the usage-based interference data 218-1, 218-2, and 218-R include parity bits 310-1, 310-2, and 310-R, respectively. Other embodiments are also possible, in which the usage-based interference data 218 is encoded in a manner that supports any of the above-mentioned error detection tests, such as error correction code checking. Although the techniques for recording memory addresses associated with erroneous usage-based interference data 218 are described with respect to parity bit errors associated with activation counts 308, these techniques are generally applicable to recording addresses of any type of usage-based interference data 218 and any type of error detection associated with such data.

[0064] Example Technology and Hardware

[0065] Figure 4 An example memory device 108 is illustrated in which aspects of recording memory addresses associated with erroneous usage-based interference data may be implemented. The memory device 108 includes a memory module 402, which may include a plurality of dies 404. As illustrated, the memory module 402 includes a first die 404-1, a second die 404-2, a third die 404-3, and a D-th die 404-D, where D represents a positive integer. The memory module 402 may be a SIMM or a DIMM. As another example, the memory module 402 may be interconnected via a bus such as a peripheral component interconnect fast Bus) to interface with other components. Figure 1 and 2 The memory device 108 illustrated in can correspond to, for example, a plurality of dies 404-1 through 404-D or a memory module 402 having two or more dies 404. As shown, the memory module 402 can include one or more electrical contacts 406 (eg, pins) to interface the memory module 402 to other components.

[0066] The memory module 402 may be implemented in various ways. For example, the memory module 402 may include a printed circuit board, and a plurality of dies 404-1 to 404-D may be mounted or otherwise attached to the printed circuit board. The dies 404 (e.g., memory dies) may be arranged in a row or arranged along two or more dimensions (e.g., forming a grid or array). The dies 404 may have similar sizes or may have different sizes. Each die 404 may be similar to another die 404 or may differ in size, shape, data capacity, or control circuitry. The die 404 may also be positioned on a single side or multiple sides of the memory module 402.

[0067] One or more of the dies 404-1 to 404-D include a usage-based interference circuit system 120, a usage-based interference data repair circuit system 122 (UBD DR circuit system 122), and memory bank groups 408-1 to 408-G, where G represents a positive integer. Each memory bank group 408 includes at least two memory banks 410, such as memory banks 410-1 to 410-B, where B represents a positive integer. In some implementations, the die 404 includes multiple instances of the usage-based interference circuit system 120, which mitigates usage-based interference across at least one of the memory banks 410. For example, multiple instances of the usage-based interference circuit system 120 can mitigate usage-based interference across memory bank groups 408-1 to 408-G, respectively. In this example, one instance of the usage-based interference circuit system 120 mitigates usage-based interference across multiple memory banks 410-1 to 410-B of the memory bank group 408. In another example, multiple instances of the usage-based interference circuitry 120 may each mitigate usage-based interference for a corresponding memory bank 410. In this case, each usage-based interference circuitry 120 mitigates usage-based interference for a single memory bank 410 within one of the memory bank groups 408-1 to 408-B. In yet another example, each usage-based interference circuitry 120 mitigates usage-based interference for a subset of memory banks 410 associated with one of the memory bank groups 408-1 to 408-G, where the subset of memory banks 410 includes at least two memory banks 410. Figure 5 The relationship between the memory banks 410 - 1 through 410 -B and the components of the usage-based disturbed data repair circuitry 122 is further described.

[0068] Figure 5An example arrangement of multiple detection circuits 124 and address recording circuits 126 on a die 404 is illustrated. The die 404 includes a bank-specific circuit system 502 and a bank-shared circuit system 504. The bank-specific circuit system 502 includes components associated with a specific bank 410. For example, the bank-specific circuit system 502 includes banks 410-1, 410-2 ... 410-(B / 2), 410-(B / 2+1), 410-(B / 2+2) ... 410-B and detection circuits 124-1, 124-2 ... 124-(B / 2), 124-(B / 2+1), 124-(B / 2+2) ... 124-B. The detection circuits 124-1 to 124-B are coupled to the banks 410-1 to 410-B, respectively. In some cases, subsets of memory banks 410-1 through 410-B are associated with different memory bank groups 408. In an example embodiment, die 404 includes 32 memory banks 410 (e.g., B equals 32). The 32 memory banks 410 form 8 memory bank groups 408 (e.g., G equals 8), where each memory bank group 408 includes 4 memory banks 410. In other cases, memory banks 410-1 through 410-B are associated with a single memory bank group 408.

[0069] Each detection circuit 124 may detect the occurrence of a fault (fault / error) associated with the usage-based interference data 218 stored in the corresponding memory bank 410. For example, the first detection circuit 124-1 may monitor for errors associated with the usage-based interference data 218 stored in the row 302 of the first memory bank 410-1. Similarly, the second detection circuit 124-2 may monitor for errors associated with the usage-based interference data 218 stored in the row 302 of the second memory bank 410-2.

[0070] The bank-shared circuitry 504 includes components associated with the plurality of banks 410. These components perform operations associated with the plurality of banks 410. Example components of the bank-shared circuitry 504 include the address recording circuitry 126 and the engine 216, if implemented. In this example, the usage-based interference circuitry 120 is also shown as part of the bank-shared circuitry 504. Alternatively, multiple instances of the usage-based interference circuitry 120 may be implemented as part of the bank-specific circuitry 502. In an example implementation, the address recording circuitry 126 is located proximate to the engine 216.

[0071] On the die 404, the bank-specific circuitry 502 is positioned on two opposite sides of the bank-shared circuitry 504. In other words, the bank-shared circuitry 504 may be centrally positioned on the die 404. Thus, the address recording circuitry 126 may be positioned closer to the center of the die 404 than to the edge of the die 404. Positioning the bank-shared circuitry 504 in the center can simplify routing between the bank-shared circuitry 504 and the bank-specific circuitry 502.

[0072] Consider a first axis 508-1 (eg, X-axis 508-1) and a second axis 508-2 (eg, Y-axis 508-2) perpendicular to the first axis 508-1. Figure 5 , the first axis 508-1 is depicted as a "horizontal" axis and the second axis 508-2 is depicted as a "vertical" axis. The components of the memory bank sharing circuit system 504 are distributed across the second axis 508-2. The first group of memory banks (e.g., memory banks 410-1 to 410-B / 2) are arranged on the "left" side of the memory bank sharing circuit system 504 along the second axis 508-2, and the second group of memory banks (e.g., memory banks 410-(B / 2+1) to 410-B) are arranged on the "right" side of the memory bank sharing circuit system 504 along the second axis 508-2. The detection circuits 124-1 to 124-B are positioned between the corresponding memory banks 410-1 to 410-B and the memory bank sharing circuit system 504. By locating the address recording circuit 126 in a central location between the detection circuits 124-1 through 124-B, it is easier to route signals between the address recording circuit 126 and the detection circuits 124-1 through 124-B. Figure 6 The operations of the detection circuit 124 and the address recording circuit 126 are further described.

[0073] Figure 6 An example of a usage-based disturbed data repair circuit system 122 coupled to a mode register 214 is illustrated. Figure 6 2 is depicted as a single register, but other implementations of mode register 214 may include more than one mode register.

[0074] In the depicted configuration, usage-based disturbed data repair circuitry 122 includes detection circuits 124-1 through 124-B and address recording circuit 126 coupled to pattern register 214. Figure 6 1. Although not explicitly shown in FIG. 1, the detection circuit 124 and / or the address recording circuit 126 may be coupled to other components of the memory device, examples of which are related to Figures 7 to 11 describe.

[0075] The usage-based disturbed data repair circuitry 122 also includes an interface 602 coupled between the detection circuits 124-1 to 124-B and the address recording circuit 126. In general, the interface 602 provides a means for communication between components at the local memory bank stage 128 (e.g., one of the detection circuits 124-1 to 124-B) and components at the multi-memory bank stage 130 (e.g., the address recording circuit 126). Figures 7 to 11 Various implementations of interface 602 are further described.

[0076] During operation, the detection circuits 124-1 to 124-B generate control signals 604-1 to 604-B, respectively. The control signals 604-1 to 604-B indicate at least whether the respective detection circuit 124-1 to 124-B detects the occurrence of erroneous usage-based disturb data 218 within the corresponding memory bank 410-1 to 410-B.

[0077] Interface 602 generates composite control signal 606 based on control signals 604-1 to 604-B. Composite control signal 606 represents some combination of local bank address recording control signals 604-1 to 604-B. Using composite control signal 606, interface 602 can pass information provided by any of control signals 604-1 to 604-B to address recording circuit 126.

[0078] The address recording circuit 126 may provide an address 608 and / or an error detection flag 610 to the mode register 214 based on the composite control signal 606. The address 608 represents at least one of the addresses 304 associated with the erroneous usage-based interference data 218 determined by the detection circuits 124-1 to 124-B. The error detection flag 610 indicates whether the erroneous usage-based interference data 218 has been detected. In one example implementation, the error detection flag 610 represents a flag dedicated to detecting an error (fault / error) associated with the usage-based interference data 218. In another example implementation, the error detection flag 610 is implemented using another flag or signal that already exists within the memory device 108. For example, the error detection flag 610 may be implemented using a reliability, availability, and serviceability (RAS) event signal or another alarm signal. The error detection flag 610 may also be referred to as an error flag, a parity flag, an activation count error flag, an activation count parity flag, and the like.

[0079] The mode register 214 stores the address 608 and / or the error detection flag 610. In some cases, the mode register 214 includes two registers that store the address 608 and the error detection flag 610, respectively. In another case, the module register 214 includes one register that stores both the address 608 and the error detection flag 610. The memory controller 114 may initiate one or more repair procedures based on the address 608 and / or the error detection flag 610 stored by the mode register 214. In some implementations, the memory controller 114 may clear the error detection flag 610 after initiating the repair procedure. Based on the use of the disturbed data repair circuitry 122, the direct or indirect address recording may be performed, such as with respect to the respective Figure 7 and 8 Further description.

[0080] Figure 7 An example implementation of a usage-based disturbing data repair circuitry 122 that performs address logging directly at the local memory bank level 128 as indicated at 700 is illustrated. In the depicted configuration, the control signal 604 indicates an address 608 associated with the erroneous usage-based disturbing data 218. In this example, the usage-based disturbing data repair circuitry 122 may be coupled to the usage-based disturbing circuitry 120. This coupling enables the detection circuits 124-1 to 124-B to operate during an array counter update procedure, as further described below.

[0081] To communicate the address 608 from the local bank stage 128 to the multi-bank stage 130, the interface 602 may be implemented using at least one internal bus 702 or at least one scan chain 704. The interface 602 may also include a conflict resolution circuit 706 that may resolve conflicts in which at least two detection circuits 124 detect occurrences of erroneous usage-based interference data 218 during the same time interval.

[0082] During operation, the usage-based disturbance circuitry 120 performs an array counter update procedure on the activation row. As part of the array counter update procedure, the usage-based disturbance circuitry 120 or the detection circuits 124-1 to 124-B perform an error detection test to detect errors associated with the usage-based disturbance data 218 (e.g., perform a parity check to detect a parity bit error associated with the activation count 308). If an error is detected, the detection circuit 124 associated with the memory bank 410 in which the error occurred determines an address 608 associated with the detected error. For example, the detection circuit 124-1 determines that the address 608-1 is associated with an error and / or the detection circuit 124-B determines that the address 608-B is associated with an error. The detection circuits 124-1 to 124-B communicate the addresses 608-1 to 608-B to the address recording circuit 126 using the control signals 604-1 to 604-B.

[0083] While direct address logging 700 is capable of logging the address 608 associated with erroneous usage-based disturbing data 218 during an array counter update procedure and enabling such address 608 to be stored in the mode register 214 with minimal delay, direct address logging 700 may increase the complexity and / or layout penalty associated with implementing the interface 602. This may increase the cost and / or size of the memory device 108. Alternatively, other embodiments of the usage-based disturbing data repair circuitry 122 may perform indirect address logging, such as with respect to FIG. Figure 8 Further description.

[0084] Figure 8An example implementation of a usage-based disturbed data repair circuitry 122 is illustrated that performs address recording at a multi-bank stage 130 indirectly as indicated at 800 with the assistance of an engine 216. The engine 216 may be an existing engine 216 within a memory device 108 that performs other functions not associated with usage-based disturb mitigation. In this case, the engine 216 accesses rows 302 within a memory array 204 in a controlled manner or in a particular sequence. The information provided by the detection circuits 124-1 to 124-B via control signals 604-1 to 604-B is based on or dependent on the row 302 being accessed by the engine 216. More specifically, if an address 608 associated with an error is related to a row 302 accessed by the engine 216, the detection circuits 124-1 to 124-B report the error using the control signals 604-1 to 604-B. This dependency enables the address recording circuitry 126 to determine the address 608 of an error at the multi-bank stage 130 based on the row 302 accessed by the engine 216, without routing the address 608 from the local bank stage 128 to the multi-bank stage 130. This controlled approach also avoids conflicts that would otherwise occur when multiple errors occur across multiple banks 410 during the same time interval. In general, the indirect address recording 800 utilizes the engine 216 to provide a controlled approach to recording the address of the usage-based disturbing data 218 having errors at the multi-bank stage 130.

[0085] In the depicted configuration, the address recording circuit 126 is coupled to the engine 216. Depending on the implementation, the detection circuit 124-1 to 124-B may be coupled to the usage-based interference circuit system 120, the engine 216, or both. An example implementation of the detection circuit 124 may include at least one error detection circuit 802 and / or at least one address comparator 804. The interface 602 may include at least one logic gate 806. The logic gate 806 may be implemented at the local memory bank level 128 and generate a composite control signal 606 based on the control signals 604-1 to 604-B. The address recording circuit 126 may include at least one latch circuit 808, which may latch information provided by the engine 216 based on the composite control signal 606. Figures 9 to 11 Example implementations of detection circuit 124, interface 602, and address recording circuit 126 are further described.

[0086] During operation, the engine 216 performs operations on the rows 302 of the memory array 204. The engine 216 controls or determines the sequence in which the rows 302 are accessed. The address recording circuit 126 is coupled to the engine 216 and receives information about the addresses 810 accessed by the engine 216. The address recording circuit 126 may latch the addresses 810 at the multi-bank stage 130 based on the composite control signal 606 indicating the occurrence of an error.

[0087] The detection circuits 124-1 to 124-B may determine the occurrence of an error in different ways. In a first example implementation, the detection circuits 124-1 to 124-B perform an error detection test based on the occurrence of the engine 216 accessing the address 810. In this case, the error detection test is performed on the rows 302 in the same order as the engine 216 accesses the rows 302. In a second example implementation, the error detection test is performed by the usage-based interference circuitry 120 or the detection circuits 124-1 to 124-B as part of or based on the occurrence of an array counter update procedure (or more generally, a procedure to update the usage-based interference data 218). The detection circuits 124-1 to 124-B store information associated with the detected error and provide this information when the address 608 of the detected error matches the address 810 accessed by the engine 216. With regard to Fig. 9 A first example implementation of detection circuits 124 - 1 through 124 -B is further described.

[0088] Fig. 9 A first example implementation of detection circuits 124-1 through 124-B for indirect address recording 800 is illustrated. In the depicted configuration, interface 602 is implemented using logic gate 806, which is depicted as OR gate 902. The inputs of OR gate 902 are coupled to the outputs of detection circuits 124-1 through 124-B. Address recording circuit 126 includes latch circuit 808, which is coupled to interface 602 and engine 216.

[0089] The detection circuits 124-1 to 124-B include error detection circuits 802-1 to 802-B, respectively. The error detection circuits 802-1 to 802-B are coupled to the engine 216 and perform error detection testing to detect erroneous usage-based interference data 218. However, the manner in which the error detection testing is performed across the rows 302 depends on the manner in which the engine 216 accesses the rows 302, as further described below.

[0090] During operation, the engine 216 performs an operation at a particular row 302. An address 810 accessed by the engine 216 is provided to the detection circuits 124-1 through 124-B. If the address 810 is within the memory bank 410 corresponding to the detection circuit 124, then the detection circuit 124 performs an error detection test on the usage-based interference data 218 associated with the address 810. For example, the detection circuit 124 performs a parity check to evaluate the parity bit 310 associated with the activation count 308. If the address 810 is not within the memory bank 410 corresponding to the detection circuit 124, then the detection circuit 124 does not perform an error detection test.

[0091] If the detection circuit 124 determines that the usage-based interference data 218 associated with the address 810 has an error, then the detection circuit 124 indicates the detection of this error via the corresponding control signal 604. The interface 602 generates a composite control signal 606, which also indicates the detection of an error. Based on the composite control signal 606 indicating the detection of an error, the latch circuit 808 latches the address 810 provided by the engine 216. The address recording circuit 126 provides the address 810 as the address 608 to the mode register 214 (not shown). In some cases, the address recording circuit 126 provides the composite control signal 606 as an error detection flag 610.

[0092] In this example, the execution of the error detection test occurs during or after the time interval in which the engine 216 accesses the address 810. In this way, error detection and address recording are synchronized across the local memory bank level 128 and the multi-memory bank level 130 based on the address 810 accessed by the engine 216. In other embodiments, error detection may occur before the engine 216 accesses the address 810, such as with respect to Fig.10 Further description.

[0093] Fig.10 A second example implementation of detection circuits 124-1 to 124-B for indirect address recording 800 is illustrated. In the depicted configuration, detection circuits 124-1 to 124-B include address comparators 804-1 to 804-B, respectively. Address comparators 804-1 to 804-B are coupled to engine 216 and usage-based interference circuitry 120. Address comparators 804-1 to 804-B may each include at least one comparator 1002 and at least one content addressable memory (CAM) 1004. Comparator 1002 enables the results of an error detection test to be reported in a manner that depends on the manner in which engine 216 accesses row 302, as further described below. Content addressable memory 1004 stores information about usage-based interference data 218 that has errors. In some implementations, content addressable memory 1004 may store one address 608 determined to have usage-based interference data 218 that has errors. In other embodiments, the content addressable memory 1004 may store the plurality of addresses 608 determined to have erroneous usage-based interference data 218 .

[0094] During operation, the usage-based interference circuitry 120 performs an array counter update procedure. As part of the array counter update procedure or based on the occurrence of the array counter update procedure, the usage-based interference circuitry 120 or the detection circuits 124-1 to 124-B perform an error detection test to detect erroneous usage-based interference data 218. If erroneous usage-based interference data 218 is detected, then the address 608 of the erroneous usage-based interference data 218 is stored in the content addressable memory 1004 of the address comparator 804.

[0095] After executing the array counter update procedure, the engine 216 accesses the address 810. The comparator 1002 of the address comparators 804-1 to 804-B compares the address 810 with the addresses 608-1 to 608-B stored in the content addressable memory 1004. Consider an example in which the address 810 is the address 608-1 stored by the address comparator 804-1. In this case, the comparator 1002 of the detection circuit 124-1 determines that the address 810 matches the address 608-1 and generates the control signal 604-1 in a manner indicating the detection of the erroneous usage-based interference data 218. The interface 602 generates the composite control signal 606, which also indicates the detection of the error. Based on the composite control signal 606 indicating the detection of the error, the latch circuit 808 latches the address 810 provided by the engine 216. The address recording circuit 126 provides the address 810 as the address 608 to the mode register 214 (not shown). In some cases, address recording circuit 126 provides composite control signal 606 as error detection flag 610 .

[0096] In this example, the execution of the error detection test occurs prior to the time interval in which the engine 216 accesses the address 810. Although the error detection and address recording may occur at different time intervals, the reporting of the error detection and address recording is synchronized across the local memory bank stage 128 and the multi-memory bank stage 130 based on the address 810 accessed by the engine 216. In other implementations, the detection circuits 124-1 to 124-B may include both the error detection circuit 802 and the address comparator 804, as described with respect to FIG. Fig.11 Further description.

[0097] Fig.11 A third example implementation of detection circuits 124-1 to 124-B is illustrated. In the depicted configuration, detection circuits 124-1 to 124-B include error detection circuits 802-1 to 802-B, address comparators 804-1 to 804-B, and optional OR gates 1102-1 to 1102-B, respectively. The operation of error detection circuits 802-1 to 802-B is similar to that described with respect to Fig. 9 The operation of the address comparators 804-1 to 804-B is similar to that described with respect to Fig.10 Describes the operation.

[0098] This implementation of the detection circuits 124-1 to 124-B provides additional opportunities for error detection testing to be performed, and thus enables the usage-based disturbing data repair circuitry 122 to more quickly detect erroneous usage-based disturbing data 218. For example, the error detection circuits 802-1 to 802-B can detect erroneous usage-based disturbing data 218 based on the occurrence of the engine 216 accessing the row, while the address comparators 804-1 to 804-B can detect erroneous usage-based disturbing data 218 based on the occurrence of the array counter update procedure. Figures 8 to 11 As seen in FIG. 1 , the indirect address record 800 enables the memory device 108 to be implemented with a less complex interface 602 and to be more efficient than the memory device 108. Figure 7 The indirect address record 800 also avoids conflict resolution by controlling the reporting of errors based on the order in which the engines 216 access the rows 302.

[0099] Instance Methods

[0100] References in this chapter Fig.12 The flowchart of describes an example method for implementing the aspect of recording memory addresses associated with erroneous usage-based interference data. These descriptions may also refer to the example only in Figures 1 to 11 The components, entities and other aspects depicted in the description are not necessarily limited to being performed by one entity or multiple entities operating on one device.

[0101] Fig.12 Method 1200 is described, which includes operations 1202 to 1208. In one aspect, the operations of method 1200 are described by reference to Figure 1 108 is described. At 1202, data associated with usage-based interference is stored in a subset of memory cells of a row. For example, row 302 stores usage-based interference data 218 in a subset of memory cells. The usage-based interference data 218 is accessible by the usage-based interference circuitry 120 and used to mitigate usage-based interference. In an example embodiment, the usage-based interference data 218 represents an activation count 308. In some embodiments, the host device 104 (e.g., the memory controller 114) cannot access the usage-based interference data 218.

[0102] At 1204, the row is accessed using an engine. For example, the engine 216 accesses the row 302. The engine 216 can access the row and perform operations on the normal data 306 stored in another subset of the memory cells of the row 302. In an example embodiment, the engine 216 is implemented as an error checking and scrubbing engine that can detect errors within the normal data 306. In some embodiments, the engine 216 does not directly perform operations associated with usage-based interference mitigation or does not perform operations on the usage-based interference data 218.

[0103] Generally speaking, the engine 216 is able to access all rows 302 within the memory array 204. This enables techniques associated with indirect address logging 800 to report occurrences of errors associated with usage-based interference data 218 in a controlled manner that avoids conflicts across multiple memory banks 410.

[0104] At 1206, an occurrence of an error associated with the data stored within the row is detected at a local bank level of the memory device. For example, the usage-based interference data repair circuitry 122 detects an occurrence of an error associated with the usage-based interference data 218 stored within the row 302 at the local bank level. In some implementations, the usage-based interference data repair circuitry 122 may directly detect the error by performing an error detection test at the local bank level. The error detection test may be performed based on the occurrence of a program executed by the usage-based interference circuitry 120 to update the usage-based interference data 218 and / or based on the occurrence of the engine 216 accessing the row 302. In other implementations, the usage-based interference circuitry 120 may directly detect the error by performing an error detection test and provide an indication to the usage-based interference data repair circuitry 122 when an error is detected.

[0105] At 1208, the address of the row is recorded at the multi-bank stage of the memory device based on the row being accessed by the engine and based on detecting an error occurrence. For example, based on the row 302 being accessed by the engine 216 and based on detecting an error occurrence (which is reported from (or indicated by) the local bank stage 128 to the multi-bank stage 130), the usage-based disturbed data repair circuitry 122 records the address 608 of the row 302 at the multi-bank stage 130 of the memory device 108. In particular, the usage-based disturbed data repair circuitry 122 may latch the address 810 accessed by the engine 216 based on the local bank stage 128 indicating an occurrence of an error associated with the address 810. The usage-based disturbed data repair circuitry 122 may store the latched address 608 and / or the error detection flag 610 in one or more mode registers 214 accessible by the host device 104. With this information, host device 104 may initiate a repair procedure that resolves the detected errors associated with usage-based interference data 218 stored within row 302 .

[0106] For the above figures, the order in which the operations are shown and / or described is not intended to be construed as limiting. Any number or combination of the described process operations can be combined or rearranged in any order to implement a given method or an alternative method. Operations can also be omitted from or added to the described methods. In addition, the described operations can be implemented in a completely or partially overlapping manner.

[0107] Aspects of this method may be implemented, for example, in hardware (eg, fixed circuitry or a processor in combination with a memory), firmware, software, or some combination thereof. The method may be implemented using Figures 1 to 11 The present invention is implemented by one or more of the devices or components shown in the figure, and its components can be further divided, combined, rearranged, etc. The devices and components of these figures generally represent: hardware, such as electronic devices, package modules, IC chips or circuits; firmware or its actions; software; or a combination thereof. Therefore, these figures illustrate some of the many possible systems or devices that can implement the described methods.

[0108] Computer-readable media includes both non-transitory computer storage media and communication media, including any media that facilitates the transfer of computer programs (such as applications) or data from one entity to another. Non-transitory computer storage media can be any available media that can be accessed by a computer, such as RAM, ROM, flash, EEPROM, optical media, and magnetic media.

[0109]

[0013] In the following, various examples for implementing aspects of recording memory addresses associated with erroneous usage-based interference data are described.

[0110] Example 1: A device comprising:

[0111] A memory device comprising:

[0112] at least one memory bank comprising a plurality of rows of memory cells, each row of the plurality of rows being configured to store data associated with usage-based interference within a subset of the memory cells;

[0113] an engine configured to access the plurality of rows of the at least one memory bank; and

[0114] a circuit system coupled to the engine and the at least one memory bank, the circuit system being configured to:

[0115] detecting an occurrence of an error associated with the stored data within a row of the plurality of rows; and

[0116] The address of the row is recorded based on the row being accessed by the engine and based on detecting that the error occurred.

[0117] Example 2: The apparatus of example 1 or any other example, wherein the circuit system comprises:

[0118] at least one first circuit coupled to the at least one memory bank and implemented at a local memory bank level, the at least one first circuit configured to report detection of the error occurrence based on the row being accessed by the engine; and

[0119] A second circuit, coupled to the at least one first circuit and implemented at a multi-bank level, is configured to latch the address of the row accessed by the engine based on the report provided by the first circuit.

[0120] Example 3: The apparatus of example 2 or any other example, wherein:

[0121] The at least one memory bank comprises a plurality of memory banks;

[0122] The at least one first circuit includes a plurality of first circuits respectively coupled to the plurality of memory banks; and

[0123] The circuit system includes logic gates coupled between the plurality of first circuits and the second circuit.

[0124] Example 4: The apparatus of example 1 or any other example, wherein the circuitry is configured to detect the occurrence of the error before the engine accesses the row.

[0125] Example 5: The apparatus of example 4 or any other example, wherein:

[0126] The memory device includes other circuitry configured to execute a program to update the data stored in the row; and

[0127] The circuit system is configured to:

[0128] storing the address of the row based on detecting the error associated with the data by an error detection test, the error detection test being performed based on occurrence of the program; and

[0129] The detection of the occurrence of the error is reported from a local bank level to a multi-bank level based on the memory address matching the address of the row accessed by the engine.

[0130] Example 6: The apparatus of example 1 or any other example, wherein the circuitry is configured to detect the occurrence of the error during or after the engine accesses the row.

[0131] Example 7: The apparatus of example 6 or any other example, wherein the circuitry is configured to perform an error detection test based on the engine accessing the row to detect the occurrence of the error.

[0132] Example 8: The apparatus of example 1 or any other example, wherein:

[0133] The memory device includes at least one mode register; and

[0134] The circuit system is configured to:

[0135] storing the recorded address in the at least one mode register; and

[0136] A flag is set within the at least one mode register to indicate the occurrence of the error.

[0137] Example 9: The apparatus of example 8 or any other example, wherein:

[0138] The memory device is configured to be coupled to a memory controller; and

[0139] The flag causes the memory controller to initiate a process to repair the row associated with the recorded address.

[0140] Example 10: The apparatus of example 1 or any other example, wherein the data associated with usage-based interference includes an activation count representing a number of times a corresponding row has been accessed since a last refresh.

[0141] Example 11: The apparatus of example 1 or any other example, wherein:

[0142] The data associated with usage-based interference includes parity bits; and

[0143] The circuitry is configured to detect the occurrence of the error based on a parity check.

[0144] Example 12: The apparatus of example 1 or any other example, wherein:

[0145] Each row of the plurality of rows is configured to store other data associated with normal memory operations within a second subset of the memory cells; and

[0146] The engine is configured to perform operations on the other data.

[0147] Example 13: The apparatus of example 12 or any other example, wherein the engine comprises an error checking and scrubbing engine configured to perform error detection on the other data.

[0148] Example 14: A method performed by a memory device, the method comprising:

[0149] storing data associated with the usage-based interference in a subset of the memory cells of the row;

[0150] Using an engine to access the row;

[0151] detecting, at a local bank level of the memory device, an occurrence of an error associated with the data stored within the row; and

[0152] An address of the row is recorded at a multi-bank level of the memory device based on the row being accessed by the engine and based on detecting the error occurring.

[0153] Example 15: The method according to example 14 or any other example, further comprising:

[0154] Detection of the error occurrence is reported from the local bank level to the multi-bank level based on the row being accessed by the engine.

[0155] Example 16: The method according to example 14 or any other example, further comprising:

[0156] An error detection test is performed on the data stored in the row to detect the error based on at least one of:

[0157] the occurrence of a procedure to update said data stored in said row; or

[0158] The engine accesses the row.

[0159] Example 17: A device comprising:

[0160] A memory device comprising:

[0161] at least one memory bank comprising a plurality of rows of memory cells, each row of the plurality of rows being configured to store data associated with usage-based interference within a subset of the memory cells;

[0162] an engine configured to access the plurality of rows of the at least one memory bank; and

[0163] A circuit system comprising:

[0164] at least one first circuit coupled to the at least one memory bank and implemented at a local memory bank level, the at least one first circuit configured to report detection of an occurrence of an error associated with the data stored within a row of the plurality of rows based on the engine accessing the row; and

[0165] A second circuit coupled to the engine and the at least one first circuit is implemented at a multi-bank level and is configured to latch an address of the row accessed by the engine based on the report detection provided by the at least one first circuit.

[0166] Example 18: The apparatus of example 17 or any other example, wherein the at least one first circuit is configured to:

[0167] performing an error detection test on the data of the row based on the engine accessing the row; and

[0168] The occurrence of the error is detected based on the error detection test.

[0169] Example 19: The apparatus of example 17 or any other example, wherein:

[0170] The memory device includes other circuitry configured to execute a program to update the data stored in the row; and

[0171] The at least one first circuit is configured to:

[0172] storing the address of the row based on detecting the error associated with the data by an error detection test, the error detection test being performed based on the program; and

[0173] The detection of the occurrence of the error is reported to the second circuit based on the memory address matching the address of the row accessed by the engine.

[0174] Example 20: The apparatus of example 17 or any other example, wherein:

[0175] The memory device includes other circuitry configured to execute a program to update the data stored in the row; and

[0176] The at least one first circuit is configured to detect the erroneous

[0177] occur:

[0178] a first error detection test performed based on said other circuitry executing said program on said row;

[0179] or

[0180] A second error detection test is performed based on the engine accessing the row.

[0181] Unless the context dictates otherwise, the use of the word "or" herein may be considered to be use of an "inclusive or" or a term that allows inclusion or application of one or more items linked together by the word "or" (e.g., the phrase "A or B" may be interpreted as allowing only "A", only "B", or both "A" and "B"). In addition, as used herein, a phrase referring to "at least one of" a list of items refers to any combination of the items, including single members. For example, "at least one of a, b, or c" may encompass a, b, c, ab, ac, bc, and abc, as well as any combination with multiple of the same element (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other ordering of a, b, and c). In addition, the items represented in the drawings and the terms discussed herein may indicate one or more items or terms, and thus the singular or plural forms of the items and terms may be referred to interchangeably in this written description.

[0182] in conclusion

[0183] Although aspects of recording memory addresses associated with erroneous usage-based interference data have been described in language specific to certain features and / or methods, the subject matter of the appended claims is not necessarily limited to the specific features or methods described. Rather, the specific features and methods are disclosed as various example implementations of recording memory addresses associated with erroneous usage-based interference data.

Claims

1. A device comprising: A memory device comprising: at least one memory bank comprising a plurality of rows of memory cells, each row of the plurality of rows being configured to store data associated with usage-based interference within a subset of the memory cells; an engine configured to access the plurality of rows of the at least one memory bank; and a circuit system coupled to the engine and the at least one memory bank, the circuit system being configured to: detecting an occurrence of an error associated with the stored data within a row of the plurality of rows; and The address of the row is recorded based on the row being accessed by the engine and based on detecting that the error occurred.

2. The apparatus of claim 1 , wherein the circuit system comprises: at least one first circuit coupled to the at least one memory bank and implemented at a local memory bank level, the at least one first circuit configured to report detection of the error occurrence based on the row being accessed by the engine; and A second circuit, coupled to the at least one first circuit and implemented at a multi-bank level, is configured to latch the address of the row accessed by the engine based on the report provided by the first circuit.

3. The apparatus according to claim 2, wherein: The at least one memory bank comprises a plurality of memory banks; The at least one first circuit includes a plurality of first circuits respectively coupled to the plurality of memory banks; and The circuit system includes logic gates coupled between the plurality of first circuits and the second circuit.

4. The apparatus of claim 1, wherein the circuitry is configured to detect the occurrence of the error before the engine accesses the row.

5. The apparatus according to claim 4, wherein: The memory device includes other circuitry configured to execute a program to update the data stored in the row; and The circuit system is configured to: storing the address of the row based on detecting the error associated with the data by an error detection test, the error detection test being performed based on an occurrence of the program; and The detection of the occurrence of the error is reported from a local bank level to a multi-bank level based on the memory address matching the address of the row accessed by the engine.

6. The apparatus of claim 1, wherein the circuitry is configured to detect the occurrence of the error during or after the engine accesses the row.

7. The apparatus of claim 6, wherein the circuitry is configured to perform an error detection test based on the engine accessing the row to detect the occurrence of the error.

8. The apparatus of claim 1, wherein: The memory device includes at least one mode register; and The circuit system is configured to: storing the recorded address in the at least one mode register; and A flag is set within the at least one mode register to indicate the occurrence of the error.

9. The apparatus of claim 8, wherein: The memory device is configured to be coupled to a memory controller; and The flag causes the memory controller to initiate a process to repair the row associated with the recorded address.

10. The apparatus of claim 1, wherein the data associated with usage-based interference comprises an activation count representing a number of times a corresponding row has been accessed since a last refresh.

11. The apparatus of claim 1, wherein: The data associated with usage-based interference includes parity bits; and The circuitry is configured to detect the occurrence of the error based on a parity check.

12. The apparatus of claim 1, wherein: Each row of the plurality of rows is configured to store other data associated with normal memory operations within a second subset of the memory cells; and The engine is configured to perform operations on the other data.

13. The apparatus of claim 12, wherein the engine comprises an error checking and scrubbing engine configured to perform error detection on the other data.

14. A method performed by a memory device, the method comprising: storing data associated with the usage-based interference in a subset of the memory cells of the row; Using an engine to access the row; detecting, at a local bank level of the memory device, an occurrence of an error associated with the data stored within the row; and An address of the row is recorded at a multi-bank level of the memory device based on the row being accessed by the engine and based on detecting the error occurring.

15. The method according to claim 14, further comprising: Detection of the error occurrence is reported from the local bank level to the multi-bank level based on the row being accessed by the engine.

16. The method according to claim 14, further comprising: An error detection test is performed on the data stored in the row to detect the error based on at least one of: the occurrence of a procedure to update said data stored in said row; or The engine accesses the row.

17. An apparatus comprising: A memory device comprising: at least one memory bank comprising a plurality of rows of memory cells, each row of the plurality of rows being configured to store data associated with usage-based interference within a subset of the memory cells; an engine configured to access the plurality of rows of the at least one memory bank; and A circuit system comprising: at least one first circuit coupled to the at least one memory bank and implemented at a local memory bank level, the at least one first circuit configured to report detection of an occurrence of an error associated with the data stored within a row of the plurality of rows based on the engine accessing the row; and A second circuit coupled to the engine and the at least one first circuit is implemented at a multi-bank level and is configured to latch an address of the row accessed by the engine based on the report detection provided by the at least one first circuit.

18. The apparatus of claim 17, wherein the at least one first circuit is configured to: performing an error detection test on the data of the row based on the engine accessing the row; and The occurrence of the error is detected based on the error detection test.

19. The apparatus of claim 17, wherein: The memory device includes other circuitry configured to execute a program to update the data stored in the row; and The at least one first circuit is configured to: storing the address of the row based on detecting the error associated with the data by an error detection test, the error detection test being performed based on the program; and The detection of the occurrence of the error is reported to the second circuit based on the memory address matching the address of the row accessed by the engine.

20. The apparatus of claim 17, wherein: The memory device includes other circuitry configured to execute a program to update the data stored in the row; and The at least one first circuit is configured to detect the occurrence of the error based on at least one of: a first error detection test performed based on said other circuitry executing said program on said row; or A second error detection test is performed based on the engine accessing the row.

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