Multi-segment storage method and device for working parameters of chip, equipment and medium

Abstract

The invention discloses a multi-segment storage method and device for working parameters of a chip, equipment and a medium, and belongs to the technical field of electronic information. The method comprises the following steps: when a target working parameter storage event is identified, reading a current numerical value from a storage address indication area to determine a storage area of a current working parameter; determining an initial address for storing the target working parameter according to a storage area of the current working parameter; determining a target storage area of a target working parameter according to the initial address and the preset number of bytes, and writing the target working parameter into the target storage area; and updating the current numerical value in the storage address indication area. According to the technical scheme, multi-segment storage and construction of an address mapping mechanism can enable the working parameters of the chip to support adjustment, and the actual use requirements of the chip are met.

Description

Technical Field

[0001] The present application belongs to the field of electronic information technology, and specifically relates to a multi-segment storage method, device, equipment and medium for chip working parameters. Background Art

[0002] With the vigorous development of science and technology, the gradual expansion of the consumer electronics and wearable device markets, electronic devices will be used in a variety of environments, so the use scenarios of chips are also gradually increasing.

[0003] In many integrated circuits, especially those that require high precision and reliability, the chip's operating parameters, such as voltage and clock frequency, need to be adjusted, that is, the chip's TRIM value needs to be adjusted. However, traditional OTP (One-Time Programmable) chips can usually only write data once, which makes them unable to flexibly support dynamic adjustment or update of TRIM values.

[0004] Therefore, how to achieve flexible adjustment of the working parameters of the chip and ensure the availability of the chip is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0005] The embodiments of the present application provide a method, device, equipment and medium for multi-segment storage of the working parameters of a chip, with the aim of enabling the working parameters of the chip to be adjusted to meet the actual usage requirements of the chip through the construction of multi-segment storage and address mapping mechanism.

[0006] In a first aspect, an embodiment of the present application provides a multi-segment storage method for working parameters of a chip, wherein the chip is provided with a storage address indication area and at least two storage areas, each storage area being composed of a preset number of bytes; the method comprises:

[0007] When a target operating parameter storage event is identified, a current value is read from the storage address indication area to determine a storage area of ​​the current operating parameter;

[0008] Determining a starting address for storing the target operating parameters according to a storage area of ​​the current operating parameters;

[0009] Determine a target storage area for target operating parameters according to the starting address and the preset number of bytes, and write the target operating parameters into the target storage area;

[0010] The current value in the storage address indication area is updated.

[0011] Furthermore, the method further comprises:

[0012] Get the actual byte length of the chip's working parameters;

[0013] According to the actual byte length, a preset number of bytes for dividing at least two storage areas is determined.

[0014] Further, reading the current value from the storage address indication area to determine the storage area of ​​the current working parameter includes:

[0015] Read the number written as the target value from the lower bit to the higher bit in the storage address indication area to obtain the current value;

[0016] According to the pre-constructed mapping relationship, the storage area corresponding to the current value is parsed to obtain the storage area of ​​the current working parameter.

[0017] Furthermore, the initial value of each bit in the storage address indication area is 0, and the target value is 1.

[0018] Further, updating the current value in the storage address indication area includes:

[0019] The higher bit of the highest bit that is rewritten as the target value in the storage address indication area is obtained and the initial value is rewritten as the target value.

[0020] Furthermore, the method further comprises:

[0021] In the storage address indication area, setting the value of each bit to an initial value;

[0022] When the initial value on each bit is rewritten as the target value, a mapping relationship between the read value of the storage address indication area and the storage area is established.

[0023] Furthermore, the method further comprises:

[0024] When it is identified that the current value in the storage address indication area is updated to the maximum reading in the storage address indication area, the storage address indication area is extended to obtain an extended indication area;

[0025] A mapping relationship between the extension indication area and the multiple storage areas obtained by extension is established.

[0026] In a second aspect, an embodiment of the present application provides a multi-segment storage device for working parameters of a chip, wherein the chip is provided with a storage address indication area and at least two storage areas, each storage area being composed of a preset number of bytes; the device comprises:

[0027] A current value reading module, used to read the current value from the storage address indication area to determine the storage area of ​​the current working parameter when a target working parameter storage event is identified;

[0028] A storage start address determination module, used to determine the start address for storing the target operating parameter according to the storage area of ​​the current operating parameter;

[0029] A target storage area determination module, used to determine a target storage area for a target operating parameter according to the start address and the preset number of bytes, and write the target operating parameter into the target storage area;

[0030] The current value updating module is used to update the current value in the storage address indication area.

[0031] In a third aspect, an embodiment of the present application provides an electronic device, which includes a processor, a memory, and a program or instruction stored in the memory and executable on the processor, wherein the program or instruction, when executed by the processor, implements the steps of the method described in the first aspect.

[0032] In a fourth aspect, an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the steps of the method described in the first aspect are implemented.

[0033] In a fifth aspect, an embodiment of the present application provides a chip, comprising a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run a program or instruction to implement the method described in the first aspect.

[0034] In an embodiment of the present application, when a target working parameter storage event is identified, the current value is read from the storage address indication area to determine the storage area of ​​the current working parameter; based on the storage area of ​​the current working parameter, the starting address for storing the target working parameter is determined; based on the starting address and the preset number of bytes, the target storage area of ​​the target working parameter is determined, and the target working parameter is written into the target storage area; the current value in the storage address indication area is updated. This technical solution, the construction of multi-segment storage and address mapping mechanism, can enable the chip's working parameters to support adjustment, meeting the actual use requirements of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a flowchart of a multi-segment storage method for chip working parameters provided in an embodiment of the present application;

[0036] Figure 2 is a schematic diagram of TRIM value storage provided in an embodiment of the present application;

[0037] Figure 3 It is a schematic diagram of the structure of a multi-segment storage device for chip working parameters provided in an embodiment of the present application;

[0038] Figure 4 It is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical scheme and advantages of the present application clearer, the specific embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. It is understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for the convenience of description, only the part related to the present application but not all the contents are shown in the accompanying drawings. Before discussing the exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flow charts. Although the flow chart describes each operation (or step) as a sequential process, many of the operations therein can be implemented in parallel, concurrently or simultaneously. In addition, the order of each operation can be rearranged. The process can be terminated when its operation is completed, but it can also have additional steps not included in the accompanying drawings. The process can correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.

[0040] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0041] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0042] In conjunction with the accompanying drawings, the multi-segment storage method, device, equipment and medium of the chip working parameters provided in the embodiments of the present application are described in detail through specific embodiments and their application scenarios.

[0043] Figure 1 It is a flow chart of the multi-segment storage method of the chip working parameters provided in the embodiment of the present application.

[0044] Wherein, the chip is provided with a storage address indication area and at least two storage areas, each storage area is composed of a preset number of bytes; Figure 1 As shown, the specific steps include:

[0045] S101, when a target operating parameter storage event is identified, reading a current value from the storage address indication area to determine a storage area of ​​the current operating parameter;

[0046] The interior of the chip can be divided into a storage address indication area and multiple storage areas, each storage area can be used to store working parameters. For example, when the working parameters need to be iterated, the updated working parameters can be stored in the next storage area of ​​the current storage area, and the updated working parameters can be used to update the working parameters of the chip.

[0047] In this solution, when a target operating parameter storage event occurs, it can be determined that a target operating parameter storage event exists when a target parameter storage request is identified. For example, when a staff member queries the storage area of ​​the current operating parameters of the chip through a tool and applies for a new storage area for the target operating parameters, it can be determined that a target operating parameter storage event exists.

[0048] The storage address indication area is used to store the current value, which is associated with the storage area of ​​the current working parameter. The storage area of ​​the current working parameter can be determined based on the association relationship and the size of the current value, and the next area of ​​the area is used as the storage area of ​​the target working parameter.

[0049] Among them, the association rules used to determine the storage area of ​​the current working parameters can be pre-set. For example, when the chip leaves the factory or is used for the first time, the storage location of the TRIM value is indicated by the first storage address. The 0x1000 address is used as the storage address indication area, and its initial value is 0. When it is used for the first time, the address is written to 1. The programmer writes the TRIM value to the area of ​​4 bytes starting from the 0x1020 address based on the byte information, that is, the data 1 in the 0x1000 address corresponds to the TRIM value in the 0x1020 address, that is, when the current value is 1, the area of ​​4 bytes starting from the 0x1020 address is determined as the storage area of ​​the current working parameters. Among them, 4 bytes are the preset number of bytes.

[0050] S102, determining a starting address for storing the target operating parameters according to a storage area of ​​the current operating parameters;

[0051] After the storage area of ​​the current working parameters is determined, the starting address of the next storage area can be determined according to its starting position and a preset number of bytes.

[0052] Specifically, each time a new TRIM value is stored, the system checks the indicated area of ​​the storage unit to decide where to store the new data. First, check whether it is 1 from the low bit, and then proceed to the high bit until 0 is detected, and then change the bit to 1. For example, when reading the 0x1000 address, if only bit0 is 1 in the data, and bit1 and above are all 0, it means that the current TRIM value is stored at the 0x1020 address, and the target working parameters need to be stored backward to 0x1024. At the same time, the data bit1 in the 0x1000 address needs to be changed from 0 to 1.

[0053] S103, determining a target storage area for target operating parameters according to the starting address and the preset number of bytes, and writing the target operating parameters into the target storage area;

[0054] After the start address of the target operating parameter is obtained, the entire target storage area used to store the target operating parameter can be determined according to the start address and a preset number of bytes.

[0055] After the target storage area is determined, the target operating parameters may be written into the target storage area.

[0056] In this embodiment, optionally, reading the current value from the storage address indication area to determine the storage area of ​​the current working parameter includes:

[0057] Read the number written as the target value from the lower bit to the higher bit in the storage address indication area to obtain the current value;

[0058] According to the pre-constructed mapping relationship, the storage area corresponding to the current value is parsed to obtain the storage area of ​​the current working parameter.

[0059] Among them, the writing of the value of the storage address indication area can be performed in order from low to high. For example, after a working parameter is stored in the first storage area, the lowest bit of the storage address indication area, that is, bit0, is rewritten from the default value to the target value. When another working parameter is stored in the second storage area, bit1 of the storage address indication area is rewritten from the default value to the target value. When another working parameter is stored in the third storage area, bit2 of the storage address indication area is rewritten from the default value to the target value, and so on.

[0060] Because the read value of the storage address indication area will change after the values ​​on different bits are written from the initial value to the target value, the association relationship between the read value and the storage area can be pre-built, so as to determine the corresponding storage area based on the current value, that is, to obtain the storage area of ​​the current working parameters. For example, when reading the 0x1000 address, if only bit0 is 1 in the data, and bits 1 and above are all 0, it means that the current TRIM value is stored at the 0x1020 address, and the newly added TRIM value needs to be stored backward to 0x1024. At the same time, the data bit1 in the 0x1000 address needs to be changed from 0 to 1, that is, 0x03 needs to be written to the 0x1000 address. Similarly, if the data read from the 0x1000 address is 0x03, bit2 needs to be changed from 0 to 1, that is, 0x07 needs to be written to the 0x1000 address, which means that the TRIM value is stored at the 0x1028 address, that is, it is determined that the TRIM value currently to be written is written to the 0x1028 storage area.

[0061] Through such a setting, the present solution can accurately parse out the storage area corresponding to the current value, and use the storage area as the basis for determining the target storage area of ​​the target operating parameter, thereby improving the flexible adjustment capability of the chip's target operating parameters.

[0062] In this embodiment, optionally, the initial value of each bit of the storage address indication area is 0, and the target value is 1.

[0063] In this solution, for the storage address indication area, the initial value of each bit can be 0, and the target value after rewriting can be 1. In this way, the read value can be determined by the number of bits where the number 1 is located, and the association with the storage area is established based on this.

[0064] This arrangement of the present solution can better obtain the association relationship between the value read in the storage address indication area and the storage area, ensure the orderly storage of the target parameters, and avoid the situation where the target parameter storage areas have intersections caused by parsing errors.

[0065] In this embodiment, optionally, updating the current value in the storage address indication area includes:

[0066] The higher bit of the highest bit that is rewritten as the target value in the storage address indication area is obtained and the initial value is rewritten as the target value.

[0067] In this solution, after the target operating parameter is stored in the target storage area, the storage address indication area can be adjusted accordingly so that the read value of the storage address indication area can correspond to the target storage position of the target operating parameter being used. Specifically, the higher bit of the highest bit that has been rewritten as the target value in the storage address indication area can be rewritten from the initial value to the target value.

[0068] Through such a setting, the present solution can achieve that the read value of the storage address indication area can accurately correspond to the current target storage area through a simple rewriting operation.

[0069] S104, updating the current value in the storage address indication area.

[0070] It can be understood that after writing the target operating parameters, such as the new TRIM value, to the target storage area, the current value in the storage address indication area needs to be updated. As described in the above example, after storing the target operating parameters to 0x1024, the data bit 1 in the 0x1000 address needs to be changed from 0 to 1.

[0071] It should be noted that before writing the target operating parameter into the target storage area, it is also feasible to update the current value in the storage address indication area. The updating of the current value and the writing of the target operating parameter can be regarded as one process, and there is no practical difference between the execution of the two in sequence. As long as the location where the target operating parameter has been stored can be determined according to the value in the storage address indication area after the storage and update are completed, it will be sufficient.

[0072] In this embodiment, optionally, the method further includes:

[0073] Get the actual byte length of the chip's working parameters;

[0074] According to the actual byte length, a preset number of bytes for dividing at least two storage areas is determined.

[0075] In this solution, the actual byte lengths of different working parameters are different, and the byte length of each storage area, that is, a preset number of bytes, can be determined according to the requirements for storing the working parameters.

[0076] In this solution, taking TRIM value as an example, each storage area of ​​the chip is divided into several small segments, each of which stores a TRIM value. This solution can determine the preset number of bytes according to the specific TRIM value size. Assuming that each TRIM value occupies 4 bytes, each storage area consists of 4 bytes, and each storage area is used to store a complete TRIM value. If a TRIM value needs to store more information, each TRIM value can be expanded into multiple storage areas to store more bytes.

[0077] Through such a setting, the present solution can improve the flexibility of storage area setting and can set the size of each storage area according to actual needs, thereby avoiding waste of storage space and avoiding the situation where each storage area cannot store complete working parameters.

[0078] In one embodiment, optionally, the method further comprises:

[0079] In the storage address indication area, setting the value of each bit to an initial value;

[0080] When the initial value on each bit is rewritten as the target value, a mapping relationship between the read value of the storage address indication area and the storage area is established.

[0081] In this solution, the content of the storage unit storing the address indication byte identifies the starting address of the storage unit actually storing the TRIM value through the address mapping relationship. When storing the TRIM value, the programmer determines the next available storage location by reading the information of the indication bit.

[0082] When the TRIM value needs to be updated, the system will jump to the next free storage area according to the information in the indicator bit and update the corresponding TRIM value.

[0083] The establishment of the mapping mechanism can be divided into the following processes:

[0084] Initial programming, that is, when the chip leaves the factory or is used for the first time, the storage location of the TRIM value is indicated by the first storage address. Assuming that the maximum number of updates of the stored TRIM value does not exceed 32 times, only 4 bytes of address are needed for storage, for example: 0x1000. The initial value of the 0x1000 address is 0. When used for the first time, the address is written to 1. The programmer writes the TRIM value to the specified storage area based on the byte information. Assume that each TRIM value occupies 4 bytes, for example: starting from the 0x1020 address, that is, the data 1 in the 0x1000 address corresponds to the TRIM value in the 0x1020 address.

[0085] Storage update, each time a new TRIM value is stored, the system checks the indication area of ​​the storage unit to decide where to store the new data. First, check whether it is 1 from the low bit, and then go to the high bit in sequence until 0 is detected, and then modify the bit to 1. For example, when reading the 0x1000 address, if only bit0 is 1 in the data, and bits 1 and above are all 0, it means that the current TRIM value is stored at the 0x1020 address, and the newly added TRIM value needs to be stored backward to 0x1024. At the same time, the data bit1 in the 0x1000 address needs to be changed from 0 to 1, that is, 0x03 needs to be written to the 0x1000 address. Similarly, if the data read from the 0x1000 address is 0x03, bit2 needs to be changed from 0 to 1, that is, 0x07 needs to be written to the 0x1000 address, which means that the TRIM value is stored at the 0x1028 address. The storage location of the TRIM value is dynamically adjusted by the increment of 1 in the indication area of ​​the storage unit.

[0086] By establishing a mapping mechanism, this solution can determine the storage area where the currently used working parameters are located by reading the values ​​in the storage address indication area, thereby achieving precise control over operations such as reading and updating the working parameters.

[0087] In one embodiment, optionally, the method further comprises:

[0088] When it is identified that the current value in the storage address indication area is updated to the maximum reading in the storage address indication area, the storage address indication area is extended to obtain an extended indication area;

[0089] A mapping relationship between the extension indication area and the multiple storage areas obtained by extension is established.

[0090] In this solution, when the current value is updated to the maximum reading in the storage address indication area, the storage address indication area needs to be expanded.

[0091] Combined with the above example, when the maximum number of updates of the stored TRIM value exceeds 32 times, the address storage area can use more continuous address storage areas for storage. At the same time, the actual stored TRIM value area address will also increase successively. For example, if the maximum number of updates of the stored TRIM value does not exceed 128 times and the starting address is 0x1000, 16 bytes of 0x1000-0x100F can be used for storage.

[0092] It can be understood that while the storage address indication area is expanding, the storage area can also continue to expand sequentially to obtain more storage areas so as to be able to store more TRIM values.

[0093] Through such a setting, the present solution can expand the storage address indication area when the number of updates of the working parameters reaches or exceeds the maximum number that the storage address indication area can record, thereby obtaining a function of recording more update times, thereby ensuring the normal update of the chip's working parameters.

[0094] The technical solution provided in this embodiment, when identifying the target working parameter storage event, reads the current value from the storage address indication area to determine the storage area of ​​the current working parameter; determines the starting address for storing the target working parameter according to the storage area of ​​the current working parameter; determines the target storage area of ​​the target working parameter according to the starting address and the preset number of bytes, and writes the target working parameter into the target storage area; updates the current value in the storage address indication area. The technical solution, the construction of multi-segment storage and address mapping mechanism, can support the adjustment of the chip's working parameters to meet the actual use requirements of the chip.

[0095] Figure 2 FIG. 1 is a schematic diagram of TRIM value storage provided by an embodiment of the present application. Figure 2 As shown: Storage structure design: The storage structure of the OTP chip adopts segmented storage, dividing the storage area into an address storage indication area and a TRIM value storage area. The address storage indication area is used to record the status of the current storage location, and the subsequent storage unit address is used to store the TRIM value. The specific design is as follows:

[0096] TRIM value storage area, the chip's storage area is divided into several small segments, each of which stores a TRIM value. Assume that each TRIM value occupies 4 bytes. Each storage unit consists of 4 bytes to store a complete TRIM value. If a TRIM value needs to store more information, each TRIM value can be expanded to multiple storage units to store multiple bytes.

[0097] The storage address indication area is used to record and read the location where the new TRIM value should be stored, and is located before the TRIM value storage area.

[0098] The storage address indication area specifically identifies the starting address of the storage unit that actually stores the TRIM value based on the address mapping relationship. When storing the TRIM value, the programmer determines the next available storage location by reading the information of the indication bit.

[0099] When the TRIM value needs to be updated, the system will jump to the next free storage area according to the information in the indicator bit and update the corresponding TRIM value.

[0100] The address mapping mechanism can be used to support storing multiple and updating TRIM values. The mechanism works as follows:

[0101] Initial programming, when the chip leaves the factory or is used for the first time, the storage location of the TRIM value is indicated by the first storage address. Assuming that the maximum number of updates to the stored TRIM value does not exceed 32 times, only 4 bytes of address are needed for storage, for example: 0x1000. The initial value of the 0x1000 address is 0. When used for the first time, the address is written to 1. The programmer writes the TRIM value to the specified storage area based on the byte information. Assume that each TRIM value occupies 4 bytes, for example: starting from address 0x1020, that is, the data 1 in address 0x1000 corresponds to the TRIM value in address 0x1020.

[0102] Storage update, each time a new TRIM value is stored, the system checks the indication area of ​​the storage unit to decide where to store the new data. First, check whether it is 1 from the low bit, and then go to the high bit in sequence until 0 is detected, and then modify the bit to 1. For example: read the 0x1000 address, if only bit0 is 1 in the data, and all bits above bit1 are 0, it means that the current TRIM value is stored at the 0x1020 address, and the newly added TRIM value needs to be stored backward to 0x1024. At the same time, the data bit1 in the 0x1000 address needs to be changed from 0 to 1, that is, 0x03 needs to be written to the 0x1000 address. Similarly, if the data read from the 0x1000 address is 0x03, bit2 needs to be changed from 0 to 1, that is, 0x07 needs to be written to the 0x1000 address, which means that the TRIM value is stored at the 0x1028 address. The storage location of the TRIM value is dynamically adjusted by the increment of 1 in the indication area of ​​the storage unit.

[0103] The storage times are processed dynamically. When the maximum number of updates of the stored TRIM value exceeds 32 times, the address storage area can use more continuous address storage areas for storage. At the same time, the actual stored TRIM value area address will also increase successively. For example, if the maximum number of updates of the stored TRIM value does not exceed 128 times and the starting address is 0x1000, 16 bytes of 0x1000-0x100F can be used for storage.

[0104] The process of programming the TRIM value consists of the following steps:

[0105] Read the current storage location;

[0106] First, the programmer reads the first location of the chip (ie, the storage address indication area) to indicate the starting address of the current storage area.

[0107] Store TRIM value;

[0108] According to the instruction byte information, the programmer writes the TRIM value to the specified storage area. Each TRIM value storage unit consists of 4 bytes (or the number of bytes can be expanded as required), and the programmer writes the data byte by byte.

[0109] The process of reading the TRIM value is similar to the programming process. The user obtains the TRIM value by reading the data in the storage area. The specific steps are as follows:

[0110] Read the indicator byte, read the bytes of the storage area, and determine the TRIM value storage location.

[0111] Read the TRIM value and extract the TRIM value from the corresponding storage unit according to the storage location.

[0112] Since this patented solution uses an address mapping mechanism, it is highly flexible and can store multiple TRIM values ​​as needed. The chip's storage area can be expanded according to actual needs:

[0113] Dynamic expansion: Each time programming is performed, the expansion of the storage area is dynamic, and there is no need to fix the storage capacity when the chip is designed.

[0114] TRIM value update: TRIM values ​​can be updated at different times and under different conditions, and the updated value will be stored in a new address without overwriting the previous TRIM value. This allows the system to make multiple adjustments based on environmental changes or different operating parameters.

[0115] The present invention can also be flexibly configured according to different application requirements, such as storing different TRIM values, storing different parameter values, and adjusting the storage location.

[0116] The storage method of the present invention breaks through the limitation that the TRIM value can only be written once in the traditional OTP chip before leaving the factory, realizes multiple writing, and provides a better solution for the practicality of the OTP chip.

[0117] Assume that there is an initial configuration as follows:

[0118] Address 0x1000: address indicating storage bit;

[0119] Address 0x1004: Address indicating storage bit (if more than 32 TRIM values ​​need to be stored, use this address);

[0120] Address 0x1020: TRIM value storage start address (the start address and offset can be customized as needed);

[0121] When the TRIM value needs to be updated, the program first checks whether the address 0x1000 is empty, that is, it does not point to other places. If so, it starts writing new TRIM data at the starting address of the storage unit, and sets 0x1000 to 0b00000000-00000000-00000000-00000001, pointing to the corresponding storage area according to the address offset relationship; otherwise, by judging the number of address indication area 1, the address offset is determined to read the latest TRIM value.

[0122] This technical solution introduces a flexible address mapping mechanism, so that multiple versions of TRIM data can be effectively managed and updated even on non-rewritable OTP media, thereby increasing the practicality of the OTP chip.

[0123] Figure 3 is a schematic diagram of the structure of a multi-segment storage device for chip working parameters provided in an embodiment of the present application; Figure 3 As shown, the chip is provided with a storage address indication area and at least two storage areas, each storage area is composed of a preset number of bytes; the device comprises:

[0124] The current value reading module 301 is used to read the current value from the storage address indication area to determine the storage area of ​​the current working parameter when a target working parameter storage event is identified;

[0125] A storage start address determination module 302 is used to determine a start address for storing the target operating parameters according to a storage area of ​​the current operating parameters;

[0126] A target storage area determination module 303, used to determine a target storage area for a target operating parameter according to the start address and the preset number of bytes, and write the target operating parameter into the target storage area;

[0127] The current value updating module 304 is used to update the current value in the storage address indication area.

[0128] The technical solution provided in this embodiment, when identifying the target working parameter storage event, reads the current value from the storage address indication area to determine the storage area of ​​the current working parameter; determines the starting address for storing the target working parameter according to the storage area of ​​the current working parameter; determines the target storage area of ​​the target working parameter according to the starting address and the preset number of bytes, and writes the target working parameter into the target storage area; updates the current value in the storage address indication area. The technical solution, the construction of multi-segment storage and address mapping mechanism, can support the adjustment of the chip's working parameters to meet the actual use requirements of the chip.

[0129] The multi-segment storage device for the working parameters of the chip in the embodiment of the present application can be a device, or a component, an integrated circuit, or a chip in a terminal. The device can be a mobile electronic device or a non-mobile electronic device. Exemplarily, the mobile electronic device can be a mobile phone, a tablet computer, a laptop computer, a PDA, an in-vehicle electronic device, a wearable device, an ultra-mobile personal computer (UMPC), a netbook or a personal digital assistant (PDA), etc., and the non-mobile electronic device can be a server, a network attached storage (NAS), a personal computer (PC), a television (TV), a teller machine or a self-service machine, etc., which is not specifically limited in the embodiment of the present application.

[0130] The chip operating parameter multi-segment storage device in the embodiment of the present application may be a device having an operating system. The operating system may be an Android operating system, an iOS operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present application.

[0131] The multi-segment storage device for chip working parameters provided in the embodiment of the present application can implement each process implemented in the above-mentioned method embodiments, and will not be described again here to avoid repetition.

[0132] Figure 4 Schematic diagram of the structure of the electronic device provided in the embodiment of the present application. Figure 4 As shown, an embodiment of the present application also provides an electronic device 400, including a processor 401, a memory 402, and a program or instruction stored in the memory 402 and executable on the processor 401. When the program or instruction is executed by the processor 401, each process of the multi-segment storage device for working parameters of the above-mentioned chip is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0133] It should be noted that the electronic devices in the embodiments of the present application include the mobile electronic devices and non-mobile electronic devices mentioned above.

[0134] An embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, each process of the multi-segment storage device for working parameters of the above-mentioned chip is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0135] The processor is a processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0136] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement various processes of the multi-segment storage device embodiment of the working parameters of the above-mentioned chip, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0137] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0138] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0139] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, a disk, or an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0140] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

[0141] The above are only preferred embodiments of the present application and the technical principles used. The present application is not limited to the specific embodiments described herein, and various obvious changes, readjustments and substitutions that can be made by those skilled in the art will not deviate from the scope of protection of the present application. Therefore, although the present application is described in more detail through the above embodiments, the present application is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the claims.

Claims

1. A multi-segment storage method for chip working parameters, characterized in that: The chip is provided with a storage address indication area and at least two storage areas, each storage area is composed of a preset number of bytes; the method comprises: When a target operating parameter storage event is identified, a current value is read from the storage address indication area to determine a storage area of ​​the current operating parameter; Determining a starting address for storing the target operating parameters according to a storage area of ​​the current operating parameters; Determine a target storage area for target operating parameters according to the starting address and the preset number of bytes, and write the target operating parameters into the target storage area; The current value in the storage address indication area is updated.

2. The multi-segment storage method of chip operating parameters according to claim 1, characterized in that: The method further comprises: Get the actual byte length of the chip's working parameters; According to the actual byte length, a preset number of bytes for dividing at least two storage areas is determined.

3. The multi-segment storage method for chip operating parameters according to claim 1, characterized in that: Reading a current value from the storage address indication area to determine a storage area of ​​a current working parameter includes: Read the number written as the target value from the lower bit to the higher bit in the storage address indication area to obtain the current value; According to the pre-constructed mapping relationship, the storage area corresponding to the current value is parsed to obtain the storage area of ​​the current working parameter.

4. The multi-segment storage method for chip operating parameters according to claim 3, characterized in that: The initial value of each bit in the storage address indication area is 0, and the target value is 1.

5. The multi-segment storage method for chip operating parameters according to claim 3, characterized in that: Updating the current value in the storage address indication area includes: The higher bit of the highest bit that is rewritten as the target value in the storage address indication area is obtained and the initial value is rewritten as the target value.

6. The multi-segment storage method for chip operating parameters according to claim 1, characterized in that: The method further comprises: In the storage address indication area, setting the value of each bit to an initial value; When the initial value on each bit is rewritten as the target value, a mapping relationship between the read value of the storage address indication area and the storage area is established.

7. The multi-segment storage method for chip operating parameters according to claim 1, characterized in that: The method further comprises: When it is identified that the current value in the storage address indication area is updated to the maximum reading in the storage address indication area, the storage address indication area is extended to obtain an extended indication area; A mapping relationship between the extension indication area and the multiple storage areas obtained by extension is established.

8. A multi-segment storage device for chip operating parameters, characterized in that: The chip is provided with a storage address indication area and at least two storage areas, each storage area is composed of a preset number of bytes; the device comprises: A current value reading module, used to read the current value from the storage address indication area to determine the storage area of ​​the current working parameter when a target working parameter storage event is identified; A storage start address determination module, used to determine the start address for storing the target operating parameter according to the storage area of ​​the current operating parameter; A target storage area determination module, used to determine a target storage area for a target operating parameter according to the start address and the preset number of bytes, and write the target operating parameter into the target storage area; The current value updating module is used to update the current value in the storage address indication area.

9. An electronic device, characterized in that: The invention comprises a processor, a memory and a program or instruction stored in the memory and executable on the processor, wherein the program or instruction, when executed by the processor, implements the steps of the multi-segment storage method for the working parameters of the chip as described in any one of claims 1 to 7.

10. A readable storage medium, characterized in that: The readable storage medium stores a program or instruction, and when the program or instruction is executed by the processor, the steps of the multi-segment storage method for the working parameters of the chip according to any one of claims 1 to 7 are implemented.

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