Flash memory cell erasing method, device and storage medium for reducing threshold voltage distribution

Abstract

The present invention discloses a flash memory cell erasing method, device, and storage medium for reducing threshold voltage distribution. The method comprises: obtaining a programming flash memory cell and an erasing flash memory cell of a storage block to be erased according to an erase instruction; performing a suppression process on the programming flash memory cell and a pre-programming process on the erasing flash memory cell to obtain a processed storage block to be erased; and performing an erasing operation on the processed storage block to be erased. The present invention suppresses the programming flash memory cell and then pre-programs the erasing flash memory cell; thereby, the programming flash memory cell is not affected by the erasing process, and the threshold voltage of the programming flash memory cell remains unchanged, thereby reducing the threshold voltage distribution range.

Description

Technical Field

[0001] The present invention relates to the technical field of data storage, and in particular to a flash memory unit erasing method, device and storage medium for reducing threshold voltage distribution. Background Art

[0002] NAND FLASH (flash memory) is a common non-volatile memory. With the growing demand for memory capacity and performance in embedded systems and electronic devices, NAND FLASH, as a low-cost, easily integrated memory solution, has become the preferred solution. NAND FLASH is widely used in embedded systems and electronic devices. However, during use, these systems and electronic devices often encounter data erase operations. During data erase operations, the flash memory cells within a NAND FLASH storage block are erased. However, a storage block contains multiple flash memory cells, with both programmed and erased states coexisting. During the erase operation, the programmed flash memory cells are affected by the erase pulse stress generated by the erased flash memory cells, causing them to be over-erased, resulting in a wide distribution of threshold voltages across the flash memory cells within the storage block. Therefore, when performing NAND FLASH erase operations, it is necessary to mitigate the impact of the erase pulse stress generated by the erased flash memory cells.

[0003] However, existing flash memory cell erasing methods typically program all flash memory cells within a memory block, thereby converting the erased flash memory cells within the memory block to the programmed state. However, during the programming operation on the erased flash memory cells, the programming flash memory cells are also programmed. This can cause the programmed flash memory cells to be over-programmed, resulting in a wide distribution of threshold voltages across the flash memory cells within the memory block, leading to reduced NAND FLASH performance.

[0004] Therefore, there is still an urgent need for a flash memory cell erasing method that can reduce threshold voltage distribution and improve NAND FLASH performance. Summary of the Invention

[0005] The main purpose of the present invention is to propose a flash memory cell erasing method, device and storage medium with reduced threshold voltage distribution, so as to solve the problem that when the existing defective NAND FLASH performs an erase operation, the threshold voltage distribution range of the flash memory cells in the storage block is large, thereby reducing the performance of the NAND FLASH.

[0006] To achieve the above object, the present invention proposes a flash memory cell erasing method for reducing threshold voltage distribution, the flash memory cell erasing method for reducing threshold voltage distribution comprising:

[0007] According to the erase instruction, the program flash memory unit and the erase flash memory unit of the storage block to be erased are obtained;

[0008] Performing suppression processing on the program flash memory unit and pre-programming processing on the erase flash memory unit to obtain a processed storage block to be erased;

[0009] An erasing operation is performed on the processed storage block to be erased.

[0010] In some embodiments, obtaining the program flash memory unit and the erase flash memory unit of the memory block to be erased includes:

[0011] Reading the current state of each flash memory cell in the memory block to be erased, wherein the current state includes a programming state and an erasing state;

[0012] If the current state of the flash memory cell is the programming state, determining that the flash memory cell is a programming flash memory cell;

[0013] If the current state of the flash memory unit is the erase state, it is determined that the flash memory unit is an erased flash memory unit.

[0014] In some embodiments, the inhibiting process on the program flash memory unit and the pre-programming process on the erasing flash memory unit include:

[0015] performing the suppression process on the programming state of the programming flash memory cell so that the programming state of the programming flash memory cell is suppressed;

[0016] The pre-programming process is performed on the erased state of the erased flash memory unit, so that the erased flash memory unit is changed from the erased state to the programmed state.

[0017] In some embodiments, before reading the current state of each flash memory cell in the memory block to be erased, the method further includes:

[0018] Get each storage block;

[0019] The storage block to be erased is determined from the storage blocks.

[0020] In some embodiments, before acquiring the program flash memory unit and the erase flash memory unit of the memory block to be erased according to the erase instruction, the method further includes:

[0021] Get the erase information entered by the user;

[0022] The erasure instruction is generated according to the erasure information input by the user.

[0023] In some embodiments, it further includes:

[0024] respectively acquiring a threshold voltage of the program flash memory cell and a threshold voltage of the erase flash memory cell during an erase operation;

[0025] determining a threshold voltage distribution value according to a distance between a threshold voltage of the program flash memory cell and a threshold voltage of the erase flash memory cell;

[0026] Determining whether the threshold voltage distribution value is less than a preset distribution value;

[0027] If the threshold voltage distribution value is smaller than the preset distribution value, it is determined that the suppression process and the pre-programming process are successful.

[0028] In some embodiments, after performing the erasing operation on the processed storage block to be erased, the method further includes:

[0029] Determining whether the erasing operation is successful;

[0030] If the erasing operation is successful, the erasing operation is ended.

[0031] In some embodiments, after the erasing operation is completed, the method further includes:

[0032] acquiring the program flash memory cell in the inhibition process;

[0033] The inhibit process of programming the flash memory cell is ended.

[0034] The present invention also provides a flash memory cell erasing device for reducing threshold voltage distribution, comprising:

[0035] at least one processor; and,

[0036] a memory communicatively connected to the at least one processor; wherein,

[0037] The memory stores instructions executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform any one of the above-mentioned flash memory cell erasing methods for reducing threshold voltage distribution.

[0038] The present invention also provides a storage medium storing a computer program, wherein the computer program includes program instructions. When executed by a processor, the program instructions enable the processor to execute any one of the above-mentioned flash memory cell erasing methods for reducing threshold voltage distribution.

[0039] The present invention suppresses the programming flash memory unit and then pre-programs the erasing flash memory unit; the programming flash memory unit is not affected whether in the pre-programming processing stage of the erasing flash memory unit or in the erasing operation of the storage block to be erased; the threshold voltage of the programming flash memory unit remains unchanged, so that when the NANDFLASH performs the erasing operation, the threshold voltage distribution range between the flash memory units in the storage block is reduced, and the performance of the NANDFLASH is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 Schematic diagram of the process of a flash memory cell erasing method for reducing threshold voltage distribution according to an embodiment of the present invention;

[0041] Figure 2 Another schematic flow chart of a flash memory cell erasing method for reducing threshold voltage distribution according to an embodiment of the present invention;

[0042] Figure 3 Another schematic flow chart of a flash memory cell erasing method for reducing threshold voltage distribution according to an embodiment of the present invention;

[0043] Figure 4 Another schematic flow chart of a flash memory cell erasing method for reducing threshold voltage distribution according to an embodiment of the present invention;

[0044] Figure 5 Another schematic flow chart of a flash memory cell erasing method for reducing threshold voltage distribution according to an embodiment of the present invention;

[0045] Figure 6 Another schematic flow chart of a flash memory cell erasing method for reducing threshold voltage distribution according to an embodiment of the present invention;

[0046] Figure 7 Another schematic flow chart of a flash memory cell erasing method for reducing threshold voltage distribution according to an embodiment of the present invention;

[0047] Figure 8 Another schematic flow chart of a flash memory cell erasing method for reducing threshold voltage distribution according to an embodiment of the present invention;

[0048] Figure 9 Schematic diagram of the structure of a flash memory cell erasing device for reducing threshold voltage distribution according to an embodiment of the present invention;

[0049] Figure 10 A schematic diagram of a threshold voltage for programming a flash memory cell and a threshold voltage for erasing a flash memory cell according to an embodiment of the present invention;

[0050] Figure 11Another schematic diagram of the threshold voltage of programming a flash memory cell and the threshold voltage of erasing a flash memory cell according to an embodiment of the present invention;

[0051] Figure 12 Another schematic diagram of the threshold voltage of programming a flash memory cell and the threshold voltage of erasing a flash memory cell according to an embodiment of the present invention;

[0052] Figure 13 Another schematic diagram of the threshold voltage of programming a flash memory cell and the threshold voltage of erasing a flash memory cell according to an embodiment of the present invention.

[0053] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0054] The following will be combined with the accompanying drawings to clearly and completely describe the solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.

[0055] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0056] It should also be noted that when an element is referred to as being "fixed on" or "disposed on" another element, it may be directly on the other element or there may be an intermediate element. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intermediate element.

[0057] In addition, the descriptions of "first", "second", etc. in the present invention are for descriptive purposes only and should not be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between the various embodiments can be combined with each other, but this must be based on the fact that they can be implemented by ordinary technicians in this field. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0058] To achieve the above-mentioned object, the present invention proposes a flash memory cell erasing method for reducing threshold voltage distribution. The flash memory cell erasing method for reducing threshold voltage distribution includes:

[0059] Step S110, obtaining the programming flash memory unit and the erasing flash memory unit of the storage block to be erased according to the erase instruction;

[0060] Step S120, performing suppression processing on the program flash memory unit and pre-programming processing on the erase flash memory unit to obtain a processed storage block to be erased;

[0061] Step S130 , performing an erase operation on the processed storage block to be erased.

[0062] In this embodiment, referring to Figure 1 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 and Figure 13 , the flash memory cell erasing method with reduced threshold voltage distribution can be applied to the flash memory cell erasing device with reduced threshold voltage distribution. The flash memory cell erasing device with reduced threshold voltage distribution can be configured inside the NAND FLASH (flash memory) so that the NAND FLASH can execute the flash memory cell erasing method with reduced threshold voltage distribution. Among them, the NAND FLASH can be an SPI NAND FLASH (Serial Peripheral Interface NAND FLASH, flash memory with serial peripheral interface) or a PPI NAND FLASH (Parallel Pin Interface NAND FLASH, flash memory with parallel peripheral interface). The NAND FLASH can reduce the threshold voltage distribution between the flash memory cells when performing the erase operation through the flash memory cell erasing device with reduced threshold voltage distribution. In this embodiment, the execution subject of the method steps is the NAND FLASH configured with the flash memory cell erasing device with reduced threshold voltage distribution.

[0063] It can be understood that NAND FLASH includes multiple storage blocks, each storage block includes multiple flash memory cells, and the storage block to be erased is a storage block waiting to be erased; some flash memory cells in the storage block are in a programming state, and some flash memory cells are in an erasing state; so that when NAND FLASH performs an erase operation on any storage block, the programming flash memory cells and the erasing flash memory cells in the storage block coexist.

[0064] exist Figures 10 to 13 The graph shown in is a graph showing the changes in the threshold voltage of the programming flash memory cell and the threshold voltage of the erasing flash memory cell as the flash memory cell erasing method of reducing the threshold voltage distribution is performed. Figures 10 to 13In the figure, erase refers to erasing the threshold voltage of the flash memory cell, program refers to programming the threshold voltage of the flash memory cell, VT (V) refers to the threshold voltage (unit: volts), and Bit refers to the number of erase pulses. The coordinate axis can be understood as the change of threshold voltage with the number of erase pulses. Figure 10 A schematic diagram of the threshold voltage when executing the erase instruction step; Figure 11 A schematic diagram of the threshold voltage after performing the inhibition process on the program flash memory cell and the pre-programming process on the erase flash memory cell; Figure 12 A schematic diagram of the threshold voltage during the process of performing an erase operation on a processed memory block to be erased; Figure 13 A schematic diagram of the threshold voltage after performing an erase operation on the processed memory block to be erased.

[0065] When the user needs to erase the NAND FLASH, they can enter an erase command into the NAND FLASH. At this point, the NAND FLASH receives the erase command and, based on the erase command, obtains the program flash memory cells and erase flash memory cells of the memory block to be erased. The NAND FLASH then distinguishes the flash memory cells in the memory block to be erased, thereby obtaining the program flash memory cells and erase flash memory cells.

[0066] At this time, the threshold voltage of the programming flash memory cell and the erasing flash memory cell can be detected. Figure 10 Since programming or erasing a memory block is performed through different threshold voltages, the threshold voltage for erasing a flash memory cell and the threshold voltage for programming a flash memory cell are on opposite sides of the coordinate axis.

[0067] After NAND FLASH distinguishes the flash memory cells in the memory block to be erased, creating programmed flash memory cells and erased flash memory cells, it first suppresses the programmed flash memory cells and then pre-programs the erased flash memory cells. This results in a processed memory block to be erased. Because NAND FLASH suppresses the programmed flash memory cells first and then pre-programs the erased flash memory cells, it prevents programming flash memory cells from being programmed, thus preventing over-programming of programmed flash memory cells.

[0068] At this time, the threshold voltage of the programming flash memory cell and the erasing flash memory cell can be detected. Figure 11Schematic diagram shown. Because the program flash memory cells are inhibited, the NAND FLASH does not program the erase flash memory cells when pre-programming them, resulting in no change in the threshold voltage of the program flash memory cells. Because the erase flash memory cells are pre-programmed, the threshold voltage of the erase flash memory cells shifts to the right, approaching the threshold voltage of the program flash memory cells. If the program flash memory cells are not inhibited first, the program flash memory cells will also be programmed when pre-programming them. In this case, the threshold voltage of the program flash memory cells will also shift to the right, resulting in no significant reduction in the distance between the threshold voltages of the erase flash memory cells and the programming flash memory cells, i.e., no significant reduction in the threshold voltage distribution. However, by first inhibiting the program flash memory cells and then pre-programming them, the threshold voltage of the program flash memory cells remains unchanged, and the threshold voltage of the erase flash memory cells shifts to the right, shortening the distance between the threshold voltages of the erase flash memory cells and the programming flash memory cells, i.e., reducing the threshold voltage distribution.

[0069] NAND FLASH read, write, and program operations operate directly on flash memory cells, while erase operations operate only on memory blocks. Therefore, NAND FLASH erase operations are performed on memory blocks. After the NAND FLASH performs suppression and pre-programming on the memory block to be erased, the erase operation can be performed on the processed memory block to be erased.

[0070] Since the erase operation is performed on the processed memory block to be erased, at this time, the threshold voltages of the programming flash memory unit and the erasing flash memory unit are detected, and the Figure 12 The programming flash memory cell and the erasing flash memory cell are both affected in the same way, so that the threshold voltage of the erasing flash memory cell and the threshold voltage of the programming flash memory cell are both shifted to the left. At this time, the distance between the threshold voltage of the erasing flash memory cell and the threshold voltage of the programming flash memory cell does not change. After the erase operation is completed on the processed memory block to be erased, Figure 13 As shown in the schematic diagram, the distance between the threshold voltage of the erased flash memory cell and the threshold voltage of the programmed flash memory cell does not change; therefore, after the threshold voltage distribution is reduced as described above, when the erase operation is performed on the processed storage block to be erased, the threshold voltage distribution does not change, so that before the NAND FLASH performs the erase operation, the programmed flash memory cell is first suppressed, and then the erased flash memory cell is pre-programmed, and then the erase operation is performed, which can reduce the threshold voltage distribution between the flash memory cells during and after the erase operation.

[0071] Similarly, if the erasing operation is performed directly without performing the suppression process and pre-programming process on the memory block to be erased, the threshold voltage of the erased flash memory cell and the threshold voltage of the programmed flash memory cell will be the same as Figure 10 As shown, they shift to the left at the same time. At this time, the distance between the threshold voltage of the erased flash memory cell and the threshold voltage of the programmed flash memory cell is very large, that is, the threshold voltage distribution is large.

[0072] This embodiment suppresses the programming of the flash memory cells and then pre-programs the erasing flash memory cells. This ensures that the programming of the flash memory cells is not affected either during the pre-programming of the erasing flash memory cells or during the erasing of the storage blocks to be erased. This ensures that the threshold voltage of the programming flash memory cells remains unchanged, thereby reducing the threshold voltage distribution range between the flash memory cells in the storage block when the NAND FLASH is erased, thereby improving the performance of the NAND FLASH.

[0073] In some embodiments, the aforementioned obtaining of program flash memory cells and erase flash memory cells of a memory block to be erased includes:

[0074] Step S140, reading the current state of each flash memory cell in the memory block to be erased, wherein the current state includes a programming state and an erasing state;

[0075] Step S141, if the current state of the flash memory cell is a programming state, determining that the flash memory cell is a programming flash memory cell;

[0076] Step S142 : If the current state of the flash memory unit is the erase state, determine that the flash memory unit is an erased flash memory unit.

[0077] In this embodiment, referring to Figure 2 When executing step S110, the NAND FLASH distinguishes flash memory cells based on their current states. The NAND FLASH includes multiple memory blocks, each of which includes multiple flash memory cells. The to-be-erased memory block is a memory block waiting to be erased. The NAND FLASH first reads each flash memory cell in the to-be-erased memory block to obtain the current state of each flash memory cell; the current state includes a programming state and an erased state.

[0078] If the NAND FLASH determines that the current state of the flash memory cell is a programming state, the flash memory cell may be determined as a programming flash memory cell.

[0079] If the NAND FLASH determines that the current state of the flash memory cell is an erase state, the flash memory cell may be determined as an erased flash memory cell.

[0080] NAND FLASH divides each flash memory cell into a program flash memory cell and an erase flash memory cell according to the current state of the flash memory cell.

[0081] In some embodiments, the aforementioned inhibiting process for programming flash memory cells and pre-programming process for erasing flash memory cells include:

[0082] Step S150, suppressing the programming state of the programming flash memory cell so that the programming state of the programming flash memory cell is suppressed;

[0083] Step S151 , performing a pre-programming process on the erased state of the erased flash memory unit, so that the erased flash memory unit is transferred from the erased state to the programmed state.

[0084] In this embodiment, referring to Figure 3 When NAND FLASH executes step S120, it first performs suppression processing and then performs pre-programming processing. NAND FLASH first suppresses the programming state of the programming flash memory cell, so that the programming state of the programming flash memory cell is suppressed; then pre-programming processing is performed on the erased state of the erased flash memory cell, so that the erased flash memory cell is changed from the erased state to the programming state. After the suppression processing is performed on the programming state of the programming flash memory cell, when the pre-programming processing is performed on the erased state of the erased flash memory cell, the programming flash memory cell will not be programmed together, thereby preventing the programming flash memory cell from being over-programmed.

[0085] In some embodiments, before reading the current state of each flash memory cell in the memory block to be erased, the process further includes:

[0086] Step S160, obtaining each storage block;

[0087] Step S161 , determining a storage block to be erased from each storage block.

[0088] In this embodiment, referring to Figure 4 Before executing step S140, NAND FLASH needs to first obtain the storage block to be erased. NAND FLASH includes multiple storage blocks, and the storage block to be erased is the storage block waiting to be erased. NAND FLASH first obtains each internal storage block, and then finds the storage block that needs to be erased from each storage block, that is, determines the storage block to be erased from each storage block. For example: NAND FLASH can determine the data to be erased based on the erase instruction, and then determine which storage block the data to be erased is stored in. After finding the storage block storing the data to be erased, it can determine the storage block as the storage block to be erased.

[0089] In some embodiments, before obtaining the program flash memory unit and the erase flash memory unit of the memory block to be erased according to the erase instruction, the method further includes:

[0090] Step S100, obtaining erasure information input by the user;

[0091] Step S101: Generate an erasure instruction according to the erasure information input by the user.

[0092] In this embodiment, referring to Figure 5 Before executing step S110, the NAND FLASH may also generate an instruction based on the information input by the user. The NAND FLASH receives the erasure information input by the user and then generates an erasure instruction based on the erasure information input by the user. For example, if a user wants to delete a portion of files in a folder in the NAND FLASH, the erasure information input may be to select the portion of files and then confirm the deletion; at this time, the NAND FLASH can receive the erasure information and then generate an erasure instruction for the portion of files based on the erasure information.

[0093] In some embodiments, the aforementioned flash memory cell erasing method for reducing threshold voltage distribution further includes:

[0094] Step S170, respectively obtaining a threshold voltage of a program flash memory cell and a threshold voltage of an erase flash memory cell during an erase operation;

[0095] Step S171, determining a threshold voltage distribution value according to a distance between a threshold voltage of a programming flash memory cell and a threshold voltage of an erasing flash memory cell;

[0096] Step S172, determining whether the threshold voltage distribution value is less than a preset distribution value;

[0097] In step S173 , if the threshold voltage distribution value is less than the preset distribution value, it is determined that the suppression process and the pre-programming process are successful.

[0098] In this embodiment, referring to Figure 6 、 Figure 10 、 Figure 11 、 Figure 12 and Figure 13 During step S130, NAND FLASH can also obtain the threshold voltage of each flash memory cell. NAND FLASH obtains the threshold voltage of the programming flash memory cell and the threshold voltage of the erasing flash memory cell during the erase operation respectively; then, based on the distance between the threshold voltage of the programming flash memory cell and the threshold voltage of the erasing flash memory cell, it determines the threshold voltage distribution value. NAND FLASH then compares the threshold voltage distribution value with a preset distribution value; wherein, the preset distribution value is customized by the user according to actual test requirements.

[0099] If the NAND FLASH determines that the threshold voltage distribution value is less than the preset distribution value, it determines that the inhibition process and the pre-programming process are successful.

[0100] If the NAND FLASH determines that the threshold voltage distribution value is greater than the preset distribution value, it determines that the inhibition process and the pre-programming process have failed. At this time, the NAND FLASH will perform the steps of inhibiting the program flash memory cell and pre-programming the erase flash memory cell twice.

[0101] Of course, NAND FLASH can obtain the threshold voltage of the programming flash memory cell and the threshold voltage of the erasing flash memory cell during any period of the erasing operation after the steps of performing the inhibition process on the programming flash memory cell and the pre-programming process on the erasing flash memory cell for judgment. For example, the threshold voltage of the programming flash memory cell and the threshold voltage of the erasing flash memory cell after the erasing operation can be obtained respectively; Figure 13 As shown, the threshold voltage distribution value is determined according to the distance between the threshold voltage of the programming flash memory cell and the threshold voltage of the erasing flash memory cell, and then it is determined whether the threshold voltage distribution value is less than the preset distribution value.

[0102] In some embodiments, after performing the erasing operation on the processed storage block to be erased, the method further includes:

[0103] Step S180, determining whether the erase operation is successful;

[0104] Step S181: If the erasing operation is successful, the erasing operation is ended.

[0105] In this embodiment, referring to Figure 7 After executing step S130, the NAND FLASH can also determine whether the erase operation is successful. After the NAND FLASH performs the erase operation on the processed storage block to be erased, it can determine whether the erase operation on the storage block to be erased is successful. If the NAND FLASH determines that the erase operation on the storage block to be erased is successful, the NAND FLASH can end the erase operation. If the NAND FLASH determines that the erase operation on the storage block to be erased fails, the NAND FLASH will perform the erase operation on the processed storage block to be erased again.

[0106] In some embodiments, after the erasing operation is completed, the method further includes:

[0107] Step S190, obtaining a program flash memory cell in the inhibition process;

[0108] Step S191, ending the inhibition process of programming the flash memory cell.

[0109] In this embodiment, referring to Figure 8 After executing step S181, the NAND FLASH also ends the inhibition process. After the NAND FLASH ends the erase operation, the NAND FLASH obtains the programming flash memory cell that is in the inhibition process, and then ends the inhibition process of the programming flash memory cell, so that the programming flash memory cell can continue the programming operation.

[0110] The present invention suppresses the programming flash memory unit and then pre-programs the erasing flash memory unit; the programming flash memory unit is not affected whether in the pre-programming processing stage of the erasing flash memory unit or in the erasing operation of the storage block to be erased; the threshold voltage of the programming flash memory unit remains unchanged, so that when the NANDFLASH performs the erasing operation, the threshold voltage distribution range between the flash memory units in the storage block is reduced, and the performance of the NANDFLASH is improved.

[0111] The flash memory cell erasing device with reduced threshold voltage distribution according to the embodiment of the present invention may be a controller capable of executing a flash memory cell erasing method with reduced threshold voltage distribution; the controller has at least one. Figure 9 As shown, the flash memory cell erasing device for reducing the threshold voltage distribution may include: a controller 1001 (e.g., a CPU), a network interface 1004, a user interface 1003, a memory 1005, and a communication bus 1002. The communication bus 1002 is used to realize the connection and communication between these components. The user interface 1003 may include a display screen (Display), an input unit, such as a keyboard (Keyboard), and the user interface 1003 may also include a standard wired interface and a wireless interface. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a WI-FI interface). The memory 1005 may be a high-speed RAM memory, or a stable memory (non-volatile memory), such as a disk memory. The memory 1005 may also be a storage device independent of the aforementioned controller 1001.

[0112] Those skilled in the art will understand that Figure 9 The structure of the flash memory cell erasing device with reduced threshold voltage distribution shown in the figure does not constitute a limitation to the flash memory cell erasing device with reduced threshold voltage distribution, and may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0113] like Figure 9 As shown, the memory 1005 as a computer storage medium may include an operating system, a network communication module, a user interface module and a computer program.

[0114] exist Figure 9In the flash memory cell erasing device with reduced threshold voltage distribution shown, the network interface 1004 is mainly used to connect to the background server and communicate data with the background server; the user interface 1003 is mainly used to connect to the client (user end) and communicate data with the client; and the controller 1001 can be used to call the computer program stored in the memory 1005. When the computer program is called and executed by the controller 1001, the steps of the flash memory cell erasing method with reduced threshold voltage distribution are implemented.

[0115] The present invention also provides a storage medium storing a computer program, wherein the computer program includes program instructions. When executed by a processor, the program instructions enable the processor to execute any one of the above-mentioned flash memory cell erasing methods for reducing threshold voltage distribution.

[0116] The above description is only a partial or preferred embodiment of the present invention. Neither the text nor the drawings can limit the scope of protection of the present invention. All equivalent structural transformations made by using the contents of the present invention description and drawings under the overall concept of the present invention, or direct / indirect application in other related technical fields are included in the scope of protection of the present invention.

Claims

1. A flash memory cell erasing method for reducing threshold voltage distribution, characterized in that: The flash memory cell erasing method for reducing threshold voltage distribution includes: According to the erase instruction, the program flash memory unit and the erase flash memory unit of the storage block to be erased are obtained; Performing suppression processing on the program flash memory unit and pre-programming processing on the erase flash memory unit to obtain a processed storage block to be erased; performing an erasing operation on the processed storage block to be erased; The step of obtaining a program flash memory unit and an erase flash memory unit of a storage block to be erased includes: Reading the current state of each flash memory cell in the memory block to be erased, wherein the current state includes a programming state and an erasing state; If the current state of the flash memory cell is the programming state, determining that the flash memory cell is a programming flash memory cell; If the current state of the flash memory unit is the erased state, determining that the flash memory unit is an erased flash memory unit; The inhibiting process on the program flash memory unit and the pre-programming process on the erase flash memory unit include: performing the suppression process on the programming state of the programming flash memory cell so that the programming state of the programming flash memory cell is suppressed; performing the pre-programming process on the erased state of the erasable flash memory unit to change the erasable flash memory unit from the erased state to the programmed state; Among them, NAND FLASH includes multiple storage blocks, and a storage block includes multiple flash memory cells. The storage block to be erased is a storage block waiting to be erased. When NAND FLASH performs an erase operation on any storage block, the programming flash memory cells and the erasing flash memory cells in the storage block coexist.

2. The flash memory cell erasing method for reducing threshold voltage distribution according to claim 1, wherein: Before reading the current state of each flash memory cell in the storage block to be erased, the method further includes: Get each storage block; The storage block to be erased is determined from the storage blocks.

3. The flash memory cell erasing method for reducing threshold voltage distribution according to claim 2, wherein: Before obtaining the program flash memory unit and the erase flash memory unit of the storage block to be erased according to the erase instruction, the method further includes: Get the erase information entered by the user; The erasure instruction is generated according to the erasure information input by the user.

4. The flash memory cell erasing method for reducing threshold voltage distribution according to claim 1, wherein: Also includes: respectively acquiring a threshold voltage of the program flash memory cell and a threshold voltage of the erase flash memory cell during an erase operation; determining a threshold voltage distribution value according to a distance between a threshold voltage of the program flash memory cell and a threshold voltage of the erase flash memory cell; Determining whether the threshold voltage distribution value is less than a preset distribution value; If the threshold voltage distribution value is smaller than the preset distribution value, it is determined that the suppression process and the pre-programming process are successful.

5. The flash memory cell erasing method for reducing threshold voltage distribution according to claim 1, wherein: After performing the erasing operation on the processed storage block to be erased, the method further includes: Determining whether the erasing operation is successful; If the erasing operation is successful, the erasing operation is ended.

6. The flash memory cell erasing method for reducing threshold voltage distribution according to claim 5, wherein: After the erasing operation is completed, the method further includes: acquiring the program flash memory cell in the inhibition process; The inhibit process of programming the flash memory cell is ended.

7. A flash memory cell erasing device with reduced threshold voltage distribution, characterized in that: include: at least one processor; as well as, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executed by the at least one processor, wherein the instructions are executed by the at least one processor so as to enable the at least one processor to perform the flash memory cell erasing method for reducing threshold voltage distribution according to any one of claims 1 to 6.

8. A storage medium, characterized in that: The storage medium stores a computer program, wherein the computer program includes program instructions. When the program instructions are executed by a processor, the processor executes the flash memory cell erasing method for reducing threshold voltage distribution according to any one of claims 1 to 6.

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