Dramless SSD read cache implementation method and device, computer equipment and storage medium
By implementing the read caching mechanism in Dramless SSD, storing and caching read commands and data, the problem of low data reading efficiency in existing Dramless SSDs is solved, improving processing performance and reducing read latency.
Patent Information
- Application Number
- CN202510015243.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-06
- Publication Date
- 2025-04-25
AI Technical Summary
The lack of local DRAM cache in the existing Dramless SSD implementation schemes results in the host reading commands being processed through a complete process, resulting in low data reading efficiency.
By receiving a read command and storing it in a preset cache memory, the target data is read from the solid state drive and cached into the HMB, and the data is sent to the host address. For the hit cache read command, read and send data directly from the HMB.
The mapping table query and reading NAND process is reduced, which significantly improves processing performance, reduces read delay and improves data reading efficiency.
Smart Images
Figure CN119883129A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of solid-state drives, and in particular to a method, device, computer equipment and storage medium for implementing a Dramless SSD read cache. Background Art
[0002] The processing flow of host read commands in the existing SSD firmware is as follows: the host read command is first parsed by the front-end protocol module to obtain the logical address information and data length of the read command; then the mapping table processing module completes the conversion from LBA address to LPA address, and queries the address mapping table to obtain the address information of the data on NAND; the media management module initiates a read request based on the NAND address information item NAND; after the NAND data is read out, the internal data path of the SSD controller sends the data to the host.
[0003] In the existing DRAMless SSD implementation, there is no local DRAM to cache host read command data, which means that all host read commands need to go through the above complete process. Based on the above process analysis, it can be seen that in typical scenarios, the read command response delay mainly lies in the data loading process on the NAND side, resulting in low data reading efficiency. Summary of the invention
[0004] The embodiments of the present invention provide a Dramless SSD read cache implementation method, apparatus, computer equipment and storage medium, aiming to solve the problem of low data reading efficiency in existing Dramless SSD implementation solutions.
[0005] In a first aspect, an embodiment of the present invention provides a method for implementing a Dramless SSD read cache, which includes:
[0006] receiving a first read command, and storing the first read command in a preset cache memory;
[0007] The target data of the first read command is read from the solid state drive, the target data of the first read command is cached in the HMB, and the target data of the first read command is sent to the host address specified by the first read command.
[0008] A further technical solution is that the method further comprises:
[0009] receiving a second read command, and determining whether the second read command hits a read command in the cache memory;
[0010] If the second read command hits the read command in the cache memory, the target data of the second read command is read from the HMB, and the target data of the second read command is sent to the host address specified by the second read command.
[0011] A further technical solution is that the determining whether the second read command hits the read command in the cache memory includes:
[0012] Determining whether a read command identical to the second read command is stored in the cache memory;
[0013] If a read command identical to the second read command is stored in the cache memory, determining that the second read command hits the read command in the cache memory;
[0014] If the cache memory does not store a read command identical to the second read command, it is determined that the second read command does not hit the read command in the cache memory.
[0015] A further technical solution is that before storing the first read command in a preset cache memory, the method further includes:
[0016] Determine whether the command depth of the solid state drive meets the preset command depth requirement;
[0017] If the command depth of the solid state drive meets the preset command depth requirement, the step of storing the first read command in a preset cache memory is performed.
[0018] A further technical solution is that the step of judging whether the command depth of the solid state drive meets a preset command depth requirement includes:
[0019] Determine whether the number of uncompleted read commands of the solid state drive is less than a preset number threshold;
[0020] If the number of uncompleted read commands of the solid state drive is less than a preset number threshold, it is determined that the command depth of the solid state drive meets the preset command depth requirement.
[0021] A further technical solution is that the step of reading the target data of the first read command from the solid state drive includes:
[0022] Parsing and obtaining the logical address contained in the first read command;
[0023] Converting the logical address into a physical address;
[0024] The target data of the first read command is read from the NADA of the solid state drive based on the physical address.
[0025] A further technical solution is that storing the first read command in a preset cache memory includes:
[0026] Obtaining the data amount of the first read command;
[0027] A storage space having the same amount of data as the first read command is applied for in the cache memory, and the first read command is stored in the storage space.
[0028] In a second aspect, an embodiment of the present invention further provides a Dramless SSD read cache implementation device, which includes a unit for executing the above method.
[0029] In a third aspect, an embodiment of the present invention further provides a computer device, which includes a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the above method when executing the computer program.
[0030] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, wherein the storage medium stores a computer program, and the computer program can implement the above method when executed by a processor.
[0031] The embodiments of the present invention provide a method, device, computer equipment and storage medium for implementing Dramless SSD read cache. The method includes: receiving a first read command, storing the first read command in a preset cache memory; reading the target data of the first read command from the solid state drive, caching the target data of the first read command in the HMB, and sending the target data of the first read command to the host address specified by the first read command. By storing the first read command in the preset cache memory and caching the target data of the first read command in the HMB, when the same read command is received, the target data of the read command can be directly read from the HMB and transmitted to the specified host address, reducing the mapping table query and NAND reading process that cause the greatest delay, thereby greatly improving the processing performance, reducing the read delay, and improving the data reading efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying any creative work.
[0033] Figure 1 A flowchart of a Dramless SSD read cache implementation method provided by an embodiment of the present invention;
[0034] Figure 2 Another flowchart of a method for implementing a Dramless SSD read cache provided by an embodiment of the present invention;
[0035] Figure 3 Another flowchart of a method for implementing a Dramless SSD read cache provided by an embodiment of the present invention;
[0036] Figure 4 A schematic block diagram of a computer device provided in an embodiment of the present invention. DETAILED DESCRIPTION
[0037] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0038] It should be understood that when used in this specification and the appended claims, the terms "include" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.
[0039] It should also be understood that the terms used in this specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the specification of the present invention and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.
[0040] It should be further understood that the term "and / or" used in the present description and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.
[0041] As used in this specification and the appended claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined" or "if [described condition or event] is detected" may be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.
[0042] See also Figure 1-Figure 3 The embodiment of the present invention provides a method for implementing a Dramless SSD read cache. The method can improve the data reading efficiency of the Dramless SSD. Figure 1 As shown, the method comprises the following steps:
[0043] S1, receiving a first read command, and storing the first read command in a preset cache memory.
[0044] In a specific implementation, the first read command may be any read command, which is not specifically limited in the embodiment of the present invention. The first read command may be issued by the host. The cache memory may be specifically a cache, which is not specifically limited in the embodiment of the present invention.
[0045] Specifically, in the embodiment of the present invention, when a first read command sent by the host is received, the first read command is stored in a preset cache memory, for example, stored in a cache.
[0046] In some embodiments, the above step of "storing the first read command in a preset cache memory" specifically includes the following steps: obtaining the data amount of the first read command; applying for storage space in the cache memory that is the same as the data amount of the first read command, and storing the first read command in the storage space.
[0047] In a specific implementation, the cache memory is a cache, and a storage space (cache space) having the same amount of data as the first read command is applied for from a cache management module, and the first read command is stored in the storage space.
[0048] In some embodiments, in order to avoid affecting the PCIE bandwidth of the solid-state drive, before storing the first read command in a preset cache memory, the method also includes: determining whether the command depth of the solid-state drive meets the preset command depth requirement; if the command depth of the solid-state drive meets the preset command depth requirement, executing the step of storing the first read command in the preset cache memory.
[0049] In a specific implementation, in a low command depth scenario, the storage process of the first read command will not occupy the PCIE bandwidth. Therefore, the embodiment of the present invention only executes the step of storing the first read command in a preset cache memory in a low command depth scenario to reduce the impact on the PCIE bandwidth.
[0050] In some embodiments, the above step of "determining whether the command depth of the solid-state drive meets the preset command depth requirement" specifically includes the following steps: determining whether the number of unfinished read commands of the solid-state drive is less than a preset number threshold; if the number of unfinished read commands of the solid-state drive is less than the preset number threshold, determining that the command depth of the solid-state drive meets the preset command depth requirement.
[0051] In a specific implementation, the quantity threshold may be set by those skilled in the art according to requirements, and the embodiment of the present invention does not specifically limit this. For example, the quantity threshold may be set to 4. If the number of uncompleted read commands of the solid state drive is less than the preset quantity threshold, it is determined that the command depth of the solid state drive meets the preset command depth requirement; otherwise, it is determined that the command depth of the solid state drive does not meet the preset command depth requirement.
[0052] S2, read the target data of the first read command from the solid state drive, cache the target data of the first read command in the HMB, and send the target data of the first read command to the host address specified by the first read command.
[0053] In a specific implementation, the target data of the first read command is read from the solid state drive, the target data of the first read command is cached in the HMB of the host, and the target data of the first read command is sent to the host address specified by the first read command.
[0054] By caching the target data of the first read command in the HMB of the host, the same data can be directly read from the HMB when it is read later, thereby improving the reading efficiency.
[0055] In some embodiments, the above step of "reading the target data of the first read command from the solid-state drive" specifically includes the following steps: parsing and obtaining the logical address contained in the first read command; converting the logical address into a physical address; and reading the target data of the first read command from the NADA of the solid-state drive based on the physical address.
[0056] In a specific implementation, the logical address is converted into a physical address through a mapping table processing module, and the target data of the first read command is read from the NADA of the solid state drive based on the physical address through a media management module.
[0057] Furthermore, after the SSD controller completes the data transmission, the firmware back-end processing module reports the corresponding completion status to the mapping table management module; after the mapping table management module recovers the back-end request, it reports the command completion status to the front-end firmware module; the front-end firmware module updates the read cache status; and the front-end firmware module reports the command completion information to the host.
[0058] Furthermore, in some embodiments, the method further comprises the following steps:
[0059] S3, receiving a second read command, and determining whether the second read command hits the read command in the cache memory.
[0060] In a specific implementation, the second read command may be any read command, which is not specifically limited in the embodiment of the present invention.
[0061] In the embodiment of the present invention, when a second read command sent by the host is received, it is determined whether the second read command hits the read command in the cache memory. If so, it indicates that the target data requested by the second read command has been requested before.
[0062] In one embodiment, the above step of "determining whether the second read command hits the read command in the cache memory" specifically includes the following steps: determining whether a read command identical to the second read command is stored in the cache memory; if a read command identical to the second read command is stored in the cache memory, determining that the second read command hits the read command in the cache memory; if a read command identical to the second read command is not stored in the cache memory, determining that the second read command does not hit the read command in the cache memory.
[0063] In a specific implementation, it is determined whether the cache memory stores a read command identical to the second read command, that is, the requested target data is the same read command. If the cache memory stores a read command identical to the second read command, it is determined that the second read command hits the read command in the cache memory; if the cache memory does not store a read command identical to the second read command, it is determined that the second read command does not hit the read command in the cache memory.
[0064] S4: If the second read command hits the read command in the cache memory, the target data of the second read command is read from the HMB, and the target data of the second read command is sent to the host address specified by the second read command.
[0065] In a specific implementation, if the second read command hits the read command in the cache memory, it means that the target data of the second read command is stored in the HMB. Therefore, the target data of the second read command is read from the HMB and sent to the host address specified by the second read command.
[0066] Specifically, the SSD front-end module initiates a data transfer request to the SSD controller, and the SSD controller transfers the cache data in the HMB to the address specified by the host read command; after the data transfer is completed, the SSD front-end module reports the command completion information to the host.
[0067] During this process, for host read scenarios that hit the read cache, the mapping table query and NAND read processes that cause the greatest delay are reduced, thereby greatly improving processing performance and reducing read latency.
[0068] The embodiment of the present invention proposes a Dramless SSD read cache implementation method, the method comprising: receiving a first read command, storing the first read command in a preset cache memory; reading the target data of the first read command from the solid state drive, caching the target data of the first read command in the HMB, and sending the target data of the first read command to the host address specified by the first read command. By storing the first read command in the preset cache memory and caching the target data of the first read command in the HMB, when the same read command is received, the target data of the read command can be directly read from the HMB and transmitted to the specified host address, reducing the mapping table query and NAND reading process that cause the greatest delay, thereby greatly improving the processing performance, reducing the read delay, and improving the data reading efficiency.
[0069] Corresponding to the above Dramless SSD read cache implementation method, the present invention also provides a Dramless SSD read cache implementation device. The Dramless SSD read cache implementation device includes a unit for executing the above Dramless SSD read cache implementation method, and the Dramless SSD read cache implementation device can be configured in a desktop computer, a tablet computer, a laptop computer, and other terminals. Specifically, the Dramless SSD read cache implementation device includes:
[0070] A first receiving unit, configured to receive a first read command and store the first read command in a preset cache memory;
[0071] A cache unit is used to read the target data of the first read command from the solid state drive, cache the target data of the first read command in the HMB, and send the target data of the first read command to the host address specified by the first read command.
[0072] In some embodiments, the Dramless SSD read cache implementation device further includes:
[0073] A second receiving unit, configured to receive a second read command, and determine whether the second read command hits the read command in the cache memory;
[0074] A reading unit is used to read the target data of the second read command from the HMB if the second read command hits the read command in the cache memory, and send the target data of the second read command to the host address specified by the second read command.
[0075] In some embodiments, the determining whether the second read command hits the read command in the cache memory includes:
[0076] Determining whether a read command identical to the second read command is stored in the cache memory;
[0077] If a read command identical to the second read command is stored in the cache memory, determining that the second read command hits the read command in the cache memory;
[0078] If the cache memory does not store a read command identical to the second read command, it is determined that the second read command does not hit the read command in the cache memory.
[0079] In some embodiments, the Dramless SSD read cache implementation device further includes:
[0080] A judging unit, used to judge whether the command depth of the solid state drive meets a preset command depth requirement;
[0081] The jump unit is used to jump to the step of storing the first read command in a preset cache memory if the command depth of the solid state drive meets the preset command depth requirement.
[0082] In some embodiments, determining whether the command depth of the solid state drive meets a preset command depth requirement includes:
[0083] Determine whether the number of uncompleted read commands of the solid state drive is less than a preset number threshold;
[0084] If the number of uncompleted read commands of the solid state drive is less than a preset number threshold, it is determined that the command depth of the solid state drive meets the preset command depth requirement.
[0085] In some embodiments, the step of reading the target data of the first read command from the solid state drive includes:
[0086] Parsing and obtaining the logical address contained in the first read command;
[0087] Converting the logical address into a physical address;
[0088] The target data of the first read command is read from the NADA of the solid state drive based on the physical address.
[0089] In some embodiments, storing the first read command in a preset cache memory includes:
[0090] Obtaining the data amount of the first read command;
[0091] A storage space having the same amount of data as the first read command is applied for in the cache memory, and the first read command is stored in the storage space.
[0092] It should be noted that technicians in the relevant field can clearly understand that the specific implementation process of the above-mentioned Dramless SSD read cache implementation device and each unit can refer to the corresponding description in the aforementioned method embodiment, and for the convenience and brevity of description, it will not be repeated here.
[0093] The Dramless SSD read cache implementation device can be implemented in the form of a computer program. The computer program can be used in Figure 4 Runs on the computer device shown.
[0094] See also Figure 4 , Figure 4 5 is a schematic block diagram of a computer device provided in an embodiment of the present application. The computer device 500 may be a terminal or a server, wherein the terminal may be an electronic device with communication functions such as a smart phone, a tablet computer, a laptop computer, a desktop computer, a personal digital assistant, and a wearable device. The server may be an independent server or a server cluster composed of multiple servers.
[0095] The computer device 500 includes a processor 502 , a memory, and a network interface 505 connected via a system bus 501 , wherein the memory may include a non-volatile storage medium 503 and an internal memory 504 .
[0096] The non-volatile storage medium 503 can store an operating system 5031 and a computer program 5032. When the computer program 5032 is executed, the processor 502 can execute a Dramless SSD read cache implementation method.
[0097] The processor 502 is used to provide computing and control capabilities to support the operation of the entire computer device 500 .
[0098] The internal memory 504 provides an environment for the operation of the computer program 5032 in the non-volatile storage medium 503. When the computer program 5032 is executed by the processor 502, the processor 502 can execute a Dramless SSD read cache implementation method.
[0099] The network interface 505 is used to communicate with other devices over the network. Those skilled in the art will appreciate that the above structure is only a block diagram of a portion of the structure related to the present application solution, and does not constitute a limitation on the computer device 500 to which the present application solution is applied. The specific computer device 500 may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.
[0100] The processor 502 is used to run the computer program 5032 stored in the memory to implement the following steps:
[0101] receiving a first read command, and storing the first read command in a preset cache memory;
[0102] The target data of the first read command is read from the solid state drive, the target data of the first read command is cached in the HMB, and the target data of the first read command is sent to the host address specified by the first read command.
[0103] In some embodiments, the method further comprises:
[0104] receiving a second read command, and determining whether the second read command hits a read command in the cache memory;
[0105] If the second read command hits the read command in the cache memory, the target data of the second read command is read from the HMB, and the target data of the second read command is sent to the host address specified by the second read command.
[0106] In some embodiments, the determining whether the second read command hits the read command in the cache memory includes:
[0107] Determining whether a read command identical to the second read command is stored in the cache memory;
[0108] If a read command identical to the second read command is stored in the cache memory, determining that the second read command hits the read command in the cache memory;
[0109] If the cache memory does not store a read command identical to the second read command, it is determined that the second read command does not hit the read command in the cache memory.
[0110] In some embodiments, before storing the first read command in a preset cache memory, the method further includes:
[0111] Determine whether the command depth of the solid state drive meets the preset command depth requirement;
[0112] If the command depth of the solid state drive meets the preset command depth requirement, the step of storing the first read command in a preset cache memory is performed.
[0113] In some embodiments, determining whether the command depth of the solid state drive meets a preset command depth requirement includes:
[0114] Determine whether the number of uncompleted read commands of the solid state drive is less than a preset number threshold;
[0115] If the number of uncompleted read commands of the solid state drive is less than a preset number threshold, it is determined that the command depth of the solid state drive meets the preset command depth requirement.
[0116] In some embodiments, the step of reading the target data of the first read command from the solid state drive includes:
[0117] Parsing and obtaining the logical address contained in the first read command;
[0118] Converting the logical address into a physical address;
[0119] The target data of the first read command is read from the NADA of the solid state drive based on the physical address.
[0120] In some embodiments, storing the first read command in a preset cache memory includes:
[0121] Obtaining the data amount of the first read command;
[0122] A storage space having the same amount of data as the first read command is applied for in the cache memory, and the first read command is stored in the storage space.
[0123] It should be understood that in the embodiment of the present application, the processor 502 may be a central processing unit (CPU), and the processor 502 may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.
[0124] It is understood by those skilled in the art that all or part of the processes in the method for implementing the above embodiment can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a storage medium, which is a computer-readable storage medium. The computer program is executed by at least one processor in the computer system to implement the process steps of the embodiment of the above method.
[0125] Therefore, the present invention also provides a storage medium. The storage medium may be a computer-readable storage medium. The storage medium stores a computer program. When the computer program is executed by a processor, the processor executes the following steps:
[0126] receiving a first read command, and storing the first read command in a preset cache memory;
[0127] The target data of the first read command is read from the solid state drive, the target data of the first read command is cached in the HMB, and the target data of the first read command is sent to the host address specified by the first read command.
[0128] In some embodiments, the method further comprises:
[0129] receiving a second read command, and determining whether the second read command hits a read command in the cache memory;
[0130] If the second read command hits the read command in the cache memory, the target data of the second read command is read from the HMB, and the target data of the second read command is sent to the host address specified by the second read command.
[0131] In some embodiments, the determining whether the second read command hits the read command in the cache memory includes:
[0132] Determining whether a read command identical to the second read command is stored in the cache memory;
[0133] If a read command identical to the second read command is stored in the cache memory, determining that the second read command hits the read command in the cache memory;
[0134] If the cache memory does not store a read command identical to the second read command, it is determined that the second read command does not hit the read command in the cache memory.
[0135] In some embodiments, before storing the first read command in a preset cache memory, the method further includes:
[0136] Determine whether the command depth of the solid state drive meets the preset command depth requirement;
[0137] If the command depth of the solid state drive meets the preset command depth requirement, the step of storing the first read command in a preset cache memory is performed.
[0138] In some embodiments, determining whether the command depth of the solid state drive meets a preset command depth requirement includes:
[0139] Determine whether the number of uncompleted read commands of the solid state drive is less than a preset number threshold;
[0140] If the number of uncompleted read commands of the solid state drive is less than a preset number threshold, it is determined that the command depth of the solid state drive meets the preset command depth requirement.
[0141] In some embodiments, the step of reading the target data of the first read command from the solid state drive includes:
[0142] Parsing and obtaining the logical address contained in the first read command;
[0143] Converting the logical address into a physical address;
[0144] The target data of the first read command is read from the NADA of the solid state drive based on the physical address.
[0145] In some embodiments, storing the first read command in a preset cache memory includes:
[0146] Obtaining the data amount of the first read command;
[0147] A storage space having the same amount of data as the first read command is applied for in the cache memory, and the first read command is stored in the storage space.
[0148] The storage medium is a physical, non-transient storage medium, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a magnetic disk, or an optical disk, etc., which can store program codes. The computer-readable storage medium can be non-volatile or volatile.
[0149] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.
[0150] In the several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of each unit is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.
[0151] The steps in the method of the embodiment of the present invention can be adjusted in order, combined and deleted according to actual needs. The units in the device of the embodiment of the present invention can be combined, divided and deleted according to actual needs. In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.
[0152] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, terminal, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention.
[0153] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0154] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.
[0155] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.
Claims
1. A Dramless SSD read cache implementation method, characterized in that: The method comprises: receiving a first read command, and storing the first read command in a preset cache memory; The target data of the first read command is read from the solid state drive, the target data of the first read command is cached in the HMB, and the target data of the first read command is sent to the host address specified by the first read command.
2. The Dramless SSD read cache implementation method according to claim 1, characterized in that: The method further comprises: receiving a second read command, and determining whether the second read command hits a read command in the cache memory; If the second read command hits the read command in the cache memory, the target data of the second read command is read from the HMB, and the target data of the second read command is sent to the host address specified by the second read command.
3. The Dramless SSD read cache implementation method according to claim 2, characterized in that: The determining whether the second read command hits the read command in the cache memory includes: Determining whether a read command identical to the second read command is stored in the cache memory; If a read command identical to the second read command is stored in the cache memory, determining that the second read command hits the read command in the cache memory; If the cache memory does not store a read command identical to the second read command, it is determined that the second read command does not hit the read command in the cache memory.
4. The Dramless SSD read cache implementation method according to claim 1, characterized in that: Before storing the first read command in a preset cache memory, the method further includes: Determine whether the command depth of the solid state drive meets the preset command depth requirement; If the command depth of the solid state drive meets the preset command depth requirement, the step of storing the first read command in a preset cache memory is performed.
5. The Dramless SSD read cache implementation method according to claim 4, characterized in that: The determining whether the command depth of the solid state drive meets a preset command depth requirement includes: Determine whether the number of uncompleted read commands of the solid state drive is less than a preset number threshold; If the number of uncompleted read commands of the solid state drive is less than a preset number threshold, it is determined that the command depth of the solid state drive meets the preset command depth requirement.
6. The Dramless SSD read cache implementation method according to claim 4, characterized in that: The step of reading the target data of the first read command from the solid state drive includes: Parsing and obtaining the logical address contained in the first read command; Converting the logical address into a physical address; The target data of the first read command is read from the NADA of the solid state drive based on the physical address.
7. The Dramless SSD read cache implementation method according to claim 1, characterized in that: The storing the first read command in a preset cache memory includes: Obtaining the data amount of the first read command; A storage space having the same amount of data as the first read command is applied for in the cache memory, and the first read command is stored in the storage space.
8. A Dramless SSD read cache implementation device, characterized in that: The method comprises a unit for executing the method according to any one of claims 1 to 7.
9. A computer device, characterized in that: The computer device includes a memory and a processor, the memory stores a computer program, and the processor implements the method according to any one of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 7 can be implemented.
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