Data acquisition chip, system and method
By adopting a new data acquisition chip design in the FPGA design and controlling data output using shift scanning chains, the layout and routing difficulties and congestion problems caused by a large number of FIFOs in the FPGA are solved, and more efficient layout and routing are achieved.
Patent Information
- Application Number
- CN202411973810.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2025-04-25
AI Technical Summary
In FPGA design, when using a large number of FIFOs for data acquisition, it is easy to cause too long or failure in layout and routing, and the aggregation structure of FIFOs will cause difficulty or failure in layout and routing.
Using a new data acquisition chip design, including a first number of first-in-first-out buffers, a second number of shift registers and a second number of data selectors, the output of data is controlled through a shift scan chain, and all first-in-first-out buffers are laid out into one chain to avoid FIFO aggregation and wiring congestion caused by traditional reading methods.
It effectively avoids the first-in-first-out buffer aggregation caused by traditional reading layout, solves the problem of wiring congestion, improves the efficiency of FPGA layout and wiring, and ensures the compilation pass rate and DUT operation frequency.
Smart Images
Figure CN119883180A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of data acquisition technology, and in particular to a data acquisition chip, system and method. Background Art
[0002] The FIFO (First Input First Output) used in the Field Programmable Gate Array (FPGA) generally refers to a buffer with a first-in-first-out feature for data storage. It is often used for data caching or high-speed asynchronous data interaction, that is, cross-clock domain signal transmission. Most FPGA designs use block random access memory (BRAM) to implement FIFO. When a large number of signals need to be collected, a large number of FIFOs need to be used. Too many FIFOs implemented with BRAM will cause the FPGA layout and routing time to be too long or fail. And when the number of FIFOs used is large, selectors are generally used to select data output from multiple FIFOs one by one. This structure will eventually be a tree structure, which will cause the FIFOs to aggregate during layout, resulting in difficulties or failures in layout and routing. Summary of the invention
[0003] The present invention provides a data acquisition chip, system and method, which can avoid the wiring congestion caused by the aggregation of first-in-first-out buffers caused by the traditional read mode layout.
[0004] In a first aspect, an embodiment of the present invention provides a data acquisition chip, comprising: a first number of first-in-first-out buffers, a second number of shift registers, and a second number of data selectors;
[0005] Each of the shift registers is connected via a data selector, the last shift register is connected to a data selector, the first FIFO buffer is connected to the first shift register, and the other FIFO buffers are connected to a data selector respectively;
[0006] The first number is one greater than the second number.
[0007] In a second aspect, an embodiment of the present invention provides a data acquisition system, including:
[0008] A data acquisition chip as described in the first aspect embodiment.
[0009] In a third aspect, an embodiment of the present invention provides a data acquisition method, which is performed by the data acquisition system described in the embodiment of the second aspect, and the method includes:
[0010] detecting a state of a first first-in-first-out buffer in the data acquisition system;
[0011] When it is detected that the first FIFO buffer is in a non-empty state, a high level of one clock cycle is generated at the shift enable terminal in the data acquisition system, and the data in the FIFO buffer in the data acquisition system starts to be output;
[0012] In the next cycle of the non-empty state, a high level of one clock cycle is generated at the read enable terminal in the data acquisition system to start reading the data in each first-in-first-out buffer in the data acquisition system;
[0013] After executing a set number of clock cycles, returning to re-execute the step of detecting the state of the first FIFO buffer in the data acquisition system, the set number is equal to the number of shift registers in the data acquisition system.
[0014] The embodiment of the present invention provides a data acquisition chip, system and method, the chip includes a first number of first-in-first-out buffers, a second number of shift registers and a second number of data selectors; each of the shift registers is connected through a data selector, the last shift register is connected to a data selector, the first first-in-first-out buffer is connected to the first shift register, and the other first-in-first-out buffers are connected to a data selector; the first number is one more than the second number. The above technical solution, in order to solve the problem of slow or failed layout and wiring in the above scenario, designs a new data output method for reading the first-in-first-out buffer, adopts a shift scan chain to control the output of data, so that all the first-in-first-out buffers can be laid out into a chain, thereby avoiding the aggregation of the first-in-first-out buffers caused by the traditional read layout method and causing wiring congestion.
[0015] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0017] Figure 1 A schematic diagram of the structure of a data shift chain in a data acquisition chip provided in the first embodiment of the present invention;
[0018] Figure 2A schematic diagram of the structure of a data shift chain in another data acquisition chip provided in the first embodiment of the present invention;
[0019] Figure 3 A schematic diagram of the structure of a read shift chain in a data acquisition chip provided in the first embodiment of the present invention;
[0020] Figure 4 A structural diagram of a data acquisition system provided in Embodiment 2 of the present invention;
[0021] Figure 5 A flowchart of a data collection method provided in Embodiment 3 of the present invention. DETAILED DESCRIPTION
[0022] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.
[0023] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0024] It should be noted that the FIFO used in FPGA generally refers to a buffer with a first-in, first-out feature for data storage, which is often used for data caching or high-speed asynchronous data interaction, that is, cross-clock domain signal transmission. Most FPGA designs use BRAM to implement FIFO. When a large number of signals need to be collected, a large number of FIFOs are required. The following is an example of an FPGA-based prototype verification system or an FPGA-based hardware simulation accelerator.
[0025] In an FPGA-based prototype verification system or an FPGA-based hardware simulation accelerator, when users simulate their own DUT, they often need to capture the waveform of the signal they are concerned about to troubleshoot the DUT problem. DUT (Device Under Test) is a device or circuit that needs to be verified during the test process. To achieve this function, the prototype verification system and the hardware simulation accelerator tool will connect the user-marked signal to the signal acquisition module inserted into the tool. This module will package the sampled data and transmit it to the storage device through a high-speed interface. Finally, the software reads the data and restores the waveform to the user. From this function, it can be seen that it is divided into two functions: signal acquisition and transmission. The two functions are generally not completed in the same clock domain, and will be processed across clock domains through FIFO.
[0026] Therefore, when the user marks a large number of signals to view the waveform, the acquisition module will instantiate a large number of FIFOs to acquire the signals. Since the acquisition module and the DUT are implemented in the same FPGA, in this case, too many FIFOs implemented with BRAM will cause the FPGA layout and routing time to be too long or fail, thereby causing the user to fail to simulate the DUT. In addition, when a large number of FIFOs are used, a selector is generally used to read the FIFO data and select the data output from multiple FIFOs one by one. This structure will eventually be a tree structure, which will cause the FIFOs to aggregate during layout, resulting in difficulties or failures in layout and routing.
[0027] Embodiment 1
[0028] Figure 1 The structure diagram of a data shift chain in a data acquisition chip provided in the first embodiment of the present invention is shown in FIG. 1 . The method can be applied to the case where data acquisition is realized based on a first-in-first-out buffer. The chip can be integrated into a data acquisition system. Figure 1 As shown, the data acquisition chip provided in the first embodiment may specifically include: a first number of first-in-first-out buffers 11, a second number of shift registers 12, and a second number of data selectors 13;
[0029] Each of the shift registers 12 is connected via a data selector 13, the last shift register 12 is connected to a data selector 13, the first FIFO buffer 11 is connected to the first shift register 12, and the other FIFO buffers 11 are connected to a data selector 13 respectively;
[0030] The first number is one greater than the second number.
[0031] In this embodiment, the data acquisition chip adopts a new data scanning method to realize the reading and transmission of the first-in-first-out buffer data, which can be applied to the FPGA prototype verification system and the FPGA-based hardware simulation accelerator system and other scenarios using FPGA, and no specific restrictions are made here. By controlling the reading data of the first-in-first-out buffer through a shift chain table, and controlling the output of the first-in-first-out buffer reading data through another shift chain table, the problem of layout and routing congestion is easily caused when a large number of first-in-first-out buffers are used to collect a large amount of data in the FPGA.
[0032] Following the above description, the shift chain table is mainly used to control the output of the first-in-first-out buffer read data. The structure of the data shift chain includes a first-in-first-out buffer (FIFO in the figure) 11, a shift register 12 and a data selector 13. The number of the first-in-first-out buffer 11 is recorded as a first number, and the number of the shift register 12 and the data selector 13 is the same, which is recorded as a second number. The first number is one more than the second number. The shift register 12 is mainly used to store and move data. Figure 1 As shown, the structure of the data shift chain includes n FIFOs, which are respectively recorded as FIFO 0, FIFO 1, FIFO 2, ..., FIFOn-1. Each FIFO includes a data write terminal (Data in), which are respectively recorded as data write terminal n-1, data write terminal n-2, data write terminal n-3, ..., data write terminal 0; includes n-1 shift registers (Shift reg), which are respectively recorded as shift register 0, shift register 1, ..., shift register n-2; and includes n-1 data selectors (mux).
[0033] In this embodiment, the structure of the data shift chain can be described as follows: each shift register 12 is connected via a data selector 13, the last shift register 12 is connected to a data selector 13, the first FIFO buffer 11 is connected to the first shift register 12, and the other FIFO buffers 11 are connected to a data selector 13 respectively.
[0034] Exemplarily, an FPGA prototype verification system or an FPGA-based hardware simulation accelerator is used as an example to illustrate that the waveform signal to be captured marked by the user will be recognized and counted by the tool and then connected to the FIFO Data in port of the sampling module. This port is the data write port of the first-in-first-out buffer. The write clock of the first-in-first-out buffer uses the signal sampling clock specified by the user. The write enable is controlled by the control software. When enabled, one frame of data will be collected and written to the first-in-first-out buffer in each sampling clock cycle. Figure 1 As shown in the figure, the input and output data bit width of each FIFO is m. When the signal to be marked by the user exceeds m, it will be divided into n groups.
[0035] It should be noted that, since the data write port of the FIFO buffer and the user-marked signal can be inserted into a multi-level register, it is possible to prevent the FIFO buffer from causing layout and routing difficulties due to the write port.
[0036] In this embodiment, the data output process of the first-in-first-out buffer can be described as follows: after each first-in-first-out buffer is written with data, it is necessary to use an m bits width transmission channel to transmit the data in each first-in-first-out buffer. Therefore, it is necessary to read the first-in-first-out buffer 11 in sequence in a certain order under the data transmission clock domain, and at the same time receive data from the data output end of the first-in-first-out buffer 11 in sequence, and then send the data out through the high-speed port after packaging the data.
[0037] In order to solve the problem of slow or failed layout and routing in the above scenarios, the above technical solution designs a new data output method for reading the FIFO buffer, which uses a shift scan chain to control the output of data so that all FIFO buffers can be laid out into a chain, thereby avoiding the aggregation of FIFO buffers caused by the traditional read layout method and causing routing congestion.
[0038] Continue to refer Figure 1 As a specific implementation method, it can be optimized that the output end of each shift register 12 is respectively connected to the first input end of each data selector 13, the output end of the first FIFO buffer 11 is connected to the input end of the first shift register 12, the output ends of the other FIFO buffers 11 are respectively connected to the second input ends of the data selectors 13, and the input ends of the other shift registers 12 are respectively connected to the output ends of the data selectors 13.
[0039] In this embodiment, the data selector 13 can adopt a two-choice channel selector, such as a mux. One input end of each data selector 13 is respectively connected to the output end of each shift register 12, and is used to obtain the data of the upper shift register 12 when the channel is connected. The other input end of each data selector 13 is respectively connected to the output end of each first-in-first-out buffer (except the first first-in-first-out buffer) 11, and is used to directly obtain the data in each first-in-first-out buffer 11 when the channel is connected. For the first first-in-first-out buffer 11, its output end is connected to the input end of the first shift register 12. The input ends of other shift registers 12 are respectively connected to the output ends of the data selector 13.
[0040] Figure 2A structural schematic diagram of a data shift chain in another data acquisition chip provided in the first embodiment of the present invention is provided. As an optional embodiment of the embodiment of the present invention, on the basis of the above embodiment, each of the data selectors 13 can be optimized to be connected to the same shift enable terminal 15 through an enable register 14, and each of the enable registers 14 is connected in sequence.
[0041] In this embodiment, the data shift chain structure in the data acquisition chip includes an enable register 14 in addition to a first-in-first-out buffer 11, a shift register 12 and a data selector 13. The number of enable registers 14 is the same as the number of data selectors 13, which is recorded as the second number. Each data selector 13 is also connected to an enable register 14, and the function of the enable register 14 is to control whether the data selector 13 receives a high level or a low level, thereby turning on which channel. Each enable register 14 is connected to the same shift enable terminal 15, and each enable register 14 is connected in sequence. Continue to refer to Figure 2 The data acquisition chip also includes n-1 enable registers (en_r), which are respectively recorded as enable register 0, enable register 1, ..., enable register n-2.
[0042] Continue to refer Figure 2 As a specific implementation, the default value of each of the enable registers 14 is a low level, and the input end of each of the enable registers 14 is respectively connected to the shift enable end 15 to receive the shift enable signal through the shift enable end 15.
[0043] In this embodiment, the default value of each of the enable registers 14 is a low level. Figure 2 As shown, the enable register 0 is set to 1'b0, and the input terminals of the enable registers 14 are respectively connected to the shift enable terminals 15, and receive the shift enable signal through the shift enable terminals 15. The shift enable signal is a binary signal used to implement control, with a high level (1) indicating enable and a low level (0) indicating disable.
[0044] As a specific implementation method, it can be optimized.
[0045] When the shift enable signal is at a high level, the first input end of each of the data selectors 13 is turned on, and the data in the connected FIFO buffer 11 is selected to the output end of the data selector 13;
[0046] When the shift enable signal is at a low level, the second input end of each of the data selectors 13 is turned on, and the data in the connected upper shift register 12 is selected to the output end of the data selector 13 .
[0047] Continue to refer Figure 2In this embodiment, the processing of the sampled data can be described as follows:
[0048] 1) Except for FIFO 0, each FIFO data output port has a data selector 13 that selects one of two. When the selection control signal of the data selector 13 is 0, the data of FIFO 11 is selected to the output port of the data selector 13, otherwise the upper shift register 12 is selected to output data to the output port of the data selector 13;
[0049] 2) The selection control signal of each data selector 13 is controlled by the output signal of the enable register 14. The enable register 14 is 0 by default. At this time, all the enable registers 14 sample data from the output port of the FIFO 11. This is called the sampling state;
[0050] 3) When the shift enable terminal (shift_ena) 15 generates a high-level signal for one clock cycle, all shift registers (en_r) 14 will be set to 1. At this time, except for the shift register (shift reg) 0, all other shift registers sample data from the output port of the upper shift register. This is called the shift state;
[0051] 4) In the shift state, since the enable register 14 is set and then released after one clock cycle, they are cleared to 0 one by one starting from en_r0, so that after n-1 clock cycles, all the enable registers 14 become 0, and the shift register 13 returns to the sampling state.
[0052] Based on the above description, it can be known that in the sampling state, as long as the shift enable terminal 15 is pulled high for one clock cycle, the output data of the first-in-first-out buffer will be output from the data output terminal (Dataout) in the order from FIFO n-1 to FIFO 0; when one round of output is completed, if all FIFO output data have been updated, the shift enable terminal 15 is pulled high for one clock cycle again to start the next round of output, thereby realizing back-to-back transmission.
[0053] Figure 3 A structural schematic diagram of a read shift chain in a data acquisition chip provided in Embodiment 1 of the present invention is provided. As an optional embodiment of the embodiment of the present invention, on the basis of the above embodiment, the chip can be optimized to also include a second number of read registers 16; each of the first-in-first-out buffers 11 is also connected via one of the read registers 16.
[0054] It should be noted that the FIFO buffer in the present embodiment uses an output data first-out type FIFO buffer. The characteristic of this FIFO buffer is that when the FIFO buffer is in a non-empty state, there is no need to send a read request, and the data output port of the FIFO buffer outputs the valid data pointed to by the current read pointer. After sending a read request, if the FIFO buffer is in a non-empty state, the output port outputs the next valid data, otherwise it outputs an invalid value. However, at this time, if the FIFO buffer is written with a new valid value and becomes a non-empty state, the output port data of the FIFO buffer will also output a valid value accordingly. This is equivalent to the first valid data in the FIFO buffer being output without a read request, and for non-first valid data, a read request is required to output the valid data.
[0055] Based on the above description, the structure of the read control shift chain of the FIFO buffer in the signal acquisition chip may include: read registers 16, the number of which is one less than the number of FIFO buffers 11, recorded as the second number. Each FIFO buffer 11 is connected via a read register 16.
[0056] Continue to refer Figure 3 As a specific implementation method, the input ends of the first read register and the first first-in-first-out buffer 11 can be optimized to be connected to the same read enable end 17, the output end of the last read register 16 is connected to the input end of the last first-in-first-out buffer 11, and the output ends of the other read registers 15 are respectively connected to the input ends of other first-in-first-out buffers 11 and the input ends of the lower-level read registers 16.
[0057] In this embodiment, the read enable terminal 17 can be specifically understood as controlling the FIFO buffer to enable or disable data reading, with a high level (1) indicating enable and a low level (0) indicating disable. The read signals of each FIFO buffer 11 are cascaded by the read register 16. Specifically, the input terminals of the first read register 16 and the first FIFO buffer 11 are both connected to a read enable terminal 17, the output terminal of the last read register 16 is connected to the input terminal of the last FIFO buffer 11, and the output terminals of the other read registers 16 are respectively connected to the input terminals of the other FIFO buffers 11 except the first FIFO buffer, and the input terminals of the lower read registers 16.
[0058] As a specific implementation, the default value of each of the read registers 16 is a low level, the input end of the first read register 16 is connected to the read enable end 17 , and a read enable signal is received through the read enable end 17 .
[0059] Continue to refer Figure 3, the read signals of each FIFO buffer 11 are cascaded by the read register 16, and these read registers are defaulted to low level (0). Under this structure, when a cycle of read enable signal is generated at the read enable terminal (FIFO read) 17, a read operation will be generated on FIFO0 to FIFO n-1 in sequence, so that the data output of FIFO0 to FIFOn-1 is updated.
[0060] The above technical solution uses a shift scan chain to control the reading of the first-in-first-out buffer, and uses another shift scan chain to control the output of data to realize data acquisition. It has strong versatility and can be used in various types of FPGAs. There is no obvious increase in the use of logic resources, which is more conducive to layout and wiring, improves the compilation pass rate, and increases the DUT operating frequency.
[0061] Embodiment 2
[0062] Figure 4 This is a schematic diagram of the structure of a data acquisition system provided in the second embodiment of the present invention. The system is applicable to the case where data acquisition is implemented based on a first-in-first-out buffer. The system can be implemented in the form of hardware and / or software.
[0063] like Figure 4 As shown, a data acquisition system provided by the second embodiment of the present invention includes: a data acquisition chip provided by the first embodiment.
[0064] Embodiment 3
[0065] Figure 5 The flowchart of a data acquisition method provided in the third embodiment of the present invention is applicable to the case of realizing data acquisition based on a first-in-first-out buffer, and the method can be executed by the data acquisition system described in the second embodiment. Figure 5 As shown, a data collection method provided by Embodiment 3 of the present invention may specifically include:
[0066] S201, detecting the state of the first FIFO buffer in the data acquisition system.
[0067] In this embodiment, a shift scan chain is used to control the reading of the first-in-first-out buffer, and another shift scan chain is used to control the output of data. By combining the shift chains of these two structures and implementing control according to the following process, the first-in-first-out buffer can be read in turn.
[0068] Specifically, the state of the first FIFO buffer (FIFO 0) is first detected until the empty signal changes to a non-empty state.
[0069] S202: When it is detected that the first FIFO buffer is not empty, a high level of one clock cycle is generated at the shift enable terminal in the data acquisition system, and the data in the FIFO buffer in the data acquisition system starts to be output.
[0070] In this embodiment, when it is detected that the first FIFO buffer is in a non-empty state, a high level of one cycle is generated at the shift enable terminal (shift_ena), and the output of the data in the FIFO buffer begins. In this embodiment, the processing of the sampled data can be described as:
[0071] 1) Except for FIFO 0, each FIFO data output port has a two-choice data selector. When the selection control signal of the data selector is 0, the data of the FIFO is selected to the output port of the data selector, otherwise the upper shift register is selected to output data to the output port of the data selector;
[0072] 2) The selection control signal of each data selector is controlled by the output signal of the enable register. The enable register is 0 by default. At this time, all enable registers sample data from the FIFO output port, which is called the sampling state;
[0073] 3) When the shift enable terminal (shift_ena) generates a high-level signal for one clock cycle, all shift registers (en_r) will be set to 1. At this time, except for the shift register (shift reg) 0, all other shift registers sample data from the output port of the upper shift register. This is called the shift state;
[0074] 4) In the shift state, since the enable register is set and then released after one clock cycle, they are cleared to 0 one by one starting from en_r0, so that after n-1 clock cycles, all the enable registers become 0 and the shift register returns to the sampling state.
[0075] Based on the above description, it can be known that in the sampling state, as long as the shift enable terminal is pulled high for one clock cycle, the output data of the first-in-first-out buffer will be output from the data output terminal (Data out) in the order from FIFO n-1 to FIFO 0; when one round of output is completed, if all FIFO output data has been updated, the shift enable terminal is pulled high for one clock cycle again to start the next round of output, thereby realizing back-to-back transmission.
[0076] S203. In the next cycle of the non-empty state, a high level of one clock cycle is generated at the read enable terminal in the data acquisition system to start reading data in each first-in-first-out buffer in the data acquisition system.
[0077] In this embodiment, in the next cycle of the non-empty state, a high level of one cycle is generated at the read enable terminal (fifo_read) to start reading the first-in-first-out buffer. Specifically, the read signals of each first-in-first-out buffer are cascaded by the read registers, and these read registers are defaulted to a low level (0). Under this structure, when a read enable signal of one cycle is generated at the read enable terminal (FIFO read), a read operation will be generated on FIFO0 to FIFO n-1 in sequence, so that the data output of FIFO0 to FIFON-1 is updated.
[0078] S204, after executing a set number of clock cycles, return to re-execute the step of detecting the state of the first FIFO buffer in the data acquisition system.
[0079] The set number is equal to the number of shift registers in the data acquisition system. For example, assuming that the number of first-in-first-out buffers is n, then the number of shift registers is n-1, and the set number is also n-1. Then, after n-1 clock cycles, return to step S201.
[0080] In order to solve the problem of slow or failed layout and routing in the above scenarios, the above technical solution adopts a new first-in-first-out read control method and read data output method, using a shift scan chain to control the reading of FIFO, and using another shift scan chain to control the output of data, so that all FIFOs can be laid out into a chain, thereby avoiding FIFO aggregation caused by traditional read layout and causing wiring congestion.
[0081] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.
[0082] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims
1. A data acquisition chip, characterized in that: include: A first number of first-in-first-out buffers, a second number of shift registers, and a second number of data selectors; Each of the shift registers is connected via a data selector, the last shift register is connected to a data selector, the first FIFO buffer is connected to the first shift register, and the other FIFO buffers are connected to a data selector respectively; The first number is one greater than the second number.
2. The data acquisition chip according to claim 1, characterized in that: The output end of each shift register is connected to the first input end of each data selector, the output end of the first first-in-first-out buffer is connected to the input end of the first shift register, the output ends of the other first-in-first-out buffers are connected to the second input ends of the data selectors, and the input ends of the other shift registers are connected to the output ends of the data selectors.
3. The data acquisition chip according to claim 2, characterized in that: It also includes a second number of enable registers, each of the data selectors is connected to the same shift enable terminal via an enable register, and the enable registers are connected in sequence.
4. The data acquisition chip according to claim 3, characterized in that: The default value of each of the enable registers is a low level, and the input end of each of the enable registers is respectively connected to the shift enable end, and receives a shift enable signal through the shift enable end.
5. The data acquisition chip according to claim 4, characterized in that: When the shift enable signal is at a high level, the first input end of each of the data selectors is turned on, and the data in the connected first-in-first-out buffer is selected to the output end of the data selector; When the shift enable signal is at a low level, the second input end of each of the data selectors is turned on, and the data in the connected upper shift register is selected to the output end of the data selector.
6. The data acquisition chip according to claim 1, characterized in that: Also including a second number of read registers; Each of the first-in-first-out buffers is also connected via a read register.
7. The data acquisition chip according to claim 6, characterized in that: The input ends of the first read register and the first first-in-first-out buffer are both connected to the same read enable end, the output end of the last read register is connected to the input end of the last first-in-first-out buffer, and the output ends of the other read registers are respectively connected to the input ends of other first-in-first-out buffers and the input ends of the lower-level read registers.
8. The data acquisition chip according to claim 7, characterized in that: The default value of each of the read registers is a low level, and the input terminal of the first read register is connected to the read enable terminal, and receives a read enable signal through the read enable terminal.
9. A data acquisition system, characterized in that: include: A data acquisition chip as described in any one of claims 1 to 8.
10. A data collection method, characterized in that: Executed by the data acquisition system of claim 9, the method comprising: detecting a state of a first first-in-first-out buffer in the data acquisition system; When it is detected that the first FIFO buffer is in a non-empty state, a high level of one clock cycle is generated at the shift enable terminal in the data acquisition system, and the data in the FIFO buffer in the data acquisition system starts to be output; In the next cycle of the non-empty state, a high level of one clock cycle is generated at the read enable terminal in the data acquisition system to start reading the data in each first-in-first-out buffer in the data acquisition system; After executing a set number of clock cycles, returning to re-execute the step of detecting the state of the first FIFO buffer in the data acquisition system, the set number is equal to the number of shift registers in the data acquisition system.