Control method of approximate addition circuit based on memristor and approximate addition operation device

Abstract

The invention discloses a control method of an approximate addition circuit based on a memristor and an approximate addition operation device, and belongs to the technical field of microelectronic logic operation. By utilizing the storage and calculation integrated characteristic of a memristor, a carry ci + 1 is set to be one of three input values of ai, bi and ci, and voltage is synchronously applied to each port of an approximate addition circuit, so that majority gate logic operation after carry negation is realized, and addition results s1, s2,..., sn of each bit are obtained in parallel; by means of the approximate addition design, it is not needed to wait for carry calculation of the last bit, parallel multi-bit addition operation is efficiently achieved, and the calculation speed is high; according to the method, the number of required devices and operation steps is small, approximate addition operation can be achieved at a high calculation speed under the condition that few devices and operation steps are adopted, hardware resource consumption is reduced, and particularly, the performance is remarkably improved when big data streams are processed and high-speed operation is conducted.

Description

Technical Field

[0001] The present invention belongs to the technical field of microelectronic logic operation, and more specifically, relates to a control method of an approximate addition circuit based on a memristor and an approximate addition operation device. Background Art

[0002] Traditional computers use the von Neumann architecture, in which the storage unit and the processing unit are physically separated. Usually, the processing unit reads data from the storage unit, completes the corresponding arithmetic and logical operations, and then writes the data back to the storage unit. The reading of stored information and the transportation of data flow bring huge requirements to the peripheral reading circuit and control circuit, and also bring great consumption and challenges to the data transmission bus, and even cause great power consumption loss. In addition, engineers usually need to adjust the speed between the processing unit, the storage unit and even the bus in order to achieve the best match and reduce the idle consumption between the units. However, this match is difficult to achieve, which often results in unreasonable resource allocation and utilization between the units. Therefore, better solving the "bottleneck problem" and "storage wall" problems existing in the existing von Neumann architecture in computers has become a research focus in the field of computer architecture.

[0003] In order to break through these bottlenecks, the integrated computing technology came into being. This technology integrates computing and storage functions on the same hardware platform, achieving advantages such as high computing parallelism, low latency and low power consumption, and has gradually become a research hotspot in academia and industry. As a new type of non-volatile memory device, memristor has the advantages of low power consumption, small size and compatibility with CMOS process, making it an ideal candidate device for in-memory computing architecture. Memristor can store information by changing its resistance state and can still maintain its resistance state after power failure, so it is naturally suitable for digital logic operations.

[0004] Approximate computing is a computing paradigm that can overcome the "power wall" of computer architecture. It allows a certain amount of error to be introduced in the calculation process in exchange for increased computing speed, reduced energy consumption or resource savings. This computing method is particularly suitable for application scenarios that do not require very high result accuracy but are very sensitive to response time or cost. It is widely used in image processing, artificial intelligence, signal processing and other fields.

[0005] The design of the approximate adder based on memristors provides a new hardware solution by combining the advantages of in-memory computing and the flexibility of approximate computing. However, in the process of multi-bit addition operations, the calculation of the summation result and the carry output of the existing memristor-based approximate adder requires a lot of computing resources and time, and the calculation of the output value of the next bit depends on the carry calculation of the previous bit. If the carry calculation of the previous bit is not completed, the output value calculation and the carry calculation of the current bit cannot be performed, resulting in a huge waste of resources and time loss. Summary of the invention

[0006] In view of the above defects or improvement needs of the prior art, the present invention provides a control method and an approximate addition operation device of an approximate addition circuit based on a memristor, the purpose of which is to realize multi-bit approximate addition operation at a faster calculation speed under the condition of using fewer devices and operation steps.

[0007] In order to achieve the above-mentioned object, in a first aspect, the present invention provides a control method of an approximate addition circuit based on a memristor, for realizing an n-bit number a=a n ......a2a1 and b=b n ...approximate addition of b2b1; The approximate addition circuit includes a memristor array and n identical resistors R1, R2, ..., R n The memristor array includes a plurality of identical memristors arranged in n rows and 3 columns, and the positive electrodes of the memristors in the jth column are all connected to the bit line BL j The negative electrodes of the memristors in the i-th row are all connected to the word line WL i Upper: word line WL i One end is left floating and the other end is connected to R i One end is connected to R i The other end is T 4i Port: the negative electrode of the i-th row memristor and the word line WL i The connection points are located on the word line WL i The floating end and R i n≥1; j=1,2,3; i=1,2,...,n; the resistance value of the resistor is the same as the low resistance value of the memristor; The above control method includes: Initialize the memristor array: set all memristors on the output column to high impedance state, and write the i-th bit number of the first input number and the second input number into the i-th row of memristors in the two input columns; Connect a voltage with an amplitude of 0 to the T1 port and the T2 port, and connect a fixed voltage V to the T3 port. cond , in T 41 ,T 42 ,...,T4n The ports are connected to voltages V1, V2, ..., V n ; Read the logical value s1, s2, ..., s corresponding to the resistance state of each memristor in the output column n ; will s n ...s2s1 and c n+1 As the approximate addition result and carry of a and b respectively; Among them, the two input columns are two columns selected arbitrarily from the memristor array; the output column is an unselected column in the memristor array; the T1 port and the T2 port are the ports of the bit lines where the two input columns are located, and the T3 port is the port of the bit line where the output column is located; the first input number and the second input number are two numbers selected arbitrarily from a, b, and c; the third input number is a number not selected from a, b, and c; c=c n ......c2c1; when the third input number is a, c i+1 = a i ; When the third input number is b, c i+1 =b i ; When the third input number is c, c i+1 = c i , c1 is the preset initial carry; if the i-th bit number in the third input number is 0, then V i =V p Otherwise, V i =2V p ; 2V p / 3 <V cond -V set <V p ,max{V p , (V p +V cond ) / 3, (2V p +V cond ) / 4}<|V reset |;V set V is the threshold value of the memristor changing from high resistance state to low resistance state; reset is the threshold value at which the memristor changes from a low-resistance state to a high-resistance state.

[0008] Further preferably, when the third input number is c, the above approximate addition circuit further comprises: a memristor M4; the positive electrode of the memristor M4 is used as the T5 port, and the negative electrode is connected to the word line WL n On the word line WL n The floating end and R n between; The above control method also includes optimizing operations: Set the memristor M4 to a high impedance state and set the T3 port to a floating state; Connect a voltage with an amplitude of 0 to the T1 port and the T2 port, and connect a fixed voltage V to the T5 port. cond , in T 4n The port is connected to the voltage V; the logic value corresponding to the resistance state of the memristor M4 is read as c n+1 The final result; If c1 is 0, then V i =V p Otherwise, V i =2V p .

[0009] More preferably, V cond = 2V set ; V p =1.2V set .

[0010] Further preferably, the corresponding logic value is written by setting the high and low resistance states of the memristor; wherein the high resistance state of the memristor corresponds to the logic value "0", and the low resistance state corresponds to the logic value "1".

[0011] In a second aspect, the present invention provides an approximate addition operation device, comprising: an approximate adder circuit and a controller; The approximate addition circuit includes a memristor array and n identical resistors R1, R2, ..., R n The memristor array includes a plurality of identical memristors arranged in n rows and 3 columns, and the positive electrodes of the memristors in the jth column are all connected to the bit line BL j The negative electrodes of the memristors in the i-th row are all connected to the word line WL i Upper: word line WL i One end is left floating and the other end is connected to R i One end is connected to R i The other end is T 4i Port: the negative electrode of the i-th row memristor and the word line WL i The connection points are located on the word line WL i The floating end and R i n≥1; j=1,2,3; i=1,2,...,n; the resistance value of the resistor is the same as the low resistance value of the memristor; The controller is used to execute the control method provided by the first aspect of the present invention.

[0012] Further preferably, the above approximate addition circuit further includes: a memristor M4; the positive electrode of the memristor M4 is used as the T5 port, and the negative electrode is connected to the word line WL n On the word line WL n The floating end and R n between; The controller is also used to execute the optimization operation in the control method provided in the first aspect of the present invention.

[0013] Further preferably, a switching ratio of each memristor in the approximate adding circuit is greater than or equal to 100.

[0014] In a third aspect, the present invention provides a control system, comprising: a memory and a processor, wherein the memory stores a computer program, and the processor executes the control method provided in the first aspect of the present invention when executing the computer program.

[0015] In a fourth aspect, the present invention further provides a computer-readable storage medium, which includes a stored computer program, wherein when the computer program is executed by a processor, the device where the storage medium is located is controlled to execute the control method provided in the first aspect of the present invention.

[0016] In a fifth aspect, the invention further provides a computer program product, comprising a computer program / instruction, which, when executed by a processor, implements the control method provided in the first aspect of the invention.

[0017] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects: 1. The present invention provides a control method for an approximate addition circuit based on a memristor and a corresponding approximate addition operation device, which utilizes the storage-computation-in-one characteristic of the memristor to carry out the addition of the carry c. i+1 Set to a i , b i and c i One of the three input values, and by synchronously applying voltage to each port of the approximate addition circuit, the majority gate logic operation after carry inversion is realized, so that the sum of each bit s1, s2, ..., s is obtained in parallel. n ; Through the above-mentioned approximate addition design, the present invention does not need to wait for the carry calculation of the previous bit, and completes the carry calculation of all bits in the initial writing link. The calculation of the sum results of different bits can be performed simultaneously, and the parallel multi-bit addition operation is efficiently realized with a faster calculation speed; and the number of devices and operation steps required for the present invention are relatively small, and the approximate addition operation can be realized at a faster calculation speed under the condition of using fewer devices and operation steps, thereby reducing the consumption of hardware resources, and showing a significant performance improvement especially when processing large data streams and high-speed operations.

[0018] 2. Further, the control method of the memristor-based approximate addition circuit and the corresponding approximate addition operation device provided by the present invention, when the third input number is c, by setting the memristor M4 to a high impedance state, setting the T3 port to a suspended state; respectively connecting a voltage with an amplitude of 0 to the T1 port and the T2 port, and connecting a fixed voltage V to the T5 portcond , in T 4n The port is connected to the voltage V, so that the carry c is obtained in the memristor M4 n+1 = a n b n As c n+1 The final result; the above operation can further improve the accuracy of n-bit approximate calculation.

[0019] 3. Further, in the control method of the memristor-based approximate adding circuit provided by the present invention, V cond =2V set ; V p =1.2V set The results of the majority logic calculations used in the present invention are stored in the resistance states of the memristors in the output columns. Selecting the above two voltage values ​​can make the change windows of the resistance states of the memristors in the output columns caused by different inputs roughly the same, thereby more accurately realizing the change of the resistance states of the memristors in the output columns, thereby further improving the accuracy of the calculations.

[0020] 4. Furthermore, in the control method of the memristor-based approximate addition circuit and the corresponding approximate addition operation device provided by the present invention, the switching ratio of each memristor in the approximate addition circuit is greater than or equal to 100, and the memristor switching ratio directly affects the resistance state change window of the memristor in the output column. The larger the switching ratio, the larger the resistance state change window of the memristor in the output column. When the switching ratio is greater than or equal to 100, the memristor in the output column can realize the resistance state change more accurately, thereby further improving the accuracy of the calculation. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of the structure of an approximate addition circuit provided by the present invention.

[0022] Figure 2 Schematic diagram of a gate-level and modular n-bit approximate adder provided in Embodiment 1 of the present invention when the third input number is b.

[0023] Figure 3 A schematic diagram of a gate-level and modular n-bit approximate adder provided in Embodiment 2 of the present invention when the third input number is c.

[0024] Figure 4 A schematic diagram of the structure of an approximate addition circuit provided in Embodiment 2 of the present invention when the third input number is c. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0026] In order to achieve the above-mentioned object, in a first solution, the present invention provides a control method of an approximate addition circuit based on a memristor, which is used to realize an n-bit number a=a n ......a2a1 and b=b n ......approximate addition of b2b1.

[0027] The exact full addition algorithm needs to obtain the output value and carry , c i+1 = a i b i +a i c i +b i c i , mainly includes two parts, one part is to calculate the output value (approximate addition result) s i , the other part is to calculate the carry c i+1 . The calculation of these two parts requires a lot of computing resources and time, and the calculation of the output value of the next bit depends on the carry calculation of the previous bit. If the carry calculation of the previous bit is not completed, the output value calculation and carry calculation of the current bit cannot be performed, resulting in a huge waste of resources and time loss. The approximate calculation algorithm proposed in the present invention does not need to wait for the carry calculation of the previous bit, because in the approximate algorithm, the carry is equal to one of the three input values ​​of the previous bit, which means that the carry calculation of all bits is completed in the initial writing link, and the output values ​​s of different bits are i Therefore, the present invention proposes an approximate addition circuit capable of realizing parallel calculation and a control method thereof, which greatly improves the calculation speed.

[0028] like Figure 1 As shown, the approximate addition circuit includes: a memristor array and n identical resistors R1, R2, ..., R n The memristor array includes a plurality of identical memristors arranged in n rows and 3 columns, and the positive electrodes of the memristors in the jth column are all connected to the bit line BL j The negative electrodes of the memristors in the i-th row are all connected to the word line WL i Upper: word line WL i One end is left floating and the other end is connected to R i One end is connected to R i The other end is T 4iPort: the negative electrode of the i-th row memristor and the word line WL i The connection points are located on the word line WL i The floating end and R i n≥1; j=1,2,3; i=1,2,...,n; the resistance value of the resistor is the same as the low resistance value of the memristor; The above control method includes: Initialize the memristor array: set all memristors on the output column to high impedance state, and write the i-th bit number of the first input number and the second input number into the i-th row of memristors in the two input columns; Connect a voltage with an amplitude of 0 to the T1 port and the T2 port, and connect a fixed voltage V to the T3 port. cond , in T 41 ,T 42 ,...,T 4n The ports are connected to voltages V1, V2, ..., V n ; Read the logical value s1, s2, ..., s corresponding to the resistance state of each memristor in the output column n ; will s n ...s2s1 and c n+1 As the approximate addition result and carry of a and b respectively; Among them, the two input columns are two columns selected arbitrarily from the memristor array; the output column is an unselected column in the memristor array; the T1 port and the T2 port are the ports of the bit lines where the two input columns are located, and the T3 port is the port of the bit line where the output column is located; the first input number and the second input number are two numbers selected arbitrarily from a, b, and c, respectively; the third input number is a number not selected from a, b, and c; c=c n ......c2c1; when the third input number is a, c i+1 = a i ; When the third input number is b, c i+1 = b i ; When the third input number is c, c i+1 = c i , c1 is the preset initial carry, which can be 0 or 1, set by the user; if the i-th bit number in the third input number is 0, then V i =V p Otherwise, V i =2V p .

[0029] The principle of the above logic operation is that the resistance value of the memristor on the same row of the two input columns and the voltage value applied to the word line of the row affect the lower electrode voltage of the memristor on the row of the output column; if the voltage of the lower electrode is too small, the resistance state of the memristor changes from a high resistance state to a low resistance state, thereby obtaining an output value of "1"; otherwise, the resistance state of the memristor remains in a high resistance state and the output value is "0".

[0030] It should be noted that in order for the memristor on the output column to change resistance correctly, the following conditions must be met: 2V p / 3 <V cond -V set <V p ; In order to ensure that the information of the input memristor is not destroyed during the entire logic operation, it is necessary to satisfy: max{V p ,(V p +V cond ) / 3, (2V p +V cond ) / 4}<|V reset |; Among them, V set V is the threshold value of the memristor changing from high resistance state to low resistance state; reset is the threshold value at which the memristor changes from a low-resistance state to a high-resistance state.

[0031] It should be noted that the approximate addition circuit control method proposed in the present invention optimizes the carry c i+1 and the output value s i , under the condition that the precision reduction is acceptable, the operation speed is greatly improved. i+1 Equal to one of the three input values ​​of the previous bit, the output value is s i It is equal to the result of performing one step of majority gate logic by inverting the other two input values ​​and the carry of the output. i+1 Depending on the selected input value, this approximate addition can be expressed in three ways, including Type A, Type B, and Type C: Under type A, the approximate addition is expressed as: Under type B, the approximate addition is expressed as: Under type C, the approximate addition is expressed as: Table 1 shows the truth table of exact addition and approximate addition (type A, type B, and type C) (taking the preset initial carry c1 = 0 as an example).

[0032] For type A, carry ci+1 = a i , the carry of each bit is completed at the beginning of writing, without waiting for idle time, and each bit directly starts to output the value s i The calculation only requires one step of majority gate logic calculation. As shown in Table 1, compared with the exact addition, the error rate of the output value of the approximate addition operation is 2 / 8, and the carry error rate is 6 / 8. The error rate is very low, which is quite practical and efficient compared with the improved speed and saved area.

[0033] For type B, carry c i+1 = b i , the carry of each bit is completed at the beginning of writing, without waiting for idle time, and each bit directly starts to output the value s i The calculation only requires one step of majority gate logic calculation. As shown in Table 1, compared with the exact addition, the error rate of the output value of the approximate addition operation is 2 / 8, and the carry error rate is 6 / 8. The error rate is very low, which is quite practical and efficient compared with the improved speed and saved area.

[0034] For type C, as shown in Table 1, compared with exact addition, the error rate of the output value of the approximate addition operation is 4 / 8, and the carry error rate is 2 / 8. i+1 = c i On the surface, this type still needs to wait for the carry of the previous bit. However, after direct iteration, c i+1 = c i , c i = c i-1 ,..., c2= c1, and in this embodiment c1= 0, so it can be found that c n+1 = c n = c n-1 =…=c2= c1=0. Therefore, the output value s i The calculation of s also degenerates into i = a i + b i , the operation becomes simpler, and the truth table can be simplified from Table 1 to Table 2. As can be seen from Table 2, when the approximate algorithm starts to iterate, the output error rate of the approximate addition is 2 / 8, and the carry error rate is 2 / 8 compared with the exact addition. The error rate is reduced by 50%, which is acceptable compared with the improved speed and saved area.

[0035] In an optional implementation, when the third input number is c, the carry c of the last step can be n+1 = a n b n, to further improve the accuracy of n-bit approximate calculations. n+1 It is also determined by only two input quantities and is also calculated in parallel. Specifically, the above approximate addition circuit also includes: a memristor M4; the positive electrode of the memristor M4 is used as the T5 port, and the negative electrode is connected to the word line WL n On the word line WL n The floating end and R n between; The above control method also includes: Set the memristor M4 to a high impedance state and set the T3 port to a floating state; the nth row memristors in the two input columns store a n and b n ; Connect a voltage with an amplitude of 0 to the T1 port and the T2 port, and connect a fixed voltage V to the T5 port. cond , in T 4n The port is connected to the voltage V; the logic value corresponding to the resistance state of the memristor M4 is read as c n+1 The final result; If c1 is 0, then V i =V p Otherwise, V i =2V p .

[0036] In an alternative embodiment, V cond = 2V set ; V p =1.2V set .

[0037] In an optional implementation, the corresponding logic value is written by setting the high and low resistance states of the memristor; wherein the high resistance state of the memristor corresponds to the logic value "0", and the low resistance state corresponds to the logic value "1".

[0038] In an optional implementation manner, a switching ratio of each memristor in the above approximate addition circuit is greater than or equal to 100.

[0039] In order to further illustrate the control method of the memristor-based approximate adding circuit provided by the present invention, it is described in detail as follows in conjunction with specific embodiments: Example 1 In this embodiment, the third input number is b as an example. i+1 = b i , c=b n-1 ......b1c1, the corresponding gate-level and modular n-bit approximate adder schematic diagram is as follows Figure 2 shown.

[0040] The control method of the approximate adding circuit includes: Initialize the memristor array: Set all memristors on the output column to high impedance, and write a to the corresponding memristors in the i-th row of the two input columns. i and c i (ie b i-1 ); Connect a voltage with an amplitude of 0 to the T1 port and the T2 port, and connect a fixed voltage V to the T3 port. cond , in T 41 ,T 42 ,...,T 4n The ports are connected to voltages V1, V2, ..., V n ; Read the logical value s1, s2, ..., s corresponding to the resistance state of each memristor in the output column n ; will s n ...s2s1 and c n+1 =b n They are respectively the approximate addition result and carry of a and b.

[0041] Example 2 In this embodiment, the third input number is c, the initial carry c1 is preset to 0, and the carry c of the last step is n+1 = a n b n For example, at this time c i+1 = c i , c n+1 = c n = c n-1 =…=c2= c1, the corresponding gate-level and modular n-bit approximate adder diagram is as follows Figure 3 shown.

[0042] like Figure 4 As shown, the approximate addition circuit in this embodiment includes 3n+1 memristors and n resistors R1, R2, ..., R n ; The first two columns in the memristor array are used as input columns, and the third column is used as output column; the bit line where the first column of memristors is located is BL1, and the memristors in the first column are respectively denoted as M 11 ,M 21 ,...,M n1 The bit line where the second column of memristors is located is BL2, and the memristors in the second column are denoted by M 12 ,M 22 ,...,M n2 The bit line where the third column of memristors is located is BL3, and the memristors in the third column are denoted by M 13 ,M 23 ,...,M n3 The word lines where the memristors in each row are located are denoted as WL1, WL2, ..., WLn The approximate addition circuit also includes a memristor M4, the positive electrode of the memristor M4 is connected to the bit line BL4, and the negative electrode is connected to the word line WL n On the word line WL n The floating end and R n between.

[0043] The control method of the above approximate adding circuit includes: Set a1,a2,...,a n One-to-one correspondence is written into the memristor M 11 ,M 21 ,...,M n1 , b1,b2,...,b n One-to-one correspondence is written into the memristor M 12 ,M 22 ,...,M n2 , “1” corresponds to the low-resistance state of the memristor, and “0” corresponds to the high-resistance state of the memristor; Apply voltage values ​​of 0, 0, V to the ports of BL1, BL2, and BL3 respectively. cond , while in WL1,WL2,...,WL n The voltage value V p , you can simultaneously implement the majority gate logic operation with inversion function on n bits, 13 ,M 23 ,...,M n3 The sum of each digit is obtained by n ; Among them, the majority gate logic operation with inversion function implemented for i bit is .

[0044] Apply voltages of 0, 0, and V to the ports of BL1, BL2, and BL4, respectively. cond BL3 is not applied with voltage and is in a floating state. n The voltage applied to the terminal is 2V p , according to the memristor M n1 and M n2 The configuration of the memristor M4 is changed, and the voltage of the lower electrode of the memristor M4 is changed, thereby changing the resistance state of the memristor M4, as the calculation result c n+1 =a n b n .

[0045] The approximate addition circuit and control method provided by the present invention can quickly realize the parallel operation of n-bit approximate addition, greatly improve the operation speed while saving area and reducing resource consumption. In practical applications, a hybrid n-bit adder combining approximate addition and precise addition is often used to comprehensively improve the circuit calculation speed and accuracy. Approximate adders are used for 1~k bits, and precise adders are used for k+1~n bits. Specifically, the memristor high resistance R H =100KΩ, low resistance R L =1KΩ, the fixed resistance R=1KΩ.

[0046] As shown in Table 3, the power consumption of the logic proposed in the present invention is simulated and analyzed, and the power consumption of the n-bit hybrid full adder as a whole is analyzed. It can be seen from Table 3 that, with the power consumption compromise, the speed and power consumption of the hybrid full adder are greatly improved.

[0047] Taking an 8-bit full adder as an example, the evaluation indexes of the hybrid full adder algorithm were simulated and analyzed, and the results in Table 4 and Table 5 were obtained. It can be seen from Table 4 and Table 5 that the calculation accuracy of the hybrid full adder provided by the present invention is within an acceptable range.

[0048] In summary, the present invention relates to an approximate addition circuit based on a memristor and a control method thereof, which can solve the problems of low speed, large area and high power consumption of traditional adders in high-bit addition, and can effectively realize parallel addition operations by utilizing the storage-computation-in-one characteristics of memristors. The circuit significantly improves the calculation speed and reduces the consumption of hardware resources by optimizing the calculation of carry and output values. The present invention is based on the high and low resistance storage function of the memristor, and realizes more efficient parallel addition operations through approximate addition operation control, especially showing significant performance improvement when processing large data streams and high-speed operations. In addition, a hybrid n-bit adder combining precise and approximate addition of the adder structure can effectively save power consumption and area while improving the calculation speed. Through simulation analysis and experimental verification, the present invention shows higher speed and lower power consumption in the application of approximate adders.

[0049] In a second aspect, the present invention provides an approximate addition operation device, comprising: an approximate adder circuit and a controller; The approximate addition circuit includes a memristor array and n identical resistors R1, R2, ..., R n The memristor array includes a plurality of identical memristors arranged in n rows and 3 columns, and the positive electrodes of the memristors in the jth column are all connected to the bit line BL jThe negative electrodes of the memristors in the i-th row are all connected to the word line WL i Upper: word line WL i One end is left floating and the other end is connected to R i One end is connected to R i The other end is T 4i Port: the negative electrode of the i-th row memristor and the word line WL i The connection points are located on the word line WL i The floating end and R i n≥1; j=1,2,3; i=1,2,...,n; the resistance value of the resistor is the same as the low resistance value of the memristor; The controller is used to execute the control method provided by the first aspect of the present invention.

[0050] In an optional implementation manner, the above approximate addition circuit further includes: a memristor M4; the positive electrode of the memristor M4 is used as the T5 port, and the negative electrode is connected to the word line WL n On the word line WL n The floating end and R n between; The controller is also used to execute the optimization operation in the control method provided in the first aspect of the present invention.

[0051] In an optional implementation manner, a switching ratio of each memristor in the above approximate addition circuit is greater than or equal to 100.

[0052] The related technical aspects are the same as the control method provided in the first aspect of the present invention, and will not be elaborated here.

[0053] In a third aspect, the present invention provides a control system, comprising: a memory and a processor, wherein the memory stores a computer program, and the processor executes the control method provided in the first aspect of the present invention when executing the computer program.

[0054] The related technical aspects are the same as the control method provided in the first aspect of the present invention, and will not be elaborated here.

[0055] In a fourth aspect, the present invention further provides a computer-readable storage medium, which includes a stored computer program, wherein when the computer program is executed by a processor, the device where the storage medium is located is controlled to execute the control method provided in the first aspect of the present invention.

[0056] The related technical aspects are the same as the control method provided in the first aspect of the present invention, and will not be elaborated here.

[0057] In a fifth aspect, the invention further provides a computer program product, comprising a computer program / instruction, which, when executed by a processor, implements the control method provided in the first aspect of the invention.

[0058] The related technical aspects are the same as the control method provided in the first aspect of the present invention, and will not be elaborated here.

[0059] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A control method for an approximate adding circuit based on a memristor, characterized in that: Used to implement n-bit number a=a n ......a2a1 and b=b n ...approximate addition of b2b1; the approximate addition circuit comprises: a memristor array and n identical resistors R1, R2, ..., R n The memristor array includes a plurality of identical memristors arranged in n rows and 3 columns, and the positive electrodes of the memristors in the jth column are all connected to the bit line BL j The negative electrodes of the memristors in the i-th row are all connected to the word line WL i Upper: word line WL i One end is left floating and the other end is connected to R i One end is connected to R i The other end is T 4i Port: the negative electrode of the i-th row memristor and the word line WL i The connection points are located on the word line WL i The floating end and R i n≥1; j=1,2,3; i=1,2,...,n; the resistance value of the resistor is the same as the low resistance state resistance value of the memristor; the control method includes: Initialize the memristor array: set all memristors on the output column to high impedance state, and write the i-th bit number of the first input number and the second input number into the i-th row of memristors in the two input columns; Connect a voltage with an amplitude of 0 to the T1 port and the T2 port, and connect a fixed voltage V to the T3 port. cond , in T 41 ,T 42 ,...,T 4n The ports are connected to voltages V1, V2, ..., V n ; Read the logical value s1, s2, ..., s corresponding to the resistance state of each memristor in the output column n ; will s n ...s2s1 and c n+1 As the approximate addition result and carry of a and b respectively; Among them, the two input columns are two columns selected arbitrarily from the memristor array; the output column is an unselected column in the memristor array; the T1 port and the T2 port are the ports of the bit lines where the two input columns are located, and the T3 port is the port of the bit line where the output column is located; the first input number and the second input number are two numbers selected arbitrarily from a, b, and c; the third input number is a number not selected from a, b, and c; c=c n ......c2c1; when the third input number is a, c i+1 = a i ; When the third input number is b, c i+1 =b i ; When the third input number is c, c i+1 = c i , c1 is the preset initial carry; if the i-th bit number in the third input number is 0, then V i =V p Otherwise, V i =2V p ; 2V p / 3 < V cond -V set < V p ,max{V p , (V p +V cond ) / 3, (2V p +V cond ) / 4}< |V reset |;V set V is the threshold value of the memristor changing from high resistance state to low resistance state; reset is the threshold value at which the memristor changes from a low-resistance state to a high-resistance state.

2. The control method according to claim 1, characterized in that: V cond = 2V set ;V p =1.2V set 。 3. The control method according to claim 1, characterized in that: The corresponding logic value is written by setting the high and low resistance states of the memristor; wherein the high resistance state of the memristor corresponds to the logic value "0", and the low resistance state corresponds to the logic value "1".

4. The control method according to any one of claims 1 to 3, characterized in that: The approximate addition circuit further includes: a memristor M4; the positive electrode of the memristor M4 is used as the T5 port, and the negative electrode is connected to the word line WL n On the word line WL n The floating end and R n between; When the third input number is c, the control method further includes: Set the memristor M4 to a high impedance state and set the T3 port to a floating state; Connect a voltage with an amplitude of 0 to the T1 port and the T2 port, and connect a fixed voltage V to the T5 port. cond , in T 4n The port is connected to the voltage V; the logic value corresponding to the resistance state of the memristor M4 is read as c n+1 The final result; If c1 is 0, then V i =V p Otherwise, V i =2V p .

5. An approximate addition operation device, characterized in that: include: Approximate adder circuits and controllers; The approximate addition circuit comprises: a memristor array and n identical resistors R1, R2, ..., R n The memristor array includes a plurality of identical memristors arranged in n rows and 3 columns, and the positive electrodes of the memristors in the jth column are all connected to the bit line BL j The negative electrodes of the memristors in the i-th row are all connected to the word line WL i Upper: word line WL i One end is left floating and the other end is connected to R i One end is connected to R i The other end is T 4i Port: the negative electrode of the i-th row memristor and the word line WL i The connection points are located on the word line WL i The floating end and R i n≥1; j=1,2,3; i=1,2,...,n; the resistance value of the resistor is the same as the low resistance value of the memristor; The controller is used to execute the control method described in any one of claims 1 to 3.

6. The approximate addition operation device according to claim 5, characterized in that: The approximate addition circuit further includes: a memristor M4; the positive electrode of the memristor M4 is used as the T5 port, and the negative electrode is connected to the word line WL n On the word line WL n The floating end and R n between; The controller is also used to execute the control method described in claim 4.

7. The approximate addition operation device according to claim 5 or 6, characterized in that: The switching ratio of each memristor in the approximate adding circuit is greater than or equal to 100.

8. A control system, characterized in that: include: A memory and a processor, wherein the memory stores a computer program, and the processor executes the control method according to any one of claims 1 to 4 when executing the computer program.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored computer program, wherein when the computer program is executed by a processor, the device where the storage medium is located is controlled to execute the control method according to any one of claims 1 to 4.

10. A computer program product, characterized in that The invention comprises a computer program / instruction, which, when executed by a processor, implements the control method described in any one of claims 1 to 4.

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