Data processing method and device, electronic equipment and storage medium

Abstract

The invention provides a data processing method and device, electronic equipment and a storage medium, and relates to the technical field of data processing. The method comprises the following steps: calling a data reading instruction in a target instruction set, reading a plurality of current elements of a target complex vector to be operated from a memory, and storing real parts and imaginary parts in the plurality of current elements into a complex register; calling a data filling instruction in the target instruction set, and storing a real constant to be operated and a preset constant into at least one constant register; and calling a data operation instruction in the target instruction set according to the data stored in the complex number register and the data stored in each constant register, determining a current operation result of the target complex number vector and the real number constant, and storing the current operation result into a memory. According to the method, the processing performance of the processor is fully exerted, the waste of host resources is avoided, and the addition and subtraction operation efficiency of the complex vector and the real constant is effectively improved.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a data processing method, device, electronic device and storage medium. Background Art

[0002] Addition and subtraction of real constants and complex vectors are commonly used vector operations in mathematics, physics, engineering, economics, statistics and other fields. Optimizing the computational efficiency of real constants and complex vectors has great research significance.

[0003] When the prior art performs addition and subtraction operations on real constants and complex vectors, the loop process only adds and subtracts the real part of one element of the input vector each time and stores it in the address memory of the output vector. The performance of the processor is not fully utilized, resulting in a waste of host resources and failure to improve computing efficiency. Summary of the invention

[0004] The purpose of this application is to provide a data processing method, device, electronic device and storage medium to address the deficiencies in the above-mentioned prior art, so as to give full play to the advantages of ARM chips, improve the efficiency of addition and subtraction operations of complex vectors and real constants, and save host resources.

[0005] To achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows: In a first aspect, an embodiment of the present application provides a data processing method for performing addition or subtraction operations on a complex vector and a real constant, the method comprising: Calling a data read instruction in a target instruction set, reading multiple current elements of a target complex vector to be calculated from a memory, and storing real parts and imaginary parts of the multiple current elements in a complex register; each of the current elements includes: a real part and an imaginary part; Calling a data filling instruction in the target instruction set to store the real constant to be calculated and the preset constant into at least one constant register; According to the data stored in the complex register and the data stored in each of the constant registers, the data operation instruction in the target instruction set is called to determine the current operation result of the target complex vector and the real constant, and the current operation result is stored in the memory, wherein the data operation instruction includes: an addition operation instruction or a subtraction operation instruction.

[0006] Optionally, calling a data read instruction in a target instruction set, reading multiple current elements of a target complex vector to be calculated from a memory, and storing real parts and imaginary parts of the multiple current elements in a complex register, includes: Calling a first data read instruction to sequentially read a plurality of current elements from the target complex vector; According to the order of each current element in the target complex vector, the real part of each current element is sequentially stored in the first initial continuous area of ​​the complex register, and the imaginary part of each current element is sequentially stored in the second initial continuous area of ​​the complex register.

[0007] Optionally, the at least one constant register includes: a first constant register and a second constant register; The calling of the data filling instruction in the target instruction set to store the real constant to be calculated and the preset constant into at least one constant register includes: The data filling instruction is called to store the real constant into the first constant register and the preset constant into the second constant register according to a first target storage number of times; the first target storage number of times is determined according to the number of the plurality of current elements read.

[0008] Optionally, calling a data operation instruction in the target instruction set according to the data stored in the complex register and the data stored in each of the constant registers to determine a current operation result of the target complex vector and the real constant includes: Calling the data operation instruction to operate on two data with the same ranking in the first initial continuous area and the first constant register to obtain first intermediate results corresponding to each ranking, and storing the first intermediate results corresponding to each ranking in the first intermediate continuous area of ​​the intermediate result register; Calling the data operation instruction to operate on two data with the same ranking in the second initial continuous area and the second constant register to obtain second intermediate results corresponding to each ranking, and storing the second intermediate results corresponding to each ranking in the second intermediate continuous area in the intermediate result register; The first data storage instruction is called to obtain the current operation result of the target complex vector and the real constant according to the data in the first intermediate continuous area and the second intermediate continuous area in the intermediate result register.

[0009] Optionally, calling a data read instruction in a target instruction set, reading multiple current elements of a target complex vector to be calculated from a memory, and storing real parts and imaginary parts of the multiple current elements in a complex register, includes: Calling a second data read instruction to sequentially read a plurality of current elements from the target complex vector; According to the forward order of each current element in the target complex vector, the real part and the imaginary part of each current element are sequentially stored in the complex register.

[0010] Optionally, the at least one constant register includes: a third constant register; the calling of the data filling instruction in the target instruction set to store the real constant to be calculated and the preset constant in the at least one constant register includes: The data filling instruction is called, and the real constant and the preset constant are sequentially and cross-stored in the third constant register according to a second target storage number, wherein the second target storage number is determined according to the number of the multiple current elements read.

[0011] Optionally, calling a data operation instruction in the target instruction set according to the data stored in the complex register and the data stored in each of the constant registers to determine a current operation result of the target complex vector and the real constant includes: Calling the data operation instruction to operate on two data with the same ranking in the complex register and the third constant register to obtain third intermediate results corresponding to each ranking, and storing the third intermediate results corresponding to each ranking in the intermediate result register; The second data storage instruction is called to obtain the current operation result of the target complex vector and the real constant according to the data in the intermediate result register.

[0012] Optionally, the current operation result includes multiple sub-operation results; The calling of the second data storage instruction to obtain the current operation result of the target complex vector and the real constant according to the data in the intermediate result register includes: According to the forward reading order of the data in the intermediate result register, read two adjacent data corresponding to the current time from the intermediate result register; The first data of two adjacent data is used as the real part of the sub-operation result corresponding to the current time, and the second data is used as the imaginary part of the sub-operation result corresponding to the current time.

[0013] Optionally, the calling of a data reading instruction in a target instruction set includes: Determining a current call quantity of the data read instruction according to a vector length of the target complex vector and a read length of the data read instruction; According to the current call quantity, a corresponding number of the data read instructions are called in parallel, and the real parts and imaginary parts of the multiple current elements read by the data read instructions are stored in the complex registers corresponding to the data read instructions.

[0014] Optionally, calling a data operation instruction in the target instruction set according to the data stored in the complex register and the data stored in each of the constant registers to determine a current operation result of the target complex vector and the real constant includes: According to the data stored in the complex registers corresponding to the data read instructions and the data stored in the constant registers, the data operation instructions corresponding to the data read instructions are called in parallel to determine the current operation results corresponding to the data operation instructions; According to the current operation results corresponding to each of the data operation instructions, the current operation results of the target complex vector and the real constant are determined.

[0015] In a second aspect, an embodiment of the present application further provides a data processing device, including: a data reading and storing module and a processing module; The data reading and storing module is used to call the data reading instruction in the target instruction set, read multiple current elements of the target complex vector to be calculated from the memory, and store the real part and the imaginary part of the multiple current elements into the complex register; each of the current elements includes: a real part and an imaginary part; The data reading and storing module is used to call the data filling instruction in the target instruction set to store the real constant to be calculated and the preset constant in at least one constant register; The processing module is used to call the data operation instruction in the target instruction set according to the data stored in the complex register and the data stored in each of the constant registers, determine the current operation result of the target complex vector and the real constant, and store the current operation result in the memory, wherein the data operation instruction includes: an addition operation instruction or a subtraction operation instruction.

[0016] Optionally, the data reading and storing module is specifically used to call a first data reading instruction to sequentially read a plurality of current elements from the target complex vector; According to the order of each current element in the target complex vector, the real part of each current element is sequentially stored in the first initial continuous area of ​​the complex register, and the imaginary part of each current element is sequentially stored in the second initial continuous area of ​​the complex register.

[0017] Optionally, the at least one constant register includes: a first constant register and a second constant register; The data reading and storage module is specifically used to call the data filling instruction, store the real constant in the first constant register according to a first target storage number of times, and store the preset constant in the second constant register; the first target storage number of times is determined according to the number of multiple current elements read.

[0018] Optionally, the processing module is specifically used to call the data operation instruction, operate on two data with the same ranking in the first initial continuous area and the first constant register, obtain the first intermediate results corresponding to each ranking, and store the first intermediate results corresponding to each ranking in the first intermediate continuous area in the intermediate result register; Calling the data operation instruction to operate on two data with the same ranking in the second initial continuous area and the second constant register to obtain second intermediate results corresponding to each ranking, and storing the second intermediate results corresponding to each ranking in the second intermediate continuous area in the intermediate result register; The first data storage instruction is called to obtain the current operation result of the target complex vector and the real constant according to the data in the first intermediate continuous area and the second intermediate continuous area in the intermediate result register.

[0019] Optionally, the data reading and storing module is specifically used to call a second data reading instruction to sequentially read a plurality of current elements from the target complex vector; According to the forward order of each current element in the target complex vector, the real part and the imaginary part of each current element are sequentially stored in the complex register.

[0020] Optionally, the at least one constant register includes: a third constant register; The data reading and storing module is specifically used to call the data filling instruction, and store the real constant and the preset constant in the third constant register in sequence according to a second target storage number, and the second target storage number is determined according to the number of multiple current elements read.

[0021] Optionally, the processing module is specifically used to call the data operation instruction, operate on two data with the same ranking in the complex register and the third constant register, obtain third intermediate results corresponding to each ranking, and store the third intermediate results corresponding to each ranking in the intermediate result register; The second data storage instruction is called to obtain the current operation result of the target complex vector and the real constant according to the data in the intermediate result register.

[0022] Optionally, the current operation result includes multiple sub-operation results; The processing module is specifically used to read two adjacent data corresponding to the current time from the intermediate result register according to the forward reading order of the data in the intermediate result register; The first data of two adjacent data is used as the real part of the sub-operation result corresponding to the current time, and the second data is used as the imaginary part of the sub-operation result corresponding to the current time.

[0023] Optionally, the data reading and storing module is specifically used to determine the current call quantity of the data reading instruction according to the vector length of the target complex vector and the reading length of the data reading instruction; According to the current call quantity, a corresponding number of the data read instructions are called in parallel, and the real parts and imaginary parts of the multiple current elements read by the data read instructions are stored in the complex registers corresponding to the data read instructions.

[0024] Optionally, the processing module is specifically used to call the data operation instructions corresponding to each data reading instruction in parallel according to the data stored in the complex register corresponding to each data reading instruction and the data stored in each constant register, and determine the current operation result corresponding to each data operation instruction; According to the current operation results corresponding to each of the data operation instructions, the current operation results of the target complex vector and the real constant are determined.

[0025] In a third aspect, an embodiment of the present application provides an electronic device, comprising: a processor, a storage medium and a bus, wherein the storage medium stores machine-readable instructions executable by the processor. When the electronic device is running, the processor and the storage medium communicate through the bus, and the processor executes the machine-readable instructions to implement the data processing method provided in the first aspect.

[0026] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the data processing method provided in the first aspect is executed.

[0027] The beneficial effects of this application are: The present application provides a data processing method, device, electronic device and storage medium, including: calling a data read instruction in a target instruction set, reading multiple current elements of a target complex vector to be calculated from a memory, and storing the real part and the imaginary part of the multiple current elements in a complex register; calling a data fill instruction in the target instruction set, storing the real constant to be calculated and the preset constant in at least one constant register; calling the data operation instruction in the target instruction set according to the data stored in the complex register and the data stored in each constant register, determining the current operation result of the target complex vector and the real constant, and storing the current operation result in the memory. This method is based on the NEON intrinsics instruction set supported by the processor of the ARM chip, making full use of the length of the 128-bit register of the ARM processor, calling the corresponding data read instruction, fill instruction and operation instruction, performing addition and subtraction operations of complex vectors and real constants in parallel, and completing the addition and subtraction operations of complex vectors and real constants after multiple cycles. The processing performance of the processor is fully utilized, the waste of host resources is avoided, and the efficiency of addition and subtraction operations of complex vectors and real constants is effectively improved.

[0028] In addition, for operations on large-dimensional data, an optimization method for loop unrolling is provided. By calling multiple computing modules in parallel, the amount of data processed in each loop can be increased, the number of loops can be reduced, and the problem of severe performance degradation caused by repeated retrieval of data from the memory due to insufficient cache can be avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0030] Figure 1 A flowchart of a data processing method provided in an embodiment of the present application; Figure 2 A flowchart of another data processing method provided in an embodiment of the present application; Figure 3 A schematic diagram of a process for performing a subtraction operation between a complex vector and a real constant provided in an embodiment of the present application; Figure 4 A flowchart of another data processing method provided in an embodiment of the present application; Figure 5 A flowchart of another data processing method provided in an embodiment of the present application; Figure 6A schematic diagram of another process of performing a subtraction operation between a complex vector and a real constant provided in an embodiment of the present application; Figure 7 A flowchart of another data processing method provided in an embodiment of the present application; Figure 8 A flowchart of another data processing method provided in an embodiment of the present application; Fig. 9 A flowchart of another data processing method provided in an embodiment of the present application; Fig.10 A schematic diagram of a cyclic calculation process provided in an embodiment of the present application; Fig.11 A flowchart of another data processing method provided in an embodiment of the present application; Fig.12 A schematic diagram of a data processing device provided in an embodiment of the present application; Fig.13 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of explanation and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn in real proportion. The flowchart used in this application shows the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowchart can be implemented out of sequence, and the steps without logical context can be reversed in order or implemented simultaneously. In addition, those skilled in the art can add one or more other operations to the flowchart under the guidance of the content of the present application, or remove one or more operations from the flowchart.

[0032] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0033] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.

[0034] SIMD (Single Instruction, Multiple Data) refers to single instruction multiple data technology, which can use a set of instructions to perform parallel operations on multiple sets of data, that is, to control multiple parallel processing units on a controller at the same time, so as to improve the computing efficiency of the CPU (Central Processing Unit), and is widely used in image processing, signal processing and other fields. Neon (instruction set) is a SIMD extension structure suitable for ARM (Advanced RISC Machine, microprocessor architecture) Cortex-A series processors. Its register group contains 32 64-bit registers and 16 128-bit registers, which are marked as D0-D31 and Q0-Q15 respectively. In fact, the D register overlaps with the Q register, that is, two D registers form a Q register.

[0035] Addition and subtraction of real constants and complex vectors are commonly used vector operations in mathematics, physics, engineering, economics, statistics and other fields, and have great optimization significance. Addition and subtraction operations refer to adding or subtracting the constant k from each element of vector B to obtain the vector . The addition and subtraction operations are performed concurrently by utilizing the characteristics of SIMD, which greatly improves the operation speed. The above-mentioned SIMD (Single Instruction Multiple Data) is a technology used for parallel computing in modern processors, such as the MMX (Multi Media eXtension), SSE (Streaming SIMD Extensions), AVX (Advanced Vector Extensions) and other generations of acceleration instruction sets supported on Intel processors; the NEON instruction set supported by ARM processors.

[0036] The existing real constant and complex vector addition and subtraction algorithms do not yet support NEON on the ARM platform. Currently, they can only use the general registers of the CPU for serial operations, that is, in one cycle, only one element can be read from the complex vector to perform addition and subtraction operations with the real constant, and the operation is repeated many times until all the elements in the complex vector and the real constant are completed. Therefore, there is a lot of room for improvement in the performance of real constant and complex vector addition and subtraction algorithms on the ARM platform.

[0037] On existing ARMv8 devices, the steps for adding and subtracting real constants and complex vectors (taking subtraction as an example) are as follows: Step S1: store the constant k into register D0; Step S2: Get the complex vector from memory First element The real part of Place it in register D1; Step S3: Subtract (add) registers D0 and D1, save the operation result to register D2, and store the calculation result D2 to vector The real part of the first element is associated with the memory; Step S4: Repeat steps S1 and S3 until the vector is calculated. Subtraction (addition) of N elements from a constant.

[0038] When the prior art performs addition and subtraction operations on real constants and complex vectors, the loop process only adds and subtracts the real part of one element of the input vector each time and stores it in the address memory of the output vector. For example, when the processed data is of single-precision float type, only the four arithmetic operations of 32-bit data are calculated each time. The actual register provided by the ARM Cortex-A series processor is up to 128 bits, that is, 128 bits of data can be processed in parallel each time. The CPU performance is not fully utilized, resulting in a waste of host resources. In addition, when the vector dimension is very large, this method will repeatedly fetch data from the memory because the cache is insufficient, resulting in a serious reduction in performance.

[0039] This solution mainly solves the problem that the ARM Cortex-A series processor-related devices cannot fully utilize the 128-bit registers of the ARM chip when implementing real constant and vector addition and subtraction operations, and the problem of performance degradation in large dimensions. It proposes to let the ARM platform process the addition and subtraction operations and read and store 128-bit data in parallel when calculating real constant and vector addition and subtraction operations, so that the advantages of the ARM chip can be fully utilized, saving host resources and improving the efficiency of the operation.

[0040] Based on this, this solution provides a data processing method, which uses the hardware characteristics of the ARM Cortex-A series processors to accelerate the addition and subtraction of real constants and complex vectors, and uses the NEONintrinsics instruction set supported by the ARM processor to perform parallel 128-bit data arithmetic operations on real constants and complex vectors, that is, calling the corresponding instructions to read, add and subtract 128-bit data in parallel, and store it in the specified vector / address, and complete the addition and subtraction of real constants and complex vectors after multiple cycles. On the ARM platform, this parallel processing method greatly improves the algorithm's computing performance compared to the traditional serial method.

[0041] It is worth noting that this method can be applied to ARM Cortex-A series processor devices, and is compatible with ARMv7 and above architectures, including ARMv8-A and ARMv8-R.

[0042] First, some of the operation instructions that may be involved in the following are explained: 1. vld2q_f32 instruction: fetch 8 32-bit float data from memory continuously, of which the first, third, fifth and seventh data are stored in D0 of the 128-bit Q0 register, and the second, fourth, sixth and eighth data are stored in D1 of the 128-bit Q0 register (Q0 is composed of two 64-bit registers, D0 and D1), realizing the separate reading of the real and imaginary parts of the four elements of the complex vector.

[0043] 2. vld1q_f32 instruction: fetch 4 32-bit float data from memory and store them in D register, so as to realize continuous reading of real and imaginary parts of two elements of complex vector.

[0044] 3. vdupq_n_f32 instruction: input constant k and store 4 k consecutively in a 128-bit register.

[0045] 4. vaddq_f32 instruction: Add the four 32-bit float data in the two NEON registers to get the added data of four 32-bit floats.

[0046] 5. vsubq_f32 instruction: subtract the four 32-bit float data in two NEON registers to obtain the subtraction data of four 32-bit floats.

[0047] 6. vst2q_f32 instruction: Contrary to the vld2q_f32 instruction, the 128-bit data (8 32-bit data) of the Q register is stored in the memory in the same order as the vld2q_f32 instruction.

[0048] 7. vst1q_f32 instruction: fetch 4 32-bit float data from the 128-bit D register and store them in memory.

[0049] Figure 1 A flow chart of a data processing method provided in an embodiment of the present application; the method can be used to perform addition or subtraction operations on complex vectors and real constants, and the execution subject of the method can be a computer device, such as Figure 1 As shown, the method may include: S101, calling a data read instruction in a target instruction set, reading multiple current elements of a target complex vector to be calculated from a memory, and storing real parts and imaginary parts of the multiple current elements into a complex register.

[0050] Each current element includes: a real part and an imaginary part.

[0051] The target instruction set can be the NEON intrinsics instruction set. The ARM NEON Intrinsics instruction set is a SIMD (Single Instruction Multiple Data) programming technology for the ARM architecture. The NEON instruction set can process multiple data elements at the same time, providing higher computing efficiency and throughput. Through parallel computing, NEON can complete more work in the same amount of time, thereby reducing power consumption. NEON Intrinsics provides a series of functions for operating SIMD registers and performing vectorized operations.

[0052] Before performing addition and subtraction operations on complex vectors and real constants, the complex vectors are stored in a memory of a computer device, wherein the real parts and imaginary parts of the elements of the complex vectors may be stored in the memory in sequence according to the arrangement order of the elements in the complex vectors.

[0053] Optionally, when performing addition and subtraction operations on complex vectors and real constants, multiple current elements of the target complex vector to be operated can be read from the memory first, and the number of current elements read can be determined according to the length of the register in the processor of the computer device.

[0054] For example, if the length of the register is 128 bits and one element occupies 32 bits, the number of current elements that can be read at one time can be 4. By reading 4 current elements at one time, all storage locations in the register can be occupied, thereby making full use of the register to achieve parallel processing and improve computing efficiency.

[0055] It is worth noting that the multiple current elements are read in sequence according to the arrangement order of the elements in the target complex vector. Taking forward reading as an example, through loop execution, each time according to the forward order of the elements in the target complex vector in the memory, the first n elements that have not been read are read from the memory as the multiple current elements.

[0056] Exemplarily, assuming that the target complex vector contains 12 elements and the number of current elements that can be read each time is 4, in the first loop, the 1st to 4th elements can be read as current elements, in the second loop, the 5th to 8th elements can be read as current elements, and in the third loop, the 9th to 12th elements can be read as current elements.

[0057] Optionally, the real part and the imaginary part of the current element read may be stored in a complex register, where the "complex number" in the complex register does not refer to the type of register, but is to distinguish it from a register used to store real constants.

[0058] S102, calling a data filling instruction in a target instruction set to store a real constant to be calculated and a preset constant in at least one constant register.

[0059] Since real constants have no imaginary part, when performing addition and subtraction operations on real constants and complex vectors, the real constants can be regarded as complex vectors with 0 imaginary part, that is, the preset constant here is 0, so that the real part of the real constant can be operated with the real part of the complex vector, and the imaginary part of the real constant can be operated with the imaginary part of the complex vector.

[0060] In some embodiments, the real number constant to be calculated and the preset constant may be stored in one constant register. Of course, the real number constant and the preset constant may be stored in different constant registers respectively.

[0061] S103. According to the data stored in the complex register and the data stored in each constant register, call the data operation instruction in the target instruction set, determine the current operation result of the target complex vector and the real constant, and store the current operation result in the memory.

[0062] The data operation instruction includes: an addition operation instruction or a subtraction operation instruction.

[0063] Optionally, if an addition operation is performed on the target complex vector and the real constant, an addition operation instruction may be called to perform an addition operation of 4-bit float data on the data in the complex register and the constant register.

[0064] If a subtraction operation is performed between a target complex vector and a real constant, a subtraction operation instruction may be called to perform a subtraction operation of 4-bit float data on the data in the complex register and the data in the constant register.

[0065] Optionally, steps S101 to S103 are executed in a loop until the calculation of each element in the target complex vector and the real constant is completed, thereby obtaining a final complete calculation result.

[0066] In one cycle, operations are performed based on multiple current elements of the read target complex vector and real constants to obtain current operation results of the target complex vector and the real constant, and the current operation result is the operation result of multiple current elements and the real constant.

[0067] For example, assume that the target complex vector is , the real constant is k, taking one loop as an example, assuming that the multiple current elements of the target complex vector read are: w 0 +x 0 i、w 1 +x 1 i、w 2 +x 2 i、w 3 +x 3i, then the current operation results of the target complex vector and the real constant include: w 0 +x 0 The result of the operation of i and k, w 1 +x 1 The result of the operation of i and k, w 2 +x 2 The result of the operation of i and k and w 3 +x 3 The result of the operation of i and k.

[0068] Among them, taking addition operation as an example, w 1 +x 1 The result of the operation of i and k can be w 1 +k+x 1 i. Taking subtraction as an example, w 1 +x 1 The result of the operation of i and k can be kw 1 -x 1 i.

[0069] In summary, the data processing method provided in this embodiment includes: calling the data read instruction in the target instruction set, reading multiple current elements of the target complex vector to be calculated from the memory, and storing the real part and the imaginary part of the multiple current elements in the complex register; calling the data fill instruction in the target instruction set, storing the real constant to be calculated and the preset constant in at least one constant register; according to the data stored in the complex register and the data stored in each constant register, calling the data operation instruction in the target instruction set, determining the current operation result of the target complex vector and the real constant, and storing the current operation result in the memory. This method is based on the NEONintrinsics instruction set supported by the processor of the ARM chip, making full use of the length of the 128-bit register of the ARM processor, calling the corresponding data read instruction, fill instruction and operation instruction, performing addition and subtraction operations of complex vectors and real constants in parallel, and completing the addition and subtraction operations of complex vectors and real constants after multiple cycles. Give full play to the processing performance of the processor, avoid the waste of host resources, and effectively improve the efficiency of addition and subtraction operations of complex vectors and real constants.

[0070] Figure 2 A flowchart of another data processing method provided by an embodiment of the present application; optionally, in step S101, calling a data read instruction in a target instruction set, reading multiple current elements of a target complex vector to be calculated from a memory, and storing the real parts and imaginary parts of the multiple current elements in a complex register may include: S201 . Call a first data read instruction to sequentially read a plurality of current elements from a target complex vector.

[0071] The first data read instruction may be a vld2q_f32 instruction, through which a plurality of current elements are sequentially read from the target complex vector each time, wherein the plurality of current elements are read in a forward order starting from an element that has not been read.

[0072] S202. According to the order of each current element in the target complex vector, the real part of each current element is sequentially stored in a first initial continuous area in the complex register, and the imaginary part of each current element is sequentially stored in a second initial continuous area in the complex register.

[0073] When storing the real part of each current element into the complex register, it can be in the order of each current element in the target complex vector, wherein it can be read in a forward order or in a reverse order. In the embodiment of the present application, the forward reading order is mainly used for illustration.

[0074] Similarly, the imaginary parts of each current element are also stored in the complex register according to the order of each current element in the target complex vector, wherein the reading order of the imaginary part is consistent with the real part, that is, when the real part is read forward, the imaginary part is also read forward, and when the real part is read reversely, the imaginary part is also read reversely.

[0075] Figure 3 A schematic diagram of a process for performing a subtraction operation between a complex vector and a real constant provided in an embodiment of the present application. Figure 3 As shown, a target complex vector is stored in the memory, and the target complex vector includes multiple elements.

[0076] In some embodiments, the real part and the imaginary part of each current element read from the memory may be stored in the vector bv, with the current number of elements being 4, respectively w 0 +x 0 i、w 1 +x 1 i、w 2 +x 2 i、w 3 +x 3 Taking i as an example, bv is composed of two vectors bv.val[0] and bv.val[1], corresponding to the hardware register S0. S0 is composed of two 128-bit Q registers, one of which is used to provide the first initial continuous region, and the other Q register is used to provide the second initial continuous region.

[0077] Where bv.val[0] stores the real parts of four elements, namely w 0 、w 1 、w 2 、w 3 , bv.val[1] stores the imaginary parts of four elements, namely x0 、x 1 、x 2 、x 3 .

[0078] The at least one constant register includes: a first constant register and a second constant register.

[0079] Continue to refer Figure 3 In some embodiments, the real constant to be calculated can be filled into the vector av0, corresponding to the hardware first constant register Q0, and the preset constant can be filled into the vector av1, corresponding to the hardware second constant register Q1.

[0080] In step S102, calling the data filling instruction in the target instruction set to store the real constant to be calculated and the preset constant in at least one constant register may include: calling the data filling instruction, storing the real constant in the first constant register according to the first target storage number, and storing the preset constant in the second constant register; the first target storage number is determined according to the number of multiple current elements read.

[0081] Optionally, the data filling instruction may be a vdupq_n_f32 instruction, and the real number constant k may be stored in av0 through the vdupq_n_f32 instruction, and the real number constant 0 may be stored in av1 through the vdupq_n_f32 instruction.

[0082] In some embodiments, when a real constant is written into the first constant register and when a preset constant is written into the second constant register, the number of times of writing corresponds to the number of current elements read.

[0083] like Figure 3 As shown, there are 4 current elements, and the real part and imaginary part are also 4 respectively. At this time, 4 real constants k are filled in the vector av0, and 4 preset constants 0 are filled in the vector av1, so that the real part and imaginary part of each current element can be calculated with the corresponding real constant and preset constant.

[0084] Figure 4 A flowchart of another data processing method provided by an embodiment of the present application; optionally, in step S103, calling a data operation instruction in a target instruction set according to the data stored in the complex register and the data stored in each constant register to determine a current operation result of the target complex vector and the real constant may include: S401, calling a data operation instruction, operating on two data with the same ranking in the first initial continuous area and the first constant register, obtaining a first intermediate result corresponding to each ranking, and storing the first intermediate result corresponding to each ranking in the first intermediate continuous area in the intermediate result register.

[0085] The data operation instruction may be an addition operation instruction vaddq_f32 or a subtraction operation instruction vsubq_f32. The vaddq_f32 instruction or the vsubq_f32 instruction may be used to perform addition or subtraction operations on four-bit float data of vector bv.val[0] and vector av0, wherein two data of the same rank may be operated to obtain first intermediate results corresponding to each rank, and the first intermediate results are stored in the intermediate result register.

[0086] Continue to refer Figure 3 Taking subtraction as an example, the vsubq_f32 instruction can be used to perform subtraction on the first-rank real constant k in vector av0 and the first-rank real data w in vector bv.val[0]. 0 Perform subtraction to obtain the first intermediate result k-w corresponding to the first rank 0 , and stored in the first position of the first intermediate continuous area in the intermediate result register. Similarly, through the vsubq_f32 instruction, the real constant k in the second rank of vector av0 and the real part data w in the second rank of vector bv.val[0] can be 1 Perform subtraction to obtain the first intermediate result k-w corresponding to the second rank 1 , and stored in the second position of the first intermediate continuous area in the intermediate result register, and so on, until all data in vector av0 and vector bv.val[0] are calculated.

[0087] S402, calling a data operation instruction, operating on two data with the same ranking in the second initial continuous area and the second constant register, obtaining second intermediate results corresponding to each ranking, and storing the second intermediate results corresponding to each ranking in the second intermediate continuous area in the intermediate result register.

[0088] Continue to refer Figure 3 , through the vsubq_f32 instruction, the preset constant 0 in the first row of vector av1 and the imaginary data x in the first row of vector bv.val[1] can be 0 Perform subtraction to obtain the second intermediate result -x corresponding to the first rank 0 , and stored in the first position of the second intermediate continuous area in the intermediate result register. Similarly, through the vsubq_f32 instruction, the preset constant 0 in the second rank of vector av1 and the real part x in the second rank of vector bv.val[1] can be 1 Perform subtraction to obtain the first intermediate result -x corresponding to the second rank 1, and stored in the second position of the second intermediate continuous area in the intermediate result register, and so on, until all data in vector av1 and vector bv.val[1] are calculated.

[0089] S403, calling the first data storage instruction, and obtaining the current operation result of the target complex vector and the real constant according to the data in the first intermediate continuous area and the second intermediate continuous area in the intermediate result register.

[0090] Next, the first data storage instruction vst2q_f32 can be used to combine the calculation results in the intermediate result register to obtain the current calculation result of the target complex vector and the real constant, and save the current calculation result to the memory. The current calculation result refers to the calculation result of the read 4 current elements and the real constant, so the current calculation result includes four calculation results.

[0091] It should be noted that if Figure 3 As shown, the intermediate result register can be the complex register S0 used to store the real and imaginary parts of the target complex vector. In this scenario, the calculated first intermediate results will be written into bv.val[0] in sequence to cover the originally stored real data, and the calculated second intermediate results will be written into bv.val[1] in sequence to cover the originally stored imaginary data.

[0092] Of course, the intermediate result register may also use a new register, and the new register may also be composed of two 128-bit Q registers. The new register may have the same structure as the complex register S0, where one Q register is used to store each first intermediate result, and the other Q register is used to store each second intermediate result.

[0093] like Figure 3 As shown, the current elements are w 0 +x 0 i、w 1 +x 1 i、w 2 +x 2 i、w 3 +x 3 i, the corresponding current calculation results are: kw 0 -x 0 i, kw 1 -x 1 i, kw 2 -x 2 i, kw 3 -x 3 i.

[0094] Based on the above method, by cyclically reading the latest current element, it is possible to traverse all elements in the target complex vector and complete the addition or subtraction operation of the target complex vector and the real constant.

[0095] Figure 5 A flowchart of another data processing method provided by an embodiment of the present application; optionally, in step S101, calling a data read instruction in a target instruction set, reading multiple current elements of a target complex vector to be calculated from a memory, and storing the real parts and imaginary parts of the multiple current elements in a complex register may include: S501 . Call a second data read instruction to sequentially read a plurality of current elements from a target complex vector.

[0096] This embodiment provides a second implementation, in which the second data read instruction vld1q_f32 may be called to sequentially read multiple current elements from the target complex vector, wherein the number of elements read each time is 2, and in one reading, the real part and the imaginary part of two consecutive current elements in the target complex vector may be read.

[0097] S502 . Store the real part and the imaginary part of each current element in the complex register in sequence according to the forward order of each current element in the target complex vector.

[0098] Optionally, the real part and the imaginary part of each current element may be stored in sequence in the complex register according to the arrangement order of each current element in the target complex vector. This embodiment also takes the forward reading order as an example.

[0099] Different from the first implementation, in the second implementation, the real part and the imaginary part of the current element are stored consecutively in the complex register, rather than storing the real part together and the imaginary part together.

[0100] The complex register here may be a different register from the complex register in the first implementation manner, and the complex register here may be a 128-bit Q register.

[0101] Figure 6 A schematic diagram of another process of performing a subtraction operation between a complex vector and a real constant provided in an embodiment of the present application; Figure 6 As shown, taking one loop as an example, the current element w can be read from the memory through the vld1q_f32 instruction 0 +x 0 i、w 1 +x 1 i, so that the real part and imaginary part of the current element are stored in the vector dv in sequence. dv stores four 32-bit float data, and the corresponding hardware is the complex register Q5.

[0102] Optionally, the at least one constant register includes: a third constant register.

[0103] In a second implementation, the constant register may be the first, or third, constant register, such as Figure 6 As shown, the third constant register is Q4.

[0104] Optionally, in step S102, calling the data fill instruction in the target instruction set to store the real constant to be calculated and the preset constant in at least one constant register may include: calling the data fill instruction, and storing the real constant and the preset constant in sequence in a third constant register cross-wise according to the second target storage number, wherein the second target storage number is determined according to the number of multiple current elements read.

[0105] In some embodiments, the data filling instruction vdupq_n_f32 can be called to store the real constants and the preset constants in the vector cv in sequence. The corresponding hardware is the third constant register Q4, where the storage quantity of the real constants and the preset constants corresponds to the number of the current elements read. In the second implementation, the number of the current elements read in one loop is 2, so Figure 6 As shown, two real constants k and two preset constants 0 are stored in the vector cv.

[0106] In another embodiment, the data filling instruction may not be called, but the vector cv={k, 0, k, 0} may be directly initialized, or the vector cv may be directly assigned {k, 0, k, 0}.

[0107] Figure 7 A flow chart of another data processing method provided by an embodiment of the present application; Optionally, in step S103, calling a data operation instruction in a target instruction set according to the data stored in the complex register and the data stored in each constant register to determine a current operation result of a target complex vector and a real constant may include: S701, call the data operation instruction, operate on two data with the same ranking in the complex register and the third constant register, obtain the third intermediate results corresponding to each ranking, and store the third intermediate results corresponding to each ranking in the intermediate result register.

[0108] The called data operation instruction can be an addition operation instruction or a subtraction operation instruction.

[0109] Continue to refer Figure 6 Taking subtraction as an example, by calling the vsubq_f32 instruction, the real constant k in the first position of the vector cv and the real part data w in the first position of the vector dv can be subtracted. 0Perform subtraction to obtain the third intermediate result k-w corresponding to the first rank 0 , and store it in the first position of the intermediate result register; similarly, by calling the vsubq_f32 instruction, the real constant 0 in the second position of the vector cv and the imaginary data x in the second position of the vector dv can be 0 Perform subtraction to obtain the third intermediate result -x corresponding to the second rank 0 , and stored in the second position of the intermediate result register; and so on, until all the data in the vector cv and the vector dv are calculated.

[0110] like Figure 3 As shown, the intermediate result register can be the complex register Q5 used to store the real and imaginary parts of the target complex vector. In this scenario, the calculated third intermediate results will be written into the vector dv in sequence to cover the real and imaginary data originally stored.

[0111] Of course, the intermediate result register may also use a new register, and the new register may also be composed of a 128-bit Q register, and the new register may have the same structure as the complex register Q5.

[0112] S702 , calling the second data storage instruction, and obtaining the current operation result of the target complex vector and the real constant according to the data in the intermediate result register.

[0113] Next, the second data storage instruction vst1q_f32 can be called to combine the calculation results in the intermediate result register to obtain the current calculation result of the target complex vector and the real constant, and save the current calculation result to the memory. Among them, the current calculation result also refers to the calculation result of the two current elements read and the real constant, so the current calculation result includes two calculation results.

[0114] like Figure 6 As shown, the current elements are w 0 +x 0 i、w 1 +x 1 i, the corresponding current calculation results are: kw 0 -x 0 i, kw 1 -x 1 i.

[0115] Based on the above method, by cyclically reading the latest current element, it is possible to traverse all elements in the target complex vector and complete the addition or subtraction operation of the target complex vector and the real constant.

[0116] Optionally, combined Figure 3 and Figure 6 , the current operation result may include multiple sub-operation results, where an element in the target complex vector and a real constant will correspond to a sub-operation result.

[0117] by Figure 3 For example, the current calculation result is kw 0 -x 0 i, kw 1 -x 1 i, kw 2 -x 2 i, kw 3 -x 3 i, then, kw 0 -x 0 i is a sub-operation result, kw 1 -x 1 i is a sub-operation result, kw 2 -x 2 i is a sub-operation result, kw 3 -x 3 i is a sub-operation result.

[0118] Figure 8 A flowchart of another data processing method provided in an embodiment of the present application; Figure 8 As shown, in step S702, calling the second data storage instruction to obtain the current operation result of the target complex vector and the real constant according to the data in the intermediate result register may include: S801. Read two adjacent data corresponding to the current time from the intermediate result register according to the forward reading order of the data in the intermediate result register.

[0119] When reading data from the intermediate result register, two adjacent data can be read in sequence each time. Figure 6 For example, when the first time is current, the two adjacent data read from the intermediate result register are kw 0 and -x 0 When the second time comes, the two adjacent data read from the intermediate result register are kw 1 and -x 1 .

[0120] S802, using the first data of two adjacent data as the real part of the sub-operation result corresponding to the current time, and using the second data as the imaginary part of the sub-operation result corresponding to the current time.

[0121] Then when the first one is current, kw 0 As the real data in the first sub-operation result corresponding to the current time, -x 0As the imaginary data in the first sub-operation result corresponding to the current time, the first sub-operation result kw corresponding to the current time can be obtained. 0 -x 0 i.

[0122] By looping and reading the two adjacent data corresponding to the current operation from the intermediate result register, all sub-operation results in the current operation result can be calculated in sequence.

[0123] By testing the performance of the above two methods on ARM devices, the second implementation method ( Figure 6 The method shown in the figure) is better than the first implementation method ( Figure 3 The method shown in the figure has better performance, shorter read and store instructions, and better data arrangement.

[0124] This is because the throughput and latency performance of the two instructions vld2q_f32 and vst2q_f32 used in the first implementation on the machine are lower than those of the two instructions vld1q_f32 and vst1q_f32 used in the second implementation. Although four elements are read each time in the first implementation, the calculation is the same as the second implementation, and 128 bits of data are calculated at a time, so the actual amount of calculation is the same.

[0125] Fig. 9 A flowchart of another data processing method provided by an embodiment of the present application; Optionally, in step S101, calling a data reading instruction in a target instruction set may include: S901. Determine the current call quantity of the data read instruction according to the vector length of the target complex vector and the read length of the data read instruction.

[0126] Assuming that the length of the complex vector is N and the real constant is k, the second implementation method needs to be run N / 2 times to obtain the final result (when N is an even number). When N is large enough, the data of the complex vector cannot be read into the cache from the memory at one time. During the calculation process, data may be read from the memory. In order to improve the negative impact of this situation on performance, this embodiment provides a loop unrolling method to reduce the number of loops by N / 2. Each loop calculates the addition and subtraction of 16 complex elements and real constants, that is, in one loop, 8 second implementation methods are executed in parallel, and the number of loops is changed to N / 16 to improve the performance of the second implementation method.

[0127] Of course, the performance of the first implementation can also be improved in this way. If the length of the complex vector is N and the real constant is k, the first implementation needs to be run N / 4 times to get the final result. By taking the loop unrolling approach, the number of loops is reduced to N / 4. Each loop calculates the addition and subtraction of 16 complex elements and real constants. That is, in one loop, four second implementations are executed in parallel, reducing the number of loops to N / 16.

[0128] Therefore, the current call number of the data read instruction can be determined according to the vector length of the target complex vector and the read length of the data read instruction.

[0129] Exemplarily, taking the second implementation as an example, assuming that the vector length of the target complex vector is N, and the read length of the data read instruction is 2, then it can be determined that the number of data read instructions called in parallel is N / 2.

[0130] In another achievable manner, the current call quantity of the data read instruction may be determined according to the read length of the data read instruction and a preset read length. The preset read length may refer to the length of data to be read in one cycle.

[0131] Exemplarily, assuming that the read length of the data read instruction is 2 and the preset read length is 16, it can be determined that the current call quantity of the data read instruction is 16 / 2, that is, 8.

[0132] In yet another achievable manner, the current call quantity of the data read instruction may be determined according to the vector length of the target complex vector, the read length of the data read instruction, and a preset number of cycles.

[0133] Exemplarily, assuming that the vector length of the target complex vector is N and the preset number of loops is 4, it can be determined that the length of data to be read in one loop is N / 4, and the length of data read by the data read instruction at one time is 2, then the number of data read instructions currently called is (N / 4) / 2.

[0134] S902 . Call a corresponding number of data read instructions in parallel according to the current call quantity, and store the real parts and imaginary parts of the multiple current elements read by the data read instructions into the complex registers corresponding to the data read instructions.

[0135] Optionally, based on the determined number of calls, a corresponding number of data read instructions may be called in parallel in one loop to read multiple current elements of the target complex vector from the memory and store them in the complex registers.

[0136] Among them, each data reading instruction called in parallel can also read the data in sequence according to the arrangement order of each element in the target complex vector when reading the data.

[0137] Exemplarily, three data read instructions are called in parallel, each data read instruction reads four current elements in one cycle, the first data read instruction reads the 1st to 4th elements in the target complex vector, the second data read instruction reads the 5th to 8th elements, and the third data read instruction reads the 9th to 12th elements, thereby adjusting the reading of only 4 elements in one cycle to the reading of 12 elements in one cycle. The real and imaginary data of the elements read by each data read instruction can also be stored in sequence when stored in the complex register.

[0138] Fig.10 A schematic diagram of a cyclic calculation process provided in an embodiment of the present application, such as Fig.10 As shown, each addition or subtraction operation of two complex elements in the target complex vector and the real constant in the second implementation method can be regarded as a 1q calculation module, that is, the method of executing the entire process of reading, storing, adding or subtracting the target complex vector and the real constant and saving the calculation results is encapsulated into a calculation module.

[0139] Assuming that 8 1q calculation modules are called in parallel, 1q calculation module 01 is used to read the first two elements in the target complex vector and perform addition or subtraction operations with the real constant, 1q calculation module 02 is used to read the third and fourth elements in the target complex vector and perform addition or subtraction operations with the real constant, and so on, 1q calculation module 08 is used to read the fifteenth and sixteenth elements in the target complex vector and perform addition or subtraction operations with the real constant. Correspondingly, the current operation result calculated by 1q calculation module 01 is stored in the first and second digits in the memory, and the current operation result calculated by 1q calculation module 02 is stored in the third and fourth digits in the memory, and so on.

[0140] Fig.11 A flow chart of another data processing method provided by an embodiment of the present application; Optionally, in step S103, calling a data operation instruction in a target instruction set according to the data stored in the complex register and the data stored in each constant register to determine a current operation result of a target complex vector and a real constant may include: S1001. Based on the data stored in the complex registers corresponding to the data read instructions and the data stored in the constant registers, the data operation instructions corresponding to the data read instructions are called in parallel to determine the current operation results corresponding to the data operation instructions.

[0141] S1002. Determine the current operation result of the target complex vector and the real constant according to the current operation result corresponding to each data operation instruction.

[0142] Among them, the specific execution steps of the data read instruction and the data operation instruction corresponding to the data read instruction can be understood with reference to the previous embodiments, and will not be repeated here.

[0143] In summary, the data processing method provided in this embodiment includes: calling the data read instruction in the target instruction set, reading multiple current elements of the target complex vector to be calculated from the memory, and storing the real part and the imaginary part of the multiple current elements in the complex register; calling the data fill instruction in the target instruction set, storing the real constant to be calculated and the preset constant in at least one constant register; according to the data stored in the complex register and the data stored in each constant register, calling the data operation instruction in the target instruction set, determining the current operation result of the target complex vector and the real constant, and storing the current operation result in the memory. This method is based on the NEONintrinsics instruction set supported by the processor of the ARM chip, making full use of the length of the 128-bit register of the ARM processor, calling the corresponding data read instruction, fill instruction and operation instruction, performing addition and subtraction operations of complex vectors and real constants in parallel, and completing the addition and subtraction operations of complex vectors and real constants after multiple cycles. Give full play to the processing performance of the processor, avoid the waste of host resources, and effectively improve the efficiency of addition and subtraction operations of complex vectors and real constants.

[0144] In addition, for operations on large-dimensional data, an optimization method for loop unrolling is provided. By calling multiple computing modules in parallel, the amount of data processed in each loop can be increased, the number of loops can be reduced, and the problem of severe performance degradation caused by repeated retrieval of data from the memory due to insufficient cache can be avoided.

[0145] The following describes the devices, equipment, storage media, etc. used to execute the data processing method provided by this application. The specific implementation process and technical effects are described above and will not be repeated below.

[0146] Fig.12 A schematic diagram of a data processing device provided in an embodiment of the present application, the functions implemented by the data processing device correspond to the steps performed by the above method. The device can be understood as the above-mentioned computer device, or server, or server processor, or can also be understood as a component independent of the above-mentioned server or processor that implements the functions of the present application under the control of the server, such as Fig.12 As shown, the device may include: a data reading module 110 and a processing module 120; The data reading and storing module 110 is used to call the data reading instruction in the target instruction set, read multiple current elements of the target complex vector to be calculated from the memory, and store the real parts and imaginary parts of the multiple current elements into the complex register; each current element includes: a real part and an imaginary part; The data reading and storing module 110 is used to call the data filling instruction in the target instruction set to store the real constant to be calculated and the preset constant into at least one constant register; The processing module 120 is used to call the data operation instruction in the target instruction set according to the data stored in the complex register and the data stored in each constant register, determine the current operation result of the target complex vector and the real constant, and store the current operation result in the memory, wherein the data operation instruction includes: addition operation instruction or subtraction operation instruction.

[0147] Optionally, the data reading and storing module 110 is specifically configured to call a first data reading instruction to sequentially read a plurality of current elements from the target complex vector; According to the order of each current element in the target complex vector, the real part of each current element is sequentially stored in the first initial continuous area of ​​the complex register, and the imaginary part of each current element is sequentially stored in the second initial continuous area of ​​the complex register.

[0148] Optionally, the at least one constant register includes: a first constant register and a second constant register; The data reading and storing module 110 is specifically used to call the data filling instruction, store the real constant in the first constant register according to the first target storage number, and store the preset constant in the second constant register; the first target storage number is determined according to the number of multiple current elements read.

[0149] Optionally, the processing module 120 is specifically configured to call a data operation instruction, operate on two data with the same ranking in the first initial continuous area and the first constant register, obtain a first intermediate result corresponding to each ranking, and store the first intermediate result corresponding to each ranking in the first intermediate continuous area in the intermediate result register; Calling a data operation instruction to operate on two data with the same ranking in the second initial continuous area and the second constant register to obtain second intermediate results corresponding to each ranking, and storing the second intermediate results corresponding to each ranking in the second intermediate continuous area of ​​the intermediate result register; The first data storage instruction is called to obtain the current operation result of the target complex vector and the real constant according to the data in the first intermediate continuous area and the second intermediate continuous area in the intermediate result register.

[0150] Optionally, the data reading and storing module 110 is specifically configured to call a second data reading instruction to sequentially read a plurality of current elements from the target complex vector; The real part and the imaginary part of each current element are stored in the complex register in sequence according to the forward order of each current element in the target complex vector.

[0151] Optionally, the at least one constant register includes: a third constant register; The data reading and storing module 110 is specifically used to call the data filling instruction, and store the real constant and the preset constant in the third constant register in sequence according to the second target storage number, and the second target storage number is determined according to the number of multiple current elements read.

[0152] Optionally, the processing module 120 is specifically configured to call a data operation instruction, operate on two data with the same ranking in the complex register and the third constant register, obtain a third intermediate result corresponding to each ranking, and store the third intermediate result corresponding to each ranking in the intermediate result register; The second data storage instruction is called to obtain the current operation result of the target complex vector and the real constant according to the data in the intermediate result register.

[0153] Optionally, the current operation result includes multiple sub-operation results; The processing module 120 is specifically configured to read two adjacent data corresponding to the current time from the intermediate result register according to the forward reading order of the data in the intermediate result register; The first data of two adjacent data is used as the real part of the sub-operation result corresponding to the current time, and the second data is used as the imaginary part of the sub-operation result corresponding to the current time.

[0154] Optionally, the data reading and storing module 110 is specifically configured to determine the current call quantity of the data reading instruction according to the vector length of the target complex vector and the read length of the data reading instruction; According to the current call quantity, a corresponding number of data read instructions are called in parallel, and the real parts and imaginary parts of the multiple current elements read by the data read instructions are stored in the complex registers corresponding to the data read instructions.

[0155] Optionally, the processing module 120 is specifically configured to call the data operation instructions corresponding to the data read instructions in parallel according to the data stored in the complex registers corresponding to the data read instructions and the data stored in the constant registers, and determine the current operation results corresponding to the data operation instructions; According to the current operation results corresponding to each data operation instruction, the current operation results of the target complex vector and the real constant are determined.

[0156] The above-mentioned device is used to execute the method provided by the aforementioned embodiment, and its implementation principle and technical effect are similar, which will not be repeated here.

[0157] The above modules may be one or more integrated circuits configured to implement the above methods, such as one or more application specific integrated circuits (ASIC), or one or more digital singnal processors (DSP), or one or more field programmable gate arrays (FPGA). For another example, when a module is implemented in the form of a processing element scheduling program code, the processing element may be a general-purpose processor, such as a central processing unit (CPU) or other processor that can call program code. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).

[0158] The above modules can be connected or communicated with each other via a wired connection or a wireless connection. The wired connection may include a metal cable, an optical cable, a hybrid cable, etc., or any combination thereof. The wireless connection may include a connection in the form of a LAN, a WAN, Bluetooth, a ZigBee, or NFC, or any combination thereof. Two or more modules may be combined into a single module, and any one module may be divided into two or more units. Those skilled in the art will clearly understand that for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the method embodiment, and will not be repeated in this application.

[0159] Fig.13 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application, which may be a computing device with data processing capabilities.

[0160] The device includes: a processor 801 and a storage medium 802 .

[0161] The storage medium 802 is used to store programs, and the processor 801 calls the programs stored in the storage medium 802 to execute the above method embodiment. The specific implementation method and technical effect are similar and will not be repeated here.

[0162] The storage medium 802 stores program code, and when the program code is executed by the processor 801, the processor 801 executes various steps of the data processing method according to various exemplary embodiments of the present application described in the above “Exemplary Method” section of this specification.

[0163] The processor 801 may be a general-purpose processor, such as a central processing unit (CPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, and may implement or execute the methods, steps and logic block diagrams disclosed in the embodiments of the present application. A general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the method disclosed in the embodiments of the present application may be directly embodied as being executed by a hardware processor, or may be executed by a combination of hardware and software modules in the processor.

[0164] The storage medium 802, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer executable programs and modules. The storage medium may include at least one type of storage medium, for example, a flash memory, a hard disk, a multimedia card, a card-type storage medium, a random access storage medium (Random Access Memory, RAM), a static random access storage medium (Static Random Access Memory, SRAM), a programmable read-only storage medium (Programmable Read Only Memory, PROM), a read-only storage medium (Read Only Memory, ROM), an electrically erasable programmable read-only storage medium (Electrically Erasable Programmable Read-Only Memory, EEPROM), a magnetic storage medium, a disk, an optical disk, and the like. The storage medium is any other medium that can be used to carry or store the desired program code in the form of an instruction or data structure and can be accessed by a computer, but is not limited thereto. The storage medium 802 in the embodiment of the present application can also be a circuit or any other device that can realize a storage function, for storing program instructions and / or data.

[0165] Optionally, the present application also provides a program product, such as a computer-readable storage medium, including a program, which is used to execute the above method embodiment when executed by a processor.

[0166] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0167] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0168] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0169] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor (English: processor) to perform some steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only storage medium (English: Read-Only Memory, referred to as: ROM), random access storage medium (English: Random Access Memory, referred to as: RAM), disk or optical disk and other media that can store program codes.

Claims

1. A data processing method, characterized in that: For performing addition or subtraction operations on complex vectors and real constants, the method comprises: Calling a data read instruction in a target instruction set, reading multiple current elements of a target complex vector to be calculated from a memory, and storing real parts and imaginary parts of the multiple current elements in a complex register; each of the current elements includes: a real part and an imaginary part; Calling a data filling instruction in the target instruction set to store the real constant to be calculated and the preset constant into at least one constant register; According to the data stored in the complex register and the data stored in each of the constant registers, the data operation instruction in the target instruction set is called to determine the current operation result of the target complex vector and the real constant, and the current operation result is stored in the memory, wherein the data operation instruction includes: an addition operation instruction or a subtraction operation instruction.

2. The method according to claim 1, characterized in that The calling of the data read instruction in the target instruction set, reading multiple current elements of the target complex vector to be calculated from the memory, and storing the real parts and imaginary parts of the multiple current elements into the complex register, includes: Calling a first data read instruction to sequentially read a plurality of current elements from the target complex vector; According to the order of each current element in the target complex vector, the real part of each current element is sequentially stored in the first initial continuous area of ​​the complex register, and the imaginary part of each current element is sequentially stored in the second initial continuous area of ​​the complex register.

3. The method according to claim 2, characterized in that The at least one constant register includes: a first constant register and a second constant register; The calling of the data filling instruction in the target instruction set to store the real constant to be calculated and the preset constant into at least one constant register includes: The data filling instruction is called to store the real constant into the first constant register and the preset constant into the second constant register according to a first target storage number of times; the first target storage number of times is determined according to the number of the plurality of current elements read.

4. The method according to claim 3, characterized in that The step of calling the data operation instruction in the target instruction set according to the data stored in the complex register and the data stored in each of the constant registers to determine the current operation result of the target complex vector and the real constant includes: Calling the data operation instruction to operate on two data with the same ranking in the first initial continuous area and the first constant register to obtain first intermediate results corresponding to each ranking, and storing the first intermediate results corresponding to each ranking in the first intermediate continuous area of ​​the intermediate result register; Calling the data operation instruction to operate on two data with the same ranking in the second initial continuous area and the second constant register to obtain second intermediate results corresponding to each ranking, and storing the second intermediate results corresponding to each ranking in the second intermediate continuous area in the intermediate result register; The first data storage instruction is called to obtain the current operation result of the target complex vector and the real constant according to the data in the first intermediate continuous area and the second intermediate continuous area in the intermediate result register.

5. The method according to claim 1, characterized in that The calling of the data read instruction in the target instruction set, reading multiple current elements of the target complex vector to be calculated from the memory, and storing the real parts and imaginary parts of the multiple current elements into the complex register, includes: Calling a second data read instruction to sequentially read a plurality of current elements from the target complex vector; According to the forward order of each current element in the target complex vector, the real part and the imaginary part of each current element are sequentially stored in the complex register.

6. The method according to claim 5, characterized in that The at least one constant register includes: a third constant register; the calling of the data filling instruction in the target instruction set to store the real constant to be calculated and the preset constant in the at least one constant register includes: The data filling instruction is called, and the real constant and the preset constant are sequentially and cross-stored in the third constant register according to a second target storage number, wherein the second target storage number is determined according to the number of the multiple current elements read.

7. The method according to claim 6, characterized in that The step of calling the data operation instruction in the target instruction set according to the data stored in the complex register and the data stored in each of the constant registers to determine the current operation result of the target complex vector and the real constant includes: Calling the data operation instruction to operate on two data with the same ranking in the complex register and the third constant register to obtain third intermediate results corresponding to each ranking, and storing the third intermediate results corresponding to each ranking in the intermediate result register; The second data storage instruction is called to obtain the current operation result of the target complex vector and the real constant according to the data in the intermediate result register.

8. The method according to claim 7, characterized in that The current operation result includes multiple sub-operation results; The calling of the second data storage instruction to obtain the current operation result of the target complex vector and the real constant according to the data in the intermediate result register includes: According to the forward reading order of the data in the intermediate result register, read two adjacent data corresponding to the current time from the intermediate result register; The first data of two adjacent data is used as the real part of the sub-operation result corresponding to the current time, and the second data is used as the imaginary part of the sub-operation result corresponding to the current time.

9. The method according to claim 1, characterized in that: The calling target instruction set includes: Determining a current call quantity of the data read instruction according to a vector length of the target complex vector and a read length of the data read instruction; According to the current call quantity, a corresponding number of the data read instructions are called in parallel, and the real parts and imaginary parts of the multiple current elements read by the data read instructions are stored in the complex registers corresponding to the data read instructions.

10. The method according to claim 9, characterized in that The step of calling the data operation instruction in the target instruction set according to the data stored in the complex register and the data stored in each of the constant registers to determine the current operation result of the target complex vector and the real constant includes: According to the data stored in the complex registers corresponding to the data read instructions and the data stored in the constant registers, the data operation instructions corresponding to the data read instructions are called in parallel to determine the current operation results corresponding to the data operation instructions; According to the current operation results corresponding to each of the data operation instructions, the current operation results of the target complex vector and the real constant are determined.

11. A data processing device, characterized in that: Used to perform addition or subtraction operations on complex vectors and real constants, the device includes: a data reading and storing module and a processing module; The data reading and storing module is used to call the data reading instruction in the target instruction set, read multiple current elements of the target complex vector to be calculated from the memory, and store the real part and the imaginary part of the multiple current elements into the complex register; each of the current elements includes: a real part and an imaginary part; The data reading and storing module is used to call the data filling instruction in the target instruction set to store the real constant to be calculated and the preset constant in at least one constant register; The processing module is used to call the data operation instruction in the target instruction set according to the data stored in the complex register and the data stored in each of the constant registers, determine the current operation result of the target complex vector and the real constant, and store the current operation result in the memory, wherein the data operation instruction includes: an addition operation instruction or a subtraction operation instruction.

12. An electronic device, characterized in that: include: A processor, a storage medium and a bus, wherein the storage medium stores program instructions executable by the processor, and when the electronic device is running, the processor and the storage medium communicate via the bus, and the processor executes the program instructions to implement the data processing method as described in any one of claims 1 to 10.

13. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by the processor, the data processing method according to any one of claims 1 to 10 is implemented.

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