Random number source and configuration method thereof

Through the fusion design of multiple random number generators, the problem of increasing hardware overhead when existing random number sources improve calculation accuracy is solved, and a random number source design with high accuracy and low hardware cost is achieved.

CN119883193APending Publication Date: 2025-04-25CHANGSHA SEMICON TECH & APPL INNOVATION RES INST
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Patent Information

Application Number
CN202411726192.4
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-11-28
Publication Date
2025-04-25

AI Technical Summary

Technical Problem

While improving the accuracy of calculation, the existing random number source design increases hardware overhead and computing cycles, resulting in challenges in practical applications.

Method used

Multiple random number generators are used to fuse in a rotational method. By connecting n-m+1 random number generators, including an m-bit random number generator and n-m 1-bit random number generator, the calculation accuracy of the random number source is improved.

Benefits of technology

This design can meet the demand for multiple circuits to generate random number sources, improve the calculation accuracy of random number sources, and reduce hardware costs.

✦ Generated by Eureka AI based on patent content.

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Abstract

The invention provides a random number source and a configuration method thereof. The random number source comprises (n-m + 1) random number generators which are connected in sequence, wherein the first random number generator is an m-bit random number generator, and the other (n-m) random number generators are 1-bit random number generators. The multiple random number generators are fused through the rotation method, the requirements of multiple circuits for generating random number sources and different progressive precisions can be met, the calculation accuracy of the random number sources is improved, and the hardware cost is reduced.
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Description

Technical Field

[0001] The invention belongs to the technical field of random number generation, and in particular relates to a random number source and a configuration method thereof. Background Art

[0002] In recent years, a variety of random source design schemes based on low-discrepancy sequences have emerged. These schemes have made important progress in design by virtue of the high accuracy and good asymptotic precision of low-discrepancy sequences. Among them, the random sources designed using Halton sequences [Alaghi et al. Stochastic circuits for real-time image-processing applications [C]. DAC, pages 136: 1-136: 6, 2013] and Sobol sequences [S. Liu and J. Han. Energy efficient stochastic computing with Sobol sequences [C]. Design, Automation and Test in Europe Conference and Exhibition (DATE), 2017: 650-653.] show good uniform distribution characteristics in the time domain. However, these random source design schemes generally face the problem of high hardware cost, resulting in most of the hardware cost of random computing circuits being occupied by them. At the same time, the random number source design based on pseudo-random number sequences, such as the design scheme using LFSR (linear feedback shift register) as a random source, although it has extremely low hardware overhead, is not satisfactory in terms of computational accuracy and asymptotic precision. In order to improve the accuracy of pseudo-random sequences, a random source capable of deterministic calculations was proposed. However, while achieving high accuracy, it greatly increases the length of the random bit sequence, which undoubtedly increases the operation cycle and hardware overhead of the random calculation circuit, making it still face certain challenges in practical applications. Summary of the invention

[0003] The purpose of the present invention is to provide a random number source and a configuration method thereof to improve the calculation accuracy of the random number source in view of the deficiencies in the prior art.

[0004] In order to achieve the above object, the technical solution adopted by the present invention is:

[0005] A random number source, comprising n-m+1 random number generators connected in sequence; wherein the first random number generator is an m-bit random number generator, and the other nm random number generators are 1-bit random number generators;

[0006] The output end of the first i random number generators is connected to the input end of the AND gate, and the output end of the AND gate is connected to the input end of the i+1th random number generator, i=1,2…,nm.

[0007] The present invention uses a plurality of random number generators to fuse using a rotation method, thereby meeting the requirements of generating random number sources of various circuits and different asymptotic precisions, and improving the calculation accuracy of the random number source.

[0008] Furthermore, the first random number generator includes a linear feedback shift register and an XOR gate. The output ends of the first m-1 triggers of the linear feedback shift register are connected to the input ends of the XOR gate. After the output of the XOR gate and the feedback coefficient of the linear feedback shift register are ANDed, they are input into the first trigger of the linear feedback shift register.

[0009] The random number generator can output a sequence of all 0s, thereby outputting all binary numbers of the corresponding bit number through the linear feedback shift register LFSR.

[0010] Based on the same inventive concept, the present invention also provides a method for configuring a random number source, comprising the following process:

[0011] S1: Initialize the configuration mode of the random number source, the configuration mode includes: initial values ​​of n-m+1 random number generators, feedback polynomial of the first random number generator, scrambling mode of the first random number generator, combination mode of the trailing bits, scrambling mode of the trailing bits, and inversion mode of the trailing bits;

[0012] S2: Simulation to obtain the calculation accuracy of the initial configuration method

[0013] S3: Update the combination mode of the trailing bits, the scrambling mode of the trailing bits, and the inversion mode of the trailing bits, and keep the other configurations in the initial configuration mode, and simulate and obtain the calculation accuracy MAE of the configuration mode;

[0014] S4: If Then the updated MAE is

[0015] S5: Repeat steps S3-S4 until all the combinations of the trailing bits, the scrambling methods of the trailing bits, and the inversion methods of the trailing bits are traversed, and the trailing bits are selected. The corresponding configuration mode is taken as the first optimal configuration mode;

[0016] S6: Simulate and obtain the first optimal configuration 2 n-1 Bit time calculation accuracy 2 n-2 Bit time calculation accuracy Bit time calculation accuracy Calculates asymptotic precision weighted value

[0017]

[0018] S7: Update the initial values ​​of n-m+1 random number generators, the feedback polynomial of the first random number generator, and the scrambling method of the first random number generator. The remaining configurations remain in the first optimal configuration mode. Simulate and obtain the 2 n-1 Bit time calculation accuracy 2 n-2 Bit time calculation accuracy Bit time calculation accuracy Calculates asymptotic precision weighted value

[0019] S8: If there is ALLErr <ALLErr min , then update ALLErr to ALLErr min ;

[0020] S9: Repeat steps S7-S8 until all the initial values ​​of the n-m+1 random number generators, the feedback polynomial of the first random number generator, and the scrambling method of the first random number generator are traversed, and ALLErr is selected min The corresponding configuration method is taken as the optimal configuration method.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] The present invention uses a plurality of random number generators to fuse using a rotation method, thereby meeting the requirements of generating random number sources of various circuits and different asymptotic precisions, improving the calculation accuracy of the random number sources and reducing hardware costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of the basic structure of a random number source of the present invention;

[0024] Figure 2 It is a schematic diagram of the structure of n-bit NLFSR;

[0025] Figure 3 Schematic diagram of asymptotically uniform spatially distributed random number source implemented for NLFSR;

[0026] Figure 4 This is a schematic diagram of the multi-element fusion circuit of the rotation method;

[0027] Figure 5 This is a schematic diagram of the equivalent relationship after multi-source fusion using the rotation method. DETAILED DESCRIPTION

[0028] The present invention will be described in detail below in conjunction with the embodiments. It should be noted that the embodiments and features of the embodiments of the present invention can be combined with each other without conflict. For the convenience of description, if the words "upper", "lower", "left" and "right" appear in the following, they only indicate that the upper, lower, left and right directions are consistent with the drawings themselves, and do not limit the structure.

[0029] Example 1

[0030] The basic architecture of the spatiotemporal uniformly distributed random number source based on multi-source fusion in this embodiment is implemented as follows: Figure 1 As shown, it contains (n-m+1) uniform random number generators, which are connected in sequence, where the first random number generator is an m-bit random number generator, and the other nm random number generators are 1-bit random number generators. It is a group of binary number generators that can generate binary numbers of all corresponding digits in the corresponding period. Figure 1 The m-bit uniform random number generator can be used in 2 m Generate all m-bit binary numbers periodically.

[0031] The framework can generate random bit sequences that meet specific asymptotic precision requirements. When any asymptotic precision value 2n-q, 0≤q≤nm is taken within the asymptotic precision range, Figure 1 The m-bit uniform random number generator in the corresponding random number generator and the random bit sequence generated by (nqm) 1-bit uniform random number generators are used as the leading bit of the m input random bit sequence, and the number set obtained by concatenating the leading bits is equivalent to the set {0,1,...,2 n-q -1}, so as to achieve uniform distribution in the corresponding asymptotic space. In addition, the framework also includes a method for generating trailing bits, which is used to generate the remaining bits of each input random bit sequence. This part does not require additional hardware, and only needs to combine the most significant bits (MSB) to efficiently generate trailing bits.

[0032] After giving the basic architecture of a random number source that can generate asymptotically uniform spatial distribution, the basic architecture of NLFSR is used to implement the specific solution with this pseudo-random number source at a lower hardware cost. For the NLFSR used, Figure 2 As shown, based on the LFSR of corresponding length n, an XOR gate with (n-1)-bit input is added so that it can output a sequence of all 0s, thereby realizing the output of all binary numbers of corresponding bits through the LFSR.

[0033] For example, the first random number generator includes a linear feedback shift register LFSR and an XOR gate. The outputs of the first m-1 triggers of the linear feedback shift register are connected to the inputs of the XOR gate. The output of the XOR gate is ANDed with the feedback coefficient of the linear feedback shift register and then input into the first trigger of the linear feedback shift register.

[0034] like Figure 3 , through two-input and three-input examples, it shows how to realize a random number source with asymptotic spatial uniform distribution. The minimum asymptotic precision range is selected as 2 4 , for the first uniform random number generator, 4 bits are selected for operation, and the random number sources are connected by rotation method. The connection method of the two random number generators is as follows Figure 4 , the output of the first i random number generator is connected to the input of the AND gate, and the output of the AND gate is connected to the input of the i+1th random number generator, i = 1, 2…, nm. When the i-th random number source outputs the selected specific suppression signal, its output result is ANDed with the suppression signal of the first i-1 random number source. Only when the current i random number sources all output suppression signals, the output of the i+1th random number source is maintained for 1 clock cycle. The design can be set according to the required progressive precision range to reduce resource consumption. Figure 5 This is a schematic diagram of the equivalent relationship after multi-source fusion using the rotation method.

[0035] For the basic structure of the constructed asymptotic spatial uniform distribution, by changing the feedback polynomial setting, initial value setting, suppression signal in the rotation method and scrambling method of the (n-m+1) random number generators, the asymptotic precision of the random number source system output can be changed without affecting the accuracy.

[0036] The entire configuration space is optimized and divided into two parts. One part explores the feedback polynomial setting, initial value setting, suppression signal selection in the rotation method and scrambling method of (n-m+1) random number generators, thereby exploring better asymptotic accuracy; the other part explores the combination of trailing bits, trailing position scrambling and inversion operations in order to obtain the optimal accuracy.

[0037] The simulated signal is 1 or 0, which makes it not respond when the excitation signal arrives, and keeps the state unchanged. Scrambling is to disrupt the output order, such as changing the output of different bits of the 8-bit output. The original output is 11110000, and the output after scrambling is 10101010. The inversion operation is to process the output, such as the original output is 11110000, and the inversion is 00001111.

[0038] The entire configuration space is optimized and the configuration iteration algorithm is as follows:

[0039] (1) Set the input to be an SC core (random computation logic circuit), an m-bit random number generator, (nm) 1-bit random number generators, and the number of feedback polynomials A of the m-bit random number generators.

[0040] (2) Set the minimum asymptotic precision weighted value ALLErr min , Best Configuration C * , 2 n Output accuracy at bit time 2 n-1 Output accuracy at bit time Output accuracy at bit time

[0041] (3) Initialization parameter value ALLErr min ←+∞、C * ←null、

[0042] (4) A configuration method is randomly determined in each of the feedback polynomial of the m-bit random number generator, the (n-m+1) random number generator initialization values, the suppression signal selection in the rotation method, and the configuration of the m-bit random number generator scrambling method.

[0043] (5) Cycle traversal correspondence The configuration space of the size traverses all the combinations of the trailing bits, the randomness of the trailing bits, and the inversion of the trailing bits. The remaining configuration operations are a set of configuration methods randomly determined during the initialization mentioned above; Indicates rounding up. Indicates rounding down, and n% indicates the remainder operation.

[0044] (6) For each random number source obtained through traversal, the SC core containing the designed random number source is used to test the specified circuit to obtain its accuracy MAE. Then the updated MAE is And update configuration C * .

[0045] (7) The loop iteration corresponds to A*(m!) 2 *2 2n-1 The configuration space of size traverses the feedback polynomials of all m-bit random number generators, the initial values ​​of (n-m+1) random number generators, the suppression signal in the rotation method, and the scrambling method of the output of the m-bit random number generator. The remaining configuration operations are C * The optimal configuration for accuracy is noted.

[0046] (8) For each traversal of the random number source, the SC core containing the designed random number source is used to test the specified circuit to obtain a set of accuracy Apply weighted If there is ALLErr <ALLErr min , then update ALLErr to ALLErr min , update all accuracy values ​​and configuration C * .

[0047] The output theoretical value of the random number source is calculated, and the mean absolute value error between the theoretical value and the simulation result is selected to measure the accuracy of the calculation result.

[0048] Based on the partial optimization of accuracy and asymptotic precision, a configuration space search method that can quickly find the optimal configuration is proposed, and a heuristic algorithm is proposed as follows;

[0049] P1: Input is an SC core, an m-bit random number generator, (nm) 1-bit random number generators, and the number of feedback polynomials A of the m-bit random number generators;

[0050] P2: Output is the minimum asymptotic precision weighted value ALLErr min , Best Configuration C * , 2 n Output accuracy 2 n-1 Output accuracy Output accuracy

[0051] P3: Initialize ALLErr min ←+∞,C * ←null,

[0052] P4: Randomly determine a configuration method from the feedback polynomial of the m-bit random number generator, the (n-m+1) random number generator initialization values, the suppression signal in the rotation method, and the scrambling method configuration, and update the configuration C * ;

[0053] P5: Determine ALLErr old Is it equal to ALLErr? min , if not equal, execute the next step, otherwise stop; ALLErr old is the asymptotic precision weighted value of the previous cycle;

[0054] P6: Select the jth trailing bit combination (j is the number of cycles of the current step);

[0055] P7: Randomly select a group of trailing positions in a random manner;

[0056] P8: Randomly select a set of trailing bit inversion methods; the rest of the configurations use C * The configuration method in the random number source is used to test the SC core composed of the specified circuit to obtain its accuracy. like Update for Update Configuration C * ;

[0057] P9: Repeat step P8 t_b times;

[0058] P10: Repeat P7 to P9 t_d times;

[0059] P11: Repeat P6 to P10 m! times;

[0060] P12: Select the feedback polynomial of the j-th m-bit random number generator (j is the number of cycles in the current step);

[0061] P13: Randomly select a set of (n-m+1) initial values ​​of the random number generator;

[0062] P14: randomly selected a set of inhibitory signals from the rotation method;

[0063] Randomly select a scrambling method for the m-bit random number generator; the rest of the configurations use C * The configuration method in the random number source is used to test the specified circuit through the SC core to obtain its accuracy Apply weighted If ALLErr <ALLErr min Then assign Update Configuration C * ;

[0064] P15: Step P14 is repeated t_b times;

[0065] P16: Steps P13 to P15 are repeated t_d times;

[0066] P17: Steps P12 to P16 are repeated A times;

[0067] P18: Jump to step P5.

[0068] This configuration method greatly reduces the search space by introducing two controllable variables t_d and t_b. For an overall search, the search space size is reduced to A*t_d*t_b+m! *t_d*t_b. At the same time, an iterative loop is added to the outer layer, and the optimal configuration is found through partial iteration. The estimated number of iterations of the outer layer is set to D, and the final search space size after optimization becomes D*(A*t_d*t_b+m! *t_d*t_b).

[0069] t_d and t_b are used to control the number of iterations. Selecting appropriate t_d and t_b can reduce the iteration time consumption while achieving the accuracy and asymptotic precision, so as to achieve a fast configuration optimization process. t_d and t_b are obtained from experience and are adjusted according to the actual optimization situation, generally around 100 to 1000.

[0070] This embodiment aims at how to generate random numbers with high accuracy and high asymptotic precision with low overhead, and proposes a random number source design with asymptotic space uniform distribution based on multi-source fusion. By dividing and merging the space under different asymptotic precision requirements, multiple random number sources are used to fuse by rotation method, and the configuration space formed by different LFSR feedback polynomials [A. Alaghi, W. Qian, and JPHayes. The promise and challenge of stochastic computing [J]. IEEE TCAD, 37 (8): 1515-1531, 2018.], seed values ​​(initial values), scrambling and negation is explored to realize a solution that satisfies multiple circuits to generate random number sources. Through this design, a balance between asymptotic precision, accuracy and hardware cost is achieved, and a random number source with high asymptotic precision, high accuracy and low hardware cost is proposed.

[0071] Example 2

[0072] This embodiment selects three existing random number source designs for comparison, namely m-SSG, U-LFSR, and m-LFSR. The implementation process of m-SSG is that for a random calculation circuit with multiple inputs, the random bit sequence of each input is generated by a Sobol sequence generator separately. U-LFSR has multiple merged k-bit LFSRs to output random bit sequences, and its output satisfies spatial uniform distribution and has good output accuracy. The m-LFSR random number source is a random calculation circuit with multiple inputs, in which a LFSR is used for each input to generate a random bit sequence, and it is the most widely used random number source design.

[0073] The consumption of the LFSR of the random number source of this design is much lower than that of the LFSR used by the m-LFSR random number source. The random number source system of this design has only n-bit delay units, and consumes less hardware resources than the U-LFSR random number source. At the same time, it can also be obtained that the hardware resource consumption of the random number source of this design is much lower than that of the m-SSG random number source based on the low-discrepancy sequence design. At the same time, in the precision optimization method, t_d and t_b are both set to 100, which ensures that each iteration has sufficient random space, ensuring that it has good accuracy performance in the end.

[0074] For the compared random number sources, a test scheme with a bit width of 8 was proposed, and each experiment was repeated 10 times.

[0075] The accuracy error rates of all the tested random number sources are shown in Table 1 (Target 1 is the final error rate when the random number source of this design only considers the final accuracy, and Target 2 considers the final error rate under both the final accuracy and the asymptotic accuracy). It can be seen that in terms of computational accuracy, m-SSG generally has sufficiently high accuracy. Thanks to the low-discrepancy sequence it generates, its accuracy performance is the best. The average error rate of Target 1 is between U-LFSR and m-LFSR. At the same time, it also has excellent accuracy performance when paying attention to asymptotic accuracy and accuracy. In general, the accuracy performance of the random number source can be controlled by the iteration condition, and it performs well in all benchmark tests.

[0076] Table 1 Accuracy error rate of all tested random number sources

[0077]

[0078] In terms of asymptotic accuracy, the asymptotic accuracy of all the random number sources mentioned above is measured by measuring their calculation accuracy under different asymptotic accuracy conditions in a 2-input multiplier. For each random number source, more than 1000 random number input tests are performed. The designed comparison random number source has a bit width of 8, so it is compared with 2 in the 2-input multiplier circuit. 8 , 2 7 , 2 6 , 2 5 , 2 4 The error rate performance under the condition of asymptotic accuracy, the results are shown in Table 2.

[0079] Due to the low-discrepancy sequence generated by m-SSG, its output point distribution is relatively uniform, achieving excellent asymptotic precision performance. At the same time, it can be seen through comparison that the random number source of this design also has excellent asymptotic precision performance. While paying attention to both accuracy and asymptotic precision, its asymptotic precision performance is extremely excellent, and the error rate of the random bit sequence it generates is very similar to that of the m-SSG random number source design using m sobol sequence generators, and even in certain circumstances, its accuracy performance is even better. Moreover, the asymptotic precision performance of the designed random number source far exceeds that of other random number sources designed based on LFSR, and the target two asymptotic precision error rate is within 2 8 , 2 7 , 2 6 , 2 5 , 2 4 In the case of progressive accuracy, the accuracy is greater than 11.65%, less than 4.55%, greater than 3.19%, greater than 12.22%, and less than 15.83% compared with m-SSG. In addition, the component area is reduced by 90% on average compared with m-SSG, which is enough to reflect the superiority of the random number source of this design.

[0080] Table 2 Error rate of asymptotic precision of all tested random number sources

[0081]

[0082] From the above, we can see that through the optimized design and reasonable configuration implemented in this example, the random circuit maintains a high calculation accuracy while reducing the hardware cost, achieving an efficient random source design. This design of the random number source has a strong effect and application prospects.

[0083] The contents explained in the above embodiments should be understood as these embodiments are only used to more clearly illustrate the present invention, and are not used to limit the scope of the present invention. After reading the present invention, various equivalent forms of modifications to the present invention by those skilled in the art all fall within the scope defined by the claims attached to this application.

Claims

1. A random number source, characterized in that: It includes n-m+1 random number generators connected in sequence; the first random number generator is an m-bit random number generator, and the other nm random number generators are 1-bit random number generators; The output ends of the first i random number generators are connected to the input end of the AND gate, and the output end of the AND gate is connected to the input end of the i+1th random number generator, i=1, 2…, nm.

2. The random number source according to claim 1, characterized in that The first random number generator includes a linear feedback shift register and an XOR gate. The output end of the first m-1 triggers of the linear feedback shift register is connected to the input end of the XOR gate. After the output of the XOR gate and the feedback coefficient of the linear feedback shift register are ANDed, they are input into the first trigger of the linear feedback shift register.

3. A method for configuring a random number source according to any one of claims 1 to 2, characterized in that: The process includes: S1: Initialize the configuration mode of the random number source, the configuration mode includes: initial values ​​of n-m+1 random number generators, feedback polynomial of the first random number generator, scrambling mode of the first random number generator, combination mode of the trailing bits, scrambling mode of the trailing bits, and inversion mode of the trailing bits; S2: Simulation to obtain the calculation accuracy of the initial configuration method S3: Update the combination mode of the trailing bits, the scrambling mode of the trailing bits, and the inversion mode of the trailing bits, and keep the other configurations in the initial configuration mode, and simulate and obtain the calculation accuracy MAE of the configuration mode; S4: If Then the updated MAE is S5: Repeat steps S3-S4 until all the combinations of the trailing bits, the scrambling methods of the trailing bits, and the inversion methods of the trailing bits are traversed, and the trailing bits are selected. The corresponding configuration mode is taken as the first optimal configuration mode; S6: Simulate and obtain the first optimal configuration 2 n-1 Bit time calculation accuracy 2 n-2 Bit time calculation accuracy Bit time calculation accuracy Calculates asymptotic precision weighted value S7: Update the initial values ​​of n-m+1 random number generators, the feedback polynomial of the first random number generator, and the scrambling method of the first random number generator. The remaining configurations remain in the first optimal configuration mode. Simulate and obtain the 2 n-1 Bit time calculation accuracy 2 n-2 Bit time calculation accuracy Bit time calculation accuracy Calculates asymptotic precision weighted value S8: If there is ALLErr <ALLErr min , then update ALLErr to ALLErr min ; S9: Repeat steps S7-S8 until all the initial values ​​of the n-m+1 random number generators, the feedback polynomial of the first random number generator, and the scrambling method of the first random number generator are traversed, and ALLErr is selected min The corresponding configuration method is taken as the optimal configuration method.