Code Generation Method, Apparatus, Device, and Readable Storage Medium

Abstract

An embodiment of the present invention provides a code generation method, apparatus, device, and readable storage medium. Based on a target syntax tree corresponding to the code to be verified, a target module node corresponding to a module to be verified in the code to be verified is determined; a delay queue node corresponding to a target delay queue is inserted into the target module node, and nodes related to a specified signal group in the target syntax tree are modified; the target delay queue is used to randomly delay the output of the specified signal group; the modified target syntax tree is converted into target code including the target delay queue; the target code is used to verify the interface timing function of the module to be verified. Through the method of syntax tree instrumentation, it is convenient to inject errors into the module to be verified, reducing the complexity of error injection and the requirement threshold for the professional skills of verification personnel. At the same time, there is no need for verification personnel to write test cases corresponding to different transmission delays one by one, saving verification time and improving verification efficiency to a certain extent.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of computer technologies, and particularly to a code generation method, apparatus, device, and readable storage medium. Background Art

[0002] In hardware verification, verification personnel usually need to fully verify a module to ensure the accuracy and stability of its functions. Taking the timing function verification of an interface as an example, it is necessary to verify based on the timing specification of the interface to ensure that the signal transmission can be carried out within the correct time window.

[0003] In related technologies, it is often necessary for verification personnel to write corresponding test cases one by one for different transmission delays, and simulate different transmission delays based on these test cases to perform the timing function verification of the interface. However, the hardware verification process like this obtains code that can achieve different transmission delay outputs by writing test cases, and the complexity of code acquisition is relatively high and the verification efficiency is relatively low. Summary of the Invention

[0004] The embodiments of the present invention provide a code generation method, apparatus, device, and readable storage medium.

[0005] To solve the above problems, the embodiments of the present invention disclose a code generation method, and the method includes:

[0006] Based on the target syntax tree corresponding to the code to be verified, determine the target module node corresponding to the module to be verified in the code to be verified;

[0007] Insert the delay queue node corresponding to the target delay queue into the target module node, and modify the nodes in the target syntax tree related to the specified signal group; the target delay queue is used to randomly delay and output each specified signal in the specified signal group;

[0008] Convert the modified target syntax tree into target code including the target delay queue; the target code is used to perform the interface timing function verification of the module to be verified.

[0009] On the other hand, the embodiments of the present invention disclose a code generation apparatus, and the apparatus includes:

[0010] The first determination module is used to determine the target module node corresponding to the module to be verified in the code to be verified based on the target syntax tree corresponding to the code to be verified;

[0011] A first insertion module, configured to insert a delay queue node corresponding to a target delay queue into the target module node, and modify nodes in the target syntax tree related to a specified signal group; the target delay queue is used to randomly delay and output each specified signal in the specified signal group;

[0012] A first conversion module, configured to convert the modified target syntax tree into target code including the target delay queue; the target code is used to verify the interface timing function of the module to be verified.

[0013] In another aspect, an embodiment of the present invention discloses an electronic device, including: a processor, a memory, a communication interface, and a communication bus, where the processor, the memory, and the communication interface complete communication with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions cause the processor to execute the foregoing method.

[0014] An embodiment of the present invention also discloses a readable storage medium, on which executable instructions are stored, and when executed by one or more processors, cause the processors to execute the method as described above.

[0015] The embodiments of the present invention have the following advantages: In the code generation method provided in the embodiments of the present invention, based on the target syntax tree corresponding to the code to be verified, a target module node corresponding to the module to be verified in the code to be verified is determined; a delay queue node corresponding to a target delay queue is inserted into the target module node, and nodes in the target syntax tree related to a specified signal group are modified; the target delay queue is used to randomly delay and output the specified signal group; the modified target syntax tree is converted into target code including the target delay queue; the target code is used to verify the timing function of the interface of the module to be verified. In this way, since the syntax tree, as an abstract representation of the source code syntax structure, can clearly show the structure and relationship of the code, by inserting nodes of the target module node and modifying nodes in the target syntax tree at the syntax tree level, the position of node insertion can be located more quickly based on the structure of the syntax tree, and the logic of randomly delaying the output of signals can be introduced without changing the original semantic logic of the module to be verified. Compared with the verifier modifying or rewriting the code to be verified, the complexity of code generation can be reduced and the requirement threshold for the professional skills of the verifier can be lowered through the method of syntax tree instrumentation. At the same time, the target delay queue can randomly delay and output each specified signal in the specified signal group, eliminating the need for the verifier to individually write test cases corresponding to different transmission delays, saving verification time and improving verification efficiency to a certain extent. Description of the Drawings

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments of the present invention. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0017] Figure 1 is a flowchart of the steps of a code generation method provided by an embodiment of the present invention;

[0018] Figure 2 is a schematic diagram of the operation of a sequential delay queue provided by an embodiment of the present invention;

[0019] Figure 3 is a schematic diagram of the operation of an out-of-order delay queue provided by an embodiment of the present invention;

[0020] Figure 4 is a detailed flowchart of the steps of a code generation method provided by an embodiment of the present invention;

[0021] Figure 5 is a schematic diagram of the delay logic of a target delay queue provided by an embodiment of the present invention;

[0022] Figure 6 is a block diagram of a code generation device provided by an embodiment of the present invention;

[0023] Figure 7 is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Detailed Embodiments

[0024] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0025] Referring to Figure 1 , which shows a flowchart of the steps of a code generation method provided by an embodiment of the present invention. As Figure 1 shown, the method may specifically include the following steps:

[0026] Step 101: Based on the target syntax tree corresponding to the code to be verified, determine the target module node corresponding to the module to be verified in the code to be verified.

[0027] In an embodiment of the present invention, the code to be verified that needs to be verified in hardware is obtained. Among them, the code to be verified can be the Register Transfer Level (RTL) code corresponding to a hardware component. The hardware component can include an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Complex Programmable Logic Device (CPLD), a System on Chip (SoC), etc. During the process of hardware verification of a hardware component, it is necessary to perform interface timing function verification based on the code to be verified corresponding to the hardware component. The interface timing function verification aims to check whether the timing behavior of the interface of the hardware component under different operating conditions meets the design requirements. This is crucial for ensuring that the hardware system can communicate correctly and stably with other components or systems. By verifying the timing function of the interface, potential design defects can be discovered and resolved, thereby improving the overall performance and reliability of the hardware system.

[0028] Based on the code to be verified, the target syntax tree corresponding to the code to be verified is obtained. Among them, the target syntax tree is a data structure generated by the front end of the compiler when parsing the code to be verified. The target syntax tree can be an Abstract Syntax Tree (AST). The abstract syntax tree is a tree-like data structure used to represent the structure of the source code of a program. It is widely used in compilers and interpreters to help analyze and process the syntax structure of the program. The target syntax tree can represent the syntax components in the code to be verified in a tree-like structure. Each node in the target syntax tree can represent a syntax element (such as a statement, an expression, a module, a signal, etc.) in the syntax structure of the code to be verified. Each instruction in the code to be verified usually corresponds to a certain node or a group of nodes in the syntax tree.

[0029] Specifically, the compiler front end can perform syntax parsing on the code to be verified, split the code to be verified into multiple word sets (such as token symbols), perform preprocessing or macro expansion on the word sets (the specific method is similar to the macro expansion of the C language), perform syntax analysis on the word sets after preprocessing to identify various syntax structures, and then convert them into a target syntax tree. Relevant information in the code to be verified, such as the port list of a certain module, etc., can be extracted from the target syntax tree.

[0030] The module to be verified can be the basic unit in the code to be verified for defining components that require timing verification of data transfer interfaces. The module to be verified can include input, output, bidirectional (inout) ports, and internal logic (such as wires, registers, variables, and procedural blocks). In hardware design, data transfer interfaces can generally be divided into two types. One is based on the ready-valid handshake signal for handshaking. This type of interface ensures accurate data transfer through the interaction of the ready and valid signals. When the valid signal at the sender is effective, it indicates that the data is valid, and when the ready signal at the receiver is effective, it indicates that the receiver is ready to receive the data. Only when both the valid and ready signals are effective will the data be transferred. The other is data transfer based only on the valid signal. This interface is relatively simple. When the valid signal is effective, the data is considered valid and transferred. However, in this case, the receiver needs to be always ready to receive the data, otherwise data may be lost. For these two different types of data transfer interfaces, different strategies and methods need to be adopted during the verification process to ensure the correctness of their functions. In the embodiments of the present invention, the module to be verified can be used as the receiver, and the module to be verified and another sending module perform data transfer based on a specified signal group.

[0031] The target module node corresponding to the module to be verified is a specific node in the target syntax tree used to represent the module to be verified. The module to be verified usually refers to a relatively large code block or component, which may contain multiple sub-modules, functions, variable declarations, etc. Correspondingly, the target module node usually appears as a subtree or a set of nodes in the target syntax tree, and these subtrees or sets of nodes represent the code structure in the module. The target module node can contain multiple child nodes, and these child nodes represent a specific element inside the module to be verified, such as a statement, an expression, a parameter, and a signal, etc. For example, the target module node can contain multiple port child nodes, signal child nodes, assignment child nodes, and internal logic definitions. The target module node can start with the keyword "module" and end with the keyword "endmodule". The target module node can start with the root node, and multiple port child nodes and signal child nodes can be connected below it. The port child nodes and signal child nodes are connected by edges, indicating their dependency relationship and connection relationship. The assignment child nodes are distributed at different positions of the target module node and are used to describe the signal assignment logic inside the module. The port child nodes represent the input and output ports of the module, which can include input ports (input), output ports (output), and bidirectional ports (inout), and are used to describe the interface between the module and the external environment. Each port child node has attributes such as name, width, and direction. The signal child nodes represent the signals used inside the module, including wire types (wire) and register types (reg), etc., and are used to describe the signal connection and logic function inside the module. Each signal child node has attributes such as name, width, and type. The assignment child nodes represent the operation of assigning a value to a signal, including continuous assignment (assign) and procedural assignment (such as the assignment in an always block), and are used to describe the signal assignment logic inside the module. The continuous assignment child node usually starts with the keyword assign, followed by the assignment expression. The procedural assignment child node is located inside a procedural block (such as an always block) and can perform assignment operations according to different triggering conditions. The assignment node can contain attributes such as the signal to be assigned and the assignment expression.

[0032] When data is transmitted between the module to be verified and the sending module, the data transmission is based on a specified signal group. Herein, the specified signal group is the port signal involved in the interface timing verification requirements of the module to be verified, which can be one signal or multiple signals, and can be specifically determined according to the interface timing verification requirements of the module to be verified. For example, the specified signal group may include multiple port signals for signal handshaking. Exemplarily, the specified signal group may include io_task_ready, io_task_valid, io_task_bits_tag, io_task_bits_set, io_task_bits_opcode, io_task_bits_param, io_task_bits_alias. In the target syntax tree, the specified signal group usually appears as a leaf node or a position close to a leaf node under the target module node of the module to be verified.

[0033] In the target syntax tree, find the target module node corresponding to the module to be verified and the sub-nodes related to the specified signal group. Specifically, based on the module name of the module to be verified in the predefined target configuration file, node traversal can be performed in the target syntax tree to determine the module node that matches the module name as the target module node. Exemplarily, the traversal can start from the root node of the target syntax tree. The root node usually represents the entry point of the entire code file or program. Adopting the depth-first search (DFS) strategy, starting from the root node, traverse down along a path of the target syntax tree until reaching the leaf node. During the traversal, each node will be visited once. For each visited node, first check whether it represents a module, which can be specifically judged by the type or label of the node. If the current node is a module node and its name or identifier matches the name of the target module, mark it as "target module found". If the current node has been marked as "target module found", continue to search for the sub-nodes related to the specified signal group in its sub-nodes. Similarly, it can be judged by the type or label of the node. If the type or label of the node is a signal node and the name is the same as the signal name of the specified signal group, determine that this node is the sub-node related to the specified signal group.

[0034] If the target signal is not found on the current path, backtrack to the previous node and attempt to traverse its unvisited child nodes. This process continues until the target signal is found or all possible paths have been traversed. When the target module and target signal are found, the traversal process can end prematurely. If the target module node corresponding to the module to be verified or the child nodes corresponding to the specified signal group are not found after traversing the entire syntax tree, the traversal fails. It can be understood that during the traversal of the target syntax tree, the positions of the module to be verified and the specified signal group in the syntax tree (such as node numbers, path information, etc.) can be recorded for subsequent processing or analysis.

[0035] Step 102, insert a delay queue node corresponding to the target delay queue into the target module node, and modify the nodes in the target syntax tree related to the specified signal group; the target delay queue is used to randomly delay and output each specified signal in the specified signal group.

[0036] In the embodiments of the present invention, since during hardware verification, it is necessary to verify the interface timing function of the module to be verified, therefore, the insertion of transmission delay logic can be based on the target module node corresponding to the module to be verified to simulate signal transmission delay and achieve the delayed output of the specified signal group in the module to be verified. Based on the pre-constructed target delay queue, obtain the delay queue node corresponding to the target delay queue. Among them, the target delay queue can be a pre-constructed code module for generating random delays to randomly delay and output each specified signal in the specified signal group, and the target delay queue can include a sequential delay queue or an out-of-order delay queue. The delay queue node corresponding to the target delay queue can be composed of one or more nodes, and the delay queue node is used to describe the code structure of the target delay queue.

[0037] Insert the delay queue node corresponding to the target delay queue into the target module node. At the same time, since inserting the delay queue node into the target module node is equivalent to introducing a delay mechanism for the specified signal group, it is necessary to modify and adjust some nodes related to the specified signal group in the target syntax tree to ensure that the module logic of the module to be verified after inserting the transmission delay logic is not affected. The nodes related to the specified signal group may include the signal declaration node corresponding to the specified signal group, the expression node involving the specified signal group, the assignment statement node, etc. It can be understood that the positioning method of the child nodes related to the specified signal group in the target syntax tree can be determined based on the node type and attributes, which is similar to the positioning method of the target module node and will not be elaborated here. The content of modifying and adjusting the child nodes related to the specified signal group can be determined according to the code structure change represented by the target syntax tree after inserting the delay queue node, and specifically may include, but is not limited to, modifying the signal name, type, connection relationship of the specified signal group, and establishing a new connection between the specified signal group and the delay queue. Modifying and adjusting the child nodes related to the specified signal group is to ensure the structural consistency of the target syntax tree after adding the delay queue node.

[0038] In a possible implementation manner, after inserting the delay queue node corresponding to the target delay queue into the target module node, the original signal names in the signal declaration nodes related to the specified signal group in the target module node can be modified to the target signal names, and the original signal names of the specified signal group in each downstream node corresponding to the code downstream of the module to be verified in the code to be verified can be modified to the target signal names. In this way, since the delay queue node is inserted into the target module node and the specified signal group is represented by the target signal name in the delay queue node, it is necessary to directly update all the places referring to the original signal name in the target module node and the downstream nodes to the target signal name to ensure that the use of the specified signal group within the module to be verified and in the downstream module is not affected.

[0039] In another possible implementation, the original port signals of a specified signal group in the port sub-nodes used to describe port declaration parameters in the target module node can be modified to target signal names, and target sub-nodes with the original port signal names as their values are recreated in the target module node to complete the signal declaration of the specified signal group with the original port signal names. Then, a delay queue node is inserted into the target module node, such that the specified signal group with the target signal name as its name is input into the target delay queue, and the output signal of the target delay queue is connected to the specified signal group with the original port signal name as its name. That is, the remaining code inside the module under verification can still access the values of this specified signal group through the original port signal names. Correspondingly, the remaining logic inside the module under verification can continue to use the original port signal names (actually, the specified signal group with the internal name of the original port signal name connected to the output of the target delay queue) for subsequent processing or operations.

[0040] Step 103: Convert the modified target syntax tree into target code including the target delay queue; the target code is used to perform interface timing function verification on the module under verification.

[0041] In the embodiments of the present invention, by inserting a delay queue node into the target module node in the target syntax tree and modifying the nodes related to the specified signal group to complete the logical injection of transmission delay, the modified target syntax tree can be reconverted into target code. Among them, the target code includes a target delay queue. The difference between the converted target code and the original code to be verified lies in the insertion of the target delay queue and the modification of the port signal names and signal connection relationships of the specified signal group. Based on the target code, the transmission delay test of the module under verification can be implemented to complete the interface timing function verification of the module under verification. Exemplarily, simulation operation can be performed based on the target code. Since the target code includes a target delay queue, when data is transmitted between the sending module and the module under verification, each specified signal will be first input into the target delay queue, and the target delay queue will randomly delay and output each specified signal. It can be verified whether the sending module and the module under verification can normally transmit data and whether the sending module and the module under verification can operate normally when the specified signals are randomly delayed and output, so as to verify the interface timing function of the module under verification.

[0042] Exemplarily, the compiler can first convert the modified target syntax tree into an intermediate representation, such as GIMPLE, then convert the intermediate representation into a low-level intermediate representation, such as low-level GIMPLE, and generate a control flow graph (CFG). The control flow graph is used to represent the control flow inside the function and divide the statements into basic blocks. The compiler will convert the low-level GIMPLE into static single assignment (SSA) form. The compiler converts the GIMPLE in SSA form into initial RTL code, specifically by converting GIMPLE instructions into RTL instructions, including data conversion and instruction conversion. Optimize the generated initial RTL code to determine the final generated target code including the target delay queue.

[0043] In summary, based on the target syntax tree corresponding to the code to be verified, determine the target module node corresponding to the module to be verified in the code to be verified; insert the delay queue node corresponding to the target delay queue into the target module node, and modify the nodes in the target syntax tree related to the specified signal group; the target delay queue is used to randomly delay the output of the specified signal group; convert the modified target syntax tree into target code including the target delay queue; the target code is used to verify the interface timing function of the module to be verified. In this way, since the syntax tree, as an abstract representation of the source code syntax structure, can clearly show the structure and relationship of the code, by inserting nodes in the target module node and modifying the nodes in the target syntax tree at the syntax tree level, it is possible to more quickly locate the position of node insertion based on the structure of the syntax tree, and introduce the logic of signal random delay output without changing the original semantic logic of the module to be verified. Compared with the verifier modifying or rewriting the code to be verified, the method of syntax tree instrumentation can reduce the complexity of code generation and lower the requirement threshold for the professional skills of the verifier. At the same time, the target delay queue can randomly delay the output of each specified signal in the specified signal group, eliminating the need for the verifier to write test cases corresponding to different transmission delays one by one, saving verification time and improving the verification efficiency to a certain extent.

[0044] Furthermore, by instrumenting the delay queue node in the target syntax tree, random delay (i.e., error injection) is introduced into the code implementation logic, and in hardware simulation verification, the delay simulation situation can be adjusted arbitrarily by simply adjusting the parameters, so that various delay situations can be verified in place, making it easier to discover potential timing problems and boundary conditions, thereby improving the test coverage and reducing the risk caused by not covering certain situations, ensuring the robustness of the module function of the module to be verified under various transmission conditions.

[0045] Optionally, "modifying the nodes in the target syntax tree related to the specified signal group" in step 102 may include the following steps:

[0046] Step 201: Based on the signal names of the specified signals in the specified signal group, determine the target port sub-nodes corresponding to the specified signal group in the target module node, and modify the original port signal names corresponding to the specified signal group in the target port sub-nodes to target signal names.

[0047] In the embodiments of the present invention, the target module node contains multiple port sub-nodes, and the port sub-nodes describe the port declaration parameters corresponding to the module to be verified. The port declaration parameters define the signal names of each port involved in the module to be verified, including the signal names corresponding to the input port (input), output port (output), and bidirectional port (inout). Determine the port sub-nodes corresponding to the specified signal group in the target module node, and modify the original port signal names corresponding to the specified signal group included in the target port sub-nodes to target signal names. The target port sub-nodes corresponding to the specified signal group may include each port sub-node in the port sub-nodes of the target syntax tree whose name is the same as the signal names of the specified signals in the specified signal group. Therefore, the target port sub-nodes corresponding to the specified signal group can be determined in the target module node based on the signal names of the specified signals in the specified signal group. The target signal names corresponding to each specified signal group can be determined based on the original port signal names corresponding to each specified signal group. For example, a prefix identifier, such as DF_auto_0__, can be added to the front of the source port signal name to determine the target signal name. Exemplarily, assuming that the original port signal names of the target port sub-nodes corresponding to the specified signal group in the target module node are io_task_ready, io_task_valid, io_task_bits_tag, io_task_bits_set, io_task_bits_opcode, io_task_bits_param, io_task_bits_alias respectively, then the original port signal names in each port sub-node can be modified to the target signal names DF_auto_0__io_task_ready, DF_auto_0__io_task_valid, DF_auto_0__io_task_bits_tag, DF_auto_0__io_task_bits_set, DF_auto_0__io_task_bits_opcode, DF_auto_0__io_task_bits_param, DF_auto_0__io_task_bits_alias.

[0048] Since the port sub-nodes are used to represent the input and output ports of a module, modifying the original port signal names corresponding to the specified signal group included in the target port sub-nodes corresponding to the specified signal group to the target signal names is equivalent to modifying the signal interface names of the to-be-verified module and the external environment (such as the sending module) for each specified signal, facilitating the target delay queue to perform delayed output on each specified signal.

[0049] Step 202: Re-create a target sub-node with the name of the original port signal name in the target module node.

[0050] In the embodiment of the present invention, a target sub-node with the value of the original port signal name is re-created in the target module node. Specifically, after modifying the signal names in the port sub-nodes corresponding to the specified signal group, a target sub-node with the name of the original port signal name can be re-created after the port sub-nodes in the target module node. The type of the target sub-node can be a signal sub-node, and the target sub-node is used to define the connection and logical functions of the specified signal group inside the module. Exemplarily, after the port sub-nodes of the target module node, for each specified signal in the specified signal group, a signal sub-node with the name of the original port signal name of each specified signal can be re-created. In this way, it is equivalent to adding a declaration about the specified signal group again at the very beginning of the module implementation logic of the to-be-verified module after the port definition of the to-be-verified module in the to-be-verified code. For example, the manifestation in the to-be-verified module can be a declaration of the specified signal group based on a statement such as "wire + original port signal name".

[0051] In the embodiment of the present invention, modifying the original port signal names of the target port sub-nodes corresponding to the specified signal group to the target signal names and at the same time re-creating a target sub-node with the name of the original port signal name can eliminate the need to manually traverse and modify all places in the target module node that use the original port signal name, greatly reducing the workload of code refactoring.

[0052] Optionally, the embodiment of the present invention may further include the following steps:

[0053] Step 301: Determine the module instance node corresponding to the target module node in the target syntax tree.

[0054] In the embodiment of the present invention, in the to-be-verified code, there will be a to-be-verified module and the module instance after instantiating the to-be-verified module. Correspondingly, in the target syntax tree, there will also be a target module node corresponding to the to-be-verified module and a module instance node corresponding to the module instance.

[0055] Exemplarily, the target syntax tree can be traversed based on the node types and node attributes of each node in the target syntax tree to determine whether the node is a node of the module instance type. If so, it is determined whether the module referenced by the node matches the identifier or name of the target module node. If the module referenced by the node is the same as the identifier or name of the target module node, it is determined that the node is the module instance node corresponding to the target module node.

[0056] Step 302: Modify the port signal names corresponding to the specified signal group in the module instance node to the target signal names.

[0057] In an embodiment of the present invention, the port signal names corresponding to the specified signal group in the module instance node are modified to the target signal names, that is, the port signals of the specified signal group of the module instance are modified to the target signal names that are the same as the port signal names of the modified specified signal group of the module to be verified.

[0058] In an embodiment of the present invention, by modifying the port signal names corresponding to the specified signal group in the module instance node corresponding to the target module node to the target signal names that are the same as the port signal names of the specified signal group of the target module node, it is ensured that the port signal names corresponding to the specified signal group of the module and the module instance are consistent, maintaining the consistency of the port signal names and avoiding errors caused by mismatched port signal names.

[0059] Optionally, step 102 may include the following steps:

[0060] Step 401: Generate a target delay queue based on a predefined target configuration file; the target configuration file includes a queue depth, a maximum delay, a minimum delay, and a switch state for parameter configuration of the target delay queue.

[0061] In an embodiment of the present invention, a predefined target configuration file is obtained. The target configuration file may include the queue depth value, the maximum delay, and the minimum delay of the delay queue. The target configuration file is parsed to obtain the configuration parameters specified by the environment variables, including the queue depth value, the maximum delay, and the minimum delay of the delay queue. A delay queue is generated according to the parsed configuration parameters. Based on a pre-customized delay queue class, such as DelayQueue, the configuration parameters are used as the initialization parameters of the delay queue class to generate an instance of the delay queue, that is, the target delay queue.

[0062] Among them, the target delay queue can be a code module. The connection logic between the specified signal group and the delay queue and the internal delay logic of the target delay queue are defined in the target delay queue. Specifically, the connection logic can include that each specified signal with the name of the target signal name is input into the target delay queue, and the output signal of the target delay queue is connected to each specified signal with the name of the original port signal name. Exemplarily, inside the target delay queue, based on Verilog statements such as io_in_data[DF_auto_0__bits], io_in_ready[DF_auto_0__io_task_ready], io_in_valid[DF_auto_0__io_task_valid], the value of the new port signal, that is, the target signal name, is assigned to the input end of the target delay queue. And, based on Verilog statements such as io_out_data[DF_auto_0__bits_out], io_out_ready[__io_task_ready], io_out_valid[io_task_valid], the output signal of the target delay queue is connected to the internal specified signal group, that is, each specified signal with the name of the original port signal name.

[0063] Step 402: Obtain the delay queue node corresponding to the target delay queue.

[0064] In the embodiment of the present invention, syntax parsing is performed on the target delay queue, the code corresponding to the target delay queue is split into multiple word sets (such as token symbols), preprocessing or macro expansion is performed on the word sets (the specific method is similar to the macro expansion of the C language), syntax analysis is performed on the word sets after preprocessing is completed to identify various syntax structures therein, and then they are converted into delay queue nodes corresponding to the target delay queue. The delay queue node can include a root node and child nodes. The root node is used to represent the target delay queue itself, and the child nodes under the root node can represent the signal connection logic and signal assignment logic of the signal output and signal input of the target delay queue, etc.

[0065] Step 403: Insert the delay queue node corresponding to the target delay queue after the target child node.

[0066] In the embodiment of the present invention, after the target child node, the delay queue node is inserted into the target syntax tree, and the delay queue node is used as the downstream node of the target child node. Here, "after" is based on the traversal order, that is, when traversing in the order of first the parent node, then the child nodes, and the sibling nodes from left to right, the delay queue node will appear after the target child node.

[0067] In the embodiments of the present invention, a specified signal group in the code to be verified is randomly delayed by means of syntax tree instrumentation. A target delay queue capable of generating random delays is inserted in the handshake path of the specified signal group. Moreover, by setting the depth of the queue, the maximum and minimum values of the random delay, and controlling whether to enable random delay and setting the size of the random delay through environment variables during simulation operation, diverse simulation can be performed, making it easier to trigger edge verification situations that were originally difficult to trigger, thereby improving the test coverage. Furthermore, by converting the target delay queue into delay queue nodes and directly inserting them into the target child nodes in the target syntax tree to implement the delay instrumentation logic, the position where the delay queue needs to be instrumented can be more accurately located, thus ensuring the accuracy of the instrumentation.

[0068] Optionally, the embodiments of the present invention may further include the following steps:

[0069] Step 501: Based on the target delay queue in the target code, delay the output of the specified signal group; the target delay queue is an ordered delay queue or an unordered delay queue.

[0070] In the embodiments of the present invention, based on the target delay queue in the target code, the received specified signals are delayed and output to complete the transmission delay test of the module to be verified. By randomly delaying and outputting each specified signal through the target delay queue, it can be further verified whether the sending module and the module to be verified can normally perform data transmission under the condition of random delay output of the specified signals, and whether the sending module and the module to be verified can operate normally to perform the interface timing verification of the module to be verified.

[0071] The target delay queue is an ordered delay queue or an unordered delay queue. Among them, the ordered delay queue delays and outputs each specified signal in the specified signal group in a predetermined order, and the elements in the ordered delay queue are sorted according to the enqueue order and the specified delay time. Only when the delay time of an element arrives, the element will be taken out for processing. The unordered delay queue allows elements to be processed in any order within the delay time, rather than being output strictly according to the enqueue order.

[0072] Optionally, when the target delay queue is an ordered delay queue, step 501 may include the following steps:

[0073] Step 601: Based on the target delay queue, sequentially receive each specified signal sent by the sending module and the module to be verified to the target delay queue.

[0074] In an embodiment of the present invention, when data is transmitted between a sending module and a module to be verified, a target delay queue will successively receive each specified signal in a specified signal group sent by the sending module and the module to be verified to the target delay queue. After receiving each specified signal, the target delay queue will store each specified signal in sequence into a target buffer as an entry in the target buffer. Among them, the target buffer can be a First Input First Output (FIFO) queue.

[0075] Step 602: Determine the output order of each of the specified signals according to the reception order of each of the specified signals.

[0076] In an embodiment of the present invention, according to the reception order in which the target delay queue receives each specified signal, the output order of each specified signal is determined. Among them, the reception order of each specified signal can be the enqueue order in which each specified signal is stored in the target buffer, and the output order of each specified signal is the same as the reception order of each specified signal, that is, the specified signal received first is output first, and the specified signal received later is output later.

[0077] Step 603: When reaching the output order of any one of the specified signals, randomly generate a first delay time for the specified signal within the target time interval corresponding to the maximum delay value and the minimum delay value.

[0078] In an embodiment of the present invention, after determining the output order for each specified signal, when reaching the output order of any one specified signal, a first delay time is randomly generated for the specified signal within the target time interval corresponding to the preset maximum delay value and the minimum delay value. The first delay time can be any value within the target time interval. The maximum delay value and the minimum delay value can be determined by the configuration parameters of the delay queue in the target configuration file, and can be set according to requirements specifically, and the embodiments of the present invention do not limit this. Exemplarily, the maximum delay value is 10 time periods, the minimum delay value is 1 time period, and assuming there are 3 specified signals, the first delay times generated for each specified signal in sequence can be 2 time periods, 8 time periods, and 5 time periods.

[0079] Step 604: When reaching the first delay time randomly generated for the specified signal, output the specified signal through the target delay queue.

[0080] In an embodiment of the present invention, for any specified signal, when reaching the first delay time randomly generated for the specified signal, the target delay queue will output the specified signal, so that the output order of the specified signal output by the target delay queue is the same as the reception order of the specified signal received by the target delay queue.

[0081] Exemplarily, as Figure 2 shown, assume that the target delay queue sequentially receives specified signals 1, 2, and 3. Then the signal output order is also the specified signals 1, 2, and 3. First, a first random time delay A is generated for the specified signal 1. When the delay A is reached, the specified signal 1 is output. Then, a first random time delay B is generated for the specified signal 2. When the delay B is reached, the specified signal 2 is output. Finally, a first random time delay C is generated for the specified signal 3. When the delay C is reached, the specified signal 3 is output.

[0082] In the embodiment of the present invention, when the target delay queue is an ordered delay queue, the ordered delay queue can ensure that each specified signal is processed according to the enqueue order and the random delay time. Since the output order of the specified signals is fixed, the simulation verification process is more controllable, which helps the verification personnel to anticipate and understand the system behavior. Moreover, since the output of the specified signals maintains the original order, when a problem occurs, the verification personnel can more easily trace the source of the problem. The sequentiality of the signal output makes problem location and analysis more intuitive and simple.

[0083] Optionally, when the target delay queue is a disordered delay queue, step 501 may include the following steps:

[0084] Step 701: Based on the target delay queue, receive each of the specified signals sent by the sending module and the module to be verified to the target delay queue.

[0085] In the embodiment of the present invention, when data is transmitted between the sending module and the module to be verified, the target delay queue will sequentially receive each of the specified signals in the specified signal group sent by the sending module and the module to be verified to the target delay queue. After receiving the specified signal, the target delay queue will store the specified signal in sequence into the target buffer (Buffer) as an entry in the target buffer.

[0086] Step 702: Based on the random selector, randomly select a specified signal from the specified signal group as the signal to be output.

[0087] In the embodiment of the present invention, based on the random selector in the target delay queue, a table entry is randomly selected in the target buffer, that is, a specified signal is selected, and this specified signal is used as the signal to be output.

[0088] Step 703: Randomly generate a second delay time for the signal to be output within the target time interval corresponding to the maximum delay and the minimum delay.

[0089] In an embodiment of the present invention, a second delay time is randomly generated for the signal to be output. The second delay time may be a value randomly generated within a target time interval corresponding to a preset maximum delay and a minimum delay. The maximum delay and the minimum delay may be determined according to configuration parameters of a delay queue in a target configuration file, and may be set according to requirements by the user. The embodiment of the present invention does not limit this. Exemplarily, the maximum delay is 10 time periods, and the minimum delay is 1 time period. Assuming that there are 3 specified signals, the first delay times generated for each specified signal in sequence may be 3 time periods, 5 time periods, and 2 time periods.

[0090] Step 704: When the second delay time corresponding to the signal to be output is reached, output the signal to be output through the target delay queue.

[0091] In an embodiment of the present invention, when the second delay time randomly generated for the signal to be output is reached, the target delay queue outputs the signal to be output.

[0092] Step 705: Randomly select a specified signal from the specified signal group again based on the random selector as the signal to be output, and start execution until all the specified signals in the specified signal group are output.

[0093] In an embodiment of the present invention, after the output of a signal to be output is completed, randomly select a specified signal from the specified signal group again based on the random selector as the signal to be output, randomly generate a second delay time for the signal to be output, and when the second delay time is reached, output the signal to be output until all the specified signal groups are output.

[0094] Exemplarily, as Figure 3 shown, assuming that the target delay queue receives specified signals 1, 2, and 3 in sequence, the signal output order is also specified signals 1, 2, and 3. Based on the random selector, the signal to be output is selected as specified signal 2. First, a second random time is generated for specified signal 2. When the second random time corresponding to specified signal 2 is reached, specified signal 2 is output. Then, based on the random selector, the signal to be output is selected as specified signal 3, and a second random time is generated for specified signal 3. When the second random time corresponding to specified signal 3 is reached, specified signal 3 is output. Finally, based on the random selector, the signal to be output is selected as specified signal 1, and a second random time is generated for specified signal 1. When the second random time corresponding to specified signal 1 is reached, specified signal 3 is output.

[0095] In an embodiment of the present invention, when the target delay queue is an out-of-order delay queue, the out-of-order delay queue allows each specified signal to reach the receiving end in any order after random delay processing. For a verification scenario that is sensitive to data order, an out-of-order delay queue is adopted, enabling the module under verification to more flexibly handle the uncertainty of signal arrival. At the same time, the out-of-order delay queue can more realistically simulate the actual signal transmission situation. Signal transmission in a network is often affected by various factors, including network congestion, transmission delay, etc., which may cause signals to arrive out of order. Using an out-of-order delay queue can better simulate this situation, thereby verifying the performance of the system in an actual environment.

[0096] Exemplarily, Figure 4 shows a specific step flowchart of a code generation method, as Figure 4 shown, the user inputs RTL code (such as Verilog or SystemVerilog) and a target configuration file (the target configuration file contains a specified signal group that needs to be error-injected), parses the RTL code, first performs lexical analysis based on a lexical analyzer (lexer), and then splits the RTL code into multiple token sets. After preprocessing, syntax analysis is performed based on a syntax analyzer (parser) to obtain an abstract syntax tree (AST), that is, the target syntax tree. Based on the specified signal group indicated in the target configuration file, the target syntax tree is modified, including modifying the port signal name of the target port sub-node corresponding to the specified signal group in the target module node corresponding to the module under verification, re-creating a target sub-node with the original port signal name, inserting a delay queue node corresponding to the target delay queue, and modifying the port signal name corresponding to the specified signal group in the module instance node to the target signal name. The modified target syntax tree is restored to obtain the new RTL code after the target delay queue is inserted.

[0097] Exemplarily, Figure 5 shows a delay logic schematic diagram of a target delay queue, as Figure 5 shown, when the target delay queue is an in-order delay queue, the specified signal is input into the target buffer area in the in-order delay queue, that is, Buffers. In the order in which the specified signals are stored in Buffers, random delays are generated for the specified signals in sequence and output. When the target delay queue is an out-of-order delay queue, the specified signal is input into the target buffer area in the in-order delay queue, that is, Buffers. A random selector randomly selects one specified signal from multiple specified signals in the target buffer area, generates a random delay for it, and outputs the specified signal.

[0098] Referring to Figure 6 , shows a block diagram of a code generation device provided by an embodiment of the present invention, as Figure 6As shown, the device may specifically include:

[0099] A first determination module 801, configured to determine a target module node corresponding to a to-be-verified module based on a target syntax tree corresponding to the to-be-verified code;

[0100] A first insertion module 802, configured to insert a delay queue node corresponding to a target delay queue into the target module node and modify nodes in the target syntax tree related to a specified signal group; the target delay queue is used to randomly delay and output each specified signal in the specified signal group;

[0101] A first conversion module 803, configured to convert the modified target syntax tree into target code including the target delay queue; the target code is used to perform interface timing function verification on the to-be-verified module.

[0102] An embodiment of the present invention provides a code generation device, which determines a target module node corresponding to a to-be-verified module in to-be-verified code based on a target syntax tree corresponding to the to-be-verified code; inserts a delay queue node corresponding to a target delay queue into the target module node and modifies nodes in the target syntax tree related to a specified signal group; the target delay queue is used to randomly delay and output a specified signal group; converts the modified target syntax tree into target code including the target delay queue; the target code is used to perform interface timing function verification on the to-be-verified module. In this way, since the syntax tree, as an abstract representation of the source code syntax structure, can clearly show the structure and relationship of the code, by completing node insertion of the target module node and node modification in the target syntax tree at the syntax tree level, it is possible to more quickly locate the position of node insertion based on the structure of the syntax tree, and introduce the logic of signal random delay output without changing the original semantic logic of the to-be-verified module. Compared with the verifier modifying or rewriting the to-be-verified code, through the method of syntax tree instrumentation, the complexity of code generation can be reduced and the requirement threshold for the professional skills of the verifier can be lowered. At the same time, the target delay queue can randomly delay and output each specified signal in the specified signal group, eliminating the need for the verifier to individually write test cases corresponding to different transmission delays, saving verification time and improving verification efficiency to a certain extent.

[0103] Optionally, the first insertion module 802 includes:

[0104] A first modification module, configured to determine a target port sub-node corresponding to the specified signal group in the target module node based on the signal names of the specified signals in the specified signal group, and modify the original port signal name corresponding to the specified signal group in the target port sub-node to a target signal name;

[0105] A first creation module, configured to recreate a target sub-node named after the original port signal name in the target module node.

[0106] Optionally, the device further includes:

[0107] A second determination module, configured to determine a module instance node corresponding to the target module node in the target syntax tree;

[0108] A second modification module, configured to modify the port signal name corresponding to the specified signal group in the module instance node to the target signal name.

[0109] Optionally, the first insertion module 802 includes:

[0110] A first generation module, configured to generate a target delay queue based on a predefined target configuration file; the target configuration file includes a queue depth, a maximum delay value, a minimum delay value, and a switch state for parameter configuration of the target delay queue;

[0111] A first acquisition module, configured to acquire a delay queue node corresponding to the target delay queue;

[0112] A first insertion sub-node, configured to insert the delay queue node corresponding to the target delay queue after the target sub-node.

[0113] Optionally, the device further includes:

[0114] A first output module, configured to perform delayed output on the specified signal group based on the target delay queue in the target code; the target delay queue is an ordered delay queue or an unordered delay queue.

[0115] Optionally, when the target delay queue is the ordered delay queue, the first delay module includes:

[0116] A first reception module, configured to sequentially receive each of the specified signals sent by a sending module and the module to be verified to the target delay queue based on the target delay queue;

[0117] A third determination module, configured to determine the output order of each of the specified signals according to the reception order of each of the specified signals;

[0118] A second generation module, configured to randomly generate a first delay time for the specified signal within a target time interval corresponding to the maximum delay value and the minimum delay value when the output order of any of the specified signals is reached;

[0119] The first output sub-module is configured to output the specified signal through the target delay queue when the first delay time randomly generated for the specified signal is reached.

[0120] Optionally, when the target delay queue is the out-of-order delay queue, the first delay module includes:

[0121] The second receiving module is configured to receive each of the specified signals sent by the sending module and the module to be verified to the target delay queue based on the target delay queue;

[0122] The first selection module is configured to randomly select a specified signal from the specified signal group as the signal to be output based on a random selector;

[0123] The third generation module is configured to randomly generate a second delay time for the signal to be output within a target time interval corresponding to a maximum delay value and a minimum delay value;

[0124] The second output sub-module is configured to output the signal to be output through the target delay queue when the second delay time corresponding to the signal to be output is reached;

[0125] The first execution module is configured to restart the execution from randomly selecting a specified signal from the specified signal group as the signal to be output based on the random selector until all the specified signals in the specified signal group are output.

[0126] Refer to Figure 7 , which is a schematic structural diagram of an electronic device provided by an embodiment of the present invention. As Figure 7 shown, the electronic device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface complete communication with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions cause the processor to execute the code generation method of the foregoing embodiment. The executable instructions may form a program.

[0127] An embodiment of the present invention provides a readable storage medium, on which executable instructions are stored. When executed by one or more processors, the executable instructions cause the processor to execute the code generation method of the foregoing embodiment.

[0128] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is the difference from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0129] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a device, or a computer program product. Therefore, the embodiments of the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code. It should be noted that all actions of obtaining signals, information, or data in this application are carried out on the premise of complying with the corresponding data protection regulations and policies of the country where the location is located and obtaining the authorization given by the owner of the corresponding device. The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal devices generate a device for implementing the functions specified in the process Figure 1 one process or multiple processes and / or blocks Figure 1 a device for implementing the functions specified in one block or multiple blocks.

[0130] These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing terminal device to work in a predictive manner, so that the instructions stored in the computer-readable memory generate a manufactured product including an instruction device, and the instruction device implements the functions specified in the process Figure 1 one process or multiple processes and / or blocks Figure 1 a device for implementing the functions specified in one block or multiple blocks.

[0131] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device, so that a series of operation steps are executed on the computer or other programmable terminal device to generate a computer-implemented process. Therefore, the instructions executed on the computer or other programmable terminal device provide steps for implementing the functions specified in the process Figure 1 one process or multiple processes and / or blocks Figure 1 a device for implementing the functions specified in one block or multiple blocks.

[0132] Although the preferred embodiments of the embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications to these embodiments once they know the basic creative concepts. Therefore, the appended claims are intended to be construed as including the preferred embodiments and all changes and modifications falling within the scope of the embodiments of the present invention.

[0133] Finally, it should also be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or terminal device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or terminal device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or terminal device comprising the said element.

[0134] The above has introduced in detail a method for generating an instruction stream file, an apparatus for generating an instruction stream file, an electronic device and a readable storage medium provided by the present invention. Specific examples are used in this text to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A code generation method, characterized in that, The method includes: Based on the target syntax tree corresponding to the code to be verified, determining a target module node corresponding to the module to be verified in the code to be verified; Inserting a delay queue node corresponding to a target delay queue into the target module node, and modifying nodes in the target syntax tree related to a specified signal group; the target delay queue is used to randomly delay and output each specified signal in the specified signal group; Converting the modified target syntax tree into target code including the target delay queue; the target code is used to verify the interface timing function of the module to be verified; Wherein, inserting a delay queue node corresponding to a target delay queue into the target module node, and modifying nodes in the target syntax tree related to a specified signal group includes: Based on a pre-constructed target delay queue, obtaining a delay queue node corresponding to the target delay queue; Inserting the delay queue node corresponding to the target delay queue into the target module node; Changing the original signal names in the signal declaration nodes related to the specified signal group in the target module node to target signal names, and changing the original signal names of the specified signal group in each downstream node corresponding to the code downstream of the module to be verified in the code to be verified to target signal names in the target syntax tree.

2. The method according to claim 1, characterized in that, The modification of the nodes in the target syntax tree related to the specified signal group further includes: Based on the signal names of the specified signals in the specified signal group, determining a target port sub-node corresponding to the specified signal group in the target module node, and changing the original port signal name corresponding to the specified signal group in the target port sub-node to a target signal name; Re-creating a target sub-node with the name of the original port signal name in the target module node.

3. The method according to claim 2, wherein The method further includes: Determining a module instance node corresponding to the target module node in the target syntax tree; Changing the port signal name corresponding to the specified signal group in the module instance node to the target signal name.

4. The method according to claim 2, wherein The insertion of a delay queue node corresponding to a target delay queue into the target module node further includes: Generating a target delay queue based on a predefined target configuration file; the target configuration file includes a queue depth, a maximum delay, a minimum delay, and a switch state for parameter configuration of the target delay queue; Obtaining a delay queue node corresponding to the target delay queue; Inserting the delay queue node corresponding to the target delay queue after the target sub-node.

5. The method according to claim 1, wherein The method further includes: Based on the target delay queue in the target code, performing a delay output on the specified signal group; the target delay queue is an ordered delay queue or an unordered delay queue.

6. The method according to claim 5, characterized in that, When the target delay queue is the ordered delay queue, the performing a delay output on the specified signal group based on the target delay queue in the target code includes: Based on the target delay queue, sequentially receiving each specified signal sent by a sending module and the module to be verified to the target delay queue; Determine the output order of each of the specified signals according to the reception order of each of the specified signals; When the output order of any one of the specified signals is reached, randomly generate a first delay time for the specified signal within the target time interval corresponding to the maximum delay value and the minimum delay value; When the first delay time randomly generated for the specified signal is reached, output the specified signal through the target delay queue.

7. The method according to claim 5, characterized in that When the target delay queue is the out-of-order delay queue, the delaying and outputting of the specified signal group based on the target delay queue in the target code includes: Based on the target delay queue, receive each of the specified signals sent by the sending module and the module to be verified to the target delay queue; Based on the random selector, randomly select a specified signal from the specified signal group as the signal to be output; Randomly generate a second delay time for the signal to be output within the target time interval corresponding to the maximum delay value and the minimum delay value; When the second delay time corresponding to the signal to be output is reached, output the signal to be output through the target delay queue; Restart from randomly selecting a specified signal from the specified signal group as the signal to be output based on the random selector until all the specified signals in the specified signal group are output.

8. A code generation device, characterized in that, The device includes: A first determination module, configured to determine a target module node corresponding to the module to be verified in the code to be verified based on a target syntax tree corresponding to the code to be verified; A first insertion module, configured to insert a delay queue node corresponding to the target delay queue into the target module node and modify nodes in the target syntax tree related to the specified signal group; the target delay queue is used to randomly delay and output each of the specified signals in the specified signal group; A first conversion module, configured to convert the modified target syntax tree into a target code including the target delay queue; the target code is used to perform interface timing function verification on the module to be verified; Wherein, the first insertion module is further configured to obtain a delay queue node corresponding to the target delay queue based on a pre-constructed target delay queue; insert the delay queue node corresponding to the target delay queue into the target module node; modify the original signal names in the signal declaration nodes related to the specified signal group in the target module node to target signal names, and modify the original signal names of the specified signal group in each downstream node corresponding to the code downstream of the module to be verified in the code to be verified to target signal names in the target syntax tree.

9. An electronic device, characterized in that, Including: A processor, a memory, a communication interface, and a communication bus, and the processor, the memory, and the communication interface complete communication with each other through the communication bus; The memory is used to store executable instructions, and the executable instructions cause the processor to execute the code generation method according to any one of claims 1 to 7.

10. A readable storage medium, characterized in that, Stored thereon are executable instructions that, when executed by one or more processors, cause the processors to perform the code generation method according to any one of claims 1 to 7.

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