Interrupt control method of computer equipment and computer equipment

Abstract

The invention provides an interrupt control method of computer equipment and the computer equipment. Relates to the technical field of servers. In view of the problem that the current fixed interrupt threshold value easily causes frequent interruption storm, the computer equipment provided by the invention comprises a kernel and a hardware register, the interrupt control method of the computer equipment comprises the steps that based on a configuration file, an interrupt threshold value of an interrupt threshold value bit of a hardware register is initialized, an interface file is created, the interface file is used for a kernel to access the hardware register, and the interrupt threshold value bit is used for storing an interrupt threshold value of a memory capable of correcting errors; under the condition that a configuration instruction for the interrupt threshold bit is received, the interrupt threshold of the interrupt threshold bit is adjusted to be a target value based on the configuration instruction and the interface file, and the configuration instruction carries the target value; the interrupt threshold in the hardware register is flexibly adjusted based on the configured interface file, and the system performance is improved.

Description

Technical Field

[0001] The present application relates to the technical field of servers, and in particular to an interrupt control method for a computer device and a computer device. Background Art

[0002] In the x86 (Intel) server field, memory reliability is crucial within the kernel reliability, availability, and serviceability (RAS) subsystem, significantly impacting system performance and maintenance costs. The error correction mechanism in the RAS subsystem can correct correctable errors (CE) in memory, preventing system crashes or data loss.

[0003] However, the system kernel sets a fixed interrupt threshold for the reporting mechanism of memory CE interrupts. The fixed interrupt threshold cannot effectively cope with the actual workload, which can easily lead to frequent interrupt storms, affect system performance, and increase the burden on the system. Summary of the Invention

[0004] According to various embodiments of the present application, a method for controlling interrupts of a computer device and a computer device are provided; the interrupt threshold of correctable memory errors can be flexibly adjusted, an interrupt reporting mechanism suitable for different application scenarios is provided, and system performance is improved.

[0005] In a first aspect, the present application provides an interrupt control method for a computer device, the computer device comprising: a kernel and a hardware register; the method comprising:

[0006] Based on the configuration file, the interrupt threshold of the interrupt threshold bit of the hardware register is initialized and an interface file is created; the interface file is used for the kernel to access the hardware register, and the interrupt threshold bit is used to store the interrupt threshold of the memory correctable error; when a configuration instruction for the interrupt threshold bit is received, the interrupt threshold of the interrupt threshold bit is adjusted to a target value based on the configuration instruction and the interface file, and the configuration instruction carries the target value.

[0007] Through the above method, the kernel configures the interface file for accessing the hardware register based on the configuration file. During the operation of the kernel, the hardware register can be read or written based on the interface file, so as to rewrite the interrupt threshold of the memory correctable error in the hardware register in the kernel state. Therefore, the interrupt threshold can be dynamically adjusted based on different application scenarios or system operation status to prevent frequent interrupt storms, improve the stability and reliability of the equipment, and at the same time reduce the occupation of processor resources and memory space by interrupts, improve the system performance of computer equipment, and reduce operation and maintenance costs; it has strong ease of use and practicality.

[0008] In a possible implementation of the first aspect, adjusting the interrupt threshold of the interrupt threshold bit to a target value based on the configuration instruction and the interface file includes:

[0009] Parsing the target value in the configuration instruction; verifying the target value; and adjusting the interrupt threshold of the interrupt threshold bit to the target value after passing the verification.

[0010] In a possible implementation of the first aspect, the kernel is further configured with a write protection flag. When the write protection flag is in an unlocked state, write operations on the interrupt threshold of the interrupt threshold bit are allowed; when the write protection flag is in a locked state, write operations on the interrupt threshold of the interrupt threshold bit are prohibited.

[0011] In a possible implementation manner of the first aspect, adjusting the interruption threshold of the interruption threshold bit to a target value includes:

[0012] When the write protection flag is in the unlocked state, the write protection flag is set to the locked state, and the interrupt threshold of the interrupt threshold bit is adjusted to the target value; after adjusting the interrupt threshold of the interrupt threshold bit to the target value, the method further includes: setting the write protection flag to the unlocked state.

[0013] In a possible implementation of the first aspect, the method further includes:

[0014] When the interrupt storm condition is met and the write protection flag is in the unlocked state, the write protection flag is set to the locked state; when the write protection flag is in the locked state, the kernel switches the working mode from the interrupt mode to the polling mode; after switching to the polling mode, the write protection flag is set to the unlocked state; the interrupt storm condition includes: the number of interrupt reports of correctable memory errors per unit time exceeds a preset reporting threshold.

[0015] In a possible implementation of the first aspect, the method further includes:

[0016] In polling mode, when the interrupt storm condition is not met and the write protection flag is in the unlocked state, the write protection flag is set to the locked state; when the write protection flag is in the locked state, the kernel switches the working mode from polling mode to interrupt mode; after switching to the interrupt mode, the write protection flag is set to the unlocked state.

[0017] The above method provides synchronization protection when rewriting the interrupt threshold of the interrupt threshold bit by configuring the write protection flag corresponding to the hardware register in the kernel, preventing concurrent modification of the hardware register, which causes the hardware register to be in an uncertain state, thereby ensuring the security and consistency of the computer device operation process.

[0018] In a possible implementation manner of the first aspect, the method further includes:

[0019] The current memory correctable error is input into an interrupt threshold decision model to obtain a target value, wherein the interrupt threshold decision model is trained based on historical memory correctable errors and historical interrupt thresholds of the interrupt threshold bit; and a configuration instruction is output based on the target value.

[0020] The above method, based on the interrupt threshold decision model, realizes adaptive adjustment of the interrupt threshold, more reasonably manages and handles interrupt storms, reduces system failures and downtime, and improves the overall response speed and performance of computer equipment.

[0021] In a second aspect, the present application provides a computer device comprising: a kernel and a hardware register, wherein the hardware register is configured with an interrupt threshold bit, and the interrupt threshold bit is used to store the interrupt threshold of a memory correctable error; the kernel is used to create an interface file during kernel startup, and the interface file is used to access the hardware register; the kernel is also used to perform a read operation or a write operation on the interrupt threshold of the interrupt threshold bit based on the interface file during kernel operation.

[0022] In a possible implementation of the second aspect, the computer device also includes an interrupt threshold decision module; the interrupt threshold decision module is used to adjust the interrupt threshold of the current interrupt threshold bit based on the interface file according to historical memory correctable errors and historical interrupt thresholds.

[0023] In a possible implementation manner of the second aspect, the computer device further includes multiple processors, and the multiple processors use an interrupt threshold in the hardware register.

[0024] In the above method, for multi-core computer devices, multiple processors can share a hardware register and perform interrupt reporting based on the interrupt threshold in a hardware register, thereby realizing resource sharing and improving resource utilization. It can also ensure the consistency of the interrupt thresholds corresponding to multiple processors and improve the stability and reliability of the computer device.

[0025] In a possible implementation of the second aspect, the kernel is further configured with a write protection flag; when the write protection flag is in an unlocked state, write operations on the interrupt threshold of the interrupt threshold bit are allowed; when the write protection flag is in a locked state, write operations on the interrupt threshold of the interrupt threshold bit are prohibited.

[0026] In a third aspect, the present application provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements any one of the methods described in the second aspect when executing the computer program.

[0027] In a fourth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the method according to any one of the second aspects is implemented.

[0028] In a fifth aspect, the present application provides a computer program product, which, when executed on a device, enables the device to execute any of the methods described in the second aspect.

[0029] It can be understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 A schematic diagram of the system architecture of a computer device provided in an embodiment of the present application;

[0032] Figure 2 A schematic diagram of the implementation flow of the interrupt control method for a computer device provided in an embodiment of the present application;

[0033] Figure 3 A schematic diagram of the configuration process provided in an embodiment of the present application;

[0034] Figure 4 A schematic diagram of a hardware register provided in an embodiment of the present application;

[0035] Figure 5 A flowchart of configuring write protection during the rewriting process is provided for an embodiment of the present application;

[0036] Figure 6 A schematic diagram of the structure of a computer device is provided for an embodiment of the present application. DETAILED DESCRIPTION

[0037] The following embodiments of the technical solution of the present application will be described in detail with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application and are therefore only examples and are not intended to limit the scope of protection of the present application.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned figure descriptions are intended to cover non-exclusive inclusions.

[0039] In the description of the embodiments of this application, the technical terms "first" and "second" are used only to distinguish different objects and should not be understood to indicate or imply relative importance or implicitly specify the quantity, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, the meaning of "plurality" is more than two, unless otherwise clearly and specifically defined.

[0040] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0041] In the description of the embodiments of this application, the term "and / or" is simply a description of the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0042] Before introducing the embodiments of the present application, the professional terms involved in the present application are explained.

[0043] 1. A correctable error (CE) refers to an error in memory that can be detected and corrected by the hardware itself. The hardware can detect and repair the error using error correction code to avoid affecting system performance.

[0044] 2. The Corrected Machine Check Interrupt (CMCI) is a mechanism that controls whether an interrupt is triggered when the number of correctable memory errors detected by the hardware reaches a certain value (such as the set interrupt threshold), notifying the software to handle the error. By setting the CMCI interrupt threshold, you can avoid interrupt storms caused by frequent correctable memory errors, which can affect system performance.

[0045] 3. An interrupt storm occurs when the system receives a large number of interrupt requests corresponding to correctable memory errors in a short period of time, causing the processor to continuously respond to these interrupt requests, thereby occupying a large amount of processor and memory resources and affecting the normal operation of the system.

[0046] 4. The kernel is an intermediate layer between the hardware and the application layer. It is responsible for passing the application layer's requests to the hardware and acts as a low-level driver to address various devices and components in the system.

[0047] 5. Reliability, availability, and serviceability (RAS) subsystem is a combination of hardware and software that is used to detect, report, and repair hardware errors to ensure long-term normal operation of the system.

[0048] In the server field, the memory reliability in the kernel RAS subsystem significantly affects system performance. In various business scenarios, applications must be able to perceive the occurrence of correctable memory errors in a timely or delayed manner in order to handle them accordingly. Currently, the kernel is relatively limited in its control strategy for reporting correctable memory errors. In the kernel, the threshold for CMCI interrupt reporting corresponding to correctable memory errors (hereinafter referred to as the interrupt threshold) is a fixed value. For example, the default interrupt threshold is 1, which means that a correctable memory error is detected, triggering a CMCI interrupt and reporting it to the software for processing. During kernel operation, the interrupt threshold remains fixed, limiting the ability to adjust the reporting frequency according to actual needs. This, in turn, hinders the effective application of artificial intelligence (AI) decision-making.

[0049] Therefore, a fixed interruption threshold cannot effectively cope with the actual workload, and is likely to lead to frequent interruption storms, thereby affecting system performance and response time and increasing the burden on the system; and a fixed interruption threshold cannot be reasonably adjusted according to specific application scenarios and needs, which may lead to too frequent interruption reporting or failure to report in a timely manner, thereby increasing operation and maintenance costs; a single interruption threshold cannot be based on AI decision-making for operation and maintenance management, resulting in the system being unable to effectively use AI decision-making for trial monitoring and automatic adjustment, and its response capability is limited; in a dynamic and changing application environment, a fixed interruption threshold makes it impossible for the system to quickly adapt to environmental changes and cannot achieve better resource utilization, thereby affecting the overall efficiency of the system.

[0050] An embodiment of the present application provides a computer device that supports flexible adjustment of interrupt thresholds by configuring a reporting strategy for memory-correctable errors, thereby not only improving system reliability but also further realizing the effective application of AI decision-making in interrupt reporting control.

[0051] The following describes the system architecture of the computer device provided in the embodiments of the present application.

[0052] See Figure 1 , Figure 1 This is a schematic diagram of the system architecture of a computer device provided in an embodiment of the present application; wherein the computer device can be a server or an operation and maintenance system for a server; the server can be a single-core or multi-core server. The following description uses the server as an example.

[0053] like Figure 1 As shown in Figure (a), the computer device may include a kernel and hardware registers; wherein the kernel includes a RAS subsystem, and the kernel is configured with a correctable interrupt check function in the RAS subsystem, that is, when the number of correctable memory errors detected reaches an interrupt threshold, an interrupt is triggered and reported to the software for processing.

[0054] Accordingly, the hardware registers are configured with interrupt threshold bits related to the interrupt check function, such as Figure 4 The hardware register shown corresponds to bits 0 to 14; the interrupt threshold is used to store the interrupt threshold for memory correctable errors, that is, the number of correctable memory errors that trigger an interrupt report. The hardware register can be a model-specific register (MSR), such as the IA32_MCi_CTL2 register, which is located in the processor's spatial architecture and has a unique address.

[0055] For example, Figure 4 As shown, this hardware register can be a 64-bit register that provides a hardware programmable interface for controlling the interrupt reporting function of memory correctable errors. Among them, bits [0:14] and bit

[30] are valid bits, and the other bits are reserved bits. Bits [0:14] represent the interrupt threshold. When the number of correctable memory errors detected is equal to the interrupt threshold, a CMCI interrupt is triggered. Bit

[30] represents the enable bit of the CMCI interrupt. For example, 1 indicates that the CMCI interrupt is enabled, and 0 indicates that the CMCI interrupt is disabled. The interrupt threshold value of the interrupt threshold bit is represented in binary, and the value range of the interrupt threshold can be 1 to 32767.

[0056] It is understandable that the representation of the above hardware registers and the division of each bit are only exemplary and can be specifically set based on actual application scenarios.

[0057] In some embodiments, the core is configured with a first function and a second function, and the first function and the second function can be configured in the RAS subsystem of the core. Figure 1As shown in FIG. 5( b ), the first function includes, during the kernel startup process, the RAS subsystem initializes the interrupt threshold of the interrupt threshold bit of the hardware register based on the configuration file, and creates an interface file for accessing the hardware register.

[0058] The configuration file includes initial values ​​or default values ​​for initializing hardware registers, such as initializing the interrupt threshold in the hardware register to 1. The configuration file also includes a configuration program for the user to create an interface file. The RAS subsystem creates an interface file for accessing the hardware registers by reading the configuration program in the configuration file.

[0059] Exemplarily, the configuration file can be a static configuration file, which is a file pre-written and stored on the disk of the computer device. The interface file created based on the configuration file defines the way and rules for the RAS subsystem to access the hardware registers, ensuring that the RAS subsystem can correctly read and write the values ​​of the hardware registers. For example, the interface file defines the address, name and function of the hardware registers that need to be accessed, the access rights to the hardware registers (such as read operations or write operations, etc.), to ensure the security and stability of the system; and defines the specific way for the RAS subsystem to access the hardware registers, such as memory mapping, I / O port, etc., to ensure the efficiency and accuracy of the access.

[0060] When there are multiple hardware registers, a unified interface file may be created for different hardware registers, or a corresponding interface file may be created for each hardware register.

[0061] In some embodiments, as Figure 1 As shown in Figure (b), the second function includes: during the operation of the kernel, reading or writing the interrupt threshold of the interrupt threshold bit based on the interface file; thereby, for different business scenarios, flexible adjustment of the interrupt threshold in the hardware register is achieved based on the configured interface file.

[0062] In some embodiments, as Figure 1 As shown, the computer device also includes an interrupt threshold decision module that can implement AI decision-making. During kernel startup, the RAS subsystem creates an interface for interacting with the interrupt threshold decision module. The interrupt threshold decision module is used to adjust the interrupt threshold of the current interrupt threshold bit through an interface file based on historical memory correctable errors and historical interrupt thresholds.

[0063] For example, Figure 1As shown in Figure (a), when the processor or memory controller detects N correctable memory errors and reaches the interrupt threshold set in the hardware register, the processor or memory controller triggers an interrupt to the kernel. After receiving the interrupt, the kernel can notify the corresponding software to handle it based on the type of correctable memory error corresponding to the interrupt. At the same time, the kernel can also send relevant information of the interrupt to the interrupt threshold decision module once based on the created interface to notify the interrupt threshold decision module of the correctable memory error that has occurred and the set interrupt threshold.

[0064] Accordingly, the interrupt threshold decision module continuously trains the interrupt threshold decision model by continuously collecting the types of correctable memory errors and the corresponding interrupt thresholds to obtain a trained interrupt threshold decision model, which can be an AI decision model. The trained interrupt threshold decision model can adaptively configure the value of the interrupt threshold based on the type of memory correction error received, and send a configuration instruction to the kernel to adjust the interrupt threshold, which includes the target value of the interrupt threshold. Among them, the trained interrupt threshold decision model adapts to different business scenarios by adaptively configuring the size of the interrupt threshold, and improves system performance while ensuring the timeliness of the interrupt reporting frequency.

[0065] In some embodiments, the computer device further includes multiple processors, and the multiple processors share an interrupt threshold in a hardware register; that is, a hardware register may correspond to multiple processors (such as a central processing unit (CPU), and different registers correspond to different numbers and ranges of processors.

[0066] For example, the hardware register IA32_MC0_CTL2 can correspond to CPU0-CPU7, and the hardware register IA32_MC1_CTL2 can correspond to CPU8-CPU15. If CPU1 frequently reports CMCI interrupts, you can modify the interrupt threshold of bits [0:14] of IA32_MC0_CTL2, for example, from 1 to 100, to reduce the frequency of CMCI interrupts triggered by CPU0-CPU7.

[0067] In some embodiments, to ensure the security and consistency of the interruption threshold configuration, such as Figure 1 As shown in Figure (a), in addition to the read and write functions of the hardware registers, the kernel is also configured with a write protection function; that is, a write protection flag is also configured in the kernel. The write protection flag can be set in the memory or in a specific register and is associated with the hardware register that stores the interrupt threshold. Before writing to the hardware register, the status of the write protection flag is first obtained to avoid concurrent modifications to the hardware register, which may cause system instability.

[0068] Exemplarily, the write protection flag is a global variable in the kernel, which is used to indicate whether a write operation is allowed to the hardware register storing the interrupt threshold, that is, to mark whether the hardware register is in a write-protected state; wherein the write operation includes a write operation to the interrupt threshold bit and the enable bit of the hardware register. For example, the states of the write protection flag include an unlocked state (such as marked as OFF or 0) and a locked state (such as marked as ON or 1); when the write protection flag is in the unlocked state, the interrupt threshold or the enable bit value of the interrupt threshold bit is allowed to be written, and when the write protection flag is in the locked state, the interrupt threshold or the enable bit value of the interrupt threshold bit is prohibited to be written, thereby avoiding concurrent modifications to the hardware register.

[0069] Accordingly, when the write protection flag of the hardware register is in the unlocked state, the write protection flag is set to the locked state; when the write protection flag is in the locked state, the kernel performs a write operation on the interrupt threshold of the interrupt threshold bit; after the write operation is completed, the write protection flag is set to the unlocked state; when the write protection flag is in the locked state, the kernel waits until the write protection flag is in the unlocked state, and then executes the above-mentioned write operation process.

[0070] The specific implementation process of the interrupt control method for a computer device is further described below through embodiments.

[0071] See Figure 2 , a schematic diagram of the implementation flow of the interrupt control method for a computer device provided in an embodiment of the present application. Figure 2 As shown, the execution subject of this method can be Figure 1 A computer device in the embodiment of the present invention, wherein the computer device includes a kernel and hardware registers; the method may include the following steps:

[0072] S201, based on the configuration file, initialize the interrupt threshold of the interrupt threshold bit and create an interface file, the interface file is used for the kernel to access the hardware register, the interrupt threshold bit is used to store the interrupt threshold of the memory correctable error.

[0073] In some embodiments, as Figure 3 As shown in Figure (a), when the computer device is powered on and the kernel boots up, the RAS subsystem retrieves the configuration file, reads the parameter information in the configuration file, and parses the parameter name and parameter value in the parameter information to obtain the target value. For example, if the parameter information is threshold = 10, the parameter name parsed is threshold (i.e., the interrupt threshold), and the parameter value is 10 (i.e., the target value). The target value is then verified to determine whether the parsed target value is within the valid bit range. For example, the valid bit corresponding to the interrupt threshold bit of the hardware register is 15, and the target value is verified to determine whether it is within the valid bit range in binary representation. If the verification is successful, the target value is saved.

[0074] Accordingly, the RAS subsystem continues to obtain the configuration program in the configuration file, creates an interface file for accessing the hardware register based on the configuration program, initializes the hardware register based on the interface file and the parsed target value, and sets the initial value or default value of the interrupt threshold bit of the hardware register.

[0075] Exemplarily, the computer device may be configured with multiple hardware registers, such as hardware register 1, hardware register 2, and hardware register 3; during kernel startup, the interrupt threshold bit of each hardware register may be initialized to set an initial value or a default value of the interrupt threshold.

[0076] S202 : When a configuration instruction for an interruption threshold bit is received, based on the configuration instruction and the interface file, the interruption threshold of the interruption threshold bit is adjusted to a target value, where the configuration instruction carries the target value.

[0077] In some embodiments, the computer device may obtain a configuration instruction input by a user via an interactive interface, or obtain a configuration instruction generated by an interrupt threshold decision module. The configuration instruction carries a target value for the interrupt threshold to be adjusted. The RAS subsystem accesses the hardware register via an interface file based on the target value in the configuration instruction and adjusts the interrupt threshold of the interrupt threshold bit to the target value.

[0078] In some embodiments, adjusting the interrupt threshold of the interrupt threshold bit to a target value based on the configuration instruction and the interface file includes:

[0079] Parsing the target value in the configuration instruction; verifying the target value; and adjusting the interrupt threshold of the interrupt threshold bit to the target value after passing the verification.

[0080] For example, Figure 3 As shown in Figure (b), during kernel operation, the RAS subsystem can obtain configuration instructions issued by the user through the application layer, read the parameter information in the configuration instructions, and parse the parameter name and parameter value in the parameter information to obtain the target value. For example, if the parameter information is threshold = 50, the parameter name parsed is threshold (i.e., the interrupt threshold), and the parameter value is 50 (i.e., the target value). The target value is verified to determine whether the parsed target value is within the valid bit range. For example, the valid bit corresponding to the interrupt threshold bit of the hardware register is 15 bits. The target value is verified to determine whether it is within the valid bit range in binary representation. If the verification is successful, the hardware register is set based on the target value, and the interrupt threshold of the interrupt threshold bit is adjusted to the target value.

[0081] Accordingly, if Figure 3As shown in Figure (b), the computer device can be configured with multiple hardware registers, such as hardware register 1, hardware register 2, and hardware register 3; during kernel operation, a write operation can be performed on the interrupt threshold bit of each hardware register to adjust the size of the interrupt threshold.

[0082] Exemplarily, the hardware register is provided with a corresponding identifier, and the configuration instruction may further include the identifier of the hardware register. Based on the identifier, a write operation is performed on the corresponding hardware register.

[0083] For example, a configuration instruction may include a parameter to write to the interrupt threshold bit of a hardware register; or, based on the parameter, to write to the interrupt threshold bits of multiple hardware registers; or, a configuration instruction may include multiple parameters to write to the interrupt threshold bits of different hardware registers. This allows for flexible and timely adjustment of the interrupt threshold in different service scenarios.

[0084] In some embodiments, unlike the kernel startup process, when performing write operations on hardware registers based on configuration instructions and interface files during kernel operation, it is necessary to read the status of the write protection flag. That is, the kernel is configured with a write protection flag for writing to hardware registers. When the write protection flag is unlocked, write operations on the interrupt threshold bits are allowed; when the write protection flag is locked, write operations on the interrupt threshold bits are prohibited. This prevents concurrent modifications to hardware registers that could lead to potential system risks, and ensures the security and consistency of interrupt threshold configuration.

[0085] like Figure 5 As shown in the figure, during the kernel operation, the process of rewriting the hardware registers based on the configuration instructions and the implementation process of switching the working mode based on the system operation status are shown.

[0086] In some embodiments, adjusting the interrupt threshold of the interrupt threshold bit to a target value includes:

[0087] When the write-protection flag is in the unlocked state, the write-protection flag is set to the locked state, and a write operation is performed on the interruption threshold of the interruption threshold bit to adjust the interruption threshold of the interruption threshold bit to a target value; after adjusting the interruption threshold of the interruption threshold bit to the target value, the process further includes: setting the write-protection flag to the unlocked state. When the write-protection flag is in the locked state, the process waits until the write-protection flag is unlocked, and then performs the above-mentioned write operation.

[0088] In the process of performing a write operation on a hardware register based on a configuration instruction, the enable bit of the hardware register is kept unchanged. For example, if the current enable bit is the first value (such as 1), that is, the working mode is in the state of enabling the interrupt mode, then the enable bit is kept unchanged. For another example, if the current enable bit is the second value (such as 0), then an interrupt storm may have occurred and the working mode has switched from the interrupt mode to the polling mode. At this time, if a configuration instruction is received to modify the interrupt threshold, the enable bit is kept unchanged. After modifying the interrupt threshold of the interrupt threshold bit, the write protection flag is set to the unlocked state, such as the OFF state.

[0089] In some embodiments, as Figure 4 As shown, the hardware register is also configured with an enable bit; before an interrupt storm occurs and the kernel working mode needs to be switched, the state of the write protection flag needs to be determined. When the write protection flag is in the unlocked state, writing to the value of the enable bit is allowed; when the write protection flag is in the locked state, writing to the value of the enable bit is prohibited; in order to avoid concurrent modifications to the hardware register.

[0090] Accordingly, the kernel is configured with two working modes: interrupt mode and polling mode. The polling mode can be called a timer interrupt, that is, it checks for correctable memory errors through periodic polling.

[0091] When an interrupt storm occurs and the write protection flag corresponding to the hardware register is in the unlocked state, the write protection flag is set to the locked state, and a write operation is performed on the hardware register, the enable bit is set from the first value (such as 1) to the second value (such as 0), and the working mode is switched to the polling mode, and then the write protection flag is set to the unlocked state.

[0092] After the interrupt storm ends and the write protection flag corresponding to the hardware register is in the unlocked state, the write protection flag is set to the locked state, and a write operation is performed on the hardware register, the enable bit is set from the second value (such as 0) to the first value (such as 1), and the working mode is switched from the polling mode to the interrupt mode, and then the write protection flag is set to the unlocked state. If the write protection flag is in the locked state, wait until the write protection flag is unlocked, and then perform the above write operation process.

[0093] The interrupt storm condition includes: the number of correctable memory error interrupt reports per unit time exceeds a preset reporting threshold. For example, if 200 correctable memory errors occur within one minute, and the interrupt storm reporting threshold is set to 200 per minute, an interrupt storm is triggered.

[0094] The following describes the application scenarios of the interrupt control method provided in the embodiments of the present application in combination with actual business scenarios.

[0095] In actual application scenarios, different interrupt thresholds can be set corresponding to different types of correctable memory errors.

[0096] When a correctable memory error occurs, a status register (such as the IA32_MCi_STATUS register) stores the error type and provides detailed information about the error. Bits [15:0] record information indicating different types of correctable memory errors. When an interrupt is reported, the error type can be further categorized and counted based on the information in the status register.

[0097] For example: 0000 0000 0000 0010 is used to indicate a microcode ROM parity error; 000F 0000 0000 11LL is used to indicate a generic cache hierarchy error; 000F 0000 0001TTLL is used to indicate a translation lookaside buffer error (TLB Errors); 000F 0000 1001CCCC is used to indicate a memory controller errors memory read error; 000F0000 1010CCCC is used to indicate a memory controller errors memory write error; and 000F 0000 1100CCCC is used to indicate a memory controller errors memory scrubbing error.

[0098] For example, in an actual business scenario, the interrupt threshold can be adjusted through the interface file based on the actual business scenario and the operating status of the device. For example, within 24 hours, the memory controller scans out 10 errors of the type "memorycontroller errors memory scrubbing error" (i.e., memory scrubbing error) in the background. This business scenario usually corresponds to a stage when the business is not busy. Since the memory scrubbing operation can be performed more easily and potential problems can be detected more easily when the system load is low, it is determined that the business is not busy at this time, and for some reason the number of correctable errors on the memory bar has a trend of gradually increasing. Then, the interrupt threshold can be adjusted to 1, that is, when a memory scrubbing error occurs, an interrupt report is triggered, so that each correctable memory error is promptly paid attention to and handled in a timely manner.

[0099] For example, if 200 memory controller errors (memory read errors) are detected within a short period of time, such as 1 minute, it usually indicates that an application is frequently reading memory data with correctable errors, that is, errors occurred during the reading of these memory data and were detected and corrected by the memory controller.

[0100] However, frequent error correction processes will occupy memory bandwidth, and the memory access performance of the business will be reduced because the memory controller occupies a certain amount of memory bandwidth for error correction, because part of the memory bandwidth that could have been used for normal data transmission is used for error correction.

[0101] If the interrupt threshold remains at 1, the application will be frequently interrupted by CMCI interrupts and be affected by them. Therefore, it is necessary to adjust the interrupt threshold to a larger target value. This will reduce the interrupt trigger frequency, reduce processor resource consumption, and help maintain application responsiveness and throughput.

[0102] Exemplarily, the above-mentioned computer device can be a multi-core server, that is, it includes multiple processors, each processor can be responsible for processing different types of services, and the interrupt threshold set in the hardware register can be a threshold for one type of memory correctable error occurring in one processor, or it can be a cumulative threshold for multiple types of memory correctable errors occurring in one processor.

[0103] It should be noted that the types of correctable memory errors, the number of times detected, the representation, the timing of adjustment, the detection time period and the corresponding business scenarios in the above embodiments are only illustrative. There is no specific limitation on the modification timing and the target value of the modification in the actual business scenario. The setting of the interruption threshold can be flexibly adapted and adjusted based on the actual business scenario and the operating status of the equipment to achieve flexible control of interruption reporting.

[0104] In some embodiments, the method further includes: inputting the current memory correctable error into an interrupt threshold decision model to obtain a target value, wherein the interrupt threshold decision model is trained based on historical memory correctable errors and historical interrupt thresholds of the interrupt threshold bit; and outputting a configuration instruction based on the target value.

[0105] Exemplarily, the interruption threshold decision model can be a reinforcement learning (RL) model. The types of historical memory correctable errors and the corresponding historical interruption thresholds are input into the interruption threshold decision model, and changes in system performance are observed as feedback. The interruption threshold decision model is trained and optimized. Through continuous trial and adjustment, the algorithm can learn the optimal interruption threshold setting strategy.

[0106] For example, if the interrupt threshold decision module significantly improves system performance metrics (such as latency and throughput) over a period of time and significantly slows the growth rate of memory errors after adjusting the threshold, the interrupt threshold decision module will record and strengthen this threshold strategy. Conversely, if system performance does not improve after adjusting the threshold, or if the memory error situation remains severe, the interrupt threshold decision module will analyze the error causes, further refine the error classification, and adopt more precise threshold settings; or conduct more in-depth hardware detection and repair. This adaptive feedback mechanism ensures that the memory correctable error management strategy is both responsive and has long-term optimization potential, thus achieving the goals of intelligence and control.

[0107] Accordingly, the current correctable memory error type and frequency are input into the interrupt threshold decision model. Based on this model, the interrupt threshold is adjusted according to the current memory error type and frequency. System performance changes are observed and used as feedback to determine the target interrupt threshold value. The interrupt threshold decision module generates a configuration instruction based on the determined target value and sends it to the kernel through an interface. The kernel's RAS subsystem adjusts the interrupt threshold to the target value by accessing the register interface file.

[0108] Through the embodiments of the present application, the threshold is dynamically adjusted during system operation, which greatly increases the flexibility of the system; the interrupt threshold is adjusted in real time according to real-time monitoring data and system load conditions, which can reduce the kernel's interrupt processing overhead, so that processor resources can be used more for actual workloads, better adapt to different system requirements and operating environments, and better control the performance and reliability of the system; by adjusting the threshold, interrupt storms triggered by frequent CE errors can be effectively prevented, the utilization of memory resources can be more effectively managed, and the stability and reliability of the system can be improved; based on real-time monitoring data, the threshold is dynamically adjusted, and the system configuration is continuously optimized through a feedback mechanism to achieve more refined system management.

[0109] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0110] Figure 6A schematic diagram of the hardware structure of the computer device 6 is shown.

[0111] like Figure 6 As shown, the computer device 6 of this embodiment includes: at least one processor 60 ( Figure 6 Only one is shown), a memory 61, wherein the memory 61 stores a computer program 62 that can be run on the processor 60. When the processor 60 executes the computer program 62, the steps in the above method embodiment are implemented, such as Figure 2 Alternatively, when the processor 60 executes the computer program 62, the functions of the modules / units in the above-mentioned device embodiments are realized.

[0112] It should be understood that the structure illustrated in the embodiments of the present application does not constitute a specific limitation on the computer device 6. In other embodiments of the present application, the computer device 6 may include more or fewer components than shown, or may combine or separate certain components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0113] The computer device 6 may include, but is not limited to, a processor 60 and a memory 61. Those skilled in the art will appreciate that Figure 6 It is only an example of the computer device 6 and does not constitute a limitation of the computer device 6. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, the server may also include an input sending device, a network access device, a bus, etc.

[0114] The processor 60 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0115] Processor 60 may also include a memory for storing instructions and data. In some embodiments, the memory in processor 60 is a cache memory. This memory can store instructions or data that have just been used or are being recycled by processor 60. If processor 60 needs to use the same instruction or data again, it can directly access the memory. This avoids duplicate accesses, reduces processor 60 latency, and thus improves system efficiency.

[0116] In some embodiments, the memory 61 may be an internal storage unit of the computer device 6, such as a hard disk or memory of the computer device 6. The memory 61 may also be an external storage device of the computer device 6, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, a flash memory card, etc. equipped on the computer device 6. Furthermore, the memory 61 may include both an internal storage unit of the computer device 6 and an external storage device. The memory 61 is used to store an operating system, application programs, a boot loader, data, and other programs, such as the program code of a computer program. The memory 61 may also be used to temporarily store data that has been sent or is about to be sent.

[0117] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0118] It should be noted that the structure of the above-mentioned electronic device is only illustrative, and based on different application scenarios, it may also include other physical structures, and the physical structure of the electronic device is not limited here.

[0119] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0120] An embodiment of the present application further provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it can implement the steps in the above-mentioned various method embodiments.

[0121] An embodiment of the present application provides a computer program product. When the computer program product runs on a server, the server can implement the steps in the above-mentioned method embodiments when executing the computer program product.

[0122] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the process in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form, etc. Computer-readable media may include: any entity or device that can carry computer program code, recording medium, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium, etc.

[0123] The computer device, computer storage medium, and computer program product provided in the above-mentioned embodiments of the present application are all used to execute the methods provided above. Therefore, the beneficial effects that can be achieved can refer to the corresponding beneficial effects of the methods provided above, and will not be repeated here.

[0124] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0125] It should be understood that the above is only to help those skilled in the art better understand the embodiments of the present application, and is not intended to limit the scope of the embodiments of the present application. Based on the above examples given, those skilled in the art can obviously make various equivalent modifications or changes. For example, certain steps in each embodiment of the above detection method may be unnecessary, or certain new steps may be added. Or a combination of any two or any multiple embodiments described above. Such modifications, changes, or combined solutions also fall within the scope of the embodiments of the present application.

[0126] It should also be understood that the division of the modes, situations, categories and embodiments in the embodiments of the present application is only for the convenience of description and should not constitute a special limitation. The features of various modes, categories, situations and embodiments can be combined without contradiction.

[0127] It should also be understood that in the various embodiments of the present application, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between different embodiments are consistent and can be referenced to each other, and the technical features in different embodiments can be combined to form new embodiments according to their internal logical relationships.

[0128] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0129] In the embodiments provided in this application, it should be understood that the disclosed devices / network equipment and methods can be implemented in other ways. For example, the device / network equipment embodiments described above are merely illustrative. For example, the division of the modules or units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0130] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of the solution of this embodiment according to actual needs.

[0131] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

[0132] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A method for controlling interruption of a computer device, characterized in that: The computer device comprises: a kernel and a hardware register; the method comprises: Initialize the interrupt threshold of the interrupt threshold bit of the hardware register based on the configuration file, and create an interface file, the interface file is used for the kernel to access the hardware register, the interrupt threshold bit is used to store the interrupt threshold of the memory correctable error; In case of receiving a configuration instruction for the interruption threshold bit, adjusting the interruption threshold of the interruption threshold bit to a target value based on the configuration instruction and the interface file, wherein the configuration instruction carries the target value.

2. The method according to claim 1, characterized in that The adjusting the interruption threshold of the interruption threshold bit to a target value based on the configuration instruction and the interface file includes: Parsing the target value in the configuration instruction; verifying the target value; After the verification is passed, the interruption threshold of the interruption threshold bit is adjusted to the target value.

3. The method according to claim 1, characterized in that The core is also configured with a write protection mark. When the write protection mark is in an unlocked state, writing operations on the interrupt threshold of the interrupt threshold bit are allowed. When the write protection mark is in a locked state, writing operations on the interrupt threshold of the interrupt threshold bit are prohibited.

4. The method according to claim 3, characterized in that The adjusting the interruption threshold of the interruption threshold bit to a target value comprises: When the write protection mark is in the unlocked state, the write protection mark is set to the locked state, and the interruption threshold of the interruption threshold bit is adjusted to the target value; The step of adjusting the interruption threshold of the interruption threshold bit to the target value further includes: The write protection flag is set to the unlocked state.

5. The method according to claim 3, characterized in that: The method further comprises: When an interrupt storm condition is met and the write protection mark is in the unlocked state, setting the write protection mark to the locked state; When the write protection mark is in the locked state, the kernel switches the working mode from the interrupt mode to the polling mode; After switching to the polling mode, setting the write protection flag to the unlocked state; The interrupt storm condition includes: the number of interrupt reports of correctable memory errors per unit time exceeds a preset reporting number threshold.

6. The method according to claim 5, characterized in that The method further comprises: In the polling mode, when the interrupt storm condition is not satisfied and the write protection mark is in the unlocked state, setting the write protection mark to the locked state; When the write protection mark is in the locked state, the kernel switches the working mode from the polling mode to the interrupt mode; After switching to the interrupt mode, the write protection flag is set to the unlock state.

7. A computer device, characterized in that: The computer device comprises: a kernel and a hardware register, wherein the hardware register is configured with an interrupt threshold bit, and the interrupt threshold bit is used to store an interrupt threshold of a memory correctable error; The kernel is used to create an interface file during the kernel startup process, and the interface file is used to access the hardware register; The kernel is also used to perform a read operation or a write operation on the interrupt threshold of the interrupt threshold bit based on the interface file during the operation of the kernel.

8. The computer device according to claim 7, characterized in that The computer device also includes a plurality of processors, the plurality of processors utilizing the interrupt threshold in one of the hardware registers.

9. The computer device according to claim 7 or 8, characterized in that: The kernel is also configured with a write protection flag; When the write protection mark is in the unlocked state, a write operation is allowed for the interruption threshold of the interruption threshold bit. When the write protection mark is in the locked state, a write operation is prohibited for the interruption threshold of the interruption threshold bit.

10. A computer device, characterized in that: The method comprises a memory and a processor, wherein the memory stores a computer program, and the processor implements the method according to any one of claims 1 to 6 when executing the computer program.

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