Statistical method and system for full-path node processing time of data packet

Abstract

The invention belongs to the technical field of data processing, and particularly relates to a statistical method and system for data packet full-path node processing time. A data packet is input into a system-on-chip along a first direction, the system-on-chip comprises a plurality of processing modules, each processing module corresponds to a circulation unit, and the method comprises the following steps: setting an identification bit at the head of the data packet to obtain a time detection packet; the time detection packet flows along a first direction, and when the time detection packet enters a flow unit, the corresponding processing module performs dotting processing on the time detection packet; when the time detection packet flows to the last flow unit, the time detection packet flows towards a test path opposite to the first direction, and dotting processing is carried out on the time detection packet through a corresponding processing module; and collecting dotting processing results and carrying out statistics. The method has the beneficial effects that the processing time of each node on the data packet in the system on chip can be accurately obtained, the processing time of the full-path nodes of the data packet can be accurately counted, and subsequent analysis is facilitated.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and in particular to a statistical method and system for data packet processing time. Background Art

[0002] In SoC (System on Chip) design, in order to optimize system performance, it is necessary to accurately know the processing time of the entire process from data input to output. However, when evaluating the design before production, it is often difficult to accurately quantify the average processing time of each node on the path for a data packet. These nodes include analog modules, digital hardware modules, and software processing nodes in the protocol stack.

[0003] In the current design process, simulation and partial statistical estimation are usually relied upon, and it is impossible to obtain real, full-path time data. In highly complex SoC systems, data packets are transmitted and processed through multiple levels of modules, involving both hardware module operations and software module protocol stack processing. Existing testing and monitoring methods cannot capture the precise time for each hardware and software node to process data packets, making it difficult to perform fine-grained analysis of the processing time of the entire path. Summary of the invention

[0004] The purpose of the present invention is to provide a statistical method for the processing time of all-path nodes of a data packet to solve the above technical problems;

[0005] The present invention also aims to provide a statistical system for processing time of all-path nodes of a data packet to solve the above technical problems;

[0006] A statistical method for processing time of nodes along the entire path of a data packet, comprising:

[0007] The data packet is input into the system on chip along the first direction. The system on chip includes a plurality of processing modules. Each of the processing modules is corresponding to a flow unit, including the following steps:

[0008] Step S1, marking the data packet as a time detection packet by setting a flag bit in the header of the data packet;

[0009] Step S2, the time detection packet flows along the first direction, and when the time detection packet enters the flow unit, the processing module corresponding to the flow unit performs dot processing on the time detection packet;

[0010] Step S3, when the time detection packet flows to the last flow unit, the time detection packet flows toward the test path opposite to the first direction, and when the time detection packet enters the flow unit, the time detection packet is dotted by the corresponding processing module;

[0011] Step S4, collecting and counting the results of the dotting process, and outputting the statistical results.

[0012] Preferably, step S2 comprises,

[0013] Step S21, when the time detection packet flows along the first direction to the first flow unit, the application node and the dynamic link library node in the first processing module respectively record the sending timestamp in the payload part of the time detection packet through the timer;

[0014] Step S22, when the time detection packet flows along the first direction to the second flow unit, the protocol stack node and the hardware driver node in the second processing module respectively record the sending timestamp in the payload part of the time detection packet through the timer;

[0015] Step S23, when the time detection packet flows along the first direction to the third flow unit, the bus node, controller node and physical layer node in the third processing module respectively record the sending timestamp in the payload part of the time detection packet through the timer.

[0016] Preferably, step S3 comprises,

[0017] Step S31, when the time detection packet flows along the test path to the third flow unit, the bus node, the controller node and the physical layer node in the third processing module respectively record a receiving timestamp in the payload portion of the time detection packet through the timer;

[0018] Step S32, when the time detection packet flows along the test path to the second flow unit, the protocol stack node and the hardware driver node in the second processing module respectively record a receiving timestamp in the payload portion of the time detection packet through the timer;

[0019] Step S33, when the time detection packet flows along the test path to the first flow unit, the application node and the dynamic link library node in the first processing module respectively record the receiving timestamp in the payload part of the time detection packet through the timer.

[0020] Preferably, step S4 includes collecting the result of the dot processing, calculating the total processing time of the time detection package in the system on chip and the node processing time in each processing module according to the result of the dot processing, obtaining the statistical result and outputting it.

[0021] Preferably, it also includes:

[0022] Step S5, comparing the node processing time with a preset time threshold, and outputting the corresponding node when the node processing time is greater than the time threshold.

[0023] A statistical system for processing time of nodes along the entire path of a data packet, comprising:

[0024] A data packet marking module, used for setting a flag bit on the header of a data packet to mark the data packet as a time detection packet;

[0025] A timestamp marking module, connected to the data packet marking module, for recording a timestamp in the payload portion of the time detection packet to obtain timestamp data, wherein the timestamp data includes a sending timestamp and a receiving timestamp;

[0026] The full path acquisition module is connected to the timestamp marking module and is used to collect and count all the timestamp data of the time detection package to obtain statistical results.

[0027] Preferably, the timestamp module includes:

[0028] A forward dotting unit connected to the data packet marking module, when the time detection packet flows in the first direction, records a sending timestamp for the payload portion of the time detection packet through a timer in a processing node;

[0029] The reverse dotting unit is connected to the forward dotting unit, and records a receiving timestamp for the payload portion of the time detection packet through the timer in the processing node when the time detection packet flows along a test path opposite to the first direction.

[0030] Preferably, the processing nodes include application nodes, dynamic link library nodes, protocol stack nodes, hardware driver nodes, bus nodes, controller nodes and physical layer nodes.

[0031] Preferably, the full path acquisition module includes:

[0032] A collection unit, used for collecting all the timestamp data of the time detection packet;

[0033] A statistical unit is connected to the acquisition unit and is used to calculate the total processing time of the time detection packet in the system on chip and the processing time of each processing node according to the timestamp data to obtain the statistical result.

[0034] Preferably, it also includes:

[0035] The abnormality identification module is connected to the full-path acquisition module and is used to compare the processing time of the processing node with a preset time threshold until the processing time of the processing node is greater than the time threshold, and output the corresponding processing node.

[0036] The beneficial effect of the present invention is that: by adopting the above technical scheme, the processing time of each node in the on-chip system for the data packet can be accurately obtained, and the processing time of the nodes of the entire path of the statistical data packet can be accurately counted, which is convenient for subsequent analysis. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a step diagram of the statistical method of the data packet full path node processing time of the present invention;

[0038] Figure 2 is a schematic diagram of step S2 of the present invention;

[0039] Figure 3 is a schematic diagram of step S3 of the present invention;

[0040] Figure 4 It is a schematic diagram of a statistical system for processing time of nodes along the entire path of a data packet according to the present invention;

[0041] Figure 5 It is a schematic diagram of the timestamp module of the present invention;

[0042] Figure 6 is a schematic diagram of the full path acquisition module of the present invention;

[0043] Figure 7 is a flow chart of data packet processing in the system on chip of the present invention;

[0044] Figure 8 It is a schematic diagram of the structure of the time detection package of the present invention;

[0045] Fig. 9 It is a flow chart of the timestamp dot of the present invention.

[0046] In the attached figure: 1. time detection packet; 11. header; 12. payload part; 2. system on chip; 21. user mode module; 211. application node; 212. dynamic link library node; 22. kernel mode module; 221. protocol stack node; 222. hardware driver node; 23. hardware module; 231. bus node; 232. controller node; 233. physical layer node; 3. flow unit; 4. timer; 5. data packet marking module; 6. timestamp dotting module; 61. forward dotting unit; 62. reverse dotting unit; 7. full path acquisition module; 71. acquisition unit; 72. statistics unit; 8. abnormal identification module. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0048] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0049] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0050] A statistical method for the processing time of nodes along the entire path of a data packet, such as Figure 1 , Figure 8 , Fig. 9 As shown, including,

[0051] The data packet is input into the system on chip 2 along the first direction. The system on chip 2 includes a plurality of processing modules. Each processing module is corresponding to a flow unit 3, which includes the following steps:

[0052] Step S1, by setting a flag bit in the header 11 of the data packet to mark the data packet as a time detection packet 1;

[0053] Step S2, the time detection packet 1 flows along the first direction. When the time detection packet 1 enters the flow unit 3, the processing module corresponding to the flow unit 3 performs dot processing on the time detection packet 1;

[0054] Step S3, when the time detection packet 1 flows to the last flow unit 3, the time detection packet 1 flows toward the test path opposite to the first direction, and when the time detection packet 1 enters the flow unit 3, the time detection packet 1 is dotted by the corresponding processing module;

[0055] Step S4, collecting and counting the results of the dot processing, and outputting the statistical results.

[0056] Specifically, the present invention provides a statistical method for processing the node processing time of the entire path of a data packet. By designing an identification bit in the data packet header and performing time stamping in each processing module, the processing time of the data packet by the internal node of each processing module in the system on chip 2 can be accurately obtained, and the processing time of the node processing time of the entire path of the statistical data packet can be accurately counted to facilitate subsequent analysis.

[0057] In a preferred embodiment, referring to Figure 2 , Figure 7 , Figure 8 , Fig. 9 , step S2 comprises,

[0058] Step S21, when the time detection packet 1 flows along the first direction to the first flow unit 3, the application node 211 and the dynamic link library node 212 in the first processing module respectively record the sending timestamp in the payload part 12 of the time detection packet 1 through the timer 4;

[0059] Step S22, when the time detection packet 1 flows along the first direction to the second flow unit 3, the protocol stack node 221 and the hardware driver node 222 in the second processing module respectively record the sending timestamp in the payload part 12 of the time detection packet 1 through the timer 4;

[0060] Step S23, when the time detection packet 1 flows along the first direction to the third flow unit 3, the bus node 231, the controller node 232 and the physical layer node 233 in the third processing module respectively record the sending timestamp in the payload part 12 of the time detection packet 1 through the timer 4.

[0061] Specifically, when the time detection packet 1 flows along the first direction to the first flow unit 3, the application node 211 and the dynamic link library node 212 in the first processing module (user state module 21) respectively record the sending timestamp (such as Fig. 9 ), and then flows to the next node in the first direction.

[0062] When the time detection packet 1 flows along the first direction to the second flow unit 3, the protocol stack node 221 and the hardware driver node 222 in the second processing module (kernel state module 22) respectively record the sending timestamp (such as Fig. 9 ), and then flows again to the next node in the first direction.

[0063] When the time detection packet 1 flows along the first direction to the third flow unit 3, the bus node 231, the controller node 232 and the physical layer node 233 in the third processing module (hardware module 23) respectively record the sending timestamp (such as Fig. 9 ), completing the forward dotting process.

[0064] In a preferred embodiment, referring to Figure 3 , Figure 7 , Figure 8 , Fig. 9 , step S3 comprises,

[0065] Step S31, when the time detection packet 1 flows along the test path to the third flow unit 3, the bus node 231, the controller node 232 and the physical layer node 233 in the third processing module respectively record the receiving timestamp in the payload part 12 of the time detection packet 1 through the timer 4;

[0066] Step S32, when the time detection packet 1 flows along the test path to the second flow unit 3, the protocol stack node 221 and the hardware driver node 222 in the second processing module respectively record the receiving timestamp in the payload part 12 of the time detection packet 1 through the timer 4;

[0067] Step S33 , when the time detection packet 1 flows along the test path to the first flow unit 3 , the application node 211 and the dynamic link library node 212 in the first processing module respectively record the receiving timestamp in the payload part 12 of the time detection packet 1 through the timer 4 .

[0068] Specifically, when the time detection packet 1 is located in the third flow unit 3, the bus node 231, the controller node 232 and the physical layer node 233 in the third processing module (hardware module 23) respectively record the receiving timestamp (such as Fig. 9 ), and then flows to the next node along the test path.

[0069] When the time detection packet 1 flows along the test path to the second flow unit 3, the protocol stack node 221 and the hardware driver node 222 in the second processing module (kernel state module 22) respectively record the receiving timestamp (such as Fig. 9 ), and then flows to the next node again along the test path.

[0070] When the time detection packet 1 flows along the test path to the first flow unit 3, the application node 211 and the dynamic link library node 212 in the first processing module (user state module 21) respectively record the receiving timestamp (such as Fig. 9 The full path dotting process is completed, and the time detection package 1 is output to the system-on-chip 2.

[0071] Reference Figure 7 , in the system on chip 2, the specific implementation process of the present invention is as follows:

[0072] First, the data packet is marked as a time detection packet 1 and input into the on-chip system 2. In the user-state module 21, it is respectively processed by the application node 211 and the dynamic link library node 212, and then flows to the kernel-state module 22 in the first direction. In the kernel-state module 22, it is respectively processed by the protocol stack node 221 and the hardware driver node 222, and then flows to the hardware module 23 in the first direction. In the hardware module 23, it is respectively processed by the bus node 231, the controller node 232, and the physical layer node 233, and then flows through the physical path in a second direction opposite to the first direction.

[0073] Then, in the hardware module 23, it is processed by the bus node 231, the controller node 232, and the physical layer node 233 respectively; in the kernel state module 22, it is processed by the protocol stack node 221 and the hardware driver node 222 respectively; in the user state module 21, it is processed by the application node 211 and the dynamic link library node 212 respectively.

[0074] Finally, the time detection packet 1 completes the entire full-path process and timestamps each processing node, effectively monitoring the processing time of the data packet at each hardware and software node in the system-on-chip 2, thereby calculating the time each node takes to process the data packet and the average processing time of the data packet along the entire path.

[0075] Reference Figure 8 The time detection packet 1 includes a header 11 and a payload portion 12 connected to the header 11. Figure 8 , from the header 11 to the payload 12, the payload 12 is marked with a 16-bit time detection packet identification field, (0xFFFF-0x0000). The identification bit of the data packet header 11 is used to mark the data packet as a test data packet 1. When the system detects the identification bit, the processing time monitoring function of the data packet is started.

[0076] In a preferred embodiment, step S4 includes collecting the results of the dot processing, calculating the total processing time of the time detection package 1 in the system on chip 2 and the node processing time in each processing module based on the results of the dot processing, obtaining statistical results and outputting them.

[0077] Specifically, after the data packet completes the entire processing path, the timestamp information of all nodes is collected, and the average processing time of a batch of time detection packets 1 is counted and analyzed by calculating the processing time of each node and the total processing time of the entire path.

[0078] In a preferred embodiment, it also includes:

[0079] Step S5, comparing the node processing time with a preset time threshold, and outputting the corresponding node when the node processing time is greater than the time threshold.

[0080] Specifically, by analyzing the processing time of a batch of time detection packets 1, the hardware or software node where the processing bottleneck is located is identified, so as to perform system optimization.

[0081] In this embodiment, the preset time threshold is 100 nanoseconds.

[0082] For processing node A, if (T2-T1)>100 nanoseconds, then processing node A is identified as a processing bottleneck node and outputs processing node A. T2 is the receiving timestamp of the test path direction of processing node A, and T1 is the sending timestamp of the first direction of processing node A. Based on the comparison between the node processing time and the preset time threshold, the hardware or software nodes with too long processing time can be accurately found, and then the system can be optimized, such as hardware upgrades or software algorithm optimization for nodes with long processing time.

[0083] A statistical system for processing time of nodes along the entire path of a data packet, referring to Figure 4 ,include,

[0084] The data packet marking module 5 is used to set a flag bit on the header 11 of the data packet to mark the data packet as a time detection packet 1;

[0085] The timestamp marking module 6 is connected to the data packet marking module 5 and is used to record the timestamp in the payload part 12 of the time detection packet 1 to obtain timestamp data, and the timestamp data includes a sending timestamp and a receiving timestamp;

[0086] The full path collection module 7 is connected to the time stamp marking module 6 and is used to collect and count all the time stamp data of the time detection package 1 to obtain statistical results.

[0087] Specifically, the present invention also provides a statistical system for processing time of nodes in the entire path of a data packet, and the data packet marking module 5 is used to mark the data packet as a test data packet (time detection packet 1). When the system detects the identification bit, the processing time monitoring function of the data packet is started. The processing time of each node in the system on chip 2 for the data packet can be accurately obtained, and the processing time of the nodes in the entire path of the data packet can be accurately counted, which is convenient for subsequent analysis.

[0088] In a preferred embodiment, referring to Figure 5 , the timestamp module 6 includes,

[0089] The forward dotting unit 61 is connected to the data packet marking module 5, and when the time detection packet 1 flows in the first direction, the timer 4 in the processing node records the sending timestamp of the payload part 12 of the time detection packet 1;

[0090] The reverse dotting unit 62 is connected to the forward dotting unit 61, and records a receiving timestamp for the payload part 12 of the time detection packet 1 through the timer 4 in the processing node when the time detection packet 1 flows along the test path opposite to the first direction;

[0091] The processing nodes include an application node 211 , a dynamic link library node 212 , a protocol stack node 221 , a hardware driver node 222 , a bus node 231 , a controller node 232 and a physical layer node 233 .

[0092] Specifically, when a data packet flows from one node to the next node in the timestamp module 6, whether it is a hardware node (such as a digital module, an analog module) or a software node (such as a protocol stack, a driver), a timestamp will be recorded at a specified position in the data packet Payload (payload part 12) through a timer 4 (timer) in the system.

[0093] By using timestamps, the processing time of data packets at each key node can be accurately measured, covering both hardware and software modules.

[0094] When the time detection packet flows in the first direction, the forward dot unit 61 uses the timer 4 in the processing node to record the sending timestamp of the payload of the time detection packet.

[0095] At the moment when the data packet enters each processing node, a time point is obtained by timer 4 and recorded in the payload of the data packet. This is equivalent to making a time mark at the entrance of each processing node during the journey of the data packet. Since each processing node has such a forward dotting operation and a reverse dotting operation, the processing time of the data packet at the processing node can be obtained by subtracting the forward dotting time from the reverse dotting time.

[0096] In a preferred embodiment, referring to Figure 6 , the full path acquisition module 7 includes,

[0097] A collection unit 71, used for collecting all timestamp data of the time detection package 1;

[0098] The statistical unit 72 is connected to the collection unit 71 and is used to calculate the total processing time of the time detection packet 1 in the system on chip 2 and the processing time of each processing node according to the timestamp data to obtain statistical results.

[0099] Specifically, the full-path acquisition module 7 is used for processing the entire path of a data packet from input to output in the system-on-chip 2 , helping designers understand the overall delay of data processing.

[0100] During the data packet flow, the collection unit 71 obtains all timestamp data of the time detection packet 1 recorded at each processing node.

[0101] When the time detection packet 1 flows in the system on chip 2, no matter it passes through the processing node along the forward path or the reverse path, the timestamp recorded by each node when it performs dot processing on the time detection packet 1 will be collected by the collection unit 71. These timestamp data contain the arrival time of the data packet at each processing node, which is the basic data for the subsequent calculation of the processing time.

[0102] The statistical unit 72 calculates the total processing time of the time detection packet 1 in the system on chip 2 according to the collected timestamp data.

[0103] By obtaining the timestamp of the input node and the timestamp of the output node of the time detection packet 1 at the system-on-chip 2 and subtracting the two, the total processing time of the data packet in the entire system can be obtained.

[0104] Whether it is a software processing node or a hardware processing node, by collecting and counting timestamp data, we can clearly know the time consumed by each node in processing data packets.

[0105] It helps to grasp the data processing efficiency of the system as a whole and understand the overall delay of the system when processing data packets. For some application scenarios with high real-time requirements, such as high-speed network communication chips or real-time control systems, accurate full-path processing time data can help designers evaluate whether the system meets performance requirements.

[0106] In a preferred embodiment, it also includes:

[0107] The abnormality identification module 8 is connected to the full-path acquisition module 7 and is used to compare the processing time of the processing node with a preset time threshold until the processing time of the processing node is greater than the time threshold, and output the corresponding processing node.

[0108] Specifically, by analyzing the processing time of multiple batches of test data packets, nodes with long processing time can be accurately found to help optimize the system.

[0109] Before production, processing performance is evaluated based on real timestamp data to help designers optimize software and hardware architecture during the design phase.

[0110] The abnormal identification module 8 is connected to the full path collection module 7, and the full path collection module 7 collects the processing time data of each processing node for the time detection package 1. The abnormal identification module 8 compares these processing time data with the preset time threshold one by one.

[0111] The preset time threshold is pre-set according to the design requirements and performance indicators of the system.

[0112] For example, when designing a high-speed data processing system on chip 2, the upper limit of the processing time of each processing node under normal circumstances is determined based on theoretical calculations and practical experience, and this is used as the time threshold.

[0113] When the processing time of a certain processing node is greater than a preset time threshold, the abnormality identification module 8 will output the processing node.

[0114] By outputting these abnormal nodes, the system can further analyze and process them to restore the normal performance of the system.

[0115] For example, if the processing time of a protocol stack node exceeds the threshold, it may be due to excessive network traffic causing congestion in protocol processing. The system can take measures such as increasing cache and optimizing protocol processing algorithms to solve the problem.

[0116] By comparing the processing time of the processing node with a preset time threshold, the node with too long processing time can be quickly found.

[0117] In the system on chip 2, there are many processing nodes, including various nodes related to software and hardware. When the system has performance problems, it is difficult to intuitively determine which node is the cause. The abnormal identification module 8 can accurately point out the nodes whose processing time exceeds the threshold, which helps to quickly locate the performance bottleneck of the system.

[0118] For example, in a system on chip 2 that integrates multiple functions such as network communication and multimedia processing, if the data processing speed slows down, this module can be used to quickly determine whether the problem occurs in the network protocol stack node, the hardware driver node or other nodes.

[0119] Once the nodes with abnormal processing time are identified, these nodes can be optimized in a targeted manner. For hardware nodes, hardware upgrades and circuit design optimization can be considered; for software nodes, code optimization and algorithm improvement can be performed. This helps to improve the overall performance and stability of the system.

[0120] For example, if it is found that the processing time of a certain dynamic link library node 212 often exceeds a threshold, the software developer can perform performance analysis and optimization on the functions in the dynamic link library, thereby improving the processing efficiency of the system at the node.

[0121] During the operation of the system, the abnormality identification module 8 can continuously monitor the time of the processing node.

[0122] For example, in an industrial control system-on-chip, if the processing time of a controller node 232 suddenly increases abnormally, it may be due to external electromagnetic interference or hardware aging. By timely detection and processing, the safety and stability of industrial production can be guaranteed.

[0123] In the design of a system-on-chip 2 for AI processing, the specific implementation steps of the present invention include:

[0124] Step 1, the input data packet enters the system on chip 2 from the sensor module;

[0125] Step 2: After the analog front end, AI processing unit and back-end data transmission module;

[0126] Step 3: Mark the data packet as a test packet by adding a flag to the data packet header;

[0127] Step 4: When processing a data packet, each node uses a local timer to mark the data packet and record the timestamp;

[0128] Step 5: When the data packet processing is completed, the system collects these timestamp data and calculates the processing time of each node;

[0129] Step six: By analyzing the processing time of a batch of data packets, it is found that the time delay of the AI ​​processing unit is long. Based on this, the hardware accelerator is optimized to improve processing performance.

[0130] In the design of a network processing system on chip 2, the specific implementation steps of the present invention include:

[0131] Step 1: The data packet enters from the Ethernet interface, is processed by the hardware MAC layer, and then enters the software protocol stack for data decoding;

[0132] Step 2: Mark each processing node and record the timestamp;

[0133] Step three: Through multiple rounds of testing, it was found that the decoding step in the software protocol stack took the longest time. Based on this, the implementation of the protocol stack was optimized to improve the system's data processing capabilities.

[0134] The above description is only a preferred embodiment of the present invention, and does not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A statistical method for the processing time of nodes along the entire path of a data packet, characterized in that: The data packet is input into the system on chip along the first direction. The system on chip includes a plurality of processing modules. Each of the processing modules is corresponding to a flow unit, including the following steps: Step S1, marking the data packet as a time detection packet by setting a flag bit in the header of the data packet; Step S2, the time detection packet flows along the first direction, and when the time detection packet enters the flow unit, the processing module corresponding to the flow unit performs dot processing on the time detection packet; Step S3, when the time detection packet flows to the last flow unit, the time detection packet flows toward the test path opposite to the first direction, and when the time detection packet enters the flow unit, the time detection packet is dotted by the corresponding processing module; Step S4, collecting and counting the results of the dotting process, and outputting the statistical results.

2. The statistical method for data packet full path node processing time according to claim 1 is characterized in that: Step S2 comprises, Step S21, when the time detection packet flows along the first direction to the first flow unit, the application node and the dynamic link library node in the first processing module respectively record the sending timestamp in the payload part of the time detection packet through the timer; Step S22, when the time detection packet flows along the first direction to the second flow unit, the protocol stack node and the hardware driver node in the second processing module respectively record the sending timestamp in the payload part of the time detection packet through the timer; Step S23, when the time detection packet flows along the first direction to the third flow unit, the bus node, controller node and physical layer node in the third processing module respectively record the sending timestamp in the payload part of the time detection packet through the timer.

3. The statistical method for data packet full path node processing time according to claim 2, characterized in that: Step S3 comprises, Step S31, when the time detection packet flows along the test path to the third flow unit, the bus node, the controller node and the physical layer node in the third processing module respectively record a receiving timestamp in the payload portion of the time detection packet through the timer; Step S32, when the time detection packet flows along the test path to the second flow unit, the protocol stack node and the hardware driver node in the second processing module respectively record a receiving timestamp in the payload portion of the time detection packet through the timer; Step S33, when the time detection packet flows along the test path to the first flow unit, the application node and the dynamic link library node in the first processing module respectively record the receiving timestamp in the payload part of the time detection packet through the timer.

4. The statistical method for data packet full path node processing time according to claim 1, characterized in that: Step S4 includes collecting the result of the dotting processing, calculating the total processing time of the time detection package in the system on chip and the node processing time in each processing module according to the result of the dotting processing, obtaining the statistical result and outputting it.

5. The statistical method for data packet full path node processing time according to claim 4 is characterized in that: Also includes, Step S5, comparing the node processing time with a preset time threshold, and outputting the corresponding node when the node processing time is greater than the time threshold.

6. A statistical system for processing time of nodes along the entire path of a data packet, characterized in that: include, A data packet marking module, used for setting a flag bit on the header of a data packet to mark the data packet as a time detection packet; A timestamp marking module, connected to the data packet marking module, for recording a timestamp in the payload portion of the time detection packet to obtain timestamp data, wherein the timestamp data includes a sending timestamp and a receiving timestamp; The full-path acquisition module is connected to the timestamp marking module and is used to collect and count all the timestamp data of the time detection package to obtain statistical results.

7. The statistical system for processing time of nodes along the entire path of a data packet according to claim 6, characterized in that: The timestamp module includes: A forward dotting unit connected to the data packet marking module, when the time detection packet flows in the first direction, records a sending timestamp for the payload portion of the time detection packet through a timer in a processing node; The reverse dotting unit is connected to the forward dotting unit, and records a receiving timestamp for the payload portion of the time detection packet through the timer in the processing node when the time detection packet flows along a test path opposite to the first direction.

8. The statistical system for data packet full path node processing time according to claim 7, characterized in that: The processing nodes include application nodes, dynamic link library nodes, protocol stack nodes, hardware driver nodes, bus nodes, controller nodes and physical layer nodes.

9. The statistical system for processing time of nodes along the entire path of a data packet according to claim 7, characterized in that: The full path acquisition module includes: A collection unit, used for collecting all the timestamp data of the time detection packet; A statistical unit is connected to the acquisition unit and is used to calculate the total processing time of the time detection packet in the system on chip and the processing time of each processing node according to the timestamp data to obtain the statistical result.

10. The statistical system for processing time of nodes along the entire path of a data packet according to claim 9, characterized in that: Also includes, The abnormality identification module is connected to the full-path acquisition module and is used to compare the processing time of the processing node with a preset time threshold until the processing time of the processing node is greater than the time threshold, and output the corresponding processing node.

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