Memory system for performing read reclaim

Abstract

The present disclosure relates to a memory system for performing read reclaim, including: a memory device including a plurality of memory blocks; and a controller suitable for controlling the memory device to perform a pre-read reclaim on a pre-sacrifice block among pre-read blocks among the plurality of memory blocks, the pre-sacrifice block including an uncorrectable error, the pre-read block being a block on which a pre-read operation has been performed.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0141913, filed on October 23, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate generally to a memory system, and more particularly, to a memory system for performing read reclamation. Background Art

[0004] The paradigm of computer environment has shifted to ubiquitous computing, which makes computing systems available anywhere, anytime. As a result, the use of portable electronic devices such as mobile phones, digital cameras, and laptop computers has increased rapidly. These portable electronic devices generally use a memory system having one or more memory devices to store data. The memory system can be used as a primary memory device or an auxiliary memory device of the portable electronic device.

[0005] Memory systems without moving parts provide excellent stability, durability, high information access speed, and low power consumption. Examples of memory systems having these advantages include Universal Serial Bus (USB) memory devices, memory cards with various interfaces, and Solid State Drives (SSDs). Summary of the invention

[0006] Various embodiments of the present disclosure are directed to a memory system that utilizes reliability information calculated during a pre-read operation to determine a pre-victim block on which read reclamation is to be performed.

[0007] Furthermore, various embodiments of the present disclosure relate to a memory system that determines a priority of a victim block that is a target of read reclamation based on a read type and performs read reclamation according to the determined priority.

[0008] An embodiment of the present disclosure may provide a memory system, comprising: a memory device, comprising a plurality of memory blocks; and a controller, adapted to control the memory device to perform pre-read recovery on a pre-sacrificial block in a pre-read block among the plurality of memory blocks, the pre-sacrificial block containing an uncorrectable error, the pre-read block being a block on which a pre-read operation has been performed.

[0009] The controller may control the memory device to perform pre-read reclamation when the number of read requests from the external device is greater than or equal to a threshold and after performing at least one of normal read reclamation and internal read reclamation, wherein the normal read reclamation is performed on a normal victim block that performs a normal read operation, and the internal read reclamation is performed on an internal victim block determined during an internal read operation that has been performed.

[0010] When performing forced garbage collection, the controller may control the memory device to perform pre-read reclamation.

[0011] The controller may process the pre-victim block storing data for which error recovery has failed among the pre-victim blocks for which pre-read recovery has been performed as a bad block.

[0012] The controller may prioritize normal read reclamation and internal read reclamation over pre-read reclamation.

[0013] The controller may reorder the order of read reclamation indicating the order of performing each of pre-read reclamation, normal read reclamation, and internal read reclamation based on the priority, the number of read requests for real-time update, and the number of uncorrectable errors.

[0014] An embodiment of the present disclosure may provide a memory system, comprising: a memory device, comprising a plurality of memory blocks; and a controller, adapted to: calculate the number of uncorrectable errors contained in each of the pre-read blocks, determine a pre-read block containing the uncorrectable errors among the plurality of memory blocks as a pre-sacrifice block, and control the memory device to perform pre-read recovery on the pre-sacrifice block, wherein, when it is determined that a pre-read operation is to be performed, each of the pre-read blocks stores sequential data.

[0015] After performing the data recovery operation on the pre-victim block, the controller may perform pre-read reclamation.

[0016] The controller may process a pre-victim block storing errors that are not recovered through a data recovery operation as a bad block.

[0017] The memory system may further include a queue buffer in which the pre-victim information of the pre-victim blocks is queued according to the determined order of the pre-victim blocks, and the normal-victim information of the normal-victim blocks is queued according to the determined order of the normal-victim blocks.

[0018] The controller may reorder the queuing order of the pre-victim information and the normal victim information based on the priority, the number of uncorrectable errors updated in real time, and the number of read requests.

[0019] After completing the execution of normal read reclamation, the controller may perform pre-read reclamation in one of the following states: a first state in which the memory system does not perform data input / output operations with an external device; a second state in which the invalidity level of data stored in a plurality of memory blocks is equal to or less than a predetermined value; and a third state in which forced garbage collection is performed. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1is a flowchart illustrating a pre-read operation according to an embodiment of the present disclosure.

[0021] Figure 2 is a flowchart illustrating a pre-read operation according to an embodiment of the present disclosure.

[0022] Figure 3 is a diagram schematically illustrating a data processing system including a memory system according to an embodiment of the present disclosure.

[0023] Figure 4 is a diagram illustrating read recycling according to an embodiment of the present disclosure.

[0024] Figure 5 is a diagram schematically illustrating a controller that performs read reclaim according to an embodiment of the present disclosure.

[0025] Figure 6 It is shown Figure 5 A flowchart of a read reclaim performed by the controller is shown.

[0026] Fig. 7A and Figure 7B is a diagram illustrating a method of reordering victim information according to the first embodiment of the present disclosure.

[0027] Figure 8 is a diagram illustrating a method of reordering victim information according to a second embodiment of the present disclosure.

[0028] Fig. 9 It shows that according to Figure 6 Flowchart of read reclamation performed with priority shown.

[0029] Fig.10 is a flowchart illustrating a detailed operation of recycling according to an embodiment of the present disclosure.

[0030] Fig.11 is a diagram illustrating garbage collection according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] Various embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. In the following description, only the parts necessary for understanding the operation of the embodiments of the present disclosure will be described, and the description of other parts will be omitted to avoid obscuring the subject matter of the present disclosure.

[0032] Figure 1 is a flowchart illustrating a pre-read operation according to an embodiment of the present disclosure.

[0033] Sequential data stored in a storage block composed of nonvolatile memory cells is likely to be requested to be read by an external device such as a host. In order to reduce the read latency of the external read request, a controller controlling the storage block may perform a read operation on the sequential data in advance before receiving the external read request. This is called a pre-read operation.

[0034] The controller may perform a pre-read operation on a pre-read block storing sequential data among the storage blocks. To this end, in S100 , the controller may perform a pre-read operation on valid data stored in the pre-read block and perform an error correction code (ECC) operation on the pre-read data.

[0035] The ECC operation refers to an operation of detecting errors and correcting the detected errors by using an ECC code. The controller may determine data containing more than a certain number of error bits as data containing uncorrectable errors. The controller may calculate the number of uncorrectable errors through the ECC operation. The number of uncorrectable errors may include the number of error bits of the included uncorrectable errors.

[0036] In S110, the controller may store the sequential data for which the error correction is completed in the output memory. Accordingly, the pre-reading operation according to the first embodiment of the present disclosure may be completed.

[0037] In this embodiment, when a read request for sequential data stored in the output memory is received from an external device, the controller can send the error-corrected valid data stored in the output memory to the external device. Therefore, the pre-read operation according to the first embodiment can reduce the read delay of the external read request.

[0038] When read reclamation must be performed after performing a pre-read operation, the controller may select a memory block containing an uncorrectable error from among multiple memory blocks as a victim block for read reclamation. To this end, the controller must perform an ECC operation on multiple memory blocks to detect errors.

[0039] In this case, even for the pre-read block for which the pre-read operation has been performed, the controller must perform the ECC operation again to detect errors. That is, since the number of uncorrectable errors calculated by the ECC operation of S100 cannot be used to determine the victim block, the error detection operation must be repeatedly performed on the pre-read block.

[0040] When the victim block is not selected during the pre-read operation but is selected for read reclamation, the victim block may be determined in a state where the damage degree of data stored in the pre-read block is higher than that of data during the pre-read operation.

[0041] Figure 2 is a flowchart illustrating a pre-read operation according to an embodiment of the present disclosure.

[0042] exist Figure 2 In the description of Figure 1 The parts described overlap.

[0043] In S210 , the controller may perform an ECC operation on the pre-read block and calculate the number of uncorrectable errors.

[0044] In S220, the controller may divide the pre-read blocks into normal blocks and abnormal blocks based on the calculated number of uncorrectable errors. A normal block is a storage block that does not contain an uncorrectable error, and an abnormal block is a storage block that contains an uncorrectable error.

[0045] In S230 , the controller may determine the abnormal block as a victim block for read reclaiming.

[0046] In S250 , the controller may store sequential data, which is stored in the normal block and on which error correction has been completed, in the output memory.

[0047] In an embodiment, the controller may select a sacrificial block for read recovery based on the number of uncorrectable errors obtained by the ECC operation performed during the pre-read operation. Therefore, when performing read recovery after performing the pre-read operation, the controller does not need to perform the ECC operation again on the pre-read block that has completed the pre-read operation to determine the sacrificial block.

[0048] In the method for performing a pre-read operation according to an embodiment of the present disclosure, a sacrificial block to be read and reclaimed can be determined during the pre-read operation. Therefore, the sacrificial block can be determined in a state where the degree of data damage is not too serious.

[0049] Figure 3 is a diagram schematically illustrating a data processing system including a memory system according to an embodiment of the present disclosure.

[0050] Reference Figure 3 , the memory system 110 operates with the external device 102 to perform data input / output operations. The memory system 110 may include a controller 130 and a memory device 150. The controller 130 includes a host interface (I / F) 141, a flash translation layer (FTL) 142, a memory interface (I / F) 143, and a memory 144.

[0051] The host interface 141 may handle commands, data, etc. sent from the external device 102. As an example and not a limitation, the host interface 141 may include a command queue (CMD QUE) 56, a buffer manager, and an event queue. The command queue 56 may sequentially store commands and data received from the external device 102, and, for example, output the stored commands and data to the buffer manager in the order in which the commands and data are stored in the command queue 56. The buffer manager may classify, manage, or adjust the commands and data received from the command queue 56. The event queue may sequentially send events for processing commands and data received from the buffer manager.

[0052] A plurality of commands or data having the same characteristics may be sent from the external device 102, or a plurality of commands and data having different characteristics may be mixed or jumbled by the external device 102 and sent to the memory system 110. For example, a plurality of commands for reading data, i.e., read commands, may be transmitted, or commands for reading data, i.e., read commands, and commands for programming or writing data, i.e., write commands, may be sent alternately to the memory system 110. The host interface 141 may sequentially store the commands and data sent from the external device 102 in the command queue 56. Thereafter, the host interface 141 may estimate or predict what type of internal operation the controller 130 will perform based on the characteristics of the commands and data sent from the external device 102. The host interface 141 may determine the processing order and priority of the commands and data based on their characteristics.

[0053] According to the characteristics of the command and data sent from the external device 102, the buffer manager in the host interface 141 is configured to determine whether the buffer manager should store the command and data in the memory 144, or whether the buffer manager should pass the command and data to the FTL 142. The event queue receives events and passes the events to the FTL 142 in the order in which the events are entered into the event queue. Events can be sent from the buffer manager, and the memory system 110 or the controller 130 executes and processes the events internally in response to the commands and data.

[0054] According to an embodiment, Figure 3 The illustrated FTL 142 may implement a multi-threading scheme to perform data input and output (input / output) (I / O) operations. The multi-threaded FTL may be implemented by a multi-core processor included in the controller 130 using multi-threading.

[0055] According to an embodiment, the FTL 142 may include a host request manager, a mapping manager, a state manager, and a block manager. The block manager may include a bad block (BB) manager 136. The host request manager may manage events sent from an event queue. The mapping manager may handle or control mapping data. The state manager may perform read recovery (RR), garbage collection (GC), or wear leveling (WL). The block manager may execute commands or instructions on blocks in the memory device 150.

[0056] As an example and not a limitation, the host request manager may utilize the mapping manager and the block manager to handle or process requests based on read and program commands and events passed from the host interface 141. The host request manager may send a query request to the mapping manager to determine the physical address corresponding to the logical address input with the event. The host request manager may send a read request with the physical address to the memory interface 143 to process the read request, i.e., handle the event. In one embodiment, the host request manager may send a program request (or write request) to the block manager to program data to a specific empty page in the memory device 150 where no data is stored. The host request manager may then send a mapping update request corresponding to the programming request to the mapping manager to update the items related to the programming data in the information in which the logical address and the physical address are mapped to each other.

[0057] The block manager may convert the program request passed from the host request manager, the mapping manager, and / or the state manager into a flash program request for the memory device 150 so as to manage the flash blocks in the memory device 150. In order to maximize or enhance the programming or writing performance of the memory system 110, the block manager may collect the program requests and send the flash program requests for multi-plane and one-shot programming operations to the memory interface 143. In an embodiment, the block manager sends multiple flash program requests to the memory interface 143 to enhance or maximize the parallel processing of the multi-channel and multi-directional flash controller.

[0058] In an embodiment, the block manager may manage blocks in the memory device 150 according to the number of valid pages, select and erase blocks without valid pages when a free block is needed, and select blocks containing the least valid pages when it is determined to perform garbage collection. The state manager may perform garbage collection to move valid data stored in the selected blocks to empty blocks and erase data stored in the selected blocks, so that the memory device 150 may have sufficient free blocks (i.e., empty blocks without data). When the block manager provides information about a block to be erased to the state manager, the state manager may check all flash memory pages of the block to be erased to determine whether each page of the block is valid.

[0059] For example, to determine the validity of each page, the state manager can identify the logical address recorded in the out-of-band (OOB) area of ​​each page. To determine whether each page is valid, the state manager can compare the physical address of the page with the physical address mapped to the logical address obtained from the query request. The state manager sends a program request for each valid page to the block manager. When the programming operation is completed, the mapping manager can update the mapping table.

[0060] The mapping manager can manage mapping data, such as a logical-physical mapping table. The mapping manager can process various requests generated by the host request manager or the state manager, such as query, update, etc. The mapping manager can store the entire mapping table in the memory device 150 (e.g., flash memory / non-volatile memory) and cache mapping entries according to the storage capacity of the memory 144. When a mapping cache miss occurs when processing a query or update request, the mapping manager can send a read request to the memory interface 143 to load the relevant mapping table stored in the memory device 150. When the number of dirty cache blocks in the mapping manager exceeds a certain threshold, a programming request can be sent to the BB manager 136 to generate a clean cache block and the dirty mapping table can be stored in the memory device 150.

[0061] When performing garbage collection, the state manager copies (multiple) valid pages into free blocks, and the host request manager may program the latest version of data for the same logical address of the page and issue an update request at the same time. When the state manager requests a mapping update in a state where the copying of (multiple) valid pages is not completed normally, the mapping manager may not perform a mapping table update. This is because when the state manager requests a mapping update and the valid page copy is completed later, the mapping request is issued using old physical information. The mapping manager may perform a mapping update operation to ensure accuracy when or only when the latest mapping table still points to the old physical address.

[0062] FTL 142 may include an error correction code (ECC) unit 138, a data recovery unit 134, and a BB manager 136. ECC unit 138, data recovery unit 134, and BB manager 136 may be implemented as separate modules, circuits, firmware, etc. included in or associated with controller 130.

[0063] The ECC unit 138 may correct the error bits of the data read from the memory device 150, and may include an error correction code (ECC) encoder and an ECC decoder. Here, the ECC encoder may perform error correction encoding on the data to be programmed into the memory device 150, thereby generating encoded data to which a parity bit is added, and storing the encoded data in the memory device 150. When the controller 130 reads the data stored in the memory device 150, the ECC decoder may detect and correct the error bits contained in the data read from the memory device 150. After performing error correction decoding on the data read from the memory device 150, the ECC unit 138 may determine whether the error correction decoding is successful or failed, and output an indication signal (e.g., an error correction success signal or an error correction failure signal). The ECC unit 138 may use the parity bit generated during the ECC encoding to correct the error bits of the read data. When the number of error bits is greater than or equal to the threshold number of correctable error bits, the ECC unit 138 may not correct the error bits, but output an error correction failure signal indicating that the error bits have failed to be corrected.

[0064] In an embodiment of the present disclosure, if the number of errors in data stored in a page is above a certain number, the ECC unit 138 may determine that the certain number exceeds the error correction capability of the ECC unit 138. Accordingly, the ECC unit 138 may determine that the errors in the corresponding page are uncorrectable.

[0065] With respect to the memory system 110, it is desirable to increase the data storage capacity while maintaining data accuracy and input / output speed. To this end, the memory system 110 may use error correction code (ECC) technology and signal processing technology to effectively improve data reliability related to data accuracy. In another embodiment, the ECC unit 138 may be implemented as a separate module, circuit, firmware, etc., which is included in the controller 130 or associated with the controller 130.

[0066] The unit of data to which error correction code (ECC) is applied to detect and correct errors in data is called a codeword. The length of a codeword is n bits. The n bits include k bits of user data and (nk) bits of parity data. The code rate is calculated as (k / n). The higher the code rate, the more user data can be stored in each codeword. Generally, the longer the codeword and the smaller the code rate, the better the error correction capability of the error correction code (ECC).

[0067] The data recovery unit 134 can decode the data or information read from the memory device 150 and sent through the channel. The data recovery unit 134 may include a decoder that performs hard decision decoding or soft decision decoding according to how many bits of data or information the data or information is represented as. For example, the decoder can use the memory cell output information represented as 1 bit to perform hard decision decoding. Here, 1 bit of information can be referred to as hard information. In addition, the decoder can use more accurate memory cell output information represented as two or more bits to perform soft decision decoding. Two or more bits of information can be referred to as soft information. Soft decision decoding has a stronger error correction capability than hard decision decoding. However, compared with hard decision decoding, soft decision decoding may require higher hardware implementation complexity and / or higher memory consumption. In addition, generating soft information may require a longer read delay than generating hard information.

[0068] The operation of reading the data stored in the memory device 150 is performed through a word line. Data stored in a plurality of memory cells connected to a single word line can be read simultaneously. In a read operation, a reference voltage is applied to the word line. The reference voltage can be compared with the threshold voltage of each memory cell to determine the data representing the information based on the comparison result. For example, the data stored in each memory cell is determined according to whether the threshold voltage has a level lower or higher than the reference voltage. Therefore, it may be necessary to sense once (i.e., read once) per word line to generate hard information. In the case of generating 2-bit soft information representing 4 levels, the level of the reference voltage is changed or adjusted, and three sensings (i.e., reading three times) can be performed using reference voltages of different levels.

[0069] When an error is detected in the data read from the memory device 150, the memory system 110 may perform error correction operations step by step. For example, when an error is found in the data read from a single page, the data recovery unit 134 may perform hard decision decoding on the data. If the error in the corresponding data cannot be corrected by hard decision decoding, the data recovery unit 134 may alternately perform read bias optimization to adjust the level of the read voltage and soft decision decoding. However, read bias optimization and soft decision decoding may require a relatively large number of sensing (reading) operations to be performed on the memory cells to recover the data read from a single page, and thus may increase read latency and reduce data quality (QoS).

[0070] In an embodiment of the present disclosure, when hard decision decoding fails at least once, the memory system 110 may utilize chipkill decoding to recover and restore data read from a single page more quickly and efficiently.

[0071] In an embodiment, chip hunting decoding can be performed in any one of two different ways or a combination of the two ways. In an embodiment, how to perform chip hunting decoding can be selected or determined based on the hardware configuration of memory system 110, but may not be changed by software designed for the operations performed by controller 130.

[0072] In order to apply chip hunting decoding to correct errors, the data stored in the memory device 150 may constitute a codeword. The codeword may be a set of data bits and error check bits, which are provided by an error correction code (ECC) algorithm for error detection and correction. The data bits may correspond to user data, and the error check bits may correspond to parity data. For example, 256 (=64×4) bits of interrelated data are stored in four different locations within the memory device 150. When the user data area of ​​the memory device 150 is designed in units of 64 bits, the size of the codeword may be 72 bits, which includes 64 bits of user data and 8 bits of error correction data (or parity data). In this case, the memory system 110 may automatically correct the error when the error is a single bit error, and truly detect a 2-bit error, which is referred to as single error correction / double error detection (SEC / DED). When an error occurs in multi-bit data read from four different locations storing 256 bits, the data recovery unit 134 may perform chip hunting decoding to correct the error contained in the 256-bit data.

[0073] In an embodiment of the present disclosure, when the hard decision decoding performed on each codeword fails, the data recovery unit 134 can perform chip hunting decoding after parallel sensing and reading the codewords at four different positions. Therefore, the increase in read delay and the decrease in quality of service (QoS) that may be caused by performing soft decision decoding after hard decision decoding can be avoided.

[0074] The memory 144 may be used as a working memory of the memory system 110 or the controller 130 when temporarily storing transaction data for operations performed in the memory system 110 and the controller 130. For example, the memory 144 may temporarily store read data entries output from the memory device 150 before the read data entries are output to the external device 102 in response to a read request from the external device (e.g., a host) 102. In addition, the controller 130 may temporarily store write data entries input from the external device 102 in the memory 144 before programming the write data entries into the memory device 150. When the controller 130 controls operations of the memory device 150 such as a data read operation, a data write or program operation, and a data erase operation, data transmitted between the controller 130 of the memory system 110 and the memory device 150 may be temporarily stored in the memory 144.

[0075] In an embodiment, the memory 144 may be implemented with volatile memory. For example, the memory 144 may be implemented with static random access memory (SRAM), dynamic random access memory (DRAM), or both. Figure 3 The memory 144 is shown to be provided in the controller 130, but the embodiment is not limited thereto. The memory 144 may be located in or outside the controller 130. For example, the memory 144 may be implemented by an external volatile memory having a memory interface that transmits data and / or signals between the memory 144 and the controller 130.

[0076] The memory 144 may store data required to perform operations such as write operations and read operations between the external device 102 and the memory device 150. The memory 144 may include a program memory, a data memory, a write buffer / cache, a read buffer / cache, a data buffer / cache, a mapping buffer / cache, etc.

[0077] The memory 144 may store state information STATE_INF including information required for background operation, pre-read operation and error correction operation and operation results. The state information STATE_INF may include the number of uncorrectable errors, sequence information, read count, threshold value and reference value.

[0078] In an embodiment, the memory 144 may include an output memory 401 for storing data to be output to the external device 102 .

[0079] The sequential information may include the number and location of sequential data included in the storage block. The read count may include the number of times a read operation is performed on the storage block in response to a read request received from the external device 102. The threshold may be a comparison basis for the read count, and the reference value may be a comparison basis for the number of errors.

[0080] The memory 144 may include a queue buffer (QUE BUF.) 403 for storing information about the victim block. The information about the victim block may include information about the pre-victim block determined based on the number of uncorrectable errors calculated during the pre-read operation, information about the normal victim block determined based on the read count, and information about the internal victim block determined based on the number of uncorrectable errors calculated during the internal read operation.

[0081] In some embodiments, the information of the pre-victim block, the information of the normal victim block, and the information of the internal victim block are stored in different queue buffers, respectively.

[0082] That is, the information of the pre-victim block, the information of the normal victim block and the information of the internal victim block can be stored in different queue buffers, respectively. Alternatively, the information of the pre-victim block, the information of the normal victim block and the information of the internal victim block can be stored in a single queue buffer.

[0083] According to the number of bits that can be stored or represented in a single memory cell, the memory device 150 may include a plurality of memory blocks, such as a single-level cell (SLC) memory block and a multi-level cell MLC memory block. The plurality of memory blocks may include a pre-read block that performs a pre-read operation, a normal read block that performs a normal read operation, and an internal read block that performs an internal read operation.

[0084] Figure 4 is a diagram illustrating read recycling according to an embodiment of the present disclosure.

[0085] Specifically, read reclaim can be Figure 3 The FTL 142 shown is executed under the control of the FTL 142.

[0086] Read reclamation includes an operation of changing a storage location of data to ensure safety by copying data stored in a memory block having a relatively high read count nRD to another memory block.

[0087] The read count nRD refers to the number of times a read operation is performed on data stored in a specific memory block. In an embodiment, the read count nRD may be counted by a read counter.

[0088] Since the degree of damage of a memory block whose read count nRD is greater than or equal to the threshold TH is high, the probability of an error in the data stored in the memory block increases. When multiple read operations are performed on a specific page included in the memory block, a read disturbance phenomenon may occur in which the cell level of other pages where the read operation is not performed increases. When errors and read disturbance phenomena accumulate, exceeding Figure 3 The probability of error occurrence may increase due to the error correction capability of the ECC unit 138.

[0089] Read recycling refers to migrating and storing the valid data of the sacrifice block to the target block, and performing an erase operation on the sacrifice block. The sacrifice block can be a block with a read count nRD greater than or equal to the threshold TH, and the target block can be a block with a relatively small read count nRD. Through this read recycling, unrecoverable errors in valid data can be avoided.

[0090] exist Figure 4 , the horizontal axis represents the number of the plurality of memory blocks BLK1 to BLK9 included in the memory device 150 , and the vertical axis represents the read count nRD of each of the plurality of memory blocks BLK1 to BLK9 included in the memory device 150 .

[0091] When the read count nRD exceeds the threshold TH, the probability of an error in the data stored in the corresponding storage block increases. Figure 4 In the example shown, the second memory block BLK2 having a read count nRD greater than or equal to the threshold TH may be determined as a bad block BB, and thus the probability that the second memory block BLK2 is unusable may increase.

[0092] like Figure 4 As shown, among the plurality of memory blocks BLK1 to BLK9 included in the memory device 150, data stored in the first memory block BLK1, the second memory block BLK2, and the fifth memory block BLK5, each having a relatively high read count nRD, can be migrated to the fourth memory block BLK4 having a relatively low read count nRD. This is called normal read recycling.

[0093] In this case, the first to fifth memory blocks BLK1 , BLK2 , and BLK5 may be referred to as victim blocks (or source blocks) of read reclamation, and the fourth memory block BLK4 may be referred to as a target block of read reclamation.

[0094] In an embodiment, read reclamation may be performed to ensure reliability of data stored in a memory block containing an uncorrectable error (UECC) or a memory block having an error number greater than a reference value.

[0095] In the case where a storage block contains uncorrectable errors (UECC) or the number of errors is greater than or equal to a reference value, the probability that the data stored in the storage block cannot correct the errors increases over time. Therefore, the probability of errors exceeding the error correction capability of the ECC unit 138 may increase. Therefore, all data of the storage block or only valid data may be migrated to another block. This is called pre-read reclamation and internal read reclamation.

[0096] In an embodiment of the present disclosure, read recycling may be performed in the memory device 150 so that valid data is not stored in bad blocks but in target blocks, thereby improving the reliability of the memory device 150 and the data stored therein.

[0097] Since the physical address of the storage location of the data corresponding to the logical block is changed by read recovery, the physical address of the physical block may become invalid. In this case, the controller 130 can keep the mapping table in the latest state by correcting the mapping table so that the changed physical address is mapped to the logical address instead of the invalid physical address. Therefore, in an embodiment of the present disclosure, the latest mapping table can be used to perform memory operations through the mapping data management in the memory device, so that the speed of the memory operation can be improved.

[0098] Figure 5 is a diagram schematically illustrating a controller 130 performing read reclaim according to an embodiment of the present disclosure.

[0099] The controller 130 may include a pre-victim determination unit 131, a normal victim determination unit 132, an internal victim determination unit 133, a data recovery unit 134, a read reclaim (RR) operation unit 135, a bad block (BB) manager 136, and an ECC unit 138. The controller 130 may include a first queue buffer 403A, a second queue buffer 403B, and a third queue buffer 403C.

[0100] The pre-sacrifice determination unit 131, normal sacrifice determination unit 132, internal sacrifice determination unit 133, data recovery unit 134, RR operation unit 135, BB manager 136 and ECC unit 138 include all circuits, systems, software, firmware and devices required for their respective operations and functions.

[0101] The ECC unit 138 may detect errors of data stored in a memory block, perform an error correction operation on the detected errors, and calculate the number of uncorrectable errors nUECC representing the reliability of the memory block.

[0102] When the number of error bits included in one data exceeds a certain number, the ECC unit 138 may not perform error correction using the ECC. That is, the ECC unit 138 may determine that the data is uncorrectable because the data exceeds the error correction capability of the ECC unit 138. The number of uncorrectable errors nUECC may include the number of data determined to be uncorrectable among the multiple data included in the storage block.

[0103] In an embodiment, the controller 130 may determine a pre-read block as a target of a pre-read operation based on the sequence information received from the external device 102 and the pattern of the read request. The pre-read operation is a read operation performed on sequential data in advance before receiving a read request from the external device 102 to reduce read latency. Each pre-read block may be a storage block storing sequential data with a high probability of being requested to be read by the external device 102.

[0104] The pre-sacrifice determination unit 131 may determine a pre-sacrifice block for which pre-read reclamation is to be performed based on the number of uncorrectable errors nUECC of the pre-read block calculated by the ECC unit 138 during the pre-read operation. The pre-sacrifice determination unit 131 may determine a pre-read block, each storing uncorrectable data, among the pre-read blocks as a pre-sacrifice block.

[0105] The pre-sacrifice determination unit 131 may queue the pre-sacrifice information PRE_INF of the pre-sacrifice blocks in the first queue buffer 403A according to the determination order of the pre-sacrifice blocks.

[0106] The pre-victim information PRE_INF may include an identifier of the pre-victim block, a queueing order of the pre-victim information PRE_INF, a read type of the pre-victim block, and the number nUECC of uncorrectable errors of the pre-victim block.

[0107] The read type may include the type of read operation performed to determine the corresponding memory block as a victim block. The read type of the pre-victim block may be "pre-read".

[0108] The controller 130 may perform a pre-read operation on other pre-read blocks except the pre-sacrificial block, and store the sequential data stored in the pre-read blocks in Figure 3 Thereafter, when a read request is received from the external device 102 , the controller 130 may transmit the sequential data stored in the output memory 401 to the external device 102 .

[0109] The normal victim determination unit 132 may determine a normal victim block to be subjected to normal read reclamation based on the read count nRD. The normal victim determination unit 132 may determine a memory block having a read count nRD greater than or equal to a threshold value among a plurality of memory blocks as a normal victim block.

[0110] The normal read operation is a read operation performed according to a read request received from the external device 102. The read count nRD may include the number of read requests received from the external device 102 or the number of times the normal read operation is performed.

[0111] The normal sacrifice determination unit 132 may queue the normal sacrifice information NOR_INF of the normal sacrifice blocks in the second queue buffer 403B according to the determination order of the normal sacrifice blocks.

[0112] The normal victim information NOR_INF may include at least one of an identifier of a normal victim block, a queue order of the normal victim information NOR_INF, a read type of the normal victim block, and a read count nRD of the normal victim block. The read type of the pre-victim block may be "normal read".

[0113] The internal victim determination unit 133 may determine an internal victim block for which internal read reclamation is to be performed based on the number nUECC of uncorrectable errors of the internal read block calculated by the ECC unit 138 during the internal read operation. The internal victim determination unit 133 may determine an internal read block storing uncorrectable data among the internal read blocks as an internal victim block.

[0114] Uncorrectable errors UECC due to deterioration of data retention characteristics and read disturbance are likely to occur in dormant blocks and weak blocks. Each dormant block may be a block that has not performed a read operation for a long time. Each weak block may be a block including a weak word line.

[0115] Therefore, the controller 130 may correct errors through an ECC operation accompanying an internal read operation to prevent uncorrectable errors UECC from occurring in dormant blocks and weak blocks.

[0116] Internal read operations may include media scan operations and weak block recovery operations.

[0117] The media scan operation is an internal read operation for preventing data stored in the dormant block from being damaged. The media scan operation may be performed according to a request of the external device 102, or may be performed according to a specific cycle determined by the controller 130. During the media scan operation, the controller 130 may determine a dormant block containing an uncorrectable error UECC or detecting a certain number of error bits or more as an internal victim block.

[0118] The weak block recovery operation is an internal read operation for preventing data stored in weak pages generated during the manufacturing process of the memory block from being damaged. Weak blocks are blocks each including weak pages having relatively poor threshold voltage characteristics. During the weak block recovery operation, the controller 130 may determine a dormant block containing an uncorrectable error UECC or detecting a certain number of error bits or more as an internal sacrificial block.

[0119] The controller 130 may perform error correction operations on the dormant blocks and the weak blocks and migrate the corrected data to other storage blocks.

[0120] The internal sacrifice determination unit 133 may queue the internal sacrifice information INT_INF of the internal sacrifice blocks in the third queue buffer 403C according to the determination order of the internal sacrifice blocks.

[0121] The internal victim information INT_INF may include at least one of an identifier of the internal victim block, a queueing order of the internal victim information INT_INF, a read type of the internal victim block, and a number of uncorrectable errors nUECC. The read type of the internal victim block may be "internal read".

[0122] The first to third queue buffers 403A to 403C may operate according to a first-in-first-out (FIFO) method.

[0123] The data recovery unit 134 may perform a data recovery operation on the pre-sacrificial block, the normal sacrificial block, and the internal sacrificial block corresponding to the sacrificial information stored in the first to third queue buffers 403A to 403C. Therefore, the uncorrectable error UECC that exceeds the error correction capability of the ECC unit 138 may be recovered through the data recovery operation.

[0124] The data recovery unit 134 may preferentially perform a data recovery operation on a victim block corresponding to information of a victim block having a higher queue order.

[0125] The data recovery unit 134 may set the priority of the data recovery operation on the normal sacrificial block to be greater than the priority of the data recovery operation on the pre-sacrificial block. In addition, the data recovery unit 134 may set the priority of the data recovery operation on the internal sacrificial block to be greater than the priority of the data recovery operation on the pre-sacrificial block. That is, the data recovery unit 134 may perform the data recovery operation on the pre-sacrificial block after the data recovery operations on the normal sacrificial block and the internal sacrificial block are completed.

[0126] The data recovery unit 134 may perform a data recovery operation on the pre-victim block in an idle state in which the memory system 110 does not perform a data input / output operation with the external device 102 after completing the data recovery operation on the normal victim block and the internal victim block.

[0127] After completing the data recovery operation on the normal sacrifice block and the internal sacrifice block, when the invalidity levels of the plurality of memory blocks are less than or equal to a predetermined value (ie, a low dirty level), the data recovery unit 134 may perform a data recovery operation on the pre-sacrifice block.

[0128] After the data recovery operation is completed for the normal victim block and the internal victim block, the data recovery unit 134 may perform the data recovery operation for the pre-victim block while performing forced garbage collection (FGC). After the memory system 110 is restarted due to a sudden power failure, when an open block where an error occurs is detected, forced garbage collection (FGC) may be performed. Forced garbage collection (FGC) may be performed according to a request of the external device 102.

[0129] The RR operation unit 135 may perform read reclaim on the pre-victim blocks, the normal victim blocks, and the internal victim blocks corresponding to the victim information stored in the first to third queue buffers 403A to 403C, respectively.

[0130] Even if the uncorrectable error UECC detected by the ECC unit 138 is recovered through the data recovery operation, the pre-sacrificial block, the normal sacrificial block, and the internal sacrificial block are still storage blocks with a high probability of the uncorrectable error UECC occurring. Therefore, the RR operation unit 135 can perform read recovery on the pre-sacrificial block, the normal sacrificial block, and the internal sacrificial block that have recovered the uncorrectable error UECC. Since the read recovery is performed on the sacrificial block that has performed the data recovery operation, the reliability of the data migrated to the target block can be higher.

[0131] According to an embodiment, the present disclosure may include an embodiment of performing read recovery only on a victim block that has failed error recovery even through a data recovery operation. That is, the present disclosure may also include an embodiment of not performing read recovery on a victim block that has completed error recovery through a data recovery operation.

[0132] The RR operation unit 135 may set the priority of the read recovery of the normal sacrifice block to be greater than the priority of the read recovery of the pre-sacrifice block. In addition, the data recovery unit 134 may set the priority of the read recovery of the internal sacrifice block to be greater than the priority of the read recovery of the pre-sacrifice block. That is, the RR operation unit 135 may perform read recovery on the pre-sacrifice block after the data read recovery of the normal sacrifice block and the internal sacrifice block is completed.

[0133] After completing read reclamation on the normal victim block and the internal victim block, the RR operation unit 135 may perform read reclamation on the pre-victim block in an idle state in which the memory system 110 does not perform a data input / output operation with the external device 102 .

[0134] After completing read reclamation on the normal victim block and the internal victim block, when invalid levels of the plurality of memory blocks are less than or equal to a predetermined value (low dirty level), the RR operation unit 135 may perform read reclamation on the pre-victim block.

[0135] After finishing performing read reclaim on the normal victim block and the internal victim block, the RR operation unit 135 may perform read reclaim on the pre-victim block while performing forced garbage collection (FGC).

[0136] The BB manager 136 may process the victim blocks including the uncorrectable error UECC among the victim blocks on which read reclamation has been completed as bad blocks.

[0137] Reference Figure 5 The read count nRD, sequence information, and number of uncorrectable errors nUECC described may be included in Figure 3 The state information STATE_INF is stored in the memory 114 , where the memory 114 is used as a buffer / cache memory of the controller 130 .

[0138] Figure 6 It is shown Figure 5 A flow chart of read recycling performed by the controller 130 is shown.

[0139] Operation S610

[0140] The controller 130 may determine the pre-victim block based on the number of uncorrectable errors nUECC of the pre-read block calculated during the pre-read operation. In S610, the controller 130 may queue pre-victim information PRE_INF of the pre-victim blocks in the first queue buffer 403A according to the order determined as the pre-victim blocks.

[0141] Even when the pre-sacrificial information PRE_INF is queued in the first queue buffer 403A, the number of uncorrectable errors nUECC of the pre-sacrificial block may change in real time. Therefore, the controller 130 may update the number of uncorrectable errors nUECC of the pre-sacrificial block in real time and reorder the queueing order of the pre-sacrificial information PRE_INF based on the updated number of uncorrectable errors nUECC.

[0142] Operation S620

[0143] The controller 130 may determine a normal victim block based on the read count nRD. The controller 130 may determine a memory block whose read count nRD is greater than a threshold value TH among the memory blocks as a normal victim block.

[0144] In S620 , the controller 130 may queue the normal victim information NOR_INF of the normal victim blocks in the second queue buffer 403B according to the order of being determined as the normal victim blocks.

[0145] Even when the normal victim information NOR_INF is queued in the second queue buffer 403B, the read count nRD of the normal victim block may change in real time. Therefore, the controller 130 can update the read count nRD of the normal victim block contained in the normal victim information NOR_INF in real time, and reorder the queue order of the normal victim information NOR_INF based on the updated read count nRD.

[0146] Operation S630

[0147] The controller 130 may determine the inner victim block based on the number nUECC of uncorrectable errors of the inner read block calculated during the inner read operation.

[0148] In S630 , the controller 130 may queue the internal victim information INT_INF of the internal victim blocks in the third queue buffer 403C according to the order of being determined as the internal victim blocks.

[0149] Even when the internal victim information INT_INF is queued in the third queue buffer 403C, the number of uncorrectable errors nUECC of the internal victim block may change in real time. Therefore, the controller 130 can update the number of uncorrectable errors nUECC of the internal victim block in real time and reorder the queueing order of the internal victim information INT_INF based on the updated number of uncorrectable errors nUECC.

[0150] In some embodiments, the controller 130 may reorder the queueing sequence of the pre-victim information PRE_INF, the normal victim information NOR_INF, and the internal victim information INT_INF so as to preferentially perform data recovery operations and read recycling on victim blocks with a larger number of uncorrectable errors nUECC.

[0151] In some embodiments, the controller 130 may queue the pre-sacrificial information PRE_INF, the normal sacrificial information NOR_INF, and the internal sacrificial information INT_INF in Figure 3 In a queue buffer of 403.

[0152] Operation S650

[0153] In S650, when it is determined that read reclamation is to be performed, the controller 130 may determine the priority of read reclamation (RR) according to the read type RD_TYPE of the victim block. In this case, the controller 130 may determine the priority of the pre-victim block to be lower than the priorities of the normal victim block and the internal victim block.

[0154] Operation S670

[0155] In operation S670 , the controller 130 may perform read reclamation on the victim block according to the priority determined in S650 and the queue order reordered by the data recovery operation.

[0156] Even while operations S610 to S670 are being performed, the reordered queue order may change in real time.

[0157] The controller 130 may perform a data recovery operation on the victim block before performing read reclamation in S670 .

[0158] Fig. 7A and Figure 7B is a diagram illustrating a method of reordering victim information according to the first embodiment of the present disclosure.

[0159] Fig. 7A An example of pre-victim information PRE_INF queued in the first queue buffer 403A is shown.

[0160] exist Fig. 7AIn the example shown, the pre-victim information PRE_INF may include an identifier BLK_ID of the pre-victim block, a queuing order Q_OD of the pre-victim information PRE_INF, a read type RD_TYPE of the pre-victim block, and a number nUECC of uncorrectable errors contained in the pre-victim block.

[0161] The pre-sacrifice information PRE_INF of the second pre-sacrifice block PRE_BLK_2, the first pre-sacrifice block PRE_BLK_1, and the third pre-sacrifice block PRE_BLK_3 may be queued in sequence in the first queue buffer 403A according to the queueing order Q_OD: PRE_BLK_2->PRE_BLK_1->PRE_BLK_3. In this case, the queueing order Q_OD may refer to the order in which the second pre-sacrifice block PRE_BLK_2, the first pre-sacrifice block PRE_BLK_1, and the third pre-sacrifice block PRE_BLK_3 are determined as pre-sacrifice blocks.

[0162] The number of uncorrectable errors nUECC of the first pre-sacrificial block PRE_BLK_1 and the third pre-sacrificial block PRE_BLK_3 is the largest (eg, 80), and the number of uncorrectable errors nUECC of the second pre-sacrificial block PRE_BLK_2 is the smallest (eg, 60), wherein the number of uncorrectable errors nUECC is PRE_BLK_1=PRE_BLK_3>PRE_BLK_2.

[0163] The controller 130 may reorder the queueing order of the pre-victim blocks PRE_BLK according to the number of uncorrectable errors nUECC. Therefore, the controller 130 may reorder the queueing order in the order of the first pre-victim block PRE_BLK_1, the third pre-victim block PRE_BLK_3, and the second pre-victim block PRE_BLK_2.

[0164] However, since the number nUECC of uncorrectable errors of the first pre-victim block PRE_BLK_1 is equal to the number nUECC of uncorrectable errors of the third pre-victim block PRE_BLK_3 , the controller 130 may reorder the queuing order of the pre-victim information PRE_INF by reflecting not only the number nUECC of uncorrectable errors but also the queuing order Q_OD.

[0165] The controller 130 may reorder the queue order of the first pre-sacrificial block PRE_BLK_1 having the longest queue time in the first queue buffer 403A, so that the queue order of the first pre-sacrificial block PRE_BLK_1 is greater than the queue order of the third pre-sacrificial block PRE_BLK_3. That is, the queue order after reordering is Q_RE_OD: PRE_BLK_1->PRE_BLK_3->PRE_BLK_2. Therefore, the controller 130 may perform pre-read recovery on the pre-sacrificial block PRE_BLK in the order of "PRE_BLK_1->PRE_BLK_3->PRE_BLK_2".

[0166] Figure 7B An example of normal victim information NOR_INF queued in the second queue buffer 403B is shown.

[0167] like Figure 7B As shown, the normal victim information NOR_INF may include an identifier BLK_ID of a normal victim block, a queue order Q_OD of the normal victim information NOR_INF, a read type RD_TYPE of the normal victim block, and a damage degree. In this embodiment, the damage degree may include a read count nRD.

[0168] The normal victim information NOR_INF of the sixth normal victim block NOR_BLK_6 , the fifth normal victim block NOR_BLK_5 , and the fourth normal victim block NOR_BLK_4 may be sequentially queued in the second queue buffer 403B according to the queue order Q_OD: NOR_BLK_6 -> NOR_BLK_5 -> NOR_BLK_4 .

[0169] The queuing order Q_OD may refer to an order in which the sixth normal victim block NOR_BLK_6 , the fifth normal victim block NOR_BLK_5 , and the fourth normal victim block NOR_BLK_4 are determined as normal victim blocks.

[0170] The read count nRD of the fourth normal sacrificial block NOR_BLK_4 is the highest (e.g., 100), and the read count nRD of the sixth normal sacrificial block NOR_BLK_6 is the lowest (e.g., 50). The read count nRD of the fifth normal sacrificial block NOR_BLK_5 may be in the middle (e.g., 80). That is, the order of the read counts is nRD: NOR_BLK_4>NOR_BLK_5>NOR_BLK_6.

[0171] The controller 130 may reorder the queueing order of the normal victim information NOR_INF according to the read count nRD. Therefore, the controller 130 may reorder the queueing order in the order of the fourth normal victim block NOR_BLK_4, the fifth normal victim block NOR_BLK_5, and the sixth normal victim block NOR_BLK_6, so that the reordered queueing order is Q_RE_OD: NOR_BLK_4->NOR_BLK_5->NOR_BLK_6. Therefore, the controller 130 may perform normal read recovery on the normal victim blocks in the order of "NOR_BLK_4->NOR_BLK_5->NOR_BLK_6".

[0172] Therefore, in Fig. 7A and Figure 7B In the description, since the pre-sacrifice information PRE_INF is stored in the first queue buffer 403A and the normal sacrifice information NOR_INF is stored in the second queue buffer 403B, the controller 130 can set the read recovery priority of the first queue buffer 403A to be lower than the read recovery priority of the second queue buffer 403B.

[0173] although Fig. 7A and Figure 7B Although not shown in the figure, the controller 130 may set the priority of the read reclaim of the first queue buffer 403A to be lower than the priority of the read reclaim of the third queue buffer 403C storing the internal sacrifice information INT_INF. Therefore, the controller 130 may determine the priority of the normal read reclaim and the internal read reclaim as the "first priority", and determine the priority of the pre-read reclaim as the "second priority".

[0174] Figure 8 is a diagram illustrating a method of reordering victim information according to a second embodiment of the present disclosure.

[0175] Figure 8 4 is a diagram illustrating an example of an operation of determining the priority of read reclaiming of pre-victim information PRE_INF and normal victim information NOR_INF stored in one queue buffer 403 .

[0176] Reference Figure 8 , the normal victim information NOR_INF and the pre-victim information PRE_INF are queued in a queue buffer 403 according to the determined order.

[0177] The sacrificial information of the second pre-sacrificial block PRE_BLK_2, the sixth normal sacrificial block NOR_BLK_6, the first pre-sacrificial block PRE_BLK_1, the fifth normal sacrificial block NOR_BLK_5, the third pre-sacrificial block PRE_BLK_3 and the fourth normal sacrificial block NOR_BLK_4 may be queued in sequence in the queue buffer 403. That is, the queueing order is Q_OD: PRE_BLK_2->NOR_BLK_6->PRE_BLK_1->NOR_BLK_5->PRE_BLK_3->NOR_BLK_4.

[0178] The queuing order Q_OD may refer to an order in which the second pre-sacrificial block PRE_BLK_2 , the sixth normal sacrificial block NOR_BLK_6 , the first pre-sacrificial block PRE_BLK_1 , the fifth normal sacrificial block NOR_BLK_5 , the third pre-sacrificial block PRE_BLK_3 , and the fourth normal sacrificial block NOR_BLK_4 are determined as sacrificial blocks.

[0179] When determining that read reclamation is to be performed, the controller 130 may determine the priority PRIOITY of read reclamation of the pre-victim information PRE_INF and the normal victim information NOR_INF according to the read type RD_TYPE.

[0180] The controller 130 may determine the priority PRIOITY of the normal victim block whose read type RD_TYPE is “normal read NOR” to be greater than the priority PRIOITY of the pre-victim block whose read type RD_TYPE is “pre-read PRE”.

[0181] The controller 130 may reorder the queueing order of the pre-sacrificial block PRE_BLK according to the priority PRIOITY. In addition, the controller 130 may reorder the queueing order not only according to the priority PRIOITY but also according to the number of uncorrectable errors nUECC and the read count nRD. In addition, the controller 130 may reorder the queueing order by additionally reflecting the queueing order Q_OD.

[0182] The controller 130 may reorder the queueing order in the order of the fourth normal sacrificial block NOR_BLK_4, the fifth normal sacrificial block NOR_BLK_5, the sixth normal sacrificial block NOR_BLK_6, the first pre-sacrificial block PRE_BLK_1, the third pre-sacrificial block PRE_BLK_3, and the second pre-sacrificial block PRE_BLK_2. Therefore, the controller 130 may perform read recovery in the order of "NOR_BLK_4->NOR_BLK_5->NOR_BLK_6->PRE_BLK_1->PRE_BLK_3->PRE_BLK_2".

[0183] As described above, the controller 130 may set the priority of pre-recycling of the pre-sacrificial information PRE_INF stored in the queue buffer 403 to be lower than the priority of normal recycling of the normal sacrificial information NOR_INF. Figure 8 Although not shown in the figure, the controller 130 may also set the priority of the pre-recycling of the pre-sacrifice information PRE_INF stored in the queue buffer 403 to be lower than the priority of the internal recycling of the internal sacrifice information INT_INF. Therefore, the controller 130 may determine the priority of the normal read recycling and the internal read recycling as the "first priority" and determine the priority of the pre-read recycling as the "second priority".

[0184] Fig. 9 It shows that according to Figure 6 The flowchart of the priority execution read reclamation S670 is shown.

[0185] The controller 130 may control the memory device 150 to perform read reclamation according to the reordered queueing order of the first to third queue buffers 403A to 403C and the determined priorities.

[0186] Reference Fig. 9 , the controller 130 may perform read recovery on the normal victim block NOR_BLK and the internal victim block INT_BLK in priority to the pre-victim block according to the determined priority. Fig. 9 In the figure, NOR-RR indicates that read recovery is performed on the normal victim block NOR_BLK, and INT-RR indicates that read recovery is performed on the internal victim block INT_BLK.

[0187] In S910, the controller 130 may preferentially perform read reclamation on the normal victim block NOR_BLK and the internal victim block INT_BLK according to the reordered queueing order of the normal victim information NOR_INF and the internal victim information INT_INF. Prior to S910, a data recovery operation may be performed on the normal victim block NOR_BLK and the internal victim block INT_BLK.

[0188] In S930 , the controller 130 may determine whether the normal read reclaim NOR-RR and the internal read reclaim INT-RR have been performed to completion.

[0189] In S950, when normal read reclamation and internal read reclamation have been completed, the controller 130 may determine whether a condition for performing pre-read reclamation is satisfied. The condition for performing pre-read reclamation may include a case where the memory system 110 is in an idle state, a case where a plurality of memory blocks each have a low dirty level, and a case where forced garbage collection (FGC) is performed.

[0190] In S970, when the normal read recovery NOR-RR and the internal read recovery INT-RR have been completed and the memory system 110 meets the condition for performing the pre-read recovery PRE-RR, the controller 130 can perform the pre-read recovery PRE-RR on the pre-sacrificial block PRE_BLK according to the reordered queue order of the pre-sacrificial information PRE_INF. Before S970, a data recovery operation can be performed on the pre-sacrificial block PRE_BLK.

[0191] Since the pre-read reclamation is performed after the normal read reclamation is completed, the pre-read reclamation does not affect the normal read reclamation. Accordingly, the pre-read reclamation may not affect the data input / output operation performed by the external device 102 and the memory system 110.

[0192] In addition, since the pre-read reclaim is performed after the internal read reclaim is completed, the pre-read reclaim does not affect the internal read reclaim. Therefore, the pre-read reclaim does not affect the operation of improving the reliability of dormant blocks and weak blocks, where the probability of uncorrectable errors UECC occurring due to the deterioration of data retention characteristics and read interference is high.

[0193] Fig.10 is a flowchart illustrating a detailed operation of recycling according to an embodiment of the present disclosure.

[0194] Specifically, Fig.10 Methods of pre-recycling, normal recycling and internal recycling are shown.

[0195] In S1001 , the controller 130 may perform a data recovery operation on a victim block for error recovery.

[0196] In S1003 , the controller 130 may migrate data whose errors have been recovered through the data recovery operation to a target block for read reclamation.

[0197] The controller 130 may divide the victim block into a block including an uncorrectable error UECC and a block not including an uncorrectable error UECC.

[0198] In S1007, the controller 130 may process the victim block including the uncorrectable error UECC as a bad block BB. The victim block processed as the bad block BB may not be used as a storage space for data storage.

[0199] In S1009 , the controller 130 may release the victim block that does not contain the uncorrectable error UECC. In addition, the controller 130 may perform garbage collection (GC) and convert the victim block into a free block for data storage.

[0200] Fig.11is a flow chart illustrating garbage collection according to an embodiment of the present disclosure.

[0201] Since valid data read from the pre-sacrificial block, the normal sacrificial block and the internal sacrificial block are migrated and stored in the target block, the controller 130 can perform an erase operation on the pre-sacrificial block, the normal sacrificial block and the internal sacrificial block and ensure that the pre-sacrificial block and the normal sacrificial block are free blocks. The erase operation can be performed by garbage collection.

[0202] Garbage collection includes the operation of migrating data stored in a memory block containing valid data to a target block and then erasing the memory block.

[0203] Fig.11 The illustrated memory device 150 includes first to eighth memory blocks BLOCK1 to BLOCK8 , and each of the first to eighth memory blocks BLOCK1 to BLOCK8 includes first to fifth pages PAGE1 to PAGE5 .

[0204] Reference Fig.11 , the first to fourth storage blocks BLOCK1 to BLOCK4 may be closed blocks storing data, and the fifth to eighth storage blocks BLOCK5 to BLOCK8 may be free blocks storing no data.

[0205] like Fig.11 As shown, valid data and invalid data may be distributed and stored in first to fifth pages PAGE1 to PAGE5 of the fourth memory block BLK4 .

[0206] In this case, the controller 130 can copy the valid data stored in the fourth storage block BLK4 to the eighth storage block BLK8 as a free block, and then perform an erase operation on the fourth storage block BLK4, thereby ensuring that the fourth storage block BLK4 is a free block. Therefore, the storage space of the storage block can be ensured.

[0207] After storing the valid data of the fourth storage block BLK4 to the eighth storage block BLK8, the remaining space can be ensured to be free space. In this case, the fourth storage block BLK4 as the target of garbage collection can be called a victim block or source block of garbage collection, and the eighth storage block BLK8 can be called a target block of garbage collection.

[0208] In addition, since the valid data of the fourth memory block BLK4 has been migrated to the eighth memory block BLK8 , all the data of the fourth memory block BLK4 may be erased and regarded as a free block.

[0209] In this way, the operation of migrating data stored in a storage block where valid data is dispersed to a free block and then erasing the data in the storage block may be referred to as garbage collection.

[0210] According to an embodiment of the present disclosure, the number of free blocks may be increased by performing garbage collection on a memory device, thereby improving the data storage efficiency of the memory device.

[0211] According to the embodiments of the present disclosure, a storage block with low reliability detected during a pre-read operation can be determined as a sacrificial block for read recovery, thereby effectively reducing the resources and time consumed in determining the sacrificial block.

[0212] According to an embodiment of the present disclosure, the priority of the pre-victim block determined during the pre-read operation may be lower than the priority of the normal victim block determined by the normal read operation. Therefore, the pre-read reclamation does not affect the normal read reclamation.

[0213] Although embodiments of the present disclosure have been described in this specification by specific examples and limited embodiments, these embodiments are provided only to help the overall understanding of the present disclosure, and the present disclosure is not limited to the embodiments herein. Those skilled in the art of the present disclosure can make various modifications and changes from this specification, and these modifications and changes should be considered as part of the present disclosure. In addition, the embodiments can be combined to form other embodiments.

Claims

1. A memory system, comprising: A memory device including a plurality of memory blocks; as well as The controller controls the memory device to perform pre-reading reclamation on a pre-victim block in the pre-read blocks among the plurality of storage blocks, the pre-victim block including an uncorrectable error, the pre-read block being a block on which a pre-reading operation has been performed.

2. The memory system according to claim 1, wherein: The controller controls the memory device to perform the pre-read reclamation when the number of read requests from the external device is greater than or equal to a threshold and after performing at least one of normal read reclamation and internal read reclamation, wherein the normal read reclamation is performed on a normal victim block that performs a normal read operation, and the internal read reclamation is performed on an internal victim block determined during an internal read operation that has been performed.

3. The memory system according to claim 2, wherein: When the memory system is in an idle state in which data input and output operations are not performed with the external device, the controller controls the memory device to perform the pre-read reclamation.

4. The memory system according to claim 2, wherein: The controller controls the memory device to perform the pre-read reclamation when an invalidity level of data stored in the plurality of memory blocks is less than or equal to a predetermined value.

5. The memory system according to claim 2, wherein: When forced garbage collection is performed, the controller controls the memory device to perform the pre-read reclamation.

6. The memory system according to claim 1, wherein: The controller controls the memory device to perform the pre-read reclamation on the pre-victim block on which the data recovery operation has been performed.

7. The memory system according to claim 6, wherein: The controller processes the pre-sacrificial block storing data that failed error recovery among the pre-sacrificial blocks that have been subjected to the pre-read recovery as a bad block.

8. The memory system according to claim 2, wherein: The controller determines the priorities of the normal read reclamation and the internal read reclamation to be greater than the priority of the pre-read reclamation.

9. The memory system according to claim 8, wherein: The controller reorders an order of read reclamation based on the priority, the number of read requests for real-time update, and the number of uncorrectable errors, the order of read reclamation indicating an order in which each of the pre-read reclamation, the normal read reclamation, and the internal read reclamation is performed.

10. The memory system according to claim 2, wherein: The controller includes a queue buffer in which first information of the pre-victim block, second information of the normal victim block, and third information of the internal victim block are queued.

11. The memory system according to claim 2, wherein: The controller comprises: a first queue buffer, in which information of the pre-sacrificial block is queued; a second queue buffer, in which the information of the normal victim block is queued; and A third queue buffer, in which information of the internal victim block is queued.

12. A memory system comprising: A memory device including a plurality of memory blocks; as well as Controller: Counting the number of uncorrectable errors contained in each of the pre-read blocks, determining a pre-read block containing an uncorrectable error among the plurality of storage blocks as a pre-victim block, and controlling the memory device to perform pre-read reclamation on the pre-victim block, When it is determined that a pre-read operation is to be performed, each of the pre-read blocks stores sequential data.

13. The memory system according to claim 12, wherein: The controller determines a normal victim block among the plurality of memory blocks in which the number of read requests from the external device is greater than or equal to a threshold value and performs a normal read operation, controlling the memory device to perform normal read reclamation on the normal victim block, and The priority of the normal read reclamation is set to be greater than the priority of the pre-read reclamation.

14. The memory system according to claim 12, wherein: The controller performs the pre-read reclamation after performing a data recovery operation on the pre-victim block.

15. The memory system of claim 14, wherein: The controller processes a pre-sacrificial block storing an error that is not recovered by the data recovery operation as a bad block.

16. The memory system according to claim 13, further comprising a queue buffer, in which the pre-sacrifice information of the pre-sacrifice block is queued according to the determined order of the pre-sacrifice block, and the normal sacrifice information of the normal sacrifice block is queued in the queue buffer according to the determined order of the normal sacrifice block.

17. The memory system according to claim 16, wherein: The queue buffer comprises: a first queue buffer, in which information of the pre-victim block is queued; and A second queue buffer, in which the information of the normal victim block is queued.

18. The memory system of claim 16, wherein: The controller reorders the queuing sequence of the pre-victim information and the normal victim information based on the priority, the number of uncorrectable errors updated in real time, and the number of read requests.

19. The memory system of claim 18, wherein: The controller performs the pre-read eviction and the normal read eviction according to the reordered queue order.

20. The memory system of claim 13, wherein: After completing the execution of the normal read reclamation, the controller executes the pre-read reclamation in one of the following states: a first state, in which the memory system does not perform a data input / output operation with the external device; a second state, in which an invalidity level of data stored in the plurality of memory blocks is equal to or less than a predetermined value; and a third state, in which a forced garbage collection is performed.

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